2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BLORP_GENX_EXEC_H
25 #define BLORP_GENX_EXEC_H
27 #include "blorp_priv.h"
28 #include "common/gen_device_info.h"
29 #include "common/gen_sample_positions.h"
30 #include "intel_aub.h"
33 * This file provides the blorp pipeline setup and execution functionality.
34 * It defines the following function:
37 * blorp_exec(struct blorp_context *blorp, void *batch_data,
38 * const struct blorp_params *params);
40 * It is the job of whoever includes this header to wrap this in something
41 * to get an externally visible symbol.
43 * In order for the blorp_exec function to work, the driver must provide
44 * implementations of the following static helper functions.
48 blorp_emit_dwords(struct blorp_batch
*batch
, unsigned n
);
51 blorp_emit_reloc(struct blorp_batch
*batch
,
52 void *location
, struct blorp_address address
, uint32_t delta
);
55 blorp_alloc_dynamic_state(struct blorp_batch
*batch
,
56 enum aub_state_struct_type type
,
61 blorp_alloc_vertex_buffer(struct blorp_batch
*batch
, uint32_t size
,
62 struct blorp_address
*addr
);
65 blorp_alloc_binding_table(struct blorp_batch
*batch
, unsigned num_entries
,
66 unsigned state_size
, unsigned state_alignment
,
67 uint32_t *bt_offset
, uint32_t *surface_offsets
,
71 blorp_flush_range(struct blorp_batch
*batch
, void *start
, size_t size
);
74 blorp_surface_reloc(struct blorp_batch
*batch
, uint32_t ss_offset
,
75 struct blorp_address address
, uint32_t delta
);
78 blorp_emit_urb_config(struct blorp_batch
*batch
, unsigned vs_entry_size
);
80 /***** BEGIN blorp_exec implementation ******/
82 #include "genxml/gen_macros.h"
85 _blorp_combine_address(struct blorp_batch
*batch
, void *location
,
86 struct blorp_address address
, uint32_t delta
)
88 if (address
.buffer
== NULL
) {
89 return address
.offset
+ delta
;
91 return blorp_emit_reloc(batch
, location
, address
, delta
);
95 #define __gen_address_type struct blorp_address
96 #define __gen_user_data struct blorp_batch
97 #define __gen_combine_address _blorp_combine_address
99 #include "genxml/genX_pack.h"
101 #define _blorp_cmd_length(cmd) cmd ## _length
102 #define _blorp_cmd_length_bias(cmd) cmd ## _length_bias
103 #define _blorp_cmd_header(cmd) cmd ## _header
104 #define _blorp_cmd_pack(cmd) cmd ## _pack
106 #define blorp_emit(batch, cmd, name) \
107 for (struct cmd name = { _blorp_cmd_header(cmd) }, \
108 *_dst = blorp_emit_dwords(batch, _blorp_cmd_length(cmd)); \
109 __builtin_expect(_dst != NULL, 1); \
110 _blorp_cmd_pack(cmd)(batch, (void *)_dst, &name), \
113 #define blorp_emitn(batch, cmd, n) ({ \
114 uint32_t *_dw = blorp_emit_dwords(batch, n); \
115 struct cmd template = { \
116 _blorp_cmd_header(cmd), \
117 .DWordLength = n - _blorp_cmd_length_bias(cmd), \
119 _blorp_cmd_pack(cmd)(batch, _dw, &template); \
120 _dw + 1; /* Array starts at dw[1] */ \
129 * Assign the entire URB to the VS. Even though the VS disabled, URB space
130 * is still needed because the clipper loads the VUE's from the URB. From
131 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
132 * Dword 1.15:0 "VS Number of URB Entries":
133 * This field is always used (even if VS Function Enable is DISABLED).
135 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
136 * safely ignore it because this batch contains only one draw call.
137 * Because of URB corruption caused by allocating a previous GS unit
138 * URB entry to the VS unit, software is required to send a “GS NULL
139 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
140 * plus a dummy DRAW call before any case where VS will be taking over
143 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
144 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
146 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
147 * programmed in order for the programming of this state to be
151 emit_urb_config(struct blorp_batch
*batch
,
152 const struct blorp_params
*params
)
154 /* Once vertex fetcher has written full VUE entries with complete
155 * header the space requirement is as follows per vertex (in bytes):
157 * Header Position Program constants
158 * +--------+------------+-------------------+
159 * | 16 | 16 | n x 16 |
160 * +--------+------------+-------------------+
162 * where 'n' stands for number of varying inputs expressed as vec4s.
164 const unsigned num_varyings
=
165 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
166 const unsigned total_needed
= 16 + 16 + num_varyings
* 16;
168 /* The URB size is expressed in units of 64 bytes (512 bits) */
169 const unsigned vs_entry_size
= DIV_ROUND_UP(total_needed
, 64);
171 blorp_emit_urb_config(batch
, vs_entry_size
);
175 blorp_emit_vertex_data(struct blorp_batch
*batch
,
176 const struct blorp_params
*params
,
177 struct blorp_address
*addr
,
180 const float vertices
[] = {
181 /* v0 */ (float)params
->x1
, (float)params
->y1
, params
->z
,
182 /* v1 */ (float)params
->x0
, (float)params
->y1
, params
->z
,
183 /* v2 */ (float)params
->x0
, (float)params
->y0
, params
->z
,
186 void *data
= blorp_alloc_vertex_buffer(batch
, sizeof(vertices
), addr
);
187 memcpy(data
, vertices
, sizeof(vertices
));
188 *size
= sizeof(vertices
);
189 blorp_flush_range(batch
, data
, *size
);
193 blorp_emit_input_varying_data(struct blorp_batch
*batch
,
194 const struct blorp_params
*params
,
195 struct blorp_address
*addr
,
198 const unsigned vec4_size_in_bytes
= 4 * sizeof(float);
199 const unsigned max_num_varyings
=
200 DIV_ROUND_UP(sizeof(params
->wm_inputs
), vec4_size_in_bytes
);
201 const unsigned num_varyings
=
202 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
204 *size
= 16 + num_varyings
* vec4_size_in_bytes
;
206 const uint32_t *const inputs_src
= (const uint32_t *)¶ms
->wm_inputs
;
207 void *data
= blorp_alloc_vertex_buffer(batch
, *size
, addr
);
208 uint32_t *inputs
= data
;
210 /* Copy in the VS inputs */
211 assert(sizeof(params
->vs_inputs
) == 16);
212 memcpy(inputs
, ¶ms
->vs_inputs
, sizeof(params
->vs_inputs
));
215 if (params
->wm_prog_data
) {
216 /* Walk over the attribute slots, determine if the attribute is used by
217 * the program and when necessary copy the values from the input storage
218 * to the vertex data buffer.
220 for (unsigned i
= 0; i
< max_num_varyings
; i
++) {
221 const gl_varying_slot attr
= VARYING_SLOT_VAR0
+ i
;
223 const int input_index
= params
->wm_prog_data
->urb_setup
[attr
];
227 memcpy(inputs
, inputs_src
+ i
* 4, vec4_size_in_bytes
);
233 blorp_flush_range(batch
, data
, *size
);
237 blorp_emit_vertex_buffers(struct blorp_batch
*batch
,
238 const struct blorp_params
*params
)
240 struct GENX(VERTEX_BUFFER_STATE
) vb
[2];
241 memset(vb
, 0, sizeof(vb
));
244 blorp_emit_vertex_data(batch
, params
, &vb
[0].BufferStartingAddress
, &size
);
245 vb
[0].VertexBufferIndex
= 0;
246 vb
[0].BufferPitch
= 3 * sizeof(float);
247 vb
[0].VertexBufferMOCS
= batch
->blorp
->mocs
.vb
;
249 vb
[0].AddressModifyEnable
= true;
252 vb
[0].BufferSize
= size
;
254 vb
[0].BufferAccessType
= VERTEXDATA
;
255 vb
[0].EndAddress
= vb
[0].BufferStartingAddress
;
256 vb
[0].EndAddress
.offset
+= size
- 1;
259 blorp_emit_input_varying_data(batch
, params
,
260 &vb
[1].BufferStartingAddress
, &size
);
261 vb
[1].VertexBufferIndex
= 1;
262 vb
[1].BufferPitch
= 0;
263 vb
[1].VertexBufferMOCS
= batch
->blorp
->mocs
.vb
;
265 vb
[1].AddressModifyEnable
= true;
268 vb
[1].BufferSize
= size
;
270 vb
[1].BufferAccessType
= INSTANCEDATA
;
271 vb
[1].EndAddress
= vb
[1].BufferStartingAddress
;
272 vb
[1].EndAddress
.offset
+= size
- 1;
275 const unsigned num_dwords
= 1 + GENX(VERTEX_BUFFER_STATE_length
) * 2;
276 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), num_dwords
);
278 for (unsigned i
= 0; i
< 2; i
++) {
279 GENX(VERTEX_BUFFER_STATE_pack
)(batch
, dw
, &vb
[i
]);
280 dw
+= GENX(VERTEX_BUFFER_STATE_length
);
285 blorp_emit_vertex_elements(struct blorp_batch
*batch
,
286 const struct blorp_params
*params
)
288 const unsigned num_varyings
=
289 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
290 const unsigned num_elements
= 2 + num_varyings
;
292 struct GENX(VERTEX_ELEMENT_STATE
) ve
[num_elements
];
293 memset(ve
, 0, num_elements
* sizeof(*ve
));
295 /* Setup VBO for the rectangle primitive..
297 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
298 * vertices. The vertices reside in screen space with DirectX
299 * coordinates (that is, (0, 0) is the upper left corner).
306 * Since the VS is disabled, the clipper loads each VUE directly from
307 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
308 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
309 * dw0: Reserved, MBZ.
310 * dw1: Render Target Array Index. Below vertex fetcher gets programmed
311 * to assign this with primitive instance identifier which will be
312 * used for layered clears. All other renders have only one instance
313 * and therefore the value will be effectively zero.
314 * dw2: Viewport Index. The HiZ op disables viewport mapping and
315 * scissoring, so set the dword to 0.
316 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive,
317 * so set the dword to 0.
318 * dw4: Vertex Position X.
319 * dw5: Vertex Position Y.
320 * dw6: Vertex Position Z.
321 * dw7: Vertex Position W.
323 * dw8: Flat vertex input 0
324 * dw9: Flat vertex input 1
326 * dwn: Flat vertex input n - 8
328 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
329 * "Vertex URB Entry (VUE) Formats".
331 * Only vertex position X and Y are going to be variable, Z is fixed to
332 * zero and W to one. Header words dw0,2,3 are zero. There is no need to
333 * include the fixed values in the vertex buffer. Vertex fetcher can be
334 * instructed to fill vertex elements with constant values of one and zero
335 * instead of reading them from the buffer.
336 * Flat inputs are program constants that are not interpolated. Moreover
337 * their values will be the same between vertices.
339 * See the vertex element setup below.
341 ve
[0].VertexBufferIndex
= 1;
343 ve
[0].SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
344 ve
[0].SourceElementOffset
= 0;
345 ve
[0].Component0Control
= VFCOMP_STORE_SRC
;
347 /* From Gen8 onwards hardware is no more instructed to overwrite components
348 * using an element specifier. Instead one has separate 3DSTATE_VF_SGVS
349 * (System Generated Value Setup) state packet for it.
352 ve
[0].Component1Control
= VFCOMP_STORE_0
;
354 ve
[0].Component1Control
= VFCOMP_STORE_IID
;
356 ve
[0].Component2Control
= VFCOMP_STORE_SRC
;
357 ve
[0].Component3Control
= VFCOMP_STORE_SRC
;
359 ve
[1].VertexBufferIndex
= 0;
361 ve
[1].SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
;
362 ve
[1].SourceElementOffset
= 0;
363 ve
[1].Component0Control
= VFCOMP_STORE_SRC
;
364 ve
[1].Component1Control
= VFCOMP_STORE_SRC
;
365 ve
[1].Component2Control
= VFCOMP_STORE_SRC
;
366 ve
[1].Component3Control
= VFCOMP_STORE_1_FP
;
368 for (unsigned i
= 0; i
< num_varyings
; ++i
) {
369 ve
[i
+ 2].VertexBufferIndex
= 1;
370 ve
[i
+ 2].Valid
= true;
371 ve
[i
+ 2].SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
372 ve
[i
+ 2].SourceElementOffset
= 16 + i
* 4 * sizeof(float);
373 ve
[i
+ 2].Component0Control
= VFCOMP_STORE_SRC
;
374 ve
[i
+ 2].Component1Control
= VFCOMP_STORE_SRC
;
375 ve
[i
+ 2].Component2Control
= VFCOMP_STORE_SRC
;
376 ve
[i
+ 2].Component3Control
= VFCOMP_STORE_SRC
;
379 const unsigned num_dwords
=
380 1 + GENX(VERTEX_ELEMENT_STATE_length
) * num_elements
;
381 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_ELEMENTS
), num_dwords
);
383 for (unsigned i
= 0; i
< num_elements
; i
++) {
384 GENX(VERTEX_ELEMENT_STATE_pack
)(batch
, dw
, &ve
[i
]);
385 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
389 /* Overwrite Render Target Array Index (2nd dword) in the VUE header with
390 * primitive instance identifier. This is used for layered clears.
392 blorp_emit(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
393 sgvs
.InstanceIDEnable
= true;
394 sgvs
.InstanceIDComponentNumber
= COMP_1
;
395 sgvs
.InstanceIDElementOffset
= 0;
398 for (unsigned i
= 0; i
< num_elements
; i
++) {
399 blorp_emit(batch
, GENX(3DSTATE_VF_INSTANCING
), vf
) {
400 vf
.VertexElementIndex
= i
;
401 vf
.InstancingEnable
= false;
405 blorp_emit(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
406 topo
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
412 blorp_emit_vs_config(struct blorp_batch
*batch
,
413 const struct blorp_params
*params
)
415 struct brw_vs_prog_data
*vs_prog_data
= params
->vs_prog_data
;
417 blorp_emit(batch
, GENX(3DSTATE_VS
), vs
) {
419 vs
.FunctionEnable
= true;
421 vs
.KernelStartPointer
= params
->vs_prog_kernel
;
423 vs
.DispatchGRFStartRegisterForURBData
=
424 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
425 vs
.VertexURBEntryReadLength
=
426 vs_prog_data
->base
.urb_read_length
;
427 vs
.VertexURBEntryReadOffset
= 0;
429 vs
.MaximumNumberofThreads
=
430 batch
->blorp
->isl_dev
->info
->max_vs_threads
- 1;
433 vs
.SIMD8DispatchEnable
=
434 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
441 blorp_emit_sf_config(struct blorp_batch
*batch
,
442 const struct blorp_params
*params
)
444 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
448 * Disable ViewportTransformEnable (dw2.1)
450 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
451 * Primitives Overview":
452 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
453 * use of screen- space coordinates).
455 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
456 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
458 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
459 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
460 * SOLID: Any triangle or rectangle object found to be front-facing
461 * is rendered as a solid object. This setting is required when
462 * (rendering rectangle (RECTLIST) objects.
467 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
);
469 blorp_emit(batch
, GENX(3DSTATE_RASTER
), raster
) {
470 raster
.CullMode
= CULLMODE_NONE
;
473 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
474 sbe
.VertexURBEntryReadOffset
= 1;
476 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
477 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
478 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
480 sbe
.NumberofSFOutputAttributes
= 0;
481 sbe
.VertexURBEntryReadLength
= 1;
483 sbe
.ForceVertexURBEntryReadLength
= true;
484 sbe
.ForceVertexURBEntryReadOffset
= true;
487 for (unsigned i
= 0; i
< 32; i
++)
488 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
494 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
495 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
496 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
498 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
499 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
502 sf
.DepthBufferSurfaceFormat
= params
->depth_format
;
506 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
507 sbe
.VertexURBEntryReadOffset
= 1;
509 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
510 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
511 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
513 sbe
.NumberofSFOutputAttributes
= 0;
514 sbe
.VertexURBEntryReadLength
= 1;
518 #else /* GEN_GEN <= 6 */
520 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
521 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
522 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
524 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
525 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
527 sf
.VertexURBEntryReadOffset
= 1;
529 sf
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
530 sf
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
531 sf
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
533 sf
.NumberofSFOutputAttributes
= 0;
534 sf
.VertexURBEntryReadLength
= 1;
542 blorp_emit_ps_config(struct blorp_batch
*batch
,
543 const struct blorp_params
*params
)
545 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
547 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
548 * nonzero to prevent the GPU from hanging. While the documentation doesn't
549 * mention this explicitly, it notes that the valid range for the field is
550 * [1,39] = [2,40] threads, which excludes zero.
552 * To be safe (and to minimize extraneous code) we go ahead and fully
553 * configure the WM state whether or not there is a WM program.
558 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
560 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
561 if (params
->src
.enabled
) {
562 ps
.SamplerCount
= 1; /* Up to 4 samplers */
563 ps
.BindingTableEntryCount
= 2;
565 ps
.BindingTableEntryCount
= 1;
569 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
570 prog_data
->base
.dispatch_grf_start_reg
;
571 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
572 prog_data
->dispatch_grf_start_reg_2
;
574 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
575 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
577 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
578 ps
.KernelStartPointer2
=
579 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
582 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
583 * it implicitly scales for different GT levels (which have some # of
586 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
589 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
591 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
593 switch (params
->fast_clear_op
) {
594 case BLORP_FAST_CLEAR_OP_NONE
:
597 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
598 ps
.RenderTargetResolveType
= RESOLVE_PARTIAL
;
600 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
601 ps
.RenderTargetResolveType
= RESOLVE_FULL
;
604 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
605 ps
.RenderTargetResolveEnable
= true;
608 case BLORP_FAST_CLEAR_OP_CLEAR
:
609 ps
.RenderTargetFastClearEnable
= true;
612 unreachable("Invalid fast clear op");
616 blorp_emit(batch
, GENX(3DSTATE_PS_EXTRA
), psx
) {
618 psx
.PixelShaderValid
= true;
619 psx
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
620 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
623 if (params
->src
.enabled
)
624 psx
.PixelShaderKillsPixel
= true;
629 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
630 switch (params
->hiz_op
) {
631 case BLORP_HIZ_OP_DEPTH_CLEAR
:
632 wm
.DepthBufferClear
= true;
634 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
635 wm
.DepthBufferResolveEnable
= true;
637 case BLORP_HIZ_OP_HIZ_RESOLVE
:
638 wm
.HierarchicalDepthBufferResolveEnable
= true;
640 case BLORP_HIZ_OP_NONE
:
643 unreachable("not reached");
647 wm
.ThreadDispatchEnable
= true;
649 if (params
->src
.enabled
)
650 wm
.PixelShaderKillsPixel
= true;
652 if (params
->num_samples
> 1) {
653 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
654 wm
.MultisampleDispatchMode
=
655 (prog_data
&& prog_data
->persample_dispatch
) ?
656 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
658 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
659 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
663 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
664 ps
.MaximumNumberofThreads
=
665 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
672 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
673 prog_data
->base
.dispatch_grf_start_reg
;
674 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
675 prog_data
->dispatch_grf_start_reg_2
;
677 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
678 ps
.KernelStartPointer2
=
679 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
681 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
682 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
684 ps
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
686 /* Gen7 hardware gets angry if we don't enable at least one dispatch
687 * mode, so just enable 16-pixel dispatch if we don't have a program.
689 ps
._16PixelDispatchEnable
= true;
692 if (params
->src
.enabled
)
693 ps
.SamplerCount
= 1; /* Up to 4 samplers */
695 switch (params
->fast_clear_op
) {
696 case BLORP_FAST_CLEAR_OP_NONE
:
698 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
699 ps
.RenderTargetResolveEnable
= true;
701 case BLORP_FAST_CLEAR_OP_CLEAR
:
702 ps
.RenderTargetFastClearEnable
= true;
705 unreachable("Invalid fast clear op");
709 #else /* GEN_GEN <= 6 */
711 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
712 wm
.MaximumNumberofThreads
=
713 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
715 switch (params
->hiz_op
) {
716 case BLORP_HIZ_OP_DEPTH_CLEAR
:
717 wm
.DepthBufferClear
= true;
719 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
720 wm
.DepthBufferResolveEnable
= true;
722 case BLORP_HIZ_OP_HIZ_RESOLVE
:
723 wm
.HierarchicalDepthBufferResolveEnable
= true;
725 case BLORP_HIZ_OP_NONE
:
728 unreachable("not reached");
732 wm
.ThreadDispatchEnable
= true;
734 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
735 prog_data
->base
.dispatch_grf_start_reg
;
736 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
737 prog_data
->dispatch_grf_start_reg_2
;
739 wm
.KernelStartPointer0
= params
->wm_prog_kernel
;
740 wm
.KernelStartPointer2
=
741 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
743 wm
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
744 wm
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
746 wm
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
749 if (params
->src
.enabled
) {
750 wm
.SamplerCount
= 1; /* Up to 4 samplers */
751 wm
.PixelShaderKillsPixel
= true; /* TODO: temporarily smash on */
754 if (params
->num_samples
> 1) {
755 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
756 wm
.MultisampleDispatchMode
=
757 (prog_data
&& prog_data
->persample_dispatch
) ?
758 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
760 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
761 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
768 static const uint32_t isl_to_gen_ds_surftype
[] = {
770 /* From the SKL PRM, "3DSTATE_DEPTH_STENCIL::SurfaceType":
772 * "If depth/stencil is enabled with 1D render target, depth/stencil
773 * surface type needs to be set to 2D surface type and height set to 1.
774 * Depth will use (legacy) TileY and stencil will use TileW. For this
775 * case only, the Surface Type of the depth buffer can be 2D while the
776 * Surface Type of the render target(s) are 1D, representing an
777 * exception to a programming note above.
779 [ISL_SURF_DIM_1D
] = SURFTYPE_2D
,
781 [ISL_SURF_DIM_1D
] = SURFTYPE_1D
,
783 [ISL_SURF_DIM_2D
] = SURFTYPE_2D
,
784 [ISL_SURF_DIM_3D
] = SURFTYPE_3D
,
788 blorp_emit_depth_stencil_config(struct blorp_batch
*batch
,
789 const struct blorp_params
*params
)
792 const uint32_t mocs
= 1; /* GEN7_MOCS_L3 */
794 const uint32_t mocs
= 0;
797 blorp_emit(batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
799 db
.DepthWriteEnable
= params
->depth
.enabled
;
800 db
.StencilWriteEnable
= params
->stencil
.enabled
;
804 db
.SeparateStencilBufferEnable
= true;
807 if (params
->depth
.enabled
) {
808 db
.SurfaceFormat
= params
->depth_format
;
809 db
.SurfaceType
= isl_to_gen_ds_surftype
[params
->depth
.surf
.dim
];
812 db
.TiledSurface
= true;
813 db
.TileWalk
= TILEWALK_YMAJOR
;
814 db
.MIPMapLayoutMode
= MIPLAYOUT_BELOW
;
817 db
.HierarchicalDepthBufferEnable
=
818 params
->depth
.aux_usage
== ISL_AUX_USAGE_HIZ
;
820 db
.Width
= params
->depth
.surf
.logical_level0_px
.width
- 1;
821 db
.Height
= params
->depth
.surf
.logical_level0_px
.height
- 1;
822 db
.RenderTargetViewExtent
= db
.Depth
=
823 params
->depth
.view
.array_len
- 1;
825 db
.LOD
= params
->depth
.view
.base_level
;
826 db
.MinimumArrayElement
= params
->depth
.view
.base_array_layer
;
828 db
.SurfacePitch
= params
->depth
.surf
.row_pitch
- 1;
831 isl_surf_get_array_pitch_el_rows(¶ms
->depth
.surf
) >> 2,
834 db
.SurfaceBaseAddress
= params
->depth
.addr
;
835 db
.DepthBufferMOCS
= mocs
;
836 } else if (params
->stencil
.enabled
) {
837 db
.SurfaceFormat
= D32_FLOAT
;
838 db
.SurfaceType
= isl_to_gen_ds_surftype
[params
->stencil
.surf
.dim
];
840 db
.Width
= params
->stencil
.surf
.logical_level0_px
.width
- 1;
841 db
.Height
= params
->stencil
.surf
.logical_level0_px
.height
- 1;
842 db
.RenderTargetViewExtent
= db
.Depth
=
843 params
->stencil
.view
.array_len
- 1;
845 db
.LOD
= params
->stencil
.view
.base_level
;
846 db
.MinimumArrayElement
= params
->stencil
.view
.base_array_layer
;
848 db
.SurfaceType
= SURFTYPE_NULL
;
849 db
.SurfaceFormat
= D32_FLOAT
;
853 blorp_emit(batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hiz
) {
854 if (params
->depth
.aux_usage
== ISL_AUX_USAGE_HIZ
) {
855 hiz
.SurfacePitch
= params
->depth
.aux_surf
.row_pitch
- 1;
856 hiz
.SurfaceBaseAddress
= params
->depth
.aux_addr
;
857 hiz
.HierarchicalDepthBufferMOCS
= mocs
;
860 isl_surf_get_array_pitch_sa_rows(¶ms
->depth
.aux_surf
) >> 2;
865 blorp_emit(batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
) {
866 if (params
->stencil
.enabled
) {
867 #if GEN_GEN >= 8 || GEN_IS_HASWELL
868 sb
.StencilBufferEnable
= true;
871 sb
.SurfacePitch
= params
->stencil
.surf
.row_pitch
- 1,
874 isl_surf_get_array_pitch_el_rows(¶ms
->stencil
.surf
) >> 2,
877 sb
.SurfaceBaseAddress
= params
->stencil
.addr
;
878 sb
.StencilBufferMOCS
= batch
->blorp
->mocs
.tex
;
882 /* 3DSTATE_CLEAR_PARAMS
884 * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS:
885 * [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE
886 * packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
888 blorp_emit(batch
, GENX(3DSTATE_CLEAR_PARAMS
), clear
) {
889 clear
.DepthClearValueValid
= true;
890 clear
.DepthClearValue
= params
->depth
.clear_color
.u32
[0];
895 blorp_emit_blend_state(struct blorp_batch
*batch
,
896 const struct blorp_params
*params
)
898 struct GENX(BLEND_STATE
) blend
;
899 memset(&blend
, 0, sizeof(blend
));
901 for (unsigned i
= 0; i
< params
->num_draw_buffers
; ++i
) {
902 blend
.Entry
[i
].PreBlendColorClampEnable
= true;
903 blend
.Entry
[i
].PostBlendColorClampEnable
= true;
904 blend
.Entry
[i
].ColorClampRange
= COLORCLAMP_RTFORMAT
;
906 blend
.Entry
[i
].WriteDisableRed
= params
->color_write_disable
[0];
907 blend
.Entry
[i
].WriteDisableGreen
= params
->color_write_disable
[1];
908 blend
.Entry
[i
].WriteDisableBlue
= params
->color_write_disable
[2];
909 blend
.Entry
[i
].WriteDisableAlpha
= params
->color_write_disable
[3];
913 void *state
= blorp_alloc_dynamic_state(batch
, AUB_TRACE_BLEND_STATE
,
914 GENX(BLEND_STATE_length
) * 4,
916 GENX(BLEND_STATE_pack
)(NULL
, state
, &blend
);
917 blorp_flush_range(batch
, state
, GENX(BLEND_STATE_length
) * 4);
920 blorp_emit(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), sp
) {
921 sp
.BlendStatePointer
= offset
;
923 sp
.BlendStatePointerValid
= true;
929 blorp_emit(batch
, GENX(3DSTATE_PS_BLEND
), ps_blend
) {
930 ps_blend
.HasWriteableRT
= true;
938 blorp_emit_color_calc_state(struct blorp_batch
*batch
,
939 const struct blorp_params
*params
)
941 struct GENX(COLOR_CALC_STATE
) cc
= { 0 };
944 cc
.StencilReferenceValue
= params
->stencil_ref
;
948 void *state
= blorp_alloc_dynamic_state(batch
, AUB_TRACE_CC_STATE
,
949 GENX(COLOR_CALC_STATE_length
) * 4,
951 GENX(COLOR_CALC_STATE_pack
)(NULL
, state
, &cc
);
952 blorp_flush_range(batch
, state
, GENX(COLOR_CALC_STATE_length
) * 4);
955 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), sp
) {
956 sp
.ColorCalcStatePointer
= offset
;
958 sp
.ColorCalcStatePointerValid
= true;
967 blorp_emit_depth_stencil_state(struct blorp_batch
*batch
,
968 const struct blorp_params
*params
)
971 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) ds
= {
972 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
975 struct GENX(DEPTH_STENCIL_STATE
) ds
= { 0 };
978 if (params
->depth
.enabled
) {
979 ds
.DepthBufferWriteEnable
= true;
981 switch (params
->hiz_op
) {
982 case BLORP_HIZ_OP_NONE
:
983 ds
.DepthTestEnable
= true;
984 ds
.DepthTestFunction
= COMPAREFUNCTION_ALWAYS
;
987 /* See the following sections of the Sandy Bridge PRM, Volume 2, Part1:
988 * - 7.5.3.1 Depth Buffer Clear
989 * - 7.5.3.2 Depth Buffer Resolve
990 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
992 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
993 ds
.DepthTestEnable
= true;
994 ds
.DepthTestFunction
= COMPAREFUNCTION_NEVER
;
997 case BLORP_HIZ_OP_DEPTH_CLEAR
:
998 case BLORP_HIZ_OP_HIZ_RESOLVE
:
999 ds
.DepthTestEnable
= false;
1004 if (params
->stencil
.enabled
) {
1005 ds
.StencilBufferWriteEnable
= true;
1006 ds
.StencilTestEnable
= true;
1007 ds
.DoubleSidedStencilEnable
= false;
1009 ds
.StencilTestFunction
= COMPAREFUNCTION_ALWAYS
;
1010 ds
.StencilPassDepthPassOp
= STENCILOP_REPLACE
;
1012 ds
.StencilWriteMask
= params
->stencil_mask
;
1014 ds
.StencilReferenceValue
= params
->stencil_ref
;
1019 uint32_t offset
= 0;
1020 uint32_t *dw
= blorp_emit_dwords(batch
,
1021 GENX(3DSTATE_WM_DEPTH_STENCIL_length
));
1022 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dw
, &ds
);
1025 void *state
= blorp_alloc_dynamic_state(batch
, AUB_TRACE_DEPTH_STENCIL_STATE
,
1026 GENX(DEPTH_STENCIL_STATE_length
) * 4,
1028 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, state
, &ds
);
1029 blorp_flush_range(batch
, state
, GENX(DEPTH_STENCIL_STATE_length
) * 4);
1033 blorp_emit(batch
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), sp
) {
1034 sp
.PointertoDEPTH_STENCIL_STATE
= offset
;
1042 blorp_emit_surface_state(struct blorp_batch
*batch
,
1043 const struct brw_blorp_surface_info
*surface
,
1044 void *state
, uint32_t state_offset
,
1045 bool is_render_target
)
1047 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1048 struct isl_surf surf
= surface
->surf
;
1050 if (surf
.dim
== ISL_SURF_DIM_1D
&&
1051 surf
.dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
) {
1052 assert(surf
.logical_level0_px
.height
== 1);
1053 surf
.dim
= ISL_SURF_DIM_2D
;
1056 /* Blorp doesn't support HiZ in any of the blit or slow-clear paths */
1057 enum isl_aux_usage aux_usage
= surface
->aux_usage
;
1058 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
1059 aux_usage
= ISL_AUX_USAGE_NONE
;
1061 const uint32_t mocs
=
1062 is_render_target
? batch
->blorp
->mocs
.rb
: batch
->blorp
->mocs
.tex
;
1064 isl_surf_fill_state(batch
->blorp
->isl_dev
, state
,
1065 .surf
= &surf
, .view
= &surface
->view
,
1066 .aux_surf
= &surface
->aux_surf
, .aux_usage
= aux_usage
,
1067 .mocs
= mocs
, .clear_color
= surface
->clear_color
);
1069 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.addr_offset
,
1072 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1073 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1074 * used to store other information. This should be ok, however, because
1075 * surface buffer addresses are always 4K page alinged.
1077 assert((surface
->aux_addr
.offset
& 0xfff) == 0);
1078 uint32_t *aux_addr
= state
+ isl_dev
->ss
.aux_addr_offset
;
1079 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.aux_addr_offset
,
1080 surface
->aux_addr
, *aux_addr
);
1083 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1087 blorp_emit_null_surface_state(struct blorp_batch
*batch
,
1088 const struct brw_blorp_surface_info
*surface
,
1091 struct GENX(RENDER_SURFACE_STATE
) ss
= {
1092 .SurfaceType
= SURFTYPE_NULL
,
1093 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
1094 .Width
= surface
->surf
.logical_level0_px
.width
- 1,
1095 .Height
= surface
->surf
.logical_level0_px
.height
- 1,
1096 .MIPCountLOD
= surface
->view
.base_level
,
1097 .MinimumArrayElement
= surface
->view
.base_array_layer
,
1098 .Depth
= surface
->view
.array_len
- 1,
1099 .RenderTargetViewExtent
= surface
->view
.array_len
- 1,
1100 .NumberofMultisamples
= ffs(surface
->surf
.samples
) - 1,
1103 .SurfaceArray
= surface
->surf
.dim
!= ISL_SURF_DIM_3D
,
1109 .TiledSurface
= true,
1113 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &ss
);
1115 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1119 blorp_emit_surface_states(struct blorp_batch
*batch
,
1120 const struct blorp_params
*params
)
1122 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1123 uint32_t bind_offset
, surface_offsets
[2];
1124 void *surface_maps
[2];
1126 if (params
->use_pre_baked_binding_table
) {
1127 bind_offset
= params
->pre_baked_binding_table_offset
;
1129 unsigned num_surfaces
= 1 + params
->src
.enabled
;
1130 blorp_alloc_binding_table(batch
, num_surfaces
,
1131 isl_dev
->ss
.size
, isl_dev
->ss
.align
,
1132 &bind_offset
, surface_offsets
, surface_maps
);
1134 if (params
->dst
.enabled
) {
1135 blorp_emit_surface_state(batch
, ¶ms
->dst
,
1136 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
],
1137 surface_offsets
[BLORP_RENDERBUFFER_BT_INDEX
],
1140 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1141 const struct brw_blorp_surface_info
*surface
=
1142 params
->depth
.enabled
? ¶ms
->depth
: ¶ms
->stencil
;
1143 blorp_emit_null_surface_state(batch
, surface
,
1144 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
]);
1147 if (params
->src
.enabled
) {
1148 blorp_emit_surface_state(batch
, ¶ms
->src
,
1149 surface_maps
[BLORP_TEXTURE_BT_INDEX
],
1150 surface_offsets
[BLORP_TEXTURE_BT_INDEX
], false);
1155 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), bt
);
1156 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_HS
), bt
);
1157 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_DS
), bt
);
1158 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_GS
), bt
);
1160 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS
), bt
) {
1161 bt
.PointertoPSBindingTable
= bind_offset
;
1164 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1165 bt
.PSBindingTableChange
= true;
1166 bt
.PointertoPSBindingTable
= bind_offset
;
1172 blorp_emit_sampler_state(struct blorp_batch
*batch
,
1173 const struct blorp_params
*params
)
1175 struct GENX(SAMPLER_STATE
) sampler
= {
1176 .MipModeFilter
= MIPFILTER_NONE
,
1177 .MagModeFilter
= MAPFILTER_LINEAR
,
1178 .MinModeFilter
= MAPFILTER_LINEAR
,
1181 .TCXAddressControlMode
= TCM_CLAMP
,
1182 .TCYAddressControlMode
= TCM_CLAMP
,
1183 .TCZAddressControlMode
= TCM_CLAMP
,
1184 .MaximumAnisotropy
= RATIO21
,
1185 .RAddressMinFilterRoundingEnable
= true,
1186 .RAddressMagFilterRoundingEnable
= true,
1187 .VAddressMinFilterRoundingEnable
= true,
1188 .VAddressMagFilterRoundingEnable
= true,
1189 .UAddressMinFilterRoundingEnable
= true,
1190 .UAddressMagFilterRoundingEnable
= true,
1191 .NonnormalizedCoordinateEnable
= true,
1195 void *state
= blorp_alloc_dynamic_state(batch
, AUB_TRACE_SAMPLER_STATE
,
1196 GENX(SAMPLER_STATE_length
) * 4,
1198 GENX(SAMPLER_STATE_pack
)(NULL
, state
, &sampler
);
1199 blorp_flush_range(batch
, state
, GENX(SAMPLER_STATE_length
) * 4);
1202 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS
), ssp
) {
1203 ssp
.PointertoPSSamplerState
= offset
;
1206 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS
), ssp
) {
1207 ssp
.VSSamplerStateChange
= true;
1208 ssp
.GSSamplerStateChange
= true;
1209 ssp
.PSSamplerStateChange
= true;
1210 ssp
.PointertoPSSamplerState
= offset
;
1216 blorp_emit_3dstate_multisample(struct blorp_batch
*batch
,
1217 const struct blorp_params
*params
)
1219 blorp_emit(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1220 ms
.NumberofMultisamples
= __builtin_ffs(params
->num_samples
) - 1;
1223 /* The PRM says that this bit is valid only for DX9:
1225 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
1226 * should not have any effect by setting or not setting this bit.
1228 ms
.PixelPositionOffsetEnable
= false;
1229 ms
.PixelLocation
= CENTER
;
1231 ms
.PixelLocation
= PIXLOC_CENTER
;
1233 switch (params
->num_samples
) {
1235 GEN_SAMPLE_POS_1X(ms
.Sample
);
1238 GEN_SAMPLE_POS_2X(ms
.Sample
);
1241 GEN_SAMPLE_POS_4X(ms
.Sample
);
1244 GEN_SAMPLE_POS_8X(ms
.Sample
);
1250 ms
.PixelLocation
= PIXLOC_CENTER
;
1251 GEN_SAMPLE_POS_4X(ms
.Sample
);
1257 /* Emits the Optimized HiZ sequence specified in the BDW+ PRMs. The
1258 * depth/stencil buffer extents are ignored to handle APIs which perform
1259 * clearing operations without such information.
1262 blorp_emit_gen8_hiz_op(struct blorp_batch
*batch
,
1263 const struct blorp_params
*params
)
1265 /* We should be performing an operation on a depth or stencil buffer.
1267 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1269 /* The stencil buffer should only be enabled if a fast clear operation is
1272 if (params
->stencil
.enabled
)
1273 assert(params
->hiz_op
== BLORP_HIZ_OP_DEPTH_CLEAR
);
1275 /* If we can't alter the depth stencil config and multiple layers are
1276 * involved, the HiZ op will fail. This is because the op requires that a
1277 * new config is emitted for each additional layer.
1279 if (batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
) {
1280 assert(params
->num_layers
<= 1);
1282 blorp_emit_depth_stencil_config(batch
, params
);
1285 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
) {
1286 switch (params
->hiz_op
) {
1287 case BLORP_HIZ_OP_DEPTH_CLEAR
:
1288 hzp
.StencilBufferClearEnable
= params
->stencil
.enabled
;
1289 hzp
.DepthBufferClearEnable
= params
->depth
.enabled
;
1290 hzp
.StencilClearValue
= params
->stencil_ref
;
1292 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
1293 hzp
.DepthBufferResolveEnable
= true;
1295 case BLORP_HIZ_OP_HIZ_RESOLVE
:
1296 hzp
.HierarchicalDepthBufferResolveEnable
= true;
1298 case BLORP_HIZ_OP_NONE
:
1299 unreachable("Invalid HIZ op");
1302 hzp
.NumberofMultisamples
= ffs(params
->num_samples
) - 1;
1303 hzp
.SampleMask
= 0xFFFF;
1305 /* Due to a hardware issue, this bit MBZ */
1306 assert(hzp
.ScissorRectangleEnable
== false);
1308 /* Contrary to the HW docs both fields are inclusive */
1309 hzp
.ClearRectangleXMin
= params
->x0
;
1310 hzp
.ClearRectangleYMin
= params
->y0
;
1312 /* Contrary to the HW docs both fields are exclusive */
1313 hzp
.ClearRectangleXMax
= params
->x1
;
1314 hzp
.ClearRectangleYMax
= params
->y1
;
1317 /* PIPE_CONTROL w/ all bits clear except for “Post-Sync Operation” must set
1318 * to “Write Immediate Data” enabled.
1320 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1321 pc
.PostSyncOperation
= WriteImmediateData
;
1324 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
);
1326 /* Perform depth clear specific flushing */
1327 if (params
->hiz_op
== BLORP_HIZ_OP_DEPTH_CLEAR
&& params
->depth
.enabled
) {
1328 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1329 pc
.DepthStallEnable
= true;
1330 pc
.DepthCacheFlushEnable
= true;
1336 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
1338 blorp_emit_viewport_state(struct blorp_batch
*batch
,
1339 const struct blorp_params
*params
)
1341 uint32_t cc_vp_offset
;
1343 void *state
= blorp_alloc_dynamic_state(batch
, AUB_TRACE_CC_VP_STATE
,
1344 GENX(CC_VIEWPORT_length
) * 4, 32,
1347 GENX(CC_VIEWPORT_pack
)(batch
, state
,
1348 &(struct GENX(CC_VIEWPORT
)) {
1349 .MinimumDepth
= 0.0,
1350 .MaximumDepth
= 1.0,
1352 blorp_flush_range(batch
, state
, GENX(CC_VIEWPORT_length
) * 4);
1355 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), vsp
) {
1356 vsp
.CCViewportPointer
= cc_vp_offset
;
1359 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vsp
) {
1360 vsp
.CCViewportStateChange
= true;
1361 vsp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
1368 * \brief Execute a blit or render pass operation.
1370 * To execute the operation, this function manually constructs and emits a
1371 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1372 * constructing and after emitting the batch.
1374 * This function alters no GL state.
1377 blorp_exec(struct blorp_batch
*batch
, const struct blorp_params
*params
)
1379 uint32_t blend_state_offset
= 0;
1380 uint32_t color_calc_state_offset
= 0;
1381 uint32_t depth_stencil_state_offset
;
1384 if (params
->hiz_op
!= BLORP_HIZ_OP_NONE
) {
1385 blorp_emit_gen8_hiz_op(batch
, params
);
1390 blorp_emit_vertex_buffers(batch
, params
);
1391 blorp_emit_vertex_elements(batch
, params
);
1393 emit_urb_config(batch
, params
);
1395 if (params
->wm_prog_data
) {
1396 blend_state_offset
= blorp_emit_blend_state(batch
, params
);
1398 color_calc_state_offset
= blorp_emit_color_calc_state(batch
, params
);
1399 depth_stencil_state_offset
= blorp_emit_depth_stencil_state(batch
, params
);
1402 /* 3DSTATE_CC_STATE_POINTERS
1404 * The pointer offsets are relative to
1405 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
1407 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
1409 * The dynamic state emit helpers emit their own STATE_POINTERS packets on
1410 * gen7+. However, on gen6 and earlier, they're all lumpped together in
1411 * one CC_STATE_POINTERS packet so we have to emit that here.
1413 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), cc
) {
1414 cc
.BLEND_STATEChange
= true;
1415 cc
.COLOR_CALC_STATEChange
= true;
1416 cc
.DEPTH_STENCIL_STATEChange
= true;
1417 cc
.PointertoBLEND_STATE
= blend_state_offset
;
1418 cc
.PointertoCOLOR_CALC_STATE
= color_calc_state_offset
;
1419 cc
.PointertoDEPTH_STENCIL_STATE
= depth_stencil_state_offset
;
1422 (void)blend_state_offset
;
1423 (void)color_calc_state_offset
;
1424 (void)depth_stencil_state_offset
;
1427 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_VS
), vs
);
1429 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_HS
), hs
);
1430 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_DS
), DS
);
1432 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_GS
), gs
);
1433 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_PS
), ps
);
1435 blorp_emit_surface_states(batch
, params
);
1437 if (params
->src
.enabled
)
1438 blorp_emit_sampler_state(batch
, params
);
1440 blorp_emit_3dstate_multisample(batch
, params
);
1442 blorp_emit(batch
, GENX(3DSTATE_SAMPLE_MASK
), mask
) {
1443 mask
.SampleMask
= (1 << params
->num_samples
) - 1;
1446 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1447 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1449 * [DevSNB] A pipeline flush must be programmed prior to a
1450 * 3DSTATE_VS command that causes the VS Function Enable to
1451 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
1452 * command with CS stall bit set and a post sync operation.
1454 * We've already done one at the start of the BLORP operation.
1456 blorp_emit_vs_config(batch
, params
);
1458 blorp_emit(batch
, GENX(3DSTATE_HS
), hs
);
1459 blorp_emit(batch
, GENX(3DSTATE_TE
), te
);
1460 blorp_emit(batch
, GENX(3DSTATE_DS
), DS
);
1461 blorp_emit(batch
, GENX(3DSTATE_STREAMOUT
), so
);
1463 blorp_emit(batch
, GENX(3DSTATE_GS
), gs
);
1465 blorp_emit(batch
, GENX(3DSTATE_CLIP
), clip
) {
1466 clip
.PerspectiveDivideDisable
= true;
1469 blorp_emit_sf_config(batch
, params
);
1470 blorp_emit_ps_config(batch
, params
);
1472 blorp_emit_viewport_state(batch
, params
);
1474 if (!(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
))
1475 blorp_emit_depth_stencil_config(batch
, params
);
1477 blorp_emit(batch
, GENX(3DPRIMITIVE
), prim
) {
1478 prim
.VertexAccessType
= SEQUENTIAL
;
1479 prim
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
1480 prim
.VertexCountPerInstance
= 3;
1481 prim
.InstanceCount
= params
->num_layers
;
1485 #endif /* BLORP_GENX_EXEC_H */