2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BLORP_GENX_EXEC_H
25 #define BLORP_GENX_EXEC_H
27 #include "blorp_priv.h"
28 #include "dev/gen_device_info.h"
29 #include "common/gen_sample_positions.h"
30 #include "common/gen_l3_config.h"
31 #include "genxml/gen_macros.h"
34 * This file provides the blorp pipeline setup and execution functionality.
35 * It defines the following function:
38 * blorp_exec(struct blorp_context *blorp, void *batch_data,
39 * const struct blorp_params *params);
41 * It is the job of whoever includes this header to wrap this in something
42 * to get an externally visible symbol.
44 * In order for the blorp_exec function to work, the driver must provide
45 * implementations of the following static helper functions.
49 blorp_emit_dwords(struct blorp_batch
*batch
, unsigned n
);
52 blorp_emit_reloc(struct blorp_batch
*batch
,
53 void *location
, struct blorp_address address
, uint32_t delta
);
56 blorp_alloc_dynamic_state(struct blorp_batch
*batch
,
61 blorp_alloc_vertex_buffer(struct blorp_batch
*batch
, uint32_t size
,
62 struct blorp_address
*addr
);
64 blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch
*batch
,
65 const struct blorp_address
*addrs
,
69 UNUSED
static struct blorp_address
70 blorp_get_workaround_page(struct blorp_batch
*batch
);
73 blorp_alloc_binding_table(struct blorp_batch
*batch
, unsigned num_entries
,
74 unsigned state_size
, unsigned state_alignment
,
75 uint32_t *bt_offset
, uint32_t *surface_offsets
,
79 blorp_flush_range(struct blorp_batch
*batch
, void *start
, size_t size
);
82 blorp_surface_reloc(struct blorp_batch
*batch
, uint32_t ss_offset
,
83 struct blorp_address address
, uint32_t delta
);
86 blorp_get_surface_address(struct blorp_batch
*batch
,
87 struct blorp_address address
);
89 #if GEN_GEN >= 7 && GEN_GEN < 10
90 static struct blorp_address
91 blorp_get_surface_base_address(struct blorp_batch
*batch
);
95 static const struct gen_l3_config
*
96 blorp_get_l3_config(struct blorp_batch
*batch
);
99 blorp_emit_urb_config(struct blorp_batch
*batch
,
100 unsigned vs_entry_size
, unsigned sf_entry_size
);
104 blorp_emit_pipeline(struct blorp_batch
*batch
,
105 const struct blorp_params
*params
);
107 /***** BEGIN blorp_exec implementation ******/
110 _blorp_combine_address(struct blorp_batch
*batch
, void *location
,
111 struct blorp_address address
, uint32_t delta
)
113 if (address
.buffer
== NULL
) {
114 return address
.offset
+ delta
;
116 return blorp_emit_reloc(batch
, location
, address
, delta
);
120 #define __gen_address_type struct blorp_address
121 #define __gen_user_data struct blorp_batch
122 #define __gen_combine_address _blorp_combine_address
124 #include "genxml/genX_pack.h"
126 #define _blorp_cmd_length(cmd) cmd ## _length
127 #define _blorp_cmd_length_bias(cmd) cmd ## _length_bias
128 #define _blorp_cmd_header(cmd) cmd ## _header
129 #define _blorp_cmd_pack(cmd) cmd ## _pack
131 #define blorp_emit(batch, cmd, name) \
132 for (struct cmd name = { _blorp_cmd_header(cmd) }, \
133 *_dst = blorp_emit_dwords(batch, _blorp_cmd_length(cmd)); \
134 __builtin_expect(_dst != NULL, 1); \
135 _blorp_cmd_pack(cmd)(batch, (void *)_dst, &name), \
138 #define blorp_emitn(batch, cmd, n, ...) ({ \
139 uint32_t *_dw = blorp_emit_dwords(batch, n); \
141 struct cmd template = { \
142 _blorp_cmd_header(cmd), \
143 .DWordLength = n - _blorp_cmd_length_bias(cmd), \
146 _blorp_cmd_pack(cmd)(batch, _dw, &template); \
148 _dw ? _dw + 1 : NULL; /* Array starts at dw[1] */ \
151 #define STRUCT_ZERO(S) ({ struct S t; memset(&t, 0, sizeof(t)); t; })
153 #define blorp_emit_dynamic(batch, state, name, align, offset) \
154 for (struct state name = STRUCT_ZERO(state), \
155 *_dst = blorp_alloc_dynamic_state(batch, \
156 _blorp_cmd_length(state) * 4, \
158 __builtin_expect(_dst != NULL, 1); \
159 _blorp_cmd_pack(state)(batch, (void *)_dst, &name), \
160 blorp_flush_range(batch, _dst, _blorp_cmd_length(state) * 4), \
169 * Assign the entire URB to the VS. Even though the VS disabled, URB space
170 * is still needed because the clipper loads the VUE's from the URB. From
171 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
172 * Dword 1.15:0 "VS Number of URB Entries":
173 * This field is always used (even if VS Function Enable is DISABLED).
175 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
176 * safely ignore it because this batch contains only one draw call.
177 * Because of URB corruption caused by allocating a previous GS unit
178 * URB entry to the VS unit, software is required to send a “GS NULL
179 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
180 * plus a dummy DRAW call before any case where VS will be taking over
183 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
184 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
186 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
187 * programmed in order for the programming of this state to be
191 emit_urb_config(struct blorp_batch
*batch
,
192 const struct blorp_params
*params
)
194 /* Once vertex fetcher has written full VUE entries with complete
195 * header the space requirement is as follows per vertex (in bytes):
197 * Header Position Program constants
198 * +--------+------------+-------------------+
199 * | 16 | 16 | n x 16 |
200 * +--------+------------+-------------------+
202 * where 'n' stands for number of varying inputs expressed as vec4s.
204 const unsigned num_varyings
=
205 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
206 const unsigned total_needed
= 16 + 16 + num_varyings
* 16;
208 /* The URB size is expressed in units of 64 bytes (512 bits) */
209 const unsigned vs_entry_size
= DIV_ROUND_UP(total_needed
, 64);
211 const unsigned sf_entry_size
=
212 params
->sf_prog_data
? params
->sf_prog_data
->urb_entry_size
: 0;
215 assert(sf_entry_size
== 0);
216 const unsigned entry_size
[4] = { vs_entry_size
, 1, 1, 1 };
218 unsigned entries
[4], start
[4];
219 gen_get_urb_config(batch
->blorp
->compiler
->devinfo
,
220 blorp_get_l3_config(batch
),
221 false, false, entry_size
, entries
, start
);
223 #if GEN_GEN == 7 && !GEN_IS_HASWELL
224 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
226 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
227 * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
228 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
229 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
230 * needs to be sent before any combination of VS associated 3DSTATE."
232 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
233 pc
.DepthStallEnable
= true;
234 pc
.PostSyncOperation
= WriteImmediateData
;
235 pc
.Address
= blorp_get_workaround_page(batch
);
239 for (int i
= 0; i
<= MESA_SHADER_GEOMETRY
; i
++) {
240 blorp_emit(batch
, GENX(3DSTATE_URB_VS
), urb
) {
241 urb
._3DCommandSubOpcode
+= i
;
242 urb
.VSURBStartingAddress
= start
[i
];
243 urb
.VSURBEntryAllocationSize
= entry_size
[i
] - 1;
244 urb
.VSNumberofURBEntries
= entries
[i
];
247 #else /* GEN_GEN < 7 */
248 blorp_emit_urb_config(batch
, vs_entry_size
, sf_entry_size
);
254 blorp_emit_memcpy(struct blorp_batch
*batch
,
255 struct blorp_address dst
,
256 struct blorp_address src
,
261 blorp_emit_vertex_data(struct blorp_batch
*batch
,
262 const struct blorp_params
*params
,
263 struct blorp_address
*addr
,
266 const float vertices
[] = {
267 /* v0 */ (float)params
->x1
, (float)params
->y1
, params
->z
,
268 /* v1 */ (float)params
->x0
, (float)params
->y1
, params
->z
,
269 /* v2 */ (float)params
->x0
, (float)params
->y0
, params
->z
,
272 void *data
= blorp_alloc_vertex_buffer(batch
, sizeof(vertices
), addr
);
273 memcpy(data
, vertices
, sizeof(vertices
));
274 *size
= sizeof(vertices
);
275 blorp_flush_range(batch
, data
, *size
);
279 blorp_emit_input_varying_data(struct blorp_batch
*batch
,
280 const struct blorp_params
*params
,
281 struct blorp_address
*addr
,
284 const unsigned vec4_size_in_bytes
= 4 * sizeof(float);
285 const unsigned max_num_varyings
=
286 DIV_ROUND_UP(sizeof(params
->wm_inputs
), vec4_size_in_bytes
);
287 const unsigned num_varyings
=
288 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
290 *size
= 16 + num_varyings
* vec4_size_in_bytes
;
292 const uint32_t *const inputs_src
= (const uint32_t *)¶ms
->wm_inputs
;
293 void *data
= blorp_alloc_vertex_buffer(batch
, *size
, addr
);
294 uint32_t *inputs
= data
;
296 /* Copy in the VS inputs */
297 assert(sizeof(params
->vs_inputs
) == 16);
298 memcpy(inputs
, ¶ms
->vs_inputs
, sizeof(params
->vs_inputs
));
301 if (params
->wm_prog_data
) {
302 /* Walk over the attribute slots, determine if the attribute is used by
303 * the program and when necessary copy the values from the input storage
304 * to the vertex data buffer.
306 for (unsigned i
= 0; i
< max_num_varyings
; i
++) {
307 const gl_varying_slot attr
= VARYING_SLOT_VAR0
+ i
;
309 const int input_index
= params
->wm_prog_data
->urb_setup
[attr
];
313 memcpy(inputs
, inputs_src
+ i
* 4, vec4_size_in_bytes
);
319 blorp_flush_range(batch
, data
, *size
);
321 if (params
->dst_clear_color_as_input
) {
323 /* In this case, the clear color isn't known statically and instead
324 * comes in through an indirect which we have to copy into the vertex
325 * buffer before we execute the 3DPRIMITIVE. We already copied the
326 * value of params->wm_inputs.clear_color into the vertex buffer in the
327 * loop above. Now we emit code to stomp it from the GPU with the
328 * actual clear color value.
330 assert(num_varyings
== 1);
332 /* The clear color is the first thing after the header */
333 struct blorp_address clear_color_input_addr
= *addr
;
334 clear_color_input_addr
.offset
+= 16;
336 const unsigned clear_color_size
=
337 GEN_GEN
< 10 ? batch
->blorp
->isl_dev
->ss
.clear_value_size
: 4 * 4;
338 blorp_emit_memcpy(batch
, clear_color_input_addr
,
339 params
->dst
.clear_color_addr
,
342 unreachable("MCS partial resolve is not a thing on SNB and earlier");
348 blorp_fill_vertex_buffer_state(struct blorp_batch
*batch
,
349 struct GENX(VERTEX_BUFFER_STATE
) *vb
,
351 struct blorp_address addr
, uint32_t size
,
354 vb
[idx
].VertexBufferIndex
= idx
;
355 vb
[idx
].BufferStartingAddress
= addr
;
356 vb
[idx
].BufferPitch
= stride
;
359 vb
[idx
].MOCS
= addr
.mocs
;
363 vb
[idx
].AddressModifyEnable
= true;
367 vb
[idx
].BufferSize
= size
;
369 vb
[idx
].BufferAccessType
= stride
> 0 ? VERTEXDATA
: INSTANCEDATA
;
370 vb
[idx
].EndAddress
= vb
[idx
].BufferStartingAddress
;
371 vb
[idx
].EndAddress
.offset
+= size
- 1;
373 vb
[idx
].BufferAccessType
= stride
> 0 ? VERTEXDATA
: INSTANCEDATA
;
374 vb
[idx
].MaxIndex
= stride
> 0 ? size
/ stride
: 0;
379 blorp_emit_vertex_buffers(struct blorp_batch
*batch
,
380 const struct blorp_params
*params
)
382 struct GENX(VERTEX_BUFFER_STATE
) vb
[3];
383 uint32_t num_vbs
= 2;
384 memset(vb
, 0, sizeof(vb
));
386 struct blorp_address addrs
[2] = {};
388 blorp_emit_vertex_data(batch
, params
, &addrs
[0], &sizes
[0]);
389 blorp_fill_vertex_buffer_state(batch
, vb
, 0, addrs
[0], sizes
[0],
392 blorp_emit_input_varying_data(batch
, params
, &addrs
[1], &sizes
[1]);
393 blorp_fill_vertex_buffer_state(batch
, vb
, 1, addrs
[1], sizes
[1], 0);
395 blorp_vf_invalidate_for_vb_48b_transitions(batch
, addrs
, sizes
, num_vbs
);
397 const unsigned num_dwords
= 1 + num_vbs
* GENX(VERTEX_BUFFER_STATE_length
);
398 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), num_dwords
);
402 for (unsigned i
= 0; i
< num_vbs
; i
++) {
403 GENX(VERTEX_BUFFER_STATE_pack
)(batch
, dw
, &vb
[i
]);
404 dw
+= GENX(VERTEX_BUFFER_STATE_length
);
409 blorp_emit_vertex_elements(struct blorp_batch
*batch
,
410 const struct blorp_params
*params
)
412 const unsigned num_varyings
=
413 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
414 bool need_ndc
= batch
->blorp
->compiler
->devinfo
->gen
<= 5;
415 const unsigned num_elements
= 2 + need_ndc
+ num_varyings
;
417 struct GENX(VERTEX_ELEMENT_STATE
) ve
[num_elements
];
418 memset(ve
, 0, num_elements
* sizeof(*ve
));
420 /* Setup VBO for the rectangle primitive..
422 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
423 * vertices. The vertices reside in screen space with DirectX
424 * coordinates (that is, (0, 0) is the upper left corner).
431 * Since the VS is disabled, the clipper loads each VUE directly from
432 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
433 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
434 * dw0: Reserved, MBZ.
435 * dw1: Render Target Array Index. Below vertex fetcher gets programmed
436 * to assign this with primitive instance identifier which will be
437 * used for layered clears. All other renders have only one instance
438 * and therefore the value will be effectively zero.
439 * dw2: Viewport Index. The HiZ op disables viewport mapping and
440 * scissoring, so set the dword to 0.
441 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive,
442 * so set the dword to 0.
443 * dw4: Vertex Position X.
444 * dw5: Vertex Position Y.
445 * dw6: Vertex Position Z.
446 * dw7: Vertex Position W.
448 * dw8: Flat vertex input 0
449 * dw9: Flat vertex input 1
451 * dwn: Flat vertex input n - 8
453 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
454 * "Vertex URB Entry (VUE) Formats".
456 * Only vertex position X and Y are going to be variable, Z is fixed to
457 * zero and W to one. Header words dw0,2,3 are zero. There is no need to
458 * include the fixed values in the vertex buffer. Vertex fetcher can be
459 * instructed to fill vertex elements with constant values of one and zero
460 * instead of reading them from the buffer.
461 * Flat inputs are program constants that are not interpolated. Moreover
462 * their values will be the same between vertices.
464 * See the vertex element setup below.
468 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
469 .VertexBufferIndex
= 1,
471 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
472 .SourceElementOffset
= 0,
473 .Component0Control
= VFCOMP_STORE_SRC
,
475 /* From Gen8 onwards hardware is no more instructed to overwrite
476 * components using an element specifier. Instead one has separate
477 * 3DSTATE_VF_SGVS (System Generated Value Setup) state packet for it.
480 .Component1Control
= VFCOMP_STORE_0
,
482 .Component1Control
= VFCOMP_STORE_IID
,
484 .Component1Control
= VFCOMP_STORE_0
,
486 .Component2Control
= VFCOMP_STORE_0
,
487 .Component3Control
= VFCOMP_STORE_0
,
489 .DestinationElementOffset
= slot
* 4,
495 /* On Iron Lake and earlier, a native device coordinates version of the
496 * position goes right after the normal VUE header and before position.
497 * Since w == 1 for all of our coordinates, this is just a copy of the
500 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
501 .VertexBufferIndex
= 0,
503 .SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
,
504 .SourceElementOffset
= 0,
505 .Component0Control
= VFCOMP_STORE_SRC
,
506 .Component1Control
= VFCOMP_STORE_SRC
,
507 .Component2Control
= VFCOMP_STORE_SRC
,
508 .Component3Control
= VFCOMP_STORE_1_FP
,
509 .DestinationElementOffset
= slot
* 4,
514 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
515 .VertexBufferIndex
= 0,
517 .SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
,
518 .SourceElementOffset
= 0,
519 .Component0Control
= VFCOMP_STORE_SRC
,
520 .Component1Control
= VFCOMP_STORE_SRC
,
521 .Component2Control
= VFCOMP_STORE_SRC
,
522 .Component3Control
= VFCOMP_STORE_1_FP
,
524 .DestinationElementOffset
= slot
* 4,
529 for (unsigned i
= 0; i
< num_varyings
; ++i
) {
530 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
531 .VertexBufferIndex
= 1,
533 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
534 .SourceElementOffset
= 16 + i
* 4 * sizeof(float),
535 .Component0Control
= VFCOMP_STORE_SRC
,
536 .Component1Control
= VFCOMP_STORE_SRC
,
537 .Component2Control
= VFCOMP_STORE_SRC
,
538 .Component3Control
= VFCOMP_STORE_SRC
,
540 .DestinationElementOffset
= slot
* 4,
546 const unsigned num_dwords
=
547 1 + GENX(VERTEX_ELEMENT_STATE_length
) * num_elements
;
548 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_ELEMENTS
), num_dwords
);
552 for (unsigned i
= 0; i
< num_elements
; i
++) {
553 GENX(VERTEX_ELEMENT_STATE_pack
)(batch
, dw
, &ve
[i
]);
554 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
557 blorp_emit(batch
, GENX(3DSTATE_VF_STATISTICS
), vf
) {
558 vf
.StatisticsEnable
= false;
562 /* Overwrite Render Target Array Index (2nd dword) in the VUE header with
563 * primitive instance identifier. This is used for layered clears.
565 blorp_emit(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
566 sgvs
.InstanceIDEnable
= true;
567 sgvs
.InstanceIDComponentNumber
= COMP_1
;
568 sgvs
.InstanceIDElementOffset
= 0;
571 for (unsigned i
= 0; i
< num_elements
; i
++) {
572 blorp_emit(batch
, GENX(3DSTATE_VF_INSTANCING
), vf
) {
573 vf
.VertexElementIndex
= i
;
574 vf
.InstancingEnable
= false;
578 blorp_emit(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
579 topo
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
584 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
586 blorp_emit_cc_viewport(struct blorp_batch
*batch
)
588 uint32_t cc_vp_offset
;
589 blorp_emit_dynamic(batch
, GENX(CC_VIEWPORT
), vp
, 32, &cc_vp_offset
) {
590 vp
.MinimumDepth
= 0.0;
591 vp
.MaximumDepth
= 1.0;
595 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), vsp
) {
596 vsp
.CCViewportPointer
= cc_vp_offset
;
599 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vsp
) {
600 vsp
.CCViewportStateChange
= true;
601 vsp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
609 blorp_emit_sampler_state(struct blorp_batch
*batch
)
612 blorp_emit_dynamic(batch
, GENX(SAMPLER_STATE
), sampler
, 32, &offset
) {
613 sampler
.MipModeFilter
= MIPFILTER_NONE
;
614 sampler
.MagModeFilter
= MAPFILTER_LINEAR
;
615 sampler
.MinModeFilter
= MAPFILTER_LINEAR
;
618 sampler
.TCXAddressControlMode
= TCM_CLAMP
;
619 sampler
.TCYAddressControlMode
= TCM_CLAMP
;
620 sampler
.TCZAddressControlMode
= TCM_CLAMP
;
621 sampler
.MaximumAnisotropy
= RATIO21
;
622 sampler
.RAddressMinFilterRoundingEnable
= true;
623 sampler
.RAddressMagFilterRoundingEnable
= true;
624 sampler
.VAddressMinFilterRoundingEnable
= true;
625 sampler
.VAddressMagFilterRoundingEnable
= true;
626 sampler
.UAddressMinFilterRoundingEnable
= true;
627 sampler
.UAddressMagFilterRoundingEnable
= true;
629 sampler
.NonnormalizedCoordinateEnable
= true;
634 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS
), ssp
) {
635 ssp
.PointertoPSSamplerState
= offset
;
638 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS
), ssp
) {
639 ssp
.VSSamplerStateChange
= true;
640 ssp
.GSSamplerStateChange
= true;
641 ssp
.PSSamplerStateChange
= true;
642 ssp
.PointertoPSSamplerState
= offset
;
649 /* What follows is the code for setting up a "pipeline" on Sandy Bridge and
650 * later hardware. This file will be included by i965 for gen4-5 as well, so
651 * this code is guarded by GEN_GEN >= 6.
656 blorp_emit_vs_config(struct blorp_batch
*batch
,
657 const struct blorp_params
*params
)
659 struct brw_vs_prog_data
*vs_prog_data
= params
->vs_prog_data
;
660 assert(!vs_prog_data
|| GEN_GEN
< 11 ||
661 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
);
663 blorp_emit(batch
, GENX(3DSTATE_VS
), vs
) {
667 vs
.KernelStartPointer
= params
->vs_prog_kernel
;
669 vs
.DispatchGRFStartRegisterForURBData
=
670 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
671 vs
.VertexURBEntryReadLength
=
672 vs_prog_data
->base
.urb_read_length
;
673 vs
.VertexURBEntryReadOffset
= 0;
675 vs
.MaximumNumberofThreads
=
676 batch
->blorp
->isl_dev
->info
->max_vs_threads
- 1;
679 vs
.SIMD8DispatchEnable
=
680 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
687 blorp_emit_sf_config(struct blorp_batch
*batch
,
688 const struct blorp_params
*params
)
690 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
694 * Disable ViewportTransformEnable (dw2.1)
696 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
697 * Primitives Overview":
698 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
699 * use of screen- space coordinates).
701 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
702 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
704 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
705 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
706 * SOLID: Any triangle or rectangle object found to be front-facing
707 * is rendered as a solid object. This setting is required when
708 * (rendering rectangle (RECTLIST) objects.
713 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
715 sf
.DerefBlockSize
= PerPolyDerefMode
;
719 blorp_emit(batch
, GENX(3DSTATE_RASTER
), raster
) {
720 raster
.CullMode
= CULLMODE_NONE
;
723 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
724 sbe
.VertexURBEntryReadOffset
= 1;
726 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
727 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
728 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
730 sbe
.NumberofSFOutputAttributes
= 0;
731 sbe
.VertexURBEntryReadLength
= 1;
733 sbe
.ForceVertexURBEntryReadLength
= true;
734 sbe
.ForceVertexURBEntryReadOffset
= true;
737 for (unsigned i
= 0; i
< 32; i
++)
738 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
744 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
745 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
746 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
748 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
749 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
752 sf
.DepthBufferSurfaceFormat
= params
->depth_format
;
756 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
757 sbe
.VertexURBEntryReadOffset
= 1;
759 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
760 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
761 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
763 sbe
.NumberofSFOutputAttributes
= 0;
764 sbe
.VertexURBEntryReadLength
= 1;
768 #else /* GEN_GEN <= 6 */
770 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
771 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
772 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
774 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
775 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
777 sf
.VertexURBEntryReadOffset
= 1;
779 sf
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
780 sf
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
781 sf
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
783 sf
.NumberofSFOutputAttributes
= 0;
784 sf
.VertexURBEntryReadLength
= 1;
792 blorp_emit_ps_config(struct blorp_batch
*batch
,
793 const struct blorp_params
*params
)
795 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
797 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
798 * nonzero to prevent the GPU from hanging. While the documentation doesn't
799 * mention this explicitly, it notes that the valid range for the field is
800 * [1,39] = [2,40] threads, which excludes zero.
802 * To be safe (and to minimize extraneous code) we go ahead and fully
803 * configure the WM state whether or not there is a WM program.
808 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
810 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
811 if (params
->src
.enabled
) {
812 ps
.SamplerCount
= 1; /* Up to 4 samplers */
813 ps
.BindingTableEntryCount
= 2;
815 ps
.BindingTableEntryCount
= 1;
818 /* SAMPLER_STATE prefetching is broken on Gen11 - WA_1606682166 */
823 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
824 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
825 ps
._32PixelDispatchEnable
= prog_data
->dispatch_32
;
827 /* From the Sky Lake PRM 3DSTATE_PS::32 Pixel Dispatch Enable:
829 * "When NUM_MULTISAMPLES = 16 or FORCE_SAMPLE_COUNT = 16, SIMD32
830 * Dispatch must not be enabled for PER_PIXEL dispatch mode."
832 * Since 16x MSAA is first introduced on SKL, we don't need to apply
833 * the workaround on any older hardware.
835 if (GEN_GEN
>= 9 && !prog_data
->persample_dispatch
&&
836 params
->num_samples
== 16) {
837 assert(ps
._8PixelDispatchEnable
|| ps
._16PixelDispatchEnable
);
838 ps
._32PixelDispatchEnable
= false;
841 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
842 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 0);
843 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
844 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 1);
845 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
846 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 2);
848 ps
.KernelStartPointer0
= params
->wm_prog_kernel
+
849 brw_wm_prog_data_prog_offset(prog_data
, ps
, 0);
850 ps
.KernelStartPointer1
= params
->wm_prog_kernel
+
851 brw_wm_prog_data_prog_offset(prog_data
, ps
, 1);
852 ps
.KernelStartPointer2
= params
->wm_prog_kernel
+
853 brw_wm_prog_data_prog_offset(prog_data
, ps
, 2);
856 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64
857 * for pre Gen11 and 128 for gen11+; On gen11+ If a programmed value is
858 * k, it implies 2(k+1) threads. It implicitly scales for different GT
859 * levels (which have some # of PSDs).
861 * In Gen8 the format is U8-2 whereas in Gen9+ it is U9-1.
864 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
866 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
868 switch (params
->fast_clear_op
) {
869 case ISL_AUX_OP_NONE
:
872 case ISL_AUX_OP_AMBIGUATE
:
873 ps
.RenderTargetFastClearEnable
= true;
874 ps
.RenderTargetResolveType
= FAST_CLEAR_0
;
878 case ISL_AUX_OP_PARTIAL_RESOLVE
:
879 ps
.RenderTargetResolveType
= RESOLVE_PARTIAL
;
881 case ISL_AUX_OP_FULL_RESOLVE
:
882 ps
.RenderTargetResolveType
= RESOLVE_FULL
;
885 case ISL_AUX_OP_FULL_RESOLVE
:
886 ps
.RenderTargetResolveEnable
= true;
889 case ISL_AUX_OP_FAST_CLEAR
:
890 ps
.RenderTargetFastClearEnable
= true;
893 unreachable("Invalid fast clear op");
897 blorp_emit(batch
, GENX(3DSTATE_PS_EXTRA
), psx
) {
899 psx
.PixelShaderValid
= true;
900 psx
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
901 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
904 if (params
->src
.enabled
)
905 psx
.PixelShaderKillsPixel
= true;
910 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
911 switch (params
->hiz_op
) {
912 case ISL_AUX_OP_FAST_CLEAR
:
913 wm
.DepthBufferClear
= true;
915 case ISL_AUX_OP_FULL_RESOLVE
:
916 wm
.DepthBufferResolveEnable
= true;
918 case ISL_AUX_OP_AMBIGUATE
:
919 wm
.HierarchicalDepthBufferResolveEnable
= true;
921 case ISL_AUX_OP_NONE
:
924 unreachable("not reached");
928 wm
.ThreadDispatchEnable
= true;
930 if (params
->src
.enabled
)
931 wm
.PixelShaderKillsPixel
= true;
933 if (params
->num_samples
> 1) {
934 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
935 wm
.MultisampleDispatchMode
=
936 (prog_data
&& prog_data
->persample_dispatch
) ?
937 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
939 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
940 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
944 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
945 ps
.MaximumNumberofThreads
=
946 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
953 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
954 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
955 ps
._32PixelDispatchEnable
= prog_data
->dispatch_32
;
957 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
958 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 0);
959 ps
.DispatchGRFStartRegisterForConstantSetupData1
=
960 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 1);
961 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
962 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, ps
, 2);
964 ps
.KernelStartPointer0
= params
->wm_prog_kernel
+
965 brw_wm_prog_data_prog_offset(prog_data
, ps
, 0);
966 ps
.KernelStartPointer1
= params
->wm_prog_kernel
+
967 brw_wm_prog_data_prog_offset(prog_data
, ps
, 1);
968 ps
.KernelStartPointer2
= params
->wm_prog_kernel
+
969 brw_wm_prog_data_prog_offset(prog_data
, ps
, 2);
971 ps
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
973 /* Gen7 hardware gets angry if we don't enable at least one dispatch
974 * mode, so just enable 16-pixel dispatch if we don't have a program.
976 ps
._16PixelDispatchEnable
= true;
979 if (params
->src
.enabled
)
980 ps
.SamplerCount
= 1; /* Up to 4 samplers */
982 switch (params
->fast_clear_op
) {
983 case ISL_AUX_OP_NONE
:
985 case ISL_AUX_OP_FULL_RESOLVE
:
986 ps
.RenderTargetResolveEnable
= true;
988 case ISL_AUX_OP_FAST_CLEAR
:
989 ps
.RenderTargetFastClearEnable
= true;
992 unreachable("Invalid fast clear op");
996 #else /* GEN_GEN <= 6 */
998 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
999 wm
.MaximumNumberofThreads
=
1000 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
1002 switch (params
->hiz_op
) {
1003 case ISL_AUX_OP_FAST_CLEAR
:
1004 wm
.DepthBufferClear
= true;
1006 case ISL_AUX_OP_FULL_RESOLVE
:
1007 wm
.DepthBufferResolveEnable
= true;
1009 case ISL_AUX_OP_AMBIGUATE
:
1010 wm
.HierarchicalDepthBufferResolveEnable
= true;
1012 case ISL_AUX_OP_NONE
:
1015 unreachable("not reached");
1019 wm
.ThreadDispatchEnable
= true;
1021 wm
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
1022 wm
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
1023 wm
._32PixelDispatchEnable
= prog_data
->dispatch_32
;
1025 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
1026 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, wm
, 0);
1027 wm
.DispatchGRFStartRegisterForConstantSetupData1
=
1028 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, wm
, 1);
1029 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
1030 brw_wm_prog_data_dispatch_grf_start_reg(prog_data
, wm
, 2);
1032 wm
.KernelStartPointer0
= params
->wm_prog_kernel
+
1033 brw_wm_prog_data_prog_offset(prog_data
, wm
, 0);
1034 wm
.KernelStartPointer1
= params
->wm_prog_kernel
+
1035 brw_wm_prog_data_prog_offset(prog_data
, wm
, 1);
1036 wm
.KernelStartPointer2
= params
->wm_prog_kernel
+
1037 brw_wm_prog_data_prog_offset(prog_data
, wm
, 2);
1039 wm
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
1042 if (params
->src
.enabled
) {
1043 wm
.SamplerCount
= 1; /* Up to 4 samplers */
1044 wm
.PixelShaderKillsPixel
= true; /* TODO: temporarily smash on */
1047 if (params
->num_samples
> 1) {
1048 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
1049 wm
.MultisampleDispatchMode
=
1050 (prog_data
&& prog_data
->persample_dispatch
) ?
1051 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
1053 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
1054 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
1058 #endif /* GEN_GEN */
1062 blorp_emit_blend_state(struct blorp_batch
*batch
,
1063 const struct blorp_params
*params
)
1065 struct GENX(BLEND_STATE
) blend
;
1066 memset(&blend
, 0, sizeof(blend
));
1069 int size
= GENX(BLEND_STATE_length
) * 4;
1070 size
+= GENX(BLEND_STATE_ENTRY_length
) * 4 * params
->num_draw_buffers
;
1071 uint32_t *state
= blorp_alloc_dynamic_state(batch
, size
, 64, &offset
);
1072 uint32_t *pos
= state
;
1074 GENX(BLEND_STATE_pack
)(NULL
, pos
, &blend
);
1075 pos
+= GENX(BLEND_STATE_length
);
1077 for (unsigned i
= 0; i
< params
->num_draw_buffers
; ++i
) {
1078 struct GENX(BLEND_STATE_ENTRY
) entry
= {
1079 .PreBlendColorClampEnable
= true,
1080 .PostBlendColorClampEnable
= true,
1081 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
1083 .WriteDisableRed
= params
->color_write_disable
[0],
1084 .WriteDisableGreen
= params
->color_write_disable
[1],
1085 .WriteDisableBlue
= params
->color_write_disable
[2],
1086 .WriteDisableAlpha
= params
->color_write_disable
[3],
1088 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, pos
, &entry
);
1089 pos
+= GENX(BLEND_STATE_ENTRY_length
);
1092 blorp_flush_range(batch
, state
, size
);
1095 blorp_emit(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), sp
) {
1096 sp
.BlendStatePointer
= offset
;
1098 sp
.BlendStatePointerValid
= true;
1104 blorp_emit(batch
, GENX(3DSTATE_PS_BLEND
), ps_blend
) {
1105 ps_blend
.HasWriteableRT
= true;
1113 blorp_emit_color_calc_state(struct blorp_batch
*batch
,
1114 UNUSED
const struct blorp_params
*params
)
1117 blorp_emit_dynamic(batch
, GENX(COLOR_CALC_STATE
), cc
, 64, &offset
) {
1119 cc
.StencilReferenceValue
= params
->stencil_ref
;
1124 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), sp
) {
1125 sp
.ColorCalcStatePointer
= offset
;
1127 sp
.ColorCalcStatePointerValid
= true;
1136 blorp_emit_depth_stencil_state(struct blorp_batch
*batch
,
1137 const struct blorp_params
*params
)
1140 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) ds
= {
1141 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
1144 struct GENX(DEPTH_STENCIL_STATE
) ds
= { 0 };
1147 if (params
->depth
.enabled
) {
1148 ds
.DepthBufferWriteEnable
= true;
1150 switch (params
->hiz_op
) {
1151 /* See the following sections of the Sandy Bridge PRM, Volume 2, Part1:
1152 * - 7.5.3.1 Depth Buffer Clear
1153 * - 7.5.3.2 Depth Buffer Resolve
1154 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1156 case ISL_AUX_OP_FULL_RESOLVE
:
1157 ds
.DepthTestEnable
= true;
1158 ds
.DepthTestFunction
= COMPAREFUNCTION_NEVER
;
1161 case ISL_AUX_OP_NONE
:
1162 case ISL_AUX_OP_FAST_CLEAR
:
1163 case ISL_AUX_OP_AMBIGUATE
:
1164 ds
.DepthTestEnable
= false;
1166 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1167 unreachable("Invalid HIZ op");
1171 if (params
->stencil
.enabled
) {
1172 ds
.StencilBufferWriteEnable
= true;
1173 ds
.StencilTestEnable
= true;
1174 ds
.DoubleSidedStencilEnable
= false;
1176 ds
.StencilTestFunction
= COMPAREFUNCTION_ALWAYS
;
1177 ds
.StencilPassDepthPassOp
= STENCILOP_REPLACE
;
1179 ds
.StencilWriteMask
= params
->stencil_mask
;
1181 ds
.StencilReferenceValue
= params
->stencil_ref
;
1186 uint32_t offset
= 0;
1187 uint32_t *dw
= blorp_emit_dwords(batch
,
1188 GENX(3DSTATE_WM_DEPTH_STENCIL_length
));
1192 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dw
, &ds
);
1195 void *state
= blorp_alloc_dynamic_state(batch
,
1196 GENX(DEPTH_STENCIL_STATE_length
) * 4,
1198 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, state
, &ds
);
1199 blorp_flush_range(batch
, state
, GENX(DEPTH_STENCIL_STATE_length
) * 4);
1203 blorp_emit(batch
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), sp
) {
1204 sp
.PointertoDEPTH_STENCIL_STATE
= offset
;
1212 blorp_emit_3dstate_multisample(struct blorp_batch
*batch
,
1213 const struct blorp_params
*params
)
1215 blorp_emit(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1216 ms
.NumberofMultisamples
= __builtin_ffs(params
->num_samples
) - 1;
1219 /* The PRM says that this bit is valid only for DX9:
1221 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
1222 * should not have any effect by setting or not setting this bit.
1224 ms
.PixelPositionOffsetEnable
= false;
1227 switch (params
->num_samples
) {
1229 GEN_SAMPLE_POS_1X(ms
.Sample
);
1232 GEN_SAMPLE_POS_2X(ms
.Sample
);
1235 GEN_SAMPLE_POS_4X(ms
.Sample
);
1238 GEN_SAMPLE_POS_8X(ms
.Sample
);
1244 GEN_SAMPLE_POS_4X(ms
.Sample
);
1246 ms
.PixelLocation
= CENTER
;
1251 blorp_emit_pipeline(struct blorp_batch
*batch
,
1252 const struct blorp_params
*params
)
1254 uint32_t blend_state_offset
= 0;
1255 uint32_t color_calc_state_offset
;
1256 uint32_t depth_stencil_state_offset
;
1258 emit_urb_config(batch
, params
);
1260 if (params
->wm_prog_data
) {
1261 blend_state_offset
= blorp_emit_blend_state(batch
, params
);
1263 color_calc_state_offset
= blorp_emit_color_calc_state(batch
, params
);
1264 depth_stencil_state_offset
= blorp_emit_depth_stencil_state(batch
, params
);
1267 /* 3DSTATE_CC_STATE_POINTERS
1269 * The pointer offsets are relative to
1270 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
1272 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
1274 * The dynamic state emit helpers emit their own STATE_POINTERS packets on
1275 * gen7+. However, on gen6 and earlier, they're all lumpped together in
1276 * one CC_STATE_POINTERS packet so we have to emit that here.
1278 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), cc
) {
1279 cc
.BLEND_STATEChange
= true;
1280 cc
.ColorCalcStatePointerValid
= true;
1281 cc
.DEPTH_STENCIL_STATEChange
= true;
1282 cc
.PointertoBLEND_STATE
= blend_state_offset
;
1283 cc
.ColorCalcStatePointer
= color_calc_state_offset
;
1284 cc
.PointertoDEPTH_STENCIL_STATE
= depth_stencil_state_offset
;
1287 (void)blend_state_offset
;
1288 (void)color_calc_state_offset
;
1289 (void)depth_stencil_state_offset
;
1293 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_ALL
), pc
) {
1294 /* Update empty push constants for all stages (bitmask = 11111b) */
1295 pc
.ShaderUpdateEnable
= 0x1f;
1298 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_VS
), vs
);
1300 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_HS
), hs
);
1301 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_DS
), DS
);
1303 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_GS
), gs
);
1304 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_PS
), ps
);
1307 if (params
->src
.enabled
)
1308 blorp_emit_sampler_state(batch
);
1310 blorp_emit_3dstate_multisample(batch
, params
);
1312 blorp_emit(batch
, GENX(3DSTATE_SAMPLE_MASK
), mask
) {
1313 mask
.SampleMask
= (1 << params
->num_samples
) - 1;
1316 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1317 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1319 * [DevSNB] A pipeline flush must be programmed prior to a
1320 * 3DSTATE_VS command that causes the VS Function Enable to
1321 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
1322 * command with CS stall bit set and a post sync operation.
1324 * We've already done one at the start of the BLORP operation.
1326 blorp_emit_vs_config(batch
, params
);
1328 blorp_emit(batch
, GENX(3DSTATE_HS
), hs
);
1329 blorp_emit(batch
, GENX(3DSTATE_TE
), te
);
1330 blorp_emit(batch
, GENX(3DSTATE_DS
), DS
);
1331 blorp_emit(batch
, GENX(3DSTATE_STREAMOUT
), so
);
1333 blorp_emit(batch
, GENX(3DSTATE_GS
), gs
);
1335 blorp_emit(batch
, GENX(3DSTATE_CLIP
), clip
) {
1336 clip
.PerspectiveDivideDisable
= true;
1339 blorp_emit_sf_config(batch
, params
);
1340 blorp_emit_ps_config(batch
, params
);
1342 blorp_emit_cc_viewport(batch
);
1345 /******** This is the end of the pipeline setup code ********/
1347 #endif /* GEN_GEN >= 6 */
1351 blorp_emit_memcpy(struct blorp_batch
*batch
,
1352 struct blorp_address dst
,
1353 struct blorp_address src
,
1356 assert(size
% 4 == 0);
1358 for (unsigned dw
= 0; dw
< size
; dw
+= 4) {
1360 blorp_emit(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
1361 cp
.DestinationMemoryAddress
= dst
;
1362 cp
.SourceMemoryAddress
= src
;
1365 /* IVB does not have a general purpose register for command streamer
1366 * commands. Therefore, we use an alternate temporary register.
1368 #define BLORP_TEMP_REG 0x2440 /* GEN7_3DPRIM_BASE_VERTEX */
1369 blorp_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), load
) {
1370 load
.RegisterAddress
= BLORP_TEMP_REG
;
1371 load
.MemoryAddress
= src
;
1373 blorp_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), store
) {
1374 store
.RegisterAddress
= BLORP_TEMP_REG
;
1375 store
.MemoryAddress
= dst
;
1377 #undef BLORP_TEMP_REG
1386 blorp_emit_surface_state(struct blorp_batch
*batch
,
1387 const struct brw_blorp_surface_info
*surface
,
1388 enum isl_aux_op aux_op
,
1389 void *state
, uint32_t state_offset
,
1390 const bool color_write_disables
[4],
1391 bool is_render_target
)
1393 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1394 struct isl_surf surf
= surface
->surf
;
1396 if (surf
.dim
== ISL_SURF_DIM_1D
&&
1397 surf
.dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
) {
1398 assert(surf
.logical_level0_px
.height
== 1);
1399 surf
.dim
= ISL_SURF_DIM_2D
;
1402 if (isl_aux_usage_has_hiz(surface
->aux_usage
)) {
1403 /* BLORP doesn't render with depth so we can't use HiZ */
1404 assert(!is_render_target
);
1405 /* We can't reinterpret HiZ */
1406 assert(surface
->surf
.format
== surface
->view
.format
);
1408 enum isl_aux_usage aux_usage
= surface
->aux_usage
;
1410 isl_channel_mask_t write_disable_mask
= 0;
1411 if (is_render_target
&& GEN_GEN
<= 5) {
1412 if (color_write_disables
[0])
1413 write_disable_mask
|= ISL_CHANNEL_RED_BIT
;
1414 if (color_write_disables
[1])
1415 write_disable_mask
|= ISL_CHANNEL_GREEN_BIT
;
1416 if (color_write_disables
[2])
1417 write_disable_mask
|= ISL_CHANNEL_BLUE_BIT
;
1418 if (color_write_disables
[3])
1419 write_disable_mask
|= ISL_CHANNEL_ALPHA_BIT
;
1422 const bool use_clear_address
=
1423 GEN_GEN
>= 10 && (surface
->clear_color_addr
.buffer
!= NULL
);
1425 isl_surf_fill_state(batch
->blorp
->isl_dev
, state
,
1426 .surf
= &surf
, .view
= &surface
->view
,
1427 .aux_surf
= &surface
->aux_surf
, .aux_usage
= aux_usage
,
1429 blorp_get_surface_address(batch
, surface
->addr
),
1430 .aux_address
= aux_usage
== ISL_AUX_USAGE_NONE
? 0 :
1431 blorp_get_surface_address(batch
, surface
->aux_addr
),
1432 .clear_address
= !use_clear_address
? 0 :
1433 blorp_get_surface_address(batch
,
1434 surface
->clear_color_addr
),
1435 .mocs
= surface
->addr
.mocs
,
1436 .clear_color
= surface
->clear_color
,
1437 .use_clear_address
= use_clear_address
,
1438 .write_disables
= write_disable_mask
);
1440 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.addr_offset
,
1443 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1444 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1445 * used to store other information. This should be ok, however, because
1446 * surface buffer addresses are always 4K page alinged.
1448 assert((surface
->aux_addr
.offset
& 0xfff) == 0);
1449 uint32_t *aux_addr
= state
+ isl_dev
->ss
.aux_addr_offset
;
1450 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.aux_addr_offset
,
1451 surface
->aux_addr
, *aux_addr
);
1454 if (aux_usage
!= ISL_AUX_USAGE_NONE
&& surface
->clear_color_addr
.buffer
) {
1456 assert((surface
->clear_color_addr
.offset
& 0x3f) == 0);
1457 uint32_t *clear_addr
= state
+ isl_dev
->ss
.clear_color_state_offset
;
1458 blorp_surface_reloc(batch
, state_offset
+
1459 isl_dev
->ss
.clear_color_state_offset
,
1460 surface
->clear_color_addr
, *clear_addr
);
1462 /* Fast clears just whack the AUX surface and don't actually use the
1463 * clear color for anything. We can avoid the MI memcpy on that case.
1465 if (aux_op
!= ISL_AUX_OP_FAST_CLEAR
) {
1466 struct blorp_address dst_addr
= blorp_get_surface_base_address(batch
);
1467 dst_addr
.offset
+= state_offset
+ isl_dev
->ss
.clear_value_offset
;
1468 blorp_emit_memcpy(batch
, dst_addr
, surface
->clear_color_addr
,
1469 isl_dev
->ss
.clear_value_size
);
1472 unreachable("Fast clears are only supported on gen7+");
1476 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1480 blorp_emit_null_surface_state(struct blorp_batch
*batch
,
1481 const struct brw_blorp_surface_info
*surface
,
1484 struct GENX(RENDER_SURFACE_STATE
) ss
= {
1485 .SurfaceType
= SURFTYPE_NULL
,
1486 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
1487 .Width
= surface
->surf
.logical_level0_px
.width
- 1,
1488 .Height
= surface
->surf
.logical_level0_px
.height
- 1,
1489 .MIPCountLOD
= surface
->view
.base_level
,
1490 .MinimumArrayElement
= surface
->view
.base_array_layer
,
1491 .Depth
= surface
->view
.array_len
- 1,
1492 .RenderTargetViewExtent
= surface
->view
.array_len
- 1,
1494 .NumberofMultisamples
= ffs(surface
->surf
.samples
) - 1,
1498 .SurfaceArray
= surface
->surf
.dim
!= ISL_SURF_DIM_3D
,
1504 .TiledSurface
= true,
1508 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &ss
);
1510 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1514 blorp_emit_surface_states(struct blorp_batch
*batch
,
1515 const struct blorp_params
*params
)
1517 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1518 uint32_t bind_offset
= 0, surface_offsets
[2];
1519 void *surface_maps
[2];
1521 UNUSED
bool has_indirect_clear_color
= false;
1522 if (params
->use_pre_baked_binding_table
) {
1523 bind_offset
= params
->pre_baked_binding_table_offset
;
1525 unsigned num_surfaces
= 1 + params
->src
.enabled
;
1526 blorp_alloc_binding_table(batch
, num_surfaces
,
1527 isl_dev
->ss
.size
, isl_dev
->ss
.align
,
1528 &bind_offset
, surface_offsets
, surface_maps
);
1530 if (params
->dst
.enabled
) {
1531 blorp_emit_surface_state(batch
, ¶ms
->dst
,
1532 params
->fast_clear_op
,
1533 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
],
1534 surface_offsets
[BLORP_RENDERBUFFER_BT_INDEX
],
1535 params
->color_write_disable
, true);
1536 if (params
->dst
.clear_color_addr
.buffer
!= NULL
)
1537 has_indirect_clear_color
= true;
1539 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1540 const struct brw_blorp_surface_info
*surface
=
1541 params
->depth
.enabled
? ¶ms
->depth
: ¶ms
->stencil
;
1542 blorp_emit_null_surface_state(batch
, surface
,
1543 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
]);
1546 if (params
->src
.enabled
) {
1547 blorp_emit_surface_state(batch
, ¶ms
->src
,
1548 params
->fast_clear_op
,
1549 surface_maps
[BLORP_TEXTURE_BT_INDEX
],
1550 surface_offsets
[BLORP_TEXTURE_BT_INDEX
],
1552 if (params
->src
.clear_color_addr
.buffer
!= NULL
)
1553 has_indirect_clear_color
= true;
1558 if (has_indirect_clear_color
) {
1559 /* Updating a surface state object may require that the state cache be
1560 * invalidated. From the SKL PRM, Shared Functions -> State -> State
1563 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
1564 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
1565 * modified [...], the L1 state cache must be invalidated to ensure
1566 * the new surface or sampler state is fetched from system memory.
1568 blorp_emit(batch
, GENX(PIPE_CONTROL
), pipe
) {
1569 pipe
.StateCacheInvalidationEnable
= true;
1571 pipe
.TileCacheFlushEnable
= true;
1578 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), bt
);
1579 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_HS
), bt
);
1580 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_DS
), bt
);
1581 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_GS
), bt
);
1583 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS
), bt
) {
1584 bt
.PointertoPSBindingTable
= bind_offset
;
1587 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1588 bt
.PSBindingTableChange
= true;
1589 bt
.PointertoPSBindingTable
= bind_offset
;
1592 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1593 bt
.PointertoPSBindingTable
= bind_offset
;
1599 blorp_emit_depth_stencil_config(struct blorp_batch
*batch
,
1600 const struct blorp_params
*params
)
1602 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1604 uint32_t *dw
= blorp_emit_dwords(batch
, isl_dev
->ds
.size
/ 4);
1608 struct isl_depth_stencil_hiz_emit_info info
= { };
1610 if (params
->depth
.enabled
) {
1611 info
.view
= ¶ms
->depth
.view
;
1612 info
.mocs
= params
->depth
.addr
.mocs
;
1613 } else if (params
->stencil
.enabled
) {
1614 info
.view
= ¶ms
->stencil
.view
;
1615 info
.mocs
= params
->stencil
.addr
.mocs
;
1618 if (params
->depth
.enabled
) {
1619 info
.depth_surf
= ¶ms
->depth
.surf
;
1621 info
.depth_address
=
1622 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.depth_offset
/ 4,
1623 params
->depth
.addr
, 0);
1625 info
.hiz_usage
= params
->depth
.aux_usage
;
1626 if (isl_aux_usage_has_hiz(info
.hiz_usage
)) {
1627 info
.hiz_surf
= ¶ms
->depth
.aux_surf
;
1629 struct blorp_address hiz_address
= params
->depth
.aux_addr
;
1631 /* Sandy bridge hardware does not technically support mipmapped HiZ.
1632 * However, we have a special layout that allows us to make it work
1633 * anyway by manually offsetting to the specified miplevel.
1635 assert(info
.hiz_surf
->dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
1637 isl_surf_get_image_offset_B_tile_sa(info
.hiz_surf
,
1638 info
.view
->base_level
, 0, 0,
1639 &offset_B
, NULL
, NULL
);
1640 hiz_address
.offset
+= offset_B
;
1644 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.hiz_offset
/ 4,
1647 info
.depth_clear_value
= params
->depth
.clear_color
.f32
[0];
1651 if (params
->stencil
.enabled
) {
1652 info
.stencil_surf
= ¶ms
->stencil
.surf
;
1654 info
.stencil_aux_usage
= params
->stencil
.aux_usage
;
1655 struct blorp_address stencil_address
= params
->stencil
.addr
;
1657 /* Sandy bridge hardware does not technically support mipmapped stencil.
1658 * However, we have a special layout that allows us to make it work
1659 * anyway by manually offsetting to the specified miplevel.
1661 assert(info
.stencil_surf
->dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
1663 isl_surf_get_image_offset_B_tile_sa(info
.stencil_surf
,
1664 info
.view
->base_level
, 0, 0,
1665 &offset_B
, NULL
, NULL
);
1666 stencil_address
.offset
+= offset_B
;
1669 info
.stencil_address
=
1670 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.stencil_offset
/ 4,
1671 stencil_address
, 0);
1674 isl_emit_depth_stencil_hiz_s(isl_dev
, dw
, &info
);
1677 /* GEN:BUG:1408224581
1679 * Workaround: Gen12LP Astep only An additional pipe control with
1680 * post-sync = store dword operation would be required.( w/a is to
1681 * have an additional pipe control after the stencil state whenever
1682 * the surface state bits of this state is changing).
1684 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1685 pc
.PostSyncOperation
= WriteImmediateData
;
1686 pc
.Address
= blorp_get_workaround_page(batch
);
1692 /* Emits the Optimized HiZ sequence specified in the BDW+ PRMs. The
1693 * depth/stencil buffer extents are ignored to handle APIs which perform
1694 * clearing operations without such information.
1697 blorp_emit_gen8_hiz_op(struct blorp_batch
*batch
,
1698 const struct blorp_params
*params
)
1700 /* We should be performing an operation on a depth or stencil buffer.
1702 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1704 /* The stencil buffer should only be enabled on GEN == 12, if a fast clear
1705 * or full resolve operation is requested. On rest of the GEN, if a fast
1706 * clear operation is requested.
1708 if (params
->stencil
.enabled
) {
1710 assert(params
->hiz_op
== ISL_AUX_OP_FAST_CLEAR
||
1711 params
->hiz_op
== ISL_AUX_OP_FULL_RESOLVE
);
1713 assert(params
->hiz_op
== ISL_AUX_OP_FAST_CLEAR
);
1717 /* From the BDW PRM Volume 2, 3DSTATE_WM_HZ_OP:
1719 * 3DSTATE_MULTISAMPLE packet must be used prior to this packet to change
1720 * the Number of Multisamples. This packet must not be used to change
1721 * Number of Multisamples in a rendering sequence.
1723 * Since HIZ may be the first thing in a batch buffer, play safe and always
1724 * emit 3DSTATE_MULTISAMPLE.
1726 blorp_emit_3dstate_multisample(batch
, params
);
1728 /* From the BDW PRM Volume 7, Depth Buffer Clear:
1730 * The clear value must be between the min and max depth values
1731 * (inclusive) defined in the CC_VIEWPORT. If the depth buffer format is
1732 * D32_FLOAT, then +/-DENORM values are also allowed.
1734 * Set the bounds to match our hardware limits, [0.0, 1.0].
1736 if (params
->depth
.enabled
&& params
->hiz_op
== ISL_AUX_OP_FAST_CLEAR
) {
1737 assert(params
->depth
.clear_color
.f32
[0] >= 0.0f
);
1738 assert(params
->depth
.clear_color
.f32
[0] <= 1.0f
);
1739 blorp_emit_cc_viewport(batch
);
1742 /* According to the SKL PRM formula for WM_INT::ThreadDispatchEnable, the
1743 * 3DSTATE_WM::ForceThreadDispatchEnable field can force WM thread dispatch
1744 * even when WM_HZ_OP is active. However, WM thread dispatch is normally
1745 * disabled for HiZ ops and it appears that force-enabling it can lead to
1746 * GPU hangs on at least Skylake. Since we don't know the current state of
1747 * the 3DSTATE_WM packet, just emit a dummy one prior to 3DSTATE_WM_HZ_OP.
1749 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
1751 /* If we can't alter the depth stencil config and multiple layers are
1752 * involved, the HiZ op will fail. This is because the op requires that a
1753 * new config is emitted for each additional layer.
1755 if (batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
) {
1756 assert(params
->num_layers
<= 1);
1758 blorp_emit_depth_stencil_config(batch
, params
);
1761 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
) {
1762 switch (params
->hiz_op
) {
1763 case ISL_AUX_OP_FAST_CLEAR
:
1764 hzp
.StencilBufferClearEnable
= params
->stencil
.enabled
;
1765 hzp
.DepthBufferClearEnable
= params
->depth
.enabled
;
1766 hzp
.StencilClearValue
= params
->stencil_ref
;
1767 hzp
.FullSurfaceDepthandStencilClear
= params
->full_surface_hiz_op
;
1769 case ISL_AUX_OP_FULL_RESOLVE
:
1770 assert(params
->full_surface_hiz_op
);
1771 hzp
.DepthBufferResolveEnable
= params
->depth
.enabled
;
1773 if (params
->stencil
.enabled
) {
1774 assert(params
->stencil
.aux_usage
== ISL_AUX_USAGE_CCS_E
);
1775 hzp
.StencilBufferResolveEnable
= true;
1779 case ISL_AUX_OP_AMBIGUATE
:
1780 assert(params
->full_surface_hiz_op
);
1781 hzp
.HierarchicalDepthBufferResolveEnable
= true;
1783 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1784 case ISL_AUX_OP_NONE
:
1785 unreachable("Invalid HIZ op");
1788 hzp
.NumberofMultisamples
= ffs(params
->num_samples
) - 1;
1789 hzp
.SampleMask
= 0xFFFF;
1791 /* Due to a hardware issue, this bit MBZ */
1792 assert(hzp
.ScissorRectangleEnable
== false);
1794 /* Contrary to the HW docs both fields are inclusive */
1795 hzp
.ClearRectangleXMin
= params
->x0
;
1796 hzp
.ClearRectangleYMin
= params
->y0
;
1798 /* Contrary to the HW docs both fields are exclusive */
1799 hzp
.ClearRectangleXMax
= params
->x1
;
1800 hzp
.ClearRectangleYMax
= params
->y1
;
1803 /* PIPE_CONTROL w/ all bits clear except for “Post-Sync Operation” must set
1804 * to “Write Immediate Data” enabled.
1806 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1807 pc
.PostSyncOperation
= WriteImmediateData
;
1808 pc
.Address
= blorp_get_workaround_page(batch
);
1811 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
);
1816 blorp_update_clear_color(struct blorp_batch
*batch
,
1817 const struct brw_blorp_surface_info
*info
,
1820 if (info
->clear_color_addr
.buffer
&& op
== ISL_AUX_OP_FAST_CLEAR
) {
1822 blorp_emit(batch
, GENX(PIPE_CONTROL
), pipe
) {
1823 pipe
.CommandStreamerStallEnable
= true;
1827 const unsigned inlinedata_dw
= 2 * 2;
1828 const unsigned num_dwords
= GENX(MI_ATOMIC_length
) + inlinedata_dw
;
1830 struct blorp_address clear_addr
= info
->clear_color_addr
;
1831 uint32_t *dw
= blorp_emitn(batch
, GENX(MI_ATOMIC
), num_dwords
,
1832 .DataSize
= MI_ATOMIC_QWORD
,
1833 .ATOMICOPCODE
= MI_ATOMIC_OP_MOVE8B
,
1835 .MemoryAddress
= clear_addr
);
1836 /* dw starts at dword 1, but we need to fill dwords 3 and 5 */
1837 dw
[2] = info
->clear_color
.u32
[0];
1839 dw
[4] = info
->clear_color
.u32
[1];
1842 clear_addr
.offset
+= 8;
1843 dw
= blorp_emitn(batch
, GENX(MI_ATOMIC
), num_dwords
,
1844 .DataSize
= MI_ATOMIC_QWORD
,
1845 .ATOMICOPCODE
= MI_ATOMIC_OP_MOVE8B
,
1847 .ReturnDataControl
= true,
1849 .MemoryAddress
= clear_addr
);
1850 /* dw starts at dword 1, but we need to fill dwords 3 and 5 */
1851 dw
[2] = info
->clear_color
.u32
[2];
1853 dw
[4] = info
->clear_color
.u32
[3];
1856 blorp_emit(batch
, GENX(PIPE_CONTROL
), pipe
) {
1857 pipe
.StateCacheInvalidationEnable
= true;
1858 pipe
.TextureCacheInvalidationEnable
= true;
1862 /* According to GEN:BUG:2201730850, in the Clear Color Programming Note
1863 * under the Red channel, "Software shall write the converted Depth
1864 * Clear to this dword." The only depth formats listed under the red
1865 * channel are IEEE_FP and UNORM24_X8. These two requirements are
1866 * incompatible with the UNORM16 depth format, so just ignore that case
1867 * and simply perform the conversion for all depth formats.
1869 union isl_color_value fixed_color
= info
->clear_color
;
1870 if (GEN_GEN
== 12 && isl_surf_usage_is_depth(info
->surf
.usage
)) {
1871 isl_color_value_pack(&info
->clear_color
, info
->surf
.format
,
1875 for (int i
= 0; i
< 4; i
++) {
1876 blorp_emit(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
1877 sdi
.Address
= info
->clear_color_addr
;
1878 sdi
.Address
.offset
+= i
* 4;
1879 sdi
.ImmediateData
= fixed_color
.u32
[i
];
1882 sdi
.ForceWriteCompletionCheck
= true;
1887 /* The RENDER_SURFACE_STATE::ClearColor field states that software should
1888 * write the converted depth value 16B after the clear address:
1890 * 3D Sampler will always fetch clear depth from the location 16-bytes
1891 * above this address, where the clear depth, converted to native
1892 * surface format by software, will be stored.
1896 if (isl_surf_usage_is_depth(info
->surf
.usage
)) {
1897 blorp_emit(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
1898 sdi
.Address
= info
->clear_color_addr
;
1899 sdi
.Address
.offset
+= 4 * 4;
1900 sdi
.ImmediateData
= fixed_color
.u32
[0];
1901 sdi
.ForceWriteCompletionCheck
= true;
1907 blorp_emit(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
1908 sdi
.Address
= info
->clear_color_addr
;
1909 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
1910 ISL_CHANNEL_SELECT_GREEN
<< 22 |
1911 ISL_CHANNEL_SELECT_BLUE
<< 19 |
1912 ISL_CHANNEL_SELECT_ALPHA
<< 16;
1913 if (isl_format_has_int_channel(info
->view
.format
)) {
1914 for (unsigned i
= 0; i
< 4; i
++) {
1915 assert(info
->clear_color
.u32
[i
] == 0 ||
1916 info
->clear_color
.u32
[i
] == 1);
1918 sdi
.ImmediateData
|= (info
->clear_color
.u32
[0] != 0) << 31;
1919 sdi
.ImmediateData
|= (info
->clear_color
.u32
[1] != 0) << 30;
1920 sdi
.ImmediateData
|= (info
->clear_color
.u32
[2] != 0) << 29;
1921 sdi
.ImmediateData
|= (info
->clear_color
.u32
[3] != 0) << 28;
1923 for (unsigned i
= 0; i
< 4; i
++) {
1924 assert(info
->clear_color
.f32
[i
] == 0.0f
||
1925 info
->clear_color
.f32
[i
] == 1.0f
);
1927 sdi
.ImmediateData
|= (info
->clear_color
.f32
[0] != 0.0f
) << 31;
1928 sdi
.ImmediateData
|= (info
->clear_color
.f32
[1] != 0.0f
) << 30;
1929 sdi
.ImmediateData
|= (info
->clear_color
.f32
[2] != 0.0f
) << 29;
1930 sdi
.ImmediateData
|= (info
->clear_color
.f32
[3] != 0.0f
) << 28;
1938 * \brief Execute a blit or render pass operation.
1940 * To execute the operation, this function manually constructs and emits a
1941 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1942 * constructing and after emitting the batch.
1944 * This function alters no GL state.
1947 blorp_exec(struct blorp_batch
*batch
, const struct blorp_params
*params
)
1949 if (!(batch
->flags
& BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
)) {
1950 blorp_update_clear_color(batch
, ¶ms
->dst
, params
->fast_clear_op
);
1951 blorp_update_clear_color(batch
, ¶ms
->depth
, params
->hiz_op
);
1955 if (params
->hiz_op
!= ISL_AUX_OP_NONE
) {
1956 blorp_emit_gen8_hiz_op(batch
, params
);
1961 blorp_emit_vertex_buffers(batch
, params
);
1962 blorp_emit_vertex_elements(batch
, params
);
1964 blorp_emit_pipeline(batch
, params
);
1966 blorp_emit_surface_states(batch
, params
);
1968 if (!(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
))
1969 blorp_emit_depth_stencil_config(batch
, params
);
1971 blorp_emit(batch
, GENX(3DPRIMITIVE
), prim
) {
1972 prim
.VertexAccessType
= SEQUENTIAL
;
1973 prim
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
1975 prim
.PredicateEnable
= batch
->flags
& BLORP_BATCH_PREDICATE_ENABLE
;
1977 prim
.VertexCountPerInstance
= 3;
1978 prim
.InstanceCount
= params
->num_layers
;
1982 #endif /* BLORP_GENX_EXEC_H */