2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BLORP_GENX_EXEC_H
25 #define BLORP_GENX_EXEC_H
27 #include "blorp_priv.h"
28 #include "dev/gen_device_info.h"
29 #include "common/gen_sample_positions.h"
30 #include "genxml/gen_macros.h"
33 * This file provides the blorp pipeline setup and execution functionality.
34 * It defines the following function:
37 * blorp_exec(struct blorp_context *blorp, void *batch_data,
38 * const struct blorp_params *params);
40 * It is the job of whoever includes this header to wrap this in something
41 * to get an externally visible symbol.
43 * In order for the blorp_exec function to work, the driver must provide
44 * implementations of the following static helper functions.
48 blorp_emit_dwords(struct blorp_batch
*batch
, unsigned n
);
51 blorp_emit_reloc(struct blorp_batch
*batch
,
52 void *location
, struct blorp_address address
, uint32_t delta
);
55 blorp_alloc_dynamic_state(struct blorp_batch
*batch
,
60 blorp_alloc_vertex_buffer(struct blorp_batch
*batch
, uint32_t size
,
61 struct blorp_address
*addr
);
64 static struct blorp_address
65 blorp_get_workaround_page(struct blorp_batch
*batch
);
69 blorp_alloc_binding_table(struct blorp_batch
*batch
, unsigned num_entries
,
70 unsigned state_size
, unsigned state_alignment
,
71 uint32_t *bt_offset
, uint32_t *surface_offsets
,
75 blorp_flush_range(struct blorp_batch
*batch
, void *start
, size_t size
);
78 blorp_surface_reloc(struct blorp_batch
*batch
, uint32_t ss_offset
,
79 struct blorp_address address
, uint32_t delta
);
81 #if GEN_GEN >= 7 && GEN_GEN <= 10
82 static struct blorp_address
83 blorp_get_surface_base_address(struct blorp_batch
*batch
);
87 blorp_emit_urb_config(struct blorp_batch
*batch
,
88 unsigned vs_entry_size
, unsigned sf_entry_size
);
91 blorp_emit_pipeline(struct blorp_batch
*batch
,
92 const struct blorp_params
*params
);
94 /***** BEGIN blorp_exec implementation ******/
97 _blorp_combine_address(struct blorp_batch
*batch
, void *location
,
98 struct blorp_address address
, uint32_t delta
)
100 if (address
.buffer
== NULL
) {
101 return address
.offset
+ delta
;
103 return blorp_emit_reloc(batch
, location
, address
, delta
);
107 #define __gen_address_type struct blorp_address
108 #define __gen_user_data struct blorp_batch
109 #define __gen_combine_address _blorp_combine_address
111 #include "genxml/genX_pack.h"
113 #define _blorp_cmd_length(cmd) cmd ## _length
114 #define _blorp_cmd_length_bias(cmd) cmd ## _length_bias
115 #define _blorp_cmd_header(cmd) cmd ## _header
116 #define _blorp_cmd_pack(cmd) cmd ## _pack
118 #define blorp_emit(batch, cmd, name) \
119 for (struct cmd name = { _blorp_cmd_header(cmd) }, \
120 *_dst = blorp_emit_dwords(batch, _blorp_cmd_length(cmd)); \
121 __builtin_expect(_dst != NULL, 1); \
122 _blorp_cmd_pack(cmd)(batch, (void *)_dst, &name), \
125 #define blorp_emitn(batch, cmd, n) ({ \
126 uint32_t *_dw = blorp_emit_dwords(batch, n); \
128 struct cmd template = { \
129 _blorp_cmd_header(cmd), \
130 .DWordLength = n - _blorp_cmd_length_bias(cmd), \
132 _blorp_cmd_pack(cmd)(batch, _dw, &template); \
134 _dw ? _dw + 1 : NULL; /* Array starts at dw[1] */ \
137 #define STRUCT_ZERO(S) ({ struct S t; memset(&t, 0, sizeof(t)); t; })
139 #define blorp_emit_dynamic(batch, state, name, align, offset) \
140 for (struct state name = STRUCT_ZERO(state), \
141 *_dst = blorp_alloc_dynamic_state(batch, \
142 _blorp_cmd_length(state) * 4, \
144 __builtin_expect(_dst != NULL, 1); \
145 _blorp_cmd_pack(state)(batch, (void *)_dst, &name), \
146 blorp_flush_range(batch, _dst, _blorp_cmd_length(state) * 4), \
155 * Assign the entire URB to the VS. Even though the VS disabled, URB space
156 * is still needed because the clipper loads the VUE's from the URB. From
157 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
158 * Dword 1.15:0 "VS Number of URB Entries":
159 * This field is always used (even if VS Function Enable is DISABLED).
161 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
162 * safely ignore it because this batch contains only one draw call.
163 * Because of URB corruption caused by allocating a previous GS unit
164 * URB entry to the VS unit, software is required to send a “GS NULL
165 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
166 * plus a dummy DRAW call before any case where VS will be taking over
169 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
170 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
172 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
173 * programmed in order for the programming of this state to be
177 emit_urb_config(struct blorp_batch
*batch
,
178 const struct blorp_params
*params
)
180 /* Once vertex fetcher has written full VUE entries with complete
181 * header the space requirement is as follows per vertex (in bytes):
183 * Header Position Program constants
184 * +--------+------------+-------------------+
185 * | 16 | 16 | n x 16 |
186 * +--------+------------+-------------------+
188 * where 'n' stands for number of varying inputs expressed as vec4s.
190 const unsigned num_varyings
=
191 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
192 const unsigned total_needed
= 16 + 16 + num_varyings
* 16;
194 /* The URB size is expressed in units of 64 bytes (512 bits) */
195 const unsigned vs_entry_size
= DIV_ROUND_UP(total_needed
, 64);
197 const unsigned sf_entry_size
=
198 params
->sf_prog_data
? params
->sf_prog_data
->urb_entry_size
: 0;
200 blorp_emit_urb_config(batch
, vs_entry_size
, sf_entry_size
);
204 blorp_emit_vertex_data(struct blorp_batch
*batch
,
205 const struct blorp_params
*params
,
206 struct blorp_address
*addr
,
209 const float vertices
[] = {
210 /* v0 */ (float)params
->x1
, (float)params
->y1
, params
->z
,
211 /* v1 */ (float)params
->x0
, (float)params
->y1
, params
->z
,
212 /* v2 */ (float)params
->x0
, (float)params
->y0
, params
->z
,
215 void *data
= blorp_alloc_vertex_buffer(batch
, sizeof(vertices
), addr
);
216 memcpy(data
, vertices
, sizeof(vertices
));
217 *size
= sizeof(vertices
);
218 blorp_flush_range(batch
, data
, *size
);
222 blorp_emit_input_varying_data(struct blorp_batch
*batch
,
223 const struct blorp_params
*params
,
224 struct blorp_address
*addr
,
227 const unsigned vec4_size_in_bytes
= 4 * sizeof(float);
228 const unsigned max_num_varyings
=
229 DIV_ROUND_UP(sizeof(params
->wm_inputs
), vec4_size_in_bytes
);
230 const unsigned num_varyings
=
231 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
233 *size
= 16 + num_varyings
* vec4_size_in_bytes
;
235 const uint32_t *const inputs_src
= (const uint32_t *)¶ms
->wm_inputs
;
236 void *data
= blorp_alloc_vertex_buffer(batch
, *size
, addr
);
237 uint32_t *inputs
= data
;
239 /* Copy in the VS inputs */
240 assert(sizeof(params
->vs_inputs
) == 16);
241 memcpy(inputs
, ¶ms
->vs_inputs
, sizeof(params
->vs_inputs
));
244 if (params
->wm_prog_data
) {
245 /* Walk over the attribute slots, determine if the attribute is used by
246 * the program and when necessary copy the values from the input storage
247 * to the vertex data buffer.
249 for (unsigned i
= 0; i
< max_num_varyings
; i
++) {
250 const gl_varying_slot attr
= VARYING_SLOT_VAR0
+ i
;
252 const int input_index
= params
->wm_prog_data
->urb_setup
[attr
];
256 memcpy(inputs
, inputs_src
+ i
* 4, vec4_size_in_bytes
);
262 blorp_flush_range(batch
, data
, *size
);
266 blorp_fill_vertex_buffer_state(struct blorp_batch
*batch
,
267 struct GENX(VERTEX_BUFFER_STATE
) *vb
,
269 struct blorp_address addr
, uint32_t size
,
272 vb
[idx
].VertexBufferIndex
= idx
;
273 vb
[idx
].BufferStartingAddress
= addr
;
274 vb
[idx
].BufferPitch
= stride
;
277 vb
[idx
].VertexBufferMOCS
= addr
.mocs
;
281 vb
[idx
].AddressModifyEnable
= true;
285 vb
[idx
].BufferSize
= size
;
287 vb
[idx
].BufferAccessType
= stride
> 0 ? VERTEXDATA
: INSTANCEDATA
;
288 vb
[idx
].EndAddress
= vb
[idx
].BufferStartingAddress
;
289 vb
[idx
].EndAddress
.offset
+= size
- 1;
291 vb
[idx
].BufferAccessType
= stride
> 0 ? VERTEXDATA
: INSTANCEDATA
;
292 vb
[idx
].MaxIndex
= stride
> 0 ? size
/ stride
: 0;
297 blorp_emit_vertex_buffers(struct blorp_batch
*batch
,
298 const struct blorp_params
*params
)
300 struct GENX(VERTEX_BUFFER_STATE
) vb
[3];
301 memset(vb
, 0, sizeof(vb
));
303 struct blorp_address addr
;
305 blorp_emit_vertex_data(batch
, params
, &addr
, &size
);
306 blorp_fill_vertex_buffer_state(batch
, vb
, 0, addr
, size
, 3 * sizeof(float));
308 blorp_emit_input_varying_data(batch
, params
, &addr
, &size
);
309 blorp_fill_vertex_buffer_state(batch
, vb
, 1, addr
, size
, 0);
311 uint32_t num_vbs
= 2;
312 if (params
->dst_clear_color_as_input
) {
313 const unsigned clear_color_size
=
314 GEN_GEN
< 10 ? batch
->blorp
->isl_dev
->ss
.clear_value_size
: 4 * 4;
315 blorp_fill_vertex_buffer_state(batch
, vb
, num_vbs
++,
316 params
->dst
.clear_color_addr
,
317 clear_color_size
, 0);
320 const unsigned num_dwords
= 1 + num_vbs
* GENX(VERTEX_BUFFER_STATE_length
);
321 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), num_dwords
);
325 for (unsigned i
= 0; i
< num_vbs
; i
++) {
326 GENX(VERTEX_BUFFER_STATE_pack
)(batch
, dw
, &vb
[i
]);
327 dw
+= GENX(VERTEX_BUFFER_STATE_length
);
332 blorp_emit_vertex_elements(struct blorp_batch
*batch
,
333 const struct blorp_params
*params
)
335 const unsigned num_varyings
=
336 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
337 bool need_ndc
= batch
->blorp
->compiler
->devinfo
->gen
<= 5;
338 const unsigned num_elements
= 2 + need_ndc
+ num_varyings
;
340 struct GENX(VERTEX_ELEMENT_STATE
) ve
[num_elements
];
341 memset(ve
, 0, num_elements
* sizeof(*ve
));
343 /* Setup VBO for the rectangle primitive..
345 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
346 * vertices. The vertices reside in screen space with DirectX
347 * coordinates (that is, (0, 0) is the upper left corner).
354 * Since the VS is disabled, the clipper loads each VUE directly from
355 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
356 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
357 * dw0: Reserved, MBZ.
358 * dw1: Render Target Array Index. Below vertex fetcher gets programmed
359 * to assign this with primitive instance identifier which will be
360 * used for layered clears. All other renders have only one instance
361 * and therefore the value will be effectively zero.
362 * dw2: Viewport Index. The HiZ op disables viewport mapping and
363 * scissoring, so set the dword to 0.
364 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive,
365 * so set the dword to 0.
366 * dw4: Vertex Position X.
367 * dw5: Vertex Position Y.
368 * dw6: Vertex Position Z.
369 * dw7: Vertex Position W.
371 * dw8: Flat vertex input 0
372 * dw9: Flat vertex input 1
374 * dwn: Flat vertex input n - 8
376 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
377 * "Vertex URB Entry (VUE) Formats".
379 * Only vertex position X and Y are going to be variable, Z is fixed to
380 * zero and W to one. Header words dw0,2,3 are zero. There is no need to
381 * include the fixed values in the vertex buffer. Vertex fetcher can be
382 * instructed to fill vertex elements with constant values of one and zero
383 * instead of reading them from the buffer.
384 * Flat inputs are program constants that are not interpolated. Moreover
385 * their values will be the same between vertices.
387 * See the vertex element setup below.
391 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
392 .VertexBufferIndex
= 1,
394 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
395 .SourceElementOffset
= 0,
396 .Component0Control
= VFCOMP_STORE_SRC
,
398 /* From Gen8 onwards hardware is no more instructed to overwrite
399 * components using an element specifier. Instead one has separate
400 * 3DSTATE_VF_SGVS (System Generated Value Setup) state packet for it.
403 .Component1Control
= VFCOMP_STORE_0
,
405 .Component1Control
= VFCOMP_STORE_IID
,
407 .Component1Control
= VFCOMP_STORE_0
,
409 .Component2Control
= VFCOMP_STORE_0
,
410 .Component3Control
= VFCOMP_STORE_0
,
412 .DestinationElementOffset
= slot
* 4,
418 /* On Iron Lake and earlier, a native device coordinates version of the
419 * position goes right after the normal VUE header and before position.
420 * Since w == 1 for all of our coordinates, this is just a copy of the
423 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
424 .VertexBufferIndex
= 0,
426 .SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
,
427 .SourceElementOffset
= 0,
428 .Component0Control
= VFCOMP_STORE_SRC
,
429 .Component1Control
= VFCOMP_STORE_SRC
,
430 .Component2Control
= VFCOMP_STORE_SRC
,
431 .Component3Control
= VFCOMP_STORE_1_FP
,
432 .DestinationElementOffset
= slot
* 4,
437 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
438 .VertexBufferIndex
= 0,
440 .SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
,
441 .SourceElementOffset
= 0,
442 .Component0Control
= VFCOMP_STORE_SRC
,
443 .Component1Control
= VFCOMP_STORE_SRC
,
444 .Component2Control
= VFCOMP_STORE_SRC
,
445 .Component3Control
= VFCOMP_STORE_1_FP
,
447 .DestinationElementOffset
= slot
* 4,
452 if (params
->dst_clear_color_as_input
) {
453 /* If the caller wants the destination indirect clear color, redirect
454 * to vertex buffer 2 where we stored it earlier. The only users of
455 * an indirect clear color source have that as their only vertex
458 assert(num_varyings
== 1);
459 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
460 .VertexBufferIndex
= 2,
462 .SourceElementOffset
= 0,
463 .Component0Control
= VFCOMP_STORE_SRC
,
465 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
466 .Component1Control
= VFCOMP_STORE_SRC
,
467 .Component2Control
= VFCOMP_STORE_SRC
,
468 .Component3Control
= VFCOMP_STORE_SRC
,
470 /* Clear colors on gen7-8 are for bits out of one dword */
471 .SourceElementFormat
= ISL_FORMAT_R32_FLOAT
,
472 .Component1Control
= VFCOMP_STORE_0
,
473 .Component2Control
= VFCOMP_STORE_0
,
474 .Component3Control
= VFCOMP_STORE_0
,
479 for (unsigned i
= 0; i
< num_varyings
; ++i
) {
480 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
481 .VertexBufferIndex
= 1,
483 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
484 .SourceElementOffset
= 16 + i
* 4 * sizeof(float),
485 .Component0Control
= VFCOMP_STORE_SRC
,
486 .Component1Control
= VFCOMP_STORE_SRC
,
487 .Component2Control
= VFCOMP_STORE_SRC
,
488 .Component3Control
= VFCOMP_STORE_SRC
,
490 .DestinationElementOffset
= slot
* 4,
497 const unsigned num_dwords
=
498 1 + GENX(VERTEX_ELEMENT_STATE_length
) * num_elements
;
499 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_ELEMENTS
), num_dwords
);
503 for (unsigned i
= 0; i
< num_elements
; i
++) {
504 GENX(VERTEX_ELEMENT_STATE_pack
)(batch
, dw
, &ve
[i
]);
505 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
509 /* Overwrite Render Target Array Index (2nd dword) in the VUE header with
510 * primitive instance identifier. This is used for layered clears.
512 blorp_emit(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
513 sgvs
.InstanceIDEnable
= true;
514 sgvs
.InstanceIDComponentNumber
= COMP_1
;
515 sgvs
.InstanceIDElementOffset
= 0;
518 for (unsigned i
= 0; i
< num_elements
; i
++) {
519 blorp_emit(batch
, GENX(3DSTATE_VF_INSTANCING
), vf
) {
520 vf
.VertexElementIndex
= i
;
521 vf
.InstancingEnable
= false;
525 blorp_emit(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
526 topo
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
531 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
533 blorp_emit_cc_viewport(struct blorp_batch
*batch
)
535 uint32_t cc_vp_offset
;
536 blorp_emit_dynamic(batch
, GENX(CC_VIEWPORT
), vp
, 32, &cc_vp_offset
) {
537 vp
.MinimumDepth
= 0.0;
538 vp
.MaximumDepth
= 1.0;
542 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), vsp
) {
543 vsp
.CCViewportPointer
= cc_vp_offset
;
546 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vsp
) {
547 vsp
.CCViewportStateChange
= true;
548 vsp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
556 blorp_emit_sampler_state(struct blorp_batch
*batch
)
559 blorp_emit_dynamic(batch
, GENX(SAMPLER_STATE
), sampler
, 32, &offset
) {
560 sampler
.MipModeFilter
= MIPFILTER_NONE
;
561 sampler
.MagModeFilter
= MAPFILTER_LINEAR
;
562 sampler
.MinModeFilter
= MAPFILTER_LINEAR
;
565 sampler
.TCXAddressControlMode
= TCM_CLAMP
;
566 sampler
.TCYAddressControlMode
= TCM_CLAMP
;
567 sampler
.TCZAddressControlMode
= TCM_CLAMP
;
568 sampler
.MaximumAnisotropy
= RATIO21
;
569 sampler
.RAddressMinFilterRoundingEnable
= true;
570 sampler
.RAddressMagFilterRoundingEnable
= true;
571 sampler
.VAddressMinFilterRoundingEnable
= true;
572 sampler
.VAddressMagFilterRoundingEnable
= true;
573 sampler
.UAddressMinFilterRoundingEnable
= true;
574 sampler
.UAddressMagFilterRoundingEnable
= true;
576 sampler
.NonnormalizedCoordinateEnable
= true;
581 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS
), ssp
) {
582 ssp
.PointertoPSSamplerState
= offset
;
585 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS
), ssp
) {
586 ssp
.VSSamplerStateChange
= true;
587 ssp
.GSSamplerStateChange
= true;
588 ssp
.PSSamplerStateChange
= true;
589 ssp
.PointertoPSSamplerState
= offset
;
596 /* What follows is the code for setting up a "pipeline" on Sandy Bridge and
597 * later hardware. This file will be included by i965 for gen4-5 as well, so
598 * this code is guarded by GEN_GEN >= 6.
603 blorp_emit_vs_config(struct blorp_batch
*batch
,
604 const struct blorp_params
*params
)
606 struct brw_vs_prog_data
*vs_prog_data
= params
->vs_prog_data
;
607 assert(!vs_prog_data
|| GEN_GEN
< 11 ||
608 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
);
610 blorp_emit(batch
, GENX(3DSTATE_VS
), vs
) {
614 vs
.KernelStartPointer
= params
->vs_prog_kernel
;
616 vs
.DispatchGRFStartRegisterForURBData
=
617 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
618 vs
.VertexURBEntryReadLength
=
619 vs_prog_data
->base
.urb_read_length
;
620 vs
.VertexURBEntryReadOffset
= 0;
622 vs
.MaximumNumberofThreads
=
623 batch
->blorp
->isl_dev
->info
->max_vs_threads
- 1;
626 vs
.SIMD8DispatchEnable
=
627 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
634 blorp_emit_sf_config(struct blorp_batch
*batch
,
635 const struct blorp_params
*params
)
637 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
641 * Disable ViewportTransformEnable (dw2.1)
643 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
644 * Primitives Overview":
645 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
646 * use of screen- space coordinates).
648 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
649 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
651 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
652 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
653 * SOLID: Any triangle or rectangle object found to be front-facing
654 * is rendered as a solid object. This setting is required when
655 * (rendering rectangle (RECTLIST) objects.
660 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
);
662 blorp_emit(batch
, GENX(3DSTATE_RASTER
), raster
) {
663 raster
.CullMode
= CULLMODE_NONE
;
666 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
667 sbe
.VertexURBEntryReadOffset
= 1;
669 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
670 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
671 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
673 sbe
.NumberofSFOutputAttributes
= 0;
674 sbe
.VertexURBEntryReadLength
= 1;
676 sbe
.ForceVertexURBEntryReadLength
= true;
677 sbe
.ForceVertexURBEntryReadOffset
= true;
680 for (unsigned i
= 0; i
< 32; i
++)
681 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
687 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
688 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
689 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
691 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
692 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
695 sf
.DepthBufferSurfaceFormat
= params
->depth_format
;
699 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
700 sbe
.VertexURBEntryReadOffset
= 1;
702 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
703 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
704 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
706 sbe
.NumberofSFOutputAttributes
= 0;
707 sbe
.VertexURBEntryReadLength
= 1;
711 #else /* GEN_GEN <= 6 */
713 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
714 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
715 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
717 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
718 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
720 sf
.VertexURBEntryReadOffset
= 1;
722 sf
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
723 sf
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
724 sf
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
726 sf
.NumberofSFOutputAttributes
= 0;
727 sf
.VertexURBEntryReadLength
= 1;
735 blorp_emit_ps_config(struct blorp_batch
*batch
,
736 const struct blorp_params
*params
)
738 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
740 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
741 * nonzero to prevent the GPU from hanging. While the documentation doesn't
742 * mention this explicitly, it notes that the valid range for the field is
743 * [1,39] = [2,40] threads, which excludes zero.
745 * To be safe (and to minimize extraneous code) we go ahead and fully
746 * configure the WM state whether or not there is a WM program.
751 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
753 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
754 if (params
->src
.enabled
) {
755 ps
.SamplerCount
= 1; /* Up to 4 samplers */
756 ps
.BindingTableEntryCount
= 2;
758 ps
.BindingTableEntryCount
= 1;
762 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
763 prog_data
->base
.dispatch_grf_start_reg
;
764 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
765 prog_data
->dispatch_grf_start_reg_2
;
767 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
768 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
770 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
771 ps
.KernelStartPointer2
=
772 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
775 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64
776 * for pre Gen11 and 128 for gen11+; On gen11+ If a programmed value is
777 * k, it implies 2(k+1) threads. It implicitly scales for different GT
778 * levels (which have some # of PSDs).
780 * In Gen8 the format is U8-2 whereas in Gen9+ it is U9-1.
783 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
785 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
787 switch (params
->fast_clear_op
) {
788 case ISL_AUX_OP_NONE
:
791 case ISL_AUX_OP_PARTIAL_RESOLVE
:
792 ps
.RenderTargetResolveType
= RESOLVE_PARTIAL
;
794 case ISL_AUX_OP_FULL_RESOLVE
:
795 ps
.RenderTargetResolveType
= RESOLVE_FULL
;
798 case ISL_AUX_OP_FULL_RESOLVE
:
799 ps
.RenderTargetResolveEnable
= true;
802 case ISL_AUX_OP_FAST_CLEAR
:
803 ps
.RenderTargetFastClearEnable
= true;
806 unreachable("Invalid fast clear op");
810 blorp_emit(batch
, GENX(3DSTATE_PS_EXTRA
), psx
) {
812 psx
.PixelShaderValid
= true;
813 psx
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
814 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
817 if (params
->src
.enabled
)
818 psx
.PixelShaderKillsPixel
= true;
823 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
824 switch (params
->hiz_op
) {
825 case ISL_AUX_OP_FAST_CLEAR
:
826 wm
.DepthBufferClear
= true;
828 case ISL_AUX_OP_FULL_RESOLVE
:
829 wm
.DepthBufferResolveEnable
= true;
831 case ISL_AUX_OP_AMBIGUATE
:
832 wm
.HierarchicalDepthBufferResolveEnable
= true;
834 case ISL_AUX_OP_NONE
:
837 unreachable("not reached");
841 wm
.ThreadDispatchEnable
= true;
843 if (params
->src
.enabled
)
844 wm
.PixelShaderKillsPixel
= true;
846 if (params
->num_samples
> 1) {
847 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
848 wm
.MultisampleDispatchMode
=
849 (prog_data
&& prog_data
->persample_dispatch
) ?
850 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
852 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
853 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
857 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
858 ps
.MaximumNumberofThreads
=
859 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
866 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
867 prog_data
->base
.dispatch_grf_start_reg
;
868 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
869 prog_data
->dispatch_grf_start_reg_2
;
871 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
872 ps
.KernelStartPointer2
=
873 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
875 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
876 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
878 ps
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
880 /* Gen7 hardware gets angry if we don't enable at least one dispatch
881 * mode, so just enable 16-pixel dispatch if we don't have a program.
883 ps
._16PixelDispatchEnable
= true;
886 if (params
->src
.enabled
)
887 ps
.SamplerCount
= 1; /* Up to 4 samplers */
889 switch (params
->fast_clear_op
) {
890 case ISL_AUX_OP_NONE
:
892 case ISL_AUX_OP_FULL_RESOLVE
:
893 ps
.RenderTargetResolveEnable
= true;
895 case ISL_AUX_OP_FAST_CLEAR
:
896 ps
.RenderTargetFastClearEnable
= true;
899 unreachable("Invalid fast clear op");
903 #else /* GEN_GEN <= 6 */
905 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
906 wm
.MaximumNumberofThreads
=
907 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
909 switch (params
->hiz_op
) {
910 case ISL_AUX_OP_FAST_CLEAR
:
911 wm
.DepthBufferClear
= true;
913 case ISL_AUX_OP_FULL_RESOLVE
:
914 wm
.DepthBufferResolveEnable
= true;
916 case ISL_AUX_OP_AMBIGUATE
:
917 wm
.HierarchicalDepthBufferResolveEnable
= true;
919 case ISL_AUX_OP_NONE
:
922 unreachable("not reached");
926 wm
.ThreadDispatchEnable
= true;
928 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
929 prog_data
->base
.dispatch_grf_start_reg
;
930 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
931 prog_data
->dispatch_grf_start_reg_2
;
933 wm
.KernelStartPointer0
= params
->wm_prog_kernel
;
934 wm
.KernelStartPointer2
=
935 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
937 wm
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
938 wm
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
940 wm
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
943 if (params
->src
.enabled
) {
944 wm
.SamplerCount
= 1; /* Up to 4 samplers */
945 wm
.PixelShaderKillsPixel
= true; /* TODO: temporarily smash on */
948 if (params
->num_samples
> 1) {
949 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
950 wm
.MultisampleDispatchMode
=
951 (prog_data
&& prog_data
->persample_dispatch
) ?
952 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
954 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
955 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
963 blorp_emit_blend_state(struct blorp_batch
*batch
,
964 const struct blorp_params
*params
)
966 struct GENX(BLEND_STATE
) blend
;
967 memset(&blend
, 0, sizeof(blend
));
970 int size
= GENX(BLEND_STATE_length
) * 4;
971 size
+= GENX(BLEND_STATE_ENTRY_length
) * 4 * params
->num_draw_buffers
;
972 uint32_t *state
= blorp_alloc_dynamic_state(batch
, size
, 64, &offset
);
973 uint32_t *pos
= state
;
975 GENX(BLEND_STATE_pack
)(NULL
, pos
, &blend
);
976 pos
+= GENX(BLEND_STATE_length
);
978 for (unsigned i
= 0; i
< params
->num_draw_buffers
; ++i
) {
979 struct GENX(BLEND_STATE_ENTRY
) entry
= {
980 .PreBlendColorClampEnable
= true,
981 .PostBlendColorClampEnable
= true,
982 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
984 .WriteDisableRed
= params
->color_write_disable
[0],
985 .WriteDisableGreen
= params
->color_write_disable
[1],
986 .WriteDisableBlue
= params
->color_write_disable
[2],
987 .WriteDisableAlpha
= params
->color_write_disable
[3],
989 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, pos
, &entry
);
990 pos
+= GENX(BLEND_STATE_ENTRY_length
);
993 blorp_flush_range(batch
, state
, size
);
996 blorp_emit(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), sp
) {
997 sp
.BlendStatePointer
= offset
;
999 sp
.BlendStatePointerValid
= true;
1005 blorp_emit(batch
, GENX(3DSTATE_PS_BLEND
), ps_blend
) {
1006 ps_blend
.HasWriteableRT
= true;
1014 blorp_emit_color_calc_state(struct blorp_batch
*batch
,
1015 MAYBE_UNUSED
const struct blorp_params
*params
)
1018 blorp_emit_dynamic(batch
, GENX(COLOR_CALC_STATE
), cc
, 64, &offset
) {
1020 cc
.StencilReferenceValue
= params
->stencil_ref
;
1025 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), sp
) {
1026 sp
.ColorCalcStatePointer
= offset
;
1028 sp
.ColorCalcStatePointerValid
= true;
1037 blorp_emit_depth_stencil_state(struct blorp_batch
*batch
,
1038 const struct blorp_params
*params
)
1041 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) ds
= {
1042 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
1045 struct GENX(DEPTH_STENCIL_STATE
) ds
= { 0 };
1048 if (params
->depth
.enabled
) {
1049 ds
.DepthBufferWriteEnable
= true;
1051 switch (params
->hiz_op
) {
1052 case ISL_AUX_OP_NONE
:
1053 ds
.DepthTestEnable
= true;
1054 ds
.DepthTestFunction
= COMPAREFUNCTION_ALWAYS
;
1057 /* See the following sections of the Sandy Bridge PRM, Volume 2, Part1:
1058 * - 7.5.3.1 Depth Buffer Clear
1059 * - 7.5.3.2 Depth Buffer Resolve
1060 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1062 case ISL_AUX_OP_FULL_RESOLVE
:
1063 ds
.DepthTestEnable
= true;
1064 ds
.DepthTestFunction
= COMPAREFUNCTION_NEVER
;
1067 case ISL_AUX_OP_FAST_CLEAR
:
1068 case ISL_AUX_OP_AMBIGUATE
:
1069 ds
.DepthTestEnable
= false;
1071 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1072 unreachable("Invalid HIZ op");
1076 if (params
->stencil
.enabled
) {
1077 ds
.StencilBufferWriteEnable
= true;
1078 ds
.StencilTestEnable
= true;
1079 ds
.DoubleSidedStencilEnable
= false;
1081 ds
.StencilTestFunction
= COMPAREFUNCTION_ALWAYS
;
1082 ds
.StencilPassDepthPassOp
= STENCILOP_REPLACE
;
1084 ds
.StencilWriteMask
= params
->stencil_mask
;
1086 ds
.StencilReferenceValue
= params
->stencil_ref
;
1091 uint32_t offset
= 0;
1092 uint32_t *dw
= blorp_emit_dwords(batch
,
1093 GENX(3DSTATE_WM_DEPTH_STENCIL_length
));
1097 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dw
, &ds
);
1100 void *state
= blorp_alloc_dynamic_state(batch
,
1101 GENX(DEPTH_STENCIL_STATE_length
) * 4,
1103 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, state
, &ds
);
1104 blorp_flush_range(batch
, state
, GENX(DEPTH_STENCIL_STATE_length
) * 4);
1108 blorp_emit(batch
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), sp
) {
1109 sp
.PointertoDEPTH_STENCIL_STATE
= offset
;
1117 blorp_emit_3dstate_multisample(struct blorp_batch
*batch
,
1118 const struct blorp_params
*params
)
1120 blorp_emit(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1121 ms
.NumberofMultisamples
= __builtin_ffs(params
->num_samples
) - 1;
1124 /* The PRM says that this bit is valid only for DX9:
1126 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
1127 * should not have any effect by setting or not setting this bit.
1129 ms
.PixelPositionOffsetEnable
= false;
1132 switch (params
->num_samples
) {
1134 GEN_SAMPLE_POS_1X(ms
.Sample
);
1137 GEN_SAMPLE_POS_2X(ms
.Sample
);
1140 GEN_SAMPLE_POS_4X(ms
.Sample
);
1143 GEN_SAMPLE_POS_8X(ms
.Sample
);
1149 GEN_SAMPLE_POS_4X(ms
.Sample
);
1151 ms
.PixelLocation
= CENTER
;
1156 blorp_emit_pipeline(struct blorp_batch
*batch
,
1157 const struct blorp_params
*params
)
1159 uint32_t blend_state_offset
= 0;
1160 uint32_t color_calc_state_offset
;
1161 uint32_t depth_stencil_state_offset
;
1163 emit_urb_config(batch
, params
);
1165 if (params
->wm_prog_data
) {
1166 blend_state_offset
= blorp_emit_blend_state(batch
, params
);
1168 color_calc_state_offset
= blorp_emit_color_calc_state(batch
, params
);
1169 depth_stencil_state_offset
= blorp_emit_depth_stencil_state(batch
, params
);
1172 /* 3DSTATE_CC_STATE_POINTERS
1174 * The pointer offsets are relative to
1175 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
1177 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
1179 * The dynamic state emit helpers emit their own STATE_POINTERS packets on
1180 * gen7+. However, on gen6 and earlier, they're all lumpped together in
1181 * one CC_STATE_POINTERS packet so we have to emit that here.
1183 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), cc
) {
1184 cc
.BLEND_STATEChange
= true;
1185 cc
.ColorCalcStatePointerValid
= true;
1186 cc
.DEPTH_STENCIL_STATEChange
= true;
1187 cc
.PointertoBLEND_STATE
= blend_state_offset
;
1188 cc
.ColorCalcStatePointer
= color_calc_state_offset
;
1189 cc
.PointertoDEPTH_STENCIL_STATE
= depth_stencil_state_offset
;
1192 (void)blend_state_offset
;
1193 (void)color_calc_state_offset
;
1194 (void)depth_stencil_state_offset
;
1197 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_VS
), vs
);
1199 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_HS
), hs
);
1200 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_DS
), DS
);
1202 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_GS
), gs
);
1203 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_PS
), ps
);
1205 if (params
->src
.enabled
)
1206 blorp_emit_sampler_state(batch
);
1208 blorp_emit_3dstate_multisample(batch
, params
);
1210 blorp_emit(batch
, GENX(3DSTATE_SAMPLE_MASK
), mask
) {
1211 mask
.SampleMask
= (1 << params
->num_samples
) - 1;
1214 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1215 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1217 * [DevSNB] A pipeline flush must be programmed prior to a
1218 * 3DSTATE_VS command that causes the VS Function Enable to
1219 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
1220 * command with CS stall bit set and a post sync operation.
1222 * We've already done one at the start of the BLORP operation.
1224 blorp_emit_vs_config(batch
, params
);
1226 blorp_emit(batch
, GENX(3DSTATE_HS
), hs
);
1227 blorp_emit(batch
, GENX(3DSTATE_TE
), te
);
1228 blorp_emit(batch
, GENX(3DSTATE_DS
), DS
);
1229 blorp_emit(batch
, GENX(3DSTATE_STREAMOUT
), so
);
1231 blorp_emit(batch
, GENX(3DSTATE_GS
), gs
);
1233 blorp_emit(batch
, GENX(3DSTATE_CLIP
), clip
) {
1234 clip
.PerspectiveDivideDisable
= true;
1237 blorp_emit_sf_config(batch
, params
);
1238 blorp_emit_ps_config(batch
, params
);
1240 blorp_emit_cc_viewport(batch
);
1243 /******** This is the end of the pipeline setup code ********/
1245 #endif /* GEN_GEN >= 6 */
1247 #if GEN_GEN >= 7 && GEN_GEN <= 10
1249 blorp_emit_memcpy(struct blorp_batch
*batch
,
1250 struct blorp_address dst
,
1251 struct blorp_address src
,
1254 assert(size
% 4 == 0);
1256 for (unsigned dw
= 0; dw
< size
; dw
+= 4) {
1258 blorp_emit(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
1259 cp
.DestinationMemoryAddress
= dst
;
1260 cp
.SourceMemoryAddress
= src
;
1263 /* IVB does not have a general purpose register for command streamer
1264 * commands. Therefore, we use an alternate temporary register.
1266 #define BLORP_TEMP_REG 0x2440 /* GEN7_3DPRIM_BASE_VERTEX */
1267 blorp_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), load
) {
1268 load
.RegisterAddress
= BLORP_TEMP_REG
;
1269 load
.MemoryAddress
= src
;
1271 blorp_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), store
) {
1272 store
.RegisterAddress
= BLORP_TEMP_REG
;
1273 store
.MemoryAddress
= dst
;
1275 #undef BLORP_TEMP_REG
1284 blorp_emit_surface_state(struct blorp_batch
*batch
,
1285 const struct brw_blorp_surface_info
*surface
,
1286 void *state
, uint32_t state_offset
,
1287 const bool color_write_disables
[4],
1288 bool is_render_target
)
1290 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1291 struct isl_surf surf
= surface
->surf
;
1293 if (surf
.dim
== ISL_SURF_DIM_1D
&&
1294 surf
.dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
) {
1295 assert(surf
.logical_level0_px
.height
== 1);
1296 surf
.dim
= ISL_SURF_DIM_2D
;
1299 /* Blorp doesn't support HiZ in any of the blit or slow-clear paths */
1300 enum isl_aux_usage aux_usage
= surface
->aux_usage
;
1301 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
1302 aux_usage
= ISL_AUX_USAGE_NONE
;
1304 isl_channel_mask_t write_disable_mask
= 0;
1305 if (is_render_target
&& GEN_GEN
<= 5) {
1306 if (color_write_disables
[0])
1307 write_disable_mask
|= ISL_CHANNEL_RED_BIT
;
1308 if (color_write_disables
[1])
1309 write_disable_mask
|= ISL_CHANNEL_GREEN_BIT
;
1310 if (color_write_disables
[2])
1311 write_disable_mask
|= ISL_CHANNEL_BLUE_BIT
;
1312 if (color_write_disables
[3])
1313 write_disable_mask
|= ISL_CHANNEL_ALPHA_BIT
;
1316 const bool use_clear_address
=
1317 GEN_GEN
>= 10 && (surface
->clear_color_addr
.buffer
!= NULL
);
1319 isl_surf_fill_state(batch
->blorp
->isl_dev
, state
,
1320 .surf
= &surf
, .view
= &surface
->view
,
1321 .aux_surf
= &surface
->aux_surf
, .aux_usage
= aux_usage
,
1322 .mocs
= surface
->addr
.mocs
,
1323 .clear_color
= surface
->clear_color
,
1324 .use_clear_address
= use_clear_address
,
1325 .write_disables
= write_disable_mask
);
1327 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.addr_offset
,
1330 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1331 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1332 * used to store other information. This should be ok, however, because
1333 * surface buffer addresses are always 4K page alinged.
1335 assert((surface
->aux_addr
.offset
& 0xfff) == 0);
1336 uint32_t *aux_addr
= state
+ isl_dev
->ss
.aux_addr_offset
;
1337 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.aux_addr_offset
,
1338 surface
->aux_addr
, *aux_addr
);
1341 if (surface
->clear_color_addr
.buffer
) {
1343 assert((surface
->clear_color_addr
.offset
& 0x3f) == 0);
1344 uint32_t *clear_addr
= state
+ isl_dev
->ss
.clear_color_state_offset
;
1345 blorp_surface_reloc(batch
, state_offset
+
1346 isl_dev
->ss
.clear_color_state_offset
,
1347 surface
->clear_color_addr
, *clear_addr
);
1349 struct blorp_address dst_addr
= blorp_get_surface_base_address(batch
);
1350 dst_addr
.offset
+= state_offset
+ isl_dev
->ss
.clear_value_offset
;
1351 blorp_emit_memcpy(batch
, dst_addr
, surface
->clear_color_addr
,
1352 isl_dev
->ss
.clear_value_size
);
1354 unreachable("Fast clears are only supported on gen7+");
1358 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1362 blorp_emit_null_surface_state(struct blorp_batch
*batch
,
1363 const struct brw_blorp_surface_info
*surface
,
1366 struct GENX(RENDER_SURFACE_STATE
) ss
= {
1367 .SurfaceType
= SURFTYPE_NULL
,
1368 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
1369 .Width
= surface
->surf
.logical_level0_px
.width
- 1,
1370 .Height
= surface
->surf
.logical_level0_px
.height
- 1,
1371 .MIPCountLOD
= surface
->view
.base_level
,
1372 .MinimumArrayElement
= surface
->view
.base_array_layer
,
1373 .Depth
= surface
->view
.array_len
- 1,
1374 .RenderTargetViewExtent
= surface
->view
.array_len
- 1,
1376 .NumberofMultisamples
= ffs(surface
->surf
.samples
) - 1,
1380 .SurfaceArray
= surface
->surf
.dim
!= ISL_SURF_DIM_3D
,
1386 .TiledSurface
= true,
1390 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &ss
);
1392 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1396 blorp_emit_surface_states(struct blorp_batch
*batch
,
1397 const struct blorp_params
*params
)
1399 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1400 uint32_t bind_offset
= 0, surface_offsets
[2];
1401 void *surface_maps
[2];
1403 MAYBE_UNUSED
bool has_indirect_clear_color
= false;
1404 if (params
->use_pre_baked_binding_table
) {
1405 bind_offset
= params
->pre_baked_binding_table_offset
;
1407 unsigned num_surfaces
= 1 + params
->src
.enabled
;
1408 blorp_alloc_binding_table(batch
, num_surfaces
,
1409 isl_dev
->ss
.size
, isl_dev
->ss
.align
,
1410 &bind_offset
, surface_offsets
, surface_maps
);
1412 if (params
->dst
.enabled
) {
1413 blorp_emit_surface_state(batch
, ¶ms
->dst
,
1414 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
],
1415 surface_offsets
[BLORP_RENDERBUFFER_BT_INDEX
],
1416 params
->color_write_disable
, true);
1417 if (params
->dst
.clear_color_addr
.buffer
!= NULL
)
1418 has_indirect_clear_color
= true;
1420 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1421 const struct brw_blorp_surface_info
*surface
=
1422 params
->depth
.enabled
? ¶ms
->depth
: ¶ms
->stencil
;
1423 blorp_emit_null_surface_state(batch
, surface
,
1424 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
]);
1427 if (params
->src
.enabled
) {
1428 blorp_emit_surface_state(batch
, ¶ms
->src
,
1429 surface_maps
[BLORP_TEXTURE_BT_INDEX
],
1430 surface_offsets
[BLORP_TEXTURE_BT_INDEX
],
1432 if (params
->src
.clear_color_addr
.buffer
!= NULL
)
1433 has_indirect_clear_color
= true;
1438 if (has_indirect_clear_color
) {
1439 /* Updating a surface state object may require that the state cache be
1440 * invalidated. From the SKL PRM, Shared Functions -> State -> State
1443 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
1444 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
1445 * modified [...], the L1 state cache must be invalidated to ensure
1446 * the new surface or sampler state is fetched from system memory.
1448 blorp_emit(batch
, GENX(PIPE_CONTROL
), pipe
) {
1449 pipe
.StateCacheInvalidationEnable
= true;
1455 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), bt
);
1456 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_HS
), bt
);
1457 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_DS
), bt
);
1458 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_GS
), bt
);
1460 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS
), bt
) {
1461 bt
.PointertoPSBindingTable
= bind_offset
;
1464 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1465 bt
.PSBindingTableChange
= true;
1466 bt
.PointertoPSBindingTable
= bind_offset
;
1469 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1470 bt
.PointertoPSBindingTable
= bind_offset
;
1476 blorp_emit_depth_stencil_config(struct blorp_batch
*batch
,
1477 const struct blorp_params
*params
)
1479 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1481 uint32_t *dw
= blorp_emit_dwords(batch
, isl_dev
->ds
.size
/ 4);
1485 struct isl_depth_stencil_hiz_emit_info info
= { };
1487 if (params
->depth
.enabled
) {
1488 info
.view
= ¶ms
->depth
.view
;
1489 info
.mocs
= params
->depth
.addr
.mocs
;
1490 } else if (params
->stencil
.enabled
) {
1491 info
.view
= ¶ms
->stencil
.view
;
1492 info
.mocs
= params
->stencil
.addr
.mocs
;
1495 if (params
->depth
.enabled
) {
1496 info
.depth_surf
= ¶ms
->depth
.surf
;
1498 info
.depth_address
=
1499 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.depth_offset
/ 4,
1500 params
->depth
.addr
, 0);
1502 info
.hiz_usage
= params
->depth
.aux_usage
;
1503 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
1504 info
.hiz_surf
= ¶ms
->depth
.aux_surf
;
1506 struct blorp_address hiz_address
= params
->depth
.aux_addr
;
1508 /* Sandy bridge hardware does not technically support mipmapped HiZ.
1509 * However, we have a special layout that allows us to make it work
1510 * anyway by manually offsetting to the specified miplevel.
1512 assert(info
.hiz_surf
->dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
1514 isl_surf_get_image_offset_B_tile_sa(info
.hiz_surf
,
1515 info
.view
->base_level
, 0, 0,
1516 &offset_B
, NULL
, NULL
);
1517 hiz_address
.offset
+= offset_B
;
1521 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.hiz_offset
/ 4,
1524 info
.depth_clear_value
= params
->depth
.clear_color
.f32
[0];
1528 if (params
->stencil
.enabled
) {
1529 info
.stencil_surf
= ¶ms
->stencil
.surf
;
1531 struct blorp_address stencil_address
= params
->stencil
.addr
;
1533 /* Sandy bridge hardware does not technically support mipmapped stencil.
1534 * However, we have a special layout that allows us to make it work
1535 * anyway by manually offsetting to the specified miplevel.
1537 assert(info
.stencil_surf
->dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
1539 isl_surf_get_image_offset_B_tile_sa(info
.stencil_surf
,
1540 info
.view
->base_level
, 0, 0,
1541 &offset_B
, NULL
, NULL
);
1542 stencil_address
.offset
+= offset_B
;
1545 info
.stencil_address
=
1546 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.stencil_offset
/ 4,
1547 stencil_address
, 0);
1550 isl_emit_depth_stencil_hiz_s(isl_dev
, dw
, &info
);
1554 /* Emits the Optimized HiZ sequence specified in the BDW+ PRMs. The
1555 * depth/stencil buffer extents are ignored to handle APIs which perform
1556 * clearing operations without such information.
1559 blorp_emit_gen8_hiz_op(struct blorp_batch
*batch
,
1560 const struct blorp_params
*params
)
1562 /* We should be performing an operation on a depth or stencil buffer.
1564 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1566 /* The stencil buffer should only be enabled if a fast clear operation is
1569 if (params
->stencil
.enabled
)
1570 assert(params
->hiz_op
== ISL_AUX_OP_FAST_CLEAR
);
1572 /* From the BDW PRM Volume 2, 3DSTATE_WM_HZ_OP:
1574 * 3DSTATE_MULTISAMPLE packet must be used prior to this packet to change
1575 * the Number of Multisamples. This packet must not be used to change
1576 * Number of Multisamples in a rendering sequence.
1578 * Since HIZ may be the first thing in a batch buffer, play safe and always
1579 * emit 3DSTATE_MULTISAMPLE.
1581 blorp_emit_3dstate_multisample(batch
, params
);
1583 /* If we can't alter the depth stencil config and multiple layers are
1584 * involved, the HiZ op will fail. This is because the op requires that a
1585 * new config is emitted for each additional layer.
1587 if (batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
) {
1588 assert(params
->num_layers
<= 1);
1590 blorp_emit_depth_stencil_config(batch
, params
);
1593 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
) {
1594 switch (params
->hiz_op
) {
1595 case ISL_AUX_OP_FAST_CLEAR
:
1596 hzp
.StencilBufferClearEnable
= params
->stencil
.enabled
;
1597 hzp
.DepthBufferClearEnable
= params
->depth
.enabled
;
1598 hzp
.StencilClearValue
= params
->stencil_ref
;
1599 hzp
.FullSurfaceDepthandStencilClear
= params
->full_surface_hiz_op
;
1601 case ISL_AUX_OP_FULL_RESOLVE
:
1602 assert(params
->full_surface_hiz_op
);
1603 hzp
.DepthBufferResolveEnable
= true;
1605 case ISL_AUX_OP_AMBIGUATE
:
1606 assert(params
->full_surface_hiz_op
);
1607 hzp
.HierarchicalDepthBufferResolveEnable
= true;
1609 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1610 case ISL_AUX_OP_NONE
:
1611 unreachable("Invalid HIZ op");
1614 hzp
.NumberofMultisamples
= ffs(params
->num_samples
) - 1;
1615 hzp
.SampleMask
= 0xFFFF;
1617 /* Due to a hardware issue, this bit MBZ */
1618 assert(hzp
.ScissorRectangleEnable
== false);
1620 /* Contrary to the HW docs both fields are inclusive */
1621 hzp
.ClearRectangleXMin
= params
->x0
;
1622 hzp
.ClearRectangleYMin
= params
->y0
;
1624 /* Contrary to the HW docs both fields are exclusive */
1625 hzp
.ClearRectangleXMax
= params
->x1
;
1626 hzp
.ClearRectangleYMax
= params
->y1
;
1629 /* PIPE_CONTROL w/ all bits clear except for “Post-Sync Operation” must set
1630 * to “Write Immediate Data” enabled.
1632 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1633 pc
.PostSyncOperation
= WriteImmediateData
;
1634 pc
.Address
= blorp_get_workaround_page(batch
);
1637 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
);
1642 * \brief Execute a blit or render pass operation.
1644 * To execute the operation, this function manually constructs and emits a
1645 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1646 * constructing and after emitting the batch.
1648 * This function alters no GL state.
1651 blorp_exec(struct blorp_batch
*batch
, const struct blorp_params
*params
)
1654 if (params
->hiz_op
!= ISL_AUX_OP_NONE
) {
1655 blorp_emit_gen8_hiz_op(batch
, params
);
1660 blorp_emit_vertex_buffers(batch
, params
);
1661 blorp_emit_vertex_elements(batch
, params
);
1663 blorp_emit_pipeline(batch
, params
);
1665 blorp_emit_surface_states(batch
, params
);
1667 if (!(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
))
1668 blorp_emit_depth_stencil_config(batch
, params
);
1670 blorp_emit(batch
, GENX(3DPRIMITIVE
), prim
) {
1671 prim
.VertexAccessType
= SEQUENTIAL
;
1672 prim
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
1674 prim
.PredicateEnable
= batch
->flags
& BLORP_BATCH_PREDICATE_ENABLE
;
1676 prim
.VertexCountPerInstance
= 3;
1677 prim
.InstanceCount
= params
->num_layers
;
1681 #endif /* BLORP_GENX_EXEC_H */