2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BLORP_GENX_EXEC_H
25 #define BLORP_GENX_EXEC_H
27 #include "blorp_priv.h"
28 #include "common/gen_device_info.h"
29 #include "common/gen_sample_positions.h"
30 #include "genxml/gen_macros.h"
33 * This file provides the blorp pipeline setup and execution functionality.
34 * It defines the following function:
37 * blorp_exec(struct blorp_context *blorp, void *batch_data,
38 * const struct blorp_params *params);
40 * It is the job of whoever includes this header to wrap this in something
41 * to get an externally visible symbol.
43 * In order for the blorp_exec function to work, the driver must provide
44 * implementations of the following static helper functions.
48 blorp_emit_dwords(struct blorp_batch
*batch
, unsigned n
);
51 blorp_emit_reloc(struct blorp_batch
*batch
,
52 void *location
, struct blorp_address address
, uint32_t delta
);
55 blorp_alloc_dynamic_state(struct blorp_batch
*batch
,
60 blorp_alloc_vertex_buffer(struct blorp_batch
*batch
, uint32_t size
,
61 struct blorp_address
*addr
);
64 static struct blorp_address
65 blorp_get_workaround_page(struct blorp_batch
*batch
);
69 blorp_alloc_binding_table(struct blorp_batch
*batch
, unsigned num_entries
,
70 unsigned state_size
, unsigned state_alignment
,
71 uint32_t *bt_offset
, uint32_t *surface_offsets
,
75 blorp_flush_range(struct blorp_batch
*batch
, void *start
, size_t size
);
78 blorp_surface_reloc(struct blorp_batch
*batch
, uint32_t ss_offset
,
79 struct blorp_address address
, uint32_t delta
);
82 static struct blorp_address
83 blorp_get_surface_base_address(struct blorp_batch
*batch
);
87 blorp_emit_urb_config(struct blorp_batch
*batch
,
88 unsigned vs_entry_size
, unsigned sf_entry_size
);
91 blorp_emit_pipeline(struct blorp_batch
*batch
,
92 const struct blorp_params
*params
);
94 /***** BEGIN blorp_exec implementation ******/
97 _blorp_combine_address(struct blorp_batch
*batch
, void *location
,
98 struct blorp_address address
, uint32_t delta
)
100 if (address
.buffer
== NULL
) {
101 return address
.offset
+ delta
;
103 return blorp_emit_reloc(batch
, location
, address
, delta
);
107 #define __gen_address_type struct blorp_address
108 #define __gen_user_data struct blorp_batch
109 #define __gen_combine_address _blorp_combine_address
111 #include "genxml/genX_pack.h"
113 #define _blorp_cmd_length(cmd) cmd ## _length
114 #define _blorp_cmd_length_bias(cmd) cmd ## _length_bias
115 #define _blorp_cmd_header(cmd) cmd ## _header
116 #define _blorp_cmd_pack(cmd) cmd ## _pack
118 #define blorp_emit(batch, cmd, name) \
119 for (struct cmd name = { _blorp_cmd_header(cmd) }, \
120 *_dst = blorp_emit_dwords(batch, _blorp_cmd_length(cmd)); \
121 __builtin_expect(_dst != NULL, 1); \
122 _blorp_cmd_pack(cmd)(batch, (void *)_dst, &name), \
125 #define blorp_emitn(batch, cmd, n) ({ \
126 uint32_t *_dw = blorp_emit_dwords(batch, n); \
128 struct cmd template = { \
129 _blorp_cmd_header(cmd), \
130 .DWordLength = n - _blorp_cmd_length_bias(cmd), \
132 _blorp_cmd_pack(cmd)(batch, _dw, &template); \
134 _dw ? _dw + 1 : NULL; /* Array starts at dw[1] */ \
137 #define STRUCT_ZERO(S) ({ struct S t; memset(&t, 0, sizeof(t)); t; })
139 #define blorp_emit_dynamic(batch, state, name, align, offset) \
140 for (struct state name = STRUCT_ZERO(state), \
141 *_dst = blorp_alloc_dynamic_state(batch, \
142 _blorp_cmd_length(state) * 4, \
144 __builtin_expect(_dst != NULL, 1); \
145 _blorp_cmd_pack(state)(batch, (void *)_dst, &name), \
146 blorp_flush_range(batch, _dst, _blorp_cmd_length(state) * 4), \
155 * Assign the entire URB to the VS. Even though the VS disabled, URB space
156 * is still needed because the clipper loads the VUE's from the URB. From
157 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
158 * Dword 1.15:0 "VS Number of URB Entries":
159 * This field is always used (even if VS Function Enable is DISABLED).
161 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
162 * safely ignore it because this batch contains only one draw call.
163 * Because of URB corruption caused by allocating a previous GS unit
164 * URB entry to the VS unit, software is required to send a “GS NULL
165 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
166 * plus a dummy DRAW call before any case where VS will be taking over
169 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
170 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
172 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
173 * programmed in order for the programming of this state to be
177 emit_urb_config(struct blorp_batch
*batch
,
178 const struct blorp_params
*params
)
180 /* Once vertex fetcher has written full VUE entries with complete
181 * header the space requirement is as follows per vertex (in bytes):
183 * Header Position Program constants
184 * +--------+------------+-------------------+
185 * | 16 | 16 | n x 16 |
186 * +--------+------------+-------------------+
188 * where 'n' stands for number of varying inputs expressed as vec4s.
190 const unsigned num_varyings
=
191 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
192 const unsigned total_needed
= 16 + 16 + num_varyings
* 16;
194 /* The URB size is expressed in units of 64 bytes (512 bits) */
195 const unsigned vs_entry_size
= DIV_ROUND_UP(total_needed
, 64);
197 const unsigned sf_entry_size
=
198 params
->sf_prog_data
? params
->sf_prog_data
->urb_entry_size
: 0;
200 blorp_emit_urb_config(batch
, vs_entry_size
, sf_entry_size
);
204 blorp_emit_vertex_data(struct blorp_batch
*batch
,
205 const struct blorp_params
*params
,
206 struct blorp_address
*addr
,
209 const float vertices
[] = {
210 /* v0 */ (float)params
->x1
, (float)params
->y1
, params
->z
,
211 /* v1 */ (float)params
->x0
, (float)params
->y1
, params
->z
,
212 /* v2 */ (float)params
->x0
, (float)params
->y0
, params
->z
,
215 void *data
= blorp_alloc_vertex_buffer(batch
, sizeof(vertices
), addr
);
216 memcpy(data
, vertices
, sizeof(vertices
));
217 *size
= sizeof(vertices
);
218 blorp_flush_range(batch
, data
, *size
);
222 blorp_emit_input_varying_data(struct blorp_batch
*batch
,
223 const struct blorp_params
*params
,
224 struct blorp_address
*addr
,
227 const unsigned vec4_size_in_bytes
= 4 * sizeof(float);
228 const unsigned max_num_varyings
=
229 DIV_ROUND_UP(sizeof(params
->wm_inputs
), vec4_size_in_bytes
);
230 const unsigned num_varyings
=
231 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
233 *size
= 16 + num_varyings
* vec4_size_in_bytes
;
235 const uint32_t *const inputs_src
= (const uint32_t *)¶ms
->wm_inputs
;
236 void *data
= blorp_alloc_vertex_buffer(batch
, *size
, addr
);
237 uint32_t *inputs
= data
;
239 /* Copy in the VS inputs */
240 assert(sizeof(params
->vs_inputs
) == 16);
241 memcpy(inputs
, ¶ms
->vs_inputs
, sizeof(params
->vs_inputs
));
244 if (params
->wm_prog_data
) {
245 /* Walk over the attribute slots, determine if the attribute is used by
246 * the program and when necessary copy the values from the input storage
247 * to the vertex data buffer.
249 for (unsigned i
= 0; i
< max_num_varyings
; i
++) {
250 const gl_varying_slot attr
= VARYING_SLOT_VAR0
+ i
;
252 const int input_index
= params
->wm_prog_data
->urb_setup
[attr
];
256 memcpy(inputs
, inputs_src
+ i
* 4, vec4_size_in_bytes
);
262 blorp_flush_range(batch
, data
, *size
);
266 blorp_emit_vertex_buffers(struct blorp_batch
*batch
,
267 const struct blorp_params
*params
)
269 struct GENX(VERTEX_BUFFER_STATE
) vb
[2];
270 memset(vb
, 0, sizeof(vb
));
273 blorp_emit_vertex_data(batch
, params
, &vb
[0].BufferStartingAddress
, &size
);
274 vb
[0].VertexBufferIndex
= 0;
275 vb
[0].BufferPitch
= 3 * sizeof(float);
277 vb
[0].VertexBufferMOCS
= vb
[0].BufferStartingAddress
.mocs
;
280 vb
[0].AddressModifyEnable
= true;
283 vb
[0].BufferSize
= size
;
285 vb
[0].BufferAccessType
= VERTEXDATA
;
286 vb
[0].EndAddress
= vb
[0].BufferStartingAddress
;
287 vb
[0].EndAddress
.offset
+= size
- 1;
289 vb
[0].BufferAccessType
= VERTEXDATA
;
293 blorp_emit_input_varying_data(batch
, params
,
294 &vb
[1].BufferStartingAddress
, &size
);
295 vb
[1].VertexBufferIndex
= 1;
296 vb
[1].BufferPitch
= 0;
298 vb
[1].VertexBufferMOCS
= vb
[1].BufferStartingAddress
.mocs
;
301 vb
[1].AddressModifyEnable
= true;
304 vb
[1].BufferSize
= size
;
306 vb
[1].BufferAccessType
= INSTANCEDATA
;
307 vb
[1].EndAddress
= vb
[1].BufferStartingAddress
;
308 vb
[1].EndAddress
.offset
+= size
- 1;
310 vb
[1].BufferAccessType
= INSTANCEDATA
;
314 const unsigned num_dwords
= 1 + GENX(VERTEX_BUFFER_STATE_length
) * 2;
315 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), num_dwords
);
319 for (unsigned i
= 0; i
< 2; i
++) {
320 GENX(VERTEX_BUFFER_STATE_pack
)(batch
, dw
, &vb
[i
]);
321 dw
+= GENX(VERTEX_BUFFER_STATE_length
);
326 blorp_emit_vertex_elements(struct blorp_batch
*batch
,
327 const struct blorp_params
*params
)
329 const unsigned num_varyings
=
330 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
331 bool need_ndc
= batch
->blorp
->compiler
->devinfo
->gen
<= 5;
332 const unsigned num_elements
= 2 + need_ndc
+ num_varyings
;
334 struct GENX(VERTEX_ELEMENT_STATE
) ve
[num_elements
];
335 memset(ve
, 0, num_elements
* sizeof(*ve
));
337 /* Setup VBO for the rectangle primitive..
339 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
340 * vertices. The vertices reside in screen space with DirectX
341 * coordinates (that is, (0, 0) is the upper left corner).
348 * Since the VS is disabled, the clipper loads each VUE directly from
349 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
350 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
351 * dw0: Reserved, MBZ.
352 * dw1: Render Target Array Index. Below vertex fetcher gets programmed
353 * to assign this with primitive instance identifier which will be
354 * used for layered clears. All other renders have only one instance
355 * and therefore the value will be effectively zero.
356 * dw2: Viewport Index. The HiZ op disables viewport mapping and
357 * scissoring, so set the dword to 0.
358 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive,
359 * so set the dword to 0.
360 * dw4: Vertex Position X.
361 * dw5: Vertex Position Y.
362 * dw6: Vertex Position Z.
363 * dw7: Vertex Position W.
365 * dw8: Flat vertex input 0
366 * dw9: Flat vertex input 1
368 * dwn: Flat vertex input n - 8
370 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
371 * "Vertex URB Entry (VUE) Formats".
373 * Only vertex position X and Y are going to be variable, Z is fixed to
374 * zero and W to one. Header words dw0,2,3 are zero. There is no need to
375 * include the fixed values in the vertex buffer. Vertex fetcher can be
376 * instructed to fill vertex elements with constant values of one and zero
377 * instead of reading them from the buffer.
378 * Flat inputs are program constants that are not interpolated. Moreover
379 * their values will be the same between vertices.
381 * See the vertex element setup below.
385 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
386 .VertexBufferIndex
= 1,
388 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32B32A32_FLOAT
,
389 .SourceElementOffset
= 0,
390 .Component0Control
= VFCOMP_STORE_SRC
,
392 /* From Gen8 onwards hardware is no more instructed to overwrite
393 * components using an element specifier. Instead one has separate
394 * 3DSTATE_VF_SGVS (System Generated Value Setup) state packet for it.
397 .Component1Control
= VFCOMP_STORE_0
,
399 .Component1Control
= VFCOMP_STORE_IID
,
401 .Component1Control
= VFCOMP_STORE_0
,
403 .Component2Control
= VFCOMP_STORE_0
,
404 .Component3Control
= VFCOMP_STORE_0
,
406 .DestinationElementOffset
= slot
* 4,
412 /* On Iron Lake and earlier, a native device coordinates version of the
413 * position goes right after the normal VUE header and before position.
414 * Since w == 1 for all of our coordinates, this is just a copy of the
417 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
418 .VertexBufferIndex
= 0,
420 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32B32_FLOAT
,
421 .SourceElementOffset
= 0,
422 .Component0Control
= VFCOMP_STORE_SRC
,
423 .Component1Control
= VFCOMP_STORE_SRC
,
424 .Component2Control
= VFCOMP_STORE_SRC
,
425 .Component3Control
= VFCOMP_STORE_1_FP
,
426 .DestinationElementOffset
= slot
* 4,
431 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
432 .VertexBufferIndex
= 0,
434 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32B32_FLOAT
,
435 .SourceElementOffset
= 0,
436 .Component0Control
= VFCOMP_STORE_SRC
,
437 .Component1Control
= VFCOMP_STORE_SRC
,
438 .Component2Control
= VFCOMP_STORE_SRC
,
439 .Component3Control
= VFCOMP_STORE_1_FP
,
441 .DestinationElementOffset
= slot
* 4,
446 for (unsigned i
= 0; i
< num_varyings
; ++i
) {
447 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
448 .VertexBufferIndex
= 1,
450 .SourceElementFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R32G32B32A32_FLOAT
,
451 .SourceElementOffset
= 16 + i
* 4 * sizeof(float),
452 .Component0Control
= VFCOMP_STORE_SRC
,
453 .Component1Control
= VFCOMP_STORE_SRC
,
454 .Component2Control
= VFCOMP_STORE_SRC
,
455 .Component3Control
= VFCOMP_STORE_SRC
,
457 .DestinationElementOffset
= slot
* 4,
463 const unsigned num_dwords
=
464 1 + GENX(VERTEX_ELEMENT_STATE_length
) * num_elements
;
465 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_ELEMENTS
), num_dwords
);
469 for (unsigned i
= 0; i
< num_elements
; i
++) {
470 GENX(VERTEX_ELEMENT_STATE_pack
)(batch
, dw
, &ve
[i
]);
471 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
475 /* Overwrite Render Target Array Index (2nd dword) in the VUE header with
476 * primitive instance identifier. This is used for layered clears.
478 blorp_emit(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
479 sgvs
.InstanceIDEnable
= true;
480 sgvs
.InstanceIDComponentNumber
= COMP_1
;
481 sgvs
.InstanceIDElementOffset
= 0;
484 for (unsigned i
= 0; i
< num_elements
; i
++) {
485 blorp_emit(batch
, GENX(3DSTATE_VF_INSTANCING
), vf
) {
486 vf
.VertexElementIndex
= i
;
487 vf
.InstancingEnable
= false;
491 blorp_emit(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
492 topo
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
497 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
499 blorp_emit_cc_viewport(struct blorp_batch
*batch
,
500 const struct blorp_params
*params
)
502 uint32_t cc_vp_offset
;
503 blorp_emit_dynamic(batch
, GENX(CC_VIEWPORT
), vp
, 32, &cc_vp_offset
) {
504 vp
.MinimumDepth
= 0.0;
505 vp
.MaximumDepth
= 1.0;
509 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), vsp
) {
510 vsp
.CCViewportPointer
= cc_vp_offset
;
513 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vsp
) {
514 vsp
.CCViewportStateChange
= true;
515 vsp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
523 blorp_emit_sampler_state(struct blorp_batch
*batch
,
524 const struct blorp_params
*params
)
527 blorp_emit_dynamic(batch
, GENX(SAMPLER_STATE
), sampler
, 32, &offset
) {
528 sampler
.MipModeFilter
= MIPFILTER_NONE
;
529 sampler
.MagModeFilter
= MAPFILTER_LINEAR
;
530 sampler
.MinModeFilter
= MAPFILTER_LINEAR
;
533 sampler
.TCXAddressControlMode
= TCM_CLAMP
;
534 sampler
.TCYAddressControlMode
= TCM_CLAMP
;
535 sampler
.TCZAddressControlMode
= TCM_CLAMP
;
536 sampler
.MaximumAnisotropy
= RATIO21
;
537 sampler
.RAddressMinFilterRoundingEnable
= true;
538 sampler
.RAddressMagFilterRoundingEnable
= true;
539 sampler
.VAddressMinFilterRoundingEnable
= true;
540 sampler
.VAddressMagFilterRoundingEnable
= true;
541 sampler
.UAddressMinFilterRoundingEnable
= true;
542 sampler
.UAddressMagFilterRoundingEnable
= true;
544 sampler
.NonnormalizedCoordinateEnable
= true;
549 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS
), ssp
) {
550 ssp
.PointertoPSSamplerState
= offset
;
553 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS
), ssp
) {
554 ssp
.VSSamplerStateChange
= true;
555 ssp
.GSSamplerStateChange
= true;
556 ssp
.PSSamplerStateChange
= true;
557 ssp
.PointertoPSSamplerState
= offset
;
564 /* What follows is the code for setting up a "pipeline" on Sandy Bridge and
565 * later hardware. This file will be included by i965 for gen4-5 as well, so
566 * this code is guarded by GEN_GEN >= 6.
571 blorp_emit_vs_config(struct blorp_batch
*batch
,
572 const struct blorp_params
*params
)
574 struct brw_vs_prog_data
*vs_prog_data
= params
->vs_prog_data
;
576 blorp_emit(batch
, GENX(3DSTATE_VS
), vs
) {
580 vs
.KernelStartPointer
= params
->vs_prog_kernel
;
582 vs
.DispatchGRFStartRegisterForURBData
=
583 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
584 vs
.VertexURBEntryReadLength
=
585 vs_prog_data
->base
.urb_read_length
;
586 vs
.VertexURBEntryReadOffset
= 0;
588 vs
.MaximumNumberofThreads
=
589 batch
->blorp
->isl_dev
->info
->max_vs_threads
- 1;
592 vs
.SIMD8DispatchEnable
=
593 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
600 blorp_emit_sf_config(struct blorp_batch
*batch
,
601 const struct blorp_params
*params
)
603 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
607 * Disable ViewportTransformEnable (dw2.1)
609 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
610 * Primitives Overview":
611 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
612 * use of screen- space coordinates).
614 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
615 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
617 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
618 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
619 * SOLID: Any triangle or rectangle object found to be front-facing
620 * is rendered as a solid object. This setting is required when
621 * (rendering rectangle (RECTLIST) objects.
626 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
);
628 blorp_emit(batch
, GENX(3DSTATE_RASTER
), raster
) {
629 raster
.CullMode
= CULLMODE_NONE
;
632 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
633 sbe
.VertexURBEntryReadOffset
= 1;
635 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
636 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
637 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
639 sbe
.NumberofSFOutputAttributes
= 0;
640 sbe
.VertexURBEntryReadLength
= 1;
642 sbe
.ForceVertexURBEntryReadLength
= true;
643 sbe
.ForceVertexURBEntryReadOffset
= true;
646 for (unsigned i
= 0; i
< 32; i
++)
647 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
653 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
654 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
655 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
657 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
658 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
661 sf
.DepthBufferSurfaceFormat
= params
->depth_format
;
665 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
666 sbe
.VertexURBEntryReadOffset
= 1;
668 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
669 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
670 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
672 sbe
.NumberofSFOutputAttributes
= 0;
673 sbe
.VertexURBEntryReadLength
= 1;
677 #else /* GEN_GEN <= 6 */
679 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
680 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
681 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
683 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
684 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
686 sf
.VertexURBEntryReadOffset
= 1;
688 sf
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
689 sf
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
690 sf
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
692 sf
.NumberofSFOutputAttributes
= 0;
693 sf
.VertexURBEntryReadLength
= 1;
701 blorp_emit_ps_config(struct blorp_batch
*batch
,
702 const struct blorp_params
*params
)
704 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
706 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
707 * nonzero to prevent the GPU from hanging. While the documentation doesn't
708 * mention this explicitly, it notes that the valid range for the field is
709 * [1,39] = [2,40] threads, which excludes zero.
711 * To be safe (and to minimize extraneous code) we go ahead and fully
712 * configure the WM state whether or not there is a WM program.
717 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
719 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
720 if (params
->src
.enabled
) {
721 ps
.SamplerCount
= 1; /* Up to 4 samplers */
722 ps
.BindingTableEntryCount
= 2;
724 ps
.BindingTableEntryCount
= 1;
728 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
729 prog_data
->base
.dispatch_grf_start_reg
;
730 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
731 prog_data
->dispatch_grf_start_reg_2
;
733 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
734 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
736 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
737 ps
.KernelStartPointer2
=
738 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
741 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
742 * it implicitly scales for different GT levels (which have some # of
745 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
748 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
750 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
752 switch (params
->fast_clear_op
) {
753 case ISL_AUX_OP_NONE
:
756 case ISL_AUX_OP_PARTIAL_RESOLVE
:
757 ps
.RenderTargetResolveType
= RESOLVE_PARTIAL
;
759 case ISL_AUX_OP_FULL_RESOLVE
:
760 ps
.RenderTargetResolveType
= RESOLVE_FULL
;
763 case ISL_AUX_OP_FULL_RESOLVE
:
764 ps
.RenderTargetResolveEnable
= true;
767 case ISL_AUX_OP_FAST_CLEAR
:
768 ps
.RenderTargetFastClearEnable
= true;
771 unreachable("Invalid fast clear op");
775 blorp_emit(batch
, GENX(3DSTATE_PS_EXTRA
), psx
) {
777 psx
.PixelShaderValid
= true;
778 psx
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
779 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
782 if (params
->src
.enabled
)
783 psx
.PixelShaderKillsPixel
= true;
788 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
789 switch (params
->hiz_op
) {
790 case BLORP_HIZ_OP_DEPTH_CLEAR
:
791 wm
.DepthBufferClear
= true;
793 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
794 wm
.DepthBufferResolveEnable
= true;
796 case BLORP_HIZ_OP_HIZ_RESOLVE
:
797 wm
.HierarchicalDepthBufferResolveEnable
= true;
799 case BLORP_HIZ_OP_NONE
:
802 unreachable("not reached");
806 wm
.ThreadDispatchEnable
= true;
808 if (params
->src
.enabled
)
809 wm
.PixelShaderKillsPixel
= true;
811 if (params
->num_samples
> 1) {
812 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
813 wm
.MultisampleDispatchMode
=
814 (prog_data
&& prog_data
->persample_dispatch
) ?
815 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
817 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
818 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
822 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
823 ps
.MaximumNumberofThreads
=
824 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
831 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
832 prog_data
->base
.dispatch_grf_start_reg
;
833 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
834 prog_data
->dispatch_grf_start_reg_2
;
836 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
837 ps
.KernelStartPointer2
=
838 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
840 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
841 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
843 ps
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
845 /* Gen7 hardware gets angry if we don't enable at least one dispatch
846 * mode, so just enable 16-pixel dispatch if we don't have a program.
848 ps
._16PixelDispatchEnable
= true;
851 if (params
->src
.enabled
)
852 ps
.SamplerCount
= 1; /* Up to 4 samplers */
854 switch (params
->fast_clear_op
) {
855 case ISL_AUX_OP_NONE
:
857 case ISL_AUX_OP_FULL_RESOLVE
:
858 ps
.RenderTargetResolveEnable
= true;
860 case ISL_AUX_OP_FAST_CLEAR
:
861 ps
.RenderTargetFastClearEnable
= true;
864 unreachable("Invalid fast clear op");
868 #else /* GEN_GEN <= 6 */
870 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
871 wm
.MaximumNumberofThreads
=
872 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
874 switch (params
->hiz_op
) {
875 case BLORP_HIZ_OP_DEPTH_CLEAR
:
876 wm
.DepthBufferClear
= true;
878 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
879 wm
.DepthBufferResolveEnable
= true;
881 case BLORP_HIZ_OP_HIZ_RESOLVE
:
882 wm
.HierarchicalDepthBufferResolveEnable
= true;
884 case BLORP_HIZ_OP_NONE
:
887 unreachable("not reached");
891 wm
.ThreadDispatchEnable
= true;
893 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
894 prog_data
->base
.dispatch_grf_start_reg
;
895 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
896 prog_data
->dispatch_grf_start_reg_2
;
898 wm
.KernelStartPointer0
= params
->wm_prog_kernel
;
899 wm
.KernelStartPointer2
=
900 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
902 wm
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
903 wm
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
905 wm
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
908 if (params
->src
.enabled
) {
909 wm
.SamplerCount
= 1; /* Up to 4 samplers */
910 wm
.PixelShaderKillsPixel
= true; /* TODO: temporarily smash on */
913 if (params
->num_samples
> 1) {
914 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
915 wm
.MultisampleDispatchMode
=
916 (prog_data
&& prog_data
->persample_dispatch
) ?
917 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
919 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
920 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
928 blorp_emit_blend_state(struct blorp_batch
*batch
,
929 const struct blorp_params
*params
)
931 struct GENX(BLEND_STATE
) blend
;
932 memset(&blend
, 0, sizeof(blend
));
935 int size
= GENX(BLEND_STATE_length
) * 4;
936 size
+= GENX(BLEND_STATE_ENTRY_length
) * 4 * params
->num_draw_buffers
;
937 uint32_t *state
= blorp_alloc_dynamic_state(batch
, size
, 64, &offset
);
938 uint32_t *pos
= state
;
940 GENX(BLEND_STATE_pack
)(NULL
, pos
, &blend
);
941 pos
+= GENX(BLEND_STATE_length
);
943 for (unsigned i
= 0; i
< params
->num_draw_buffers
; ++i
) {
944 struct GENX(BLEND_STATE_ENTRY
) entry
= {
945 .PreBlendColorClampEnable
= true,
946 .PostBlendColorClampEnable
= true,
947 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
949 .WriteDisableRed
= params
->color_write_disable
[0],
950 .WriteDisableGreen
= params
->color_write_disable
[1],
951 .WriteDisableBlue
= params
->color_write_disable
[2],
952 .WriteDisableAlpha
= params
->color_write_disable
[3],
954 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, pos
, &entry
);
955 pos
+= GENX(BLEND_STATE_ENTRY_length
);
958 blorp_flush_range(batch
, state
, size
);
961 blorp_emit(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), sp
) {
962 sp
.BlendStatePointer
= offset
;
964 sp
.BlendStatePointerValid
= true;
970 blorp_emit(batch
, GENX(3DSTATE_PS_BLEND
), ps_blend
) {
971 ps_blend
.HasWriteableRT
= true;
979 blorp_emit_color_calc_state(struct blorp_batch
*batch
,
980 const struct blorp_params
*params
)
983 blorp_emit_dynamic(batch
, GENX(COLOR_CALC_STATE
), cc
, 64, &offset
) {
985 cc
.StencilReferenceValue
= params
->stencil_ref
;
990 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), sp
) {
991 sp
.ColorCalcStatePointer
= offset
;
993 sp
.ColorCalcStatePointerValid
= true;
1002 blorp_emit_depth_stencil_state(struct blorp_batch
*batch
,
1003 const struct blorp_params
*params
)
1006 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) ds
= {
1007 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
1010 struct GENX(DEPTH_STENCIL_STATE
) ds
= { 0 };
1013 if (params
->depth
.enabled
) {
1014 ds
.DepthBufferWriteEnable
= true;
1016 switch (params
->hiz_op
) {
1017 case BLORP_HIZ_OP_NONE
:
1018 ds
.DepthTestEnable
= true;
1019 ds
.DepthTestFunction
= COMPAREFUNCTION_ALWAYS
;
1022 /* See the following sections of the Sandy Bridge PRM, Volume 2, Part1:
1023 * - 7.5.3.1 Depth Buffer Clear
1024 * - 7.5.3.2 Depth Buffer Resolve
1025 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1027 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
1028 ds
.DepthTestEnable
= true;
1029 ds
.DepthTestFunction
= COMPAREFUNCTION_NEVER
;
1032 case BLORP_HIZ_OP_DEPTH_CLEAR
:
1033 case BLORP_HIZ_OP_HIZ_RESOLVE
:
1034 ds
.DepthTestEnable
= false;
1039 if (params
->stencil
.enabled
) {
1040 ds
.StencilBufferWriteEnable
= true;
1041 ds
.StencilTestEnable
= true;
1042 ds
.DoubleSidedStencilEnable
= false;
1044 ds
.StencilTestFunction
= COMPAREFUNCTION_ALWAYS
;
1045 ds
.StencilPassDepthPassOp
= STENCILOP_REPLACE
;
1047 ds
.StencilWriteMask
= params
->stencil_mask
;
1049 ds
.StencilReferenceValue
= params
->stencil_ref
;
1054 uint32_t offset
= 0;
1055 uint32_t *dw
= blorp_emit_dwords(batch
,
1056 GENX(3DSTATE_WM_DEPTH_STENCIL_length
));
1060 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dw
, &ds
);
1063 void *state
= blorp_alloc_dynamic_state(batch
,
1064 GENX(DEPTH_STENCIL_STATE_length
) * 4,
1066 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, state
, &ds
);
1067 blorp_flush_range(batch
, state
, GENX(DEPTH_STENCIL_STATE_length
) * 4);
1071 blorp_emit(batch
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), sp
) {
1072 sp
.PointertoDEPTH_STENCIL_STATE
= offset
;
1080 blorp_emit_3dstate_multisample(struct blorp_batch
*batch
,
1081 const struct blorp_params
*params
)
1083 blorp_emit(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1084 ms
.NumberofMultisamples
= __builtin_ffs(params
->num_samples
) - 1;
1087 /* The PRM says that this bit is valid only for DX9:
1089 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
1090 * should not have any effect by setting or not setting this bit.
1092 ms
.PixelPositionOffsetEnable
= false;
1095 switch (params
->num_samples
) {
1097 GEN_SAMPLE_POS_1X(ms
.Sample
);
1100 GEN_SAMPLE_POS_2X(ms
.Sample
);
1103 GEN_SAMPLE_POS_4X(ms
.Sample
);
1106 GEN_SAMPLE_POS_8X(ms
.Sample
);
1112 GEN_SAMPLE_POS_4X(ms
.Sample
);
1114 ms
.PixelLocation
= CENTER
;
1119 blorp_emit_pipeline(struct blorp_batch
*batch
,
1120 const struct blorp_params
*params
)
1122 uint32_t blend_state_offset
= 0;
1123 uint32_t color_calc_state_offset
;
1124 uint32_t depth_stencil_state_offset
;
1126 emit_urb_config(batch
, params
);
1128 if (params
->wm_prog_data
) {
1129 blend_state_offset
= blorp_emit_blend_state(batch
, params
);
1131 color_calc_state_offset
= blorp_emit_color_calc_state(batch
, params
);
1132 depth_stencil_state_offset
= blorp_emit_depth_stencil_state(batch
, params
);
1135 /* 3DSTATE_CC_STATE_POINTERS
1137 * The pointer offsets are relative to
1138 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
1140 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
1142 * The dynamic state emit helpers emit their own STATE_POINTERS packets on
1143 * gen7+. However, on gen6 and earlier, they're all lumpped together in
1144 * one CC_STATE_POINTERS packet so we have to emit that here.
1146 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), cc
) {
1147 cc
.BLEND_STATEChange
= true;
1148 cc
.ColorCalcStatePointerValid
= true;
1149 cc
.DEPTH_STENCIL_STATEChange
= true;
1150 cc
.PointertoBLEND_STATE
= blend_state_offset
;
1151 cc
.ColorCalcStatePointer
= color_calc_state_offset
;
1152 cc
.PointertoDEPTH_STENCIL_STATE
= depth_stencil_state_offset
;
1155 (void)blend_state_offset
;
1156 (void)color_calc_state_offset
;
1157 (void)depth_stencil_state_offset
;
1160 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_VS
), vs
);
1162 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_HS
), hs
);
1163 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_DS
), DS
);
1165 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_GS
), gs
);
1166 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_PS
), ps
);
1168 if (params
->src
.enabled
)
1169 blorp_emit_sampler_state(batch
, params
);
1171 blorp_emit_3dstate_multisample(batch
, params
);
1173 blorp_emit(batch
, GENX(3DSTATE_SAMPLE_MASK
), mask
) {
1174 mask
.SampleMask
= (1 << params
->num_samples
) - 1;
1177 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1178 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1180 * [DevSNB] A pipeline flush must be programmed prior to a
1181 * 3DSTATE_VS command that causes the VS Function Enable to
1182 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
1183 * command with CS stall bit set and a post sync operation.
1185 * We've already done one at the start of the BLORP operation.
1187 blorp_emit_vs_config(batch
, params
);
1189 blorp_emit(batch
, GENX(3DSTATE_HS
), hs
);
1190 blorp_emit(batch
, GENX(3DSTATE_TE
), te
);
1191 blorp_emit(batch
, GENX(3DSTATE_DS
), DS
);
1192 blorp_emit(batch
, GENX(3DSTATE_STREAMOUT
), so
);
1194 blorp_emit(batch
, GENX(3DSTATE_GS
), gs
);
1196 blorp_emit(batch
, GENX(3DSTATE_CLIP
), clip
) {
1197 clip
.PerspectiveDivideDisable
= true;
1200 blorp_emit_sf_config(batch
, params
);
1201 blorp_emit_ps_config(batch
, params
);
1203 blorp_emit_cc_viewport(batch
, params
);
1206 /******** This is the end of the pipeline setup code ********/
1208 #endif /* GEN_GEN >= 6 */
1210 #if GEN_GEN >= 7 && GEN_GEN <= 10
1212 blorp_emit_memcpy(struct blorp_batch
*batch
,
1213 struct blorp_address dst
,
1214 struct blorp_address src
,
1217 assert(size
% 4 == 0);
1219 for (unsigned dw
= 0; dw
< size
; dw
+= 4) {
1221 blorp_emit(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
1222 cp
.DestinationMemoryAddress
= dst
;
1223 cp
.SourceMemoryAddress
= src
;
1226 /* IVB does not have a general purpose register for command streamer
1227 * commands. Therefore, we use an alternate temporary register.
1229 #define BLORP_TEMP_REG 0x2440 /* GEN7_3DPRIM_BASE_VERTEX */
1230 blorp_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), load
) {
1231 load
.RegisterAddress
= BLORP_TEMP_REG
;
1232 load
.MemoryAddress
= src
;
1234 blorp_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), store
) {
1235 store
.RegisterAddress
= BLORP_TEMP_REG
;
1236 store
.MemoryAddress
= dst
;
1238 #undef BLORP_TEMP_REG
1247 blorp_emit_surface_state(struct blorp_batch
*batch
,
1248 const struct brw_blorp_surface_info
*surface
,
1249 void *state
, uint32_t state_offset
,
1250 const bool color_write_disables
[4],
1251 bool is_render_target
)
1253 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1254 struct isl_surf surf
= surface
->surf
;
1256 if (surf
.dim
== ISL_SURF_DIM_1D
&&
1257 surf
.dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
) {
1258 assert(surf
.logical_level0_px
.height
== 1);
1259 surf
.dim
= ISL_SURF_DIM_2D
;
1262 /* Blorp doesn't support HiZ in any of the blit or slow-clear paths */
1263 enum isl_aux_usage aux_usage
= surface
->aux_usage
;
1264 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
1265 aux_usage
= ISL_AUX_USAGE_NONE
;
1267 isl_channel_mask_t write_disable_mask
= 0;
1268 if (is_render_target
&& GEN_GEN
<= 5) {
1269 if (color_write_disables
[0])
1270 write_disable_mask
|= ISL_CHANNEL_RED_BIT
;
1271 if (color_write_disables
[1])
1272 write_disable_mask
|= ISL_CHANNEL_GREEN_BIT
;
1273 if (color_write_disables
[2])
1274 write_disable_mask
|= ISL_CHANNEL_BLUE_BIT
;
1275 if (color_write_disables
[3])
1276 write_disable_mask
|= ISL_CHANNEL_ALPHA_BIT
;
1279 isl_surf_fill_state(batch
->blorp
->isl_dev
, state
,
1280 .surf
= &surf
, .view
= &surface
->view
,
1281 .aux_surf
= &surface
->aux_surf
, .aux_usage
= aux_usage
,
1282 .mocs
= surface
->addr
.mocs
,
1283 .clear_color
= surface
->clear_color
,
1284 .write_disables
= write_disable_mask
);
1286 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.addr_offset
,
1289 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1290 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1291 * used to store other information. This should be ok, however, because
1292 * surface buffer addresses are always 4K page alinged.
1294 assert((surface
->aux_addr
.offset
& 0xfff) == 0);
1295 uint32_t *aux_addr
= state
+ isl_dev
->ss
.aux_addr_offset
;
1296 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.aux_addr_offset
,
1297 surface
->aux_addr
, *aux_addr
);
1300 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1302 if (surface
->clear_color_addr
.buffer
) {
1304 unreachable("Implement indirect clear support on gen11+");
1305 #elif GEN_GEN >= 7 && GEN_GEN <= 10
1306 struct blorp_address dst_addr
= blorp_get_surface_base_address(batch
);
1307 dst_addr
.offset
+= state_offset
+ isl_dev
->ss
.clear_value_offset
;
1308 blorp_emit_memcpy(batch
, dst_addr
, surface
->clear_color_addr
,
1309 isl_dev
->ss
.clear_value_size
);
1311 unreachable("Fast clears are only supported on gen7+");
1317 blorp_emit_null_surface_state(struct blorp_batch
*batch
,
1318 const struct brw_blorp_surface_info
*surface
,
1321 struct GENX(RENDER_SURFACE_STATE
) ss
= {
1322 .SurfaceType
= SURFTYPE_NULL
,
1323 .SurfaceFormat
= (enum GENX(SURFACE_FORMAT
)) ISL_FORMAT_R8G8B8A8_UNORM
,
1324 .Width
= surface
->surf
.logical_level0_px
.width
- 1,
1325 .Height
= surface
->surf
.logical_level0_px
.height
- 1,
1326 .MIPCountLOD
= surface
->view
.base_level
,
1327 .MinimumArrayElement
= surface
->view
.base_array_layer
,
1328 .Depth
= surface
->view
.array_len
- 1,
1329 .RenderTargetViewExtent
= surface
->view
.array_len
- 1,
1331 .NumberofMultisamples
= ffs(surface
->surf
.samples
) - 1,
1335 .SurfaceArray
= surface
->surf
.dim
!= ISL_SURF_DIM_3D
,
1341 .TiledSurface
= true,
1345 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &ss
);
1347 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1351 blorp_emit_surface_states(struct blorp_batch
*batch
,
1352 const struct blorp_params
*params
)
1354 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1355 uint32_t bind_offset
, surface_offsets
[2];
1356 void *surface_maps
[2];
1358 MAYBE_UNUSED
bool has_indirect_clear_color
= false;
1359 if (params
->use_pre_baked_binding_table
) {
1360 bind_offset
= params
->pre_baked_binding_table_offset
;
1362 unsigned num_surfaces
= 1 + params
->src
.enabled
;
1363 blorp_alloc_binding_table(batch
, num_surfaces
,
1364 isl_dev
->ss
.size
, isl_dev
->ss
.align
,
1365 &bind_offset
, surface_offsets
, surface_maps
);
1367 if (params
->dst
.enabled
) {
1368 blorp_emit_surface_state(batch
, ¶ms
->dst
,
1369 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
],
1370 surface_offsets
[BLORP_RENDERBUFFER_BT_INDEX
],
1371 params
->color_write_disable
, true);
1372 if (params
->dst
.clear_color_addr
.buffer
!= NULL
)
1373 has_indirect_clear_color
= true;
1375 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1376 const struct brw_blorp_surface_info
*surface
=
1377 params
->depth
.enabled
? ¶ms
->depth
: ¶ms
->stencil
;
1378 blorp_emit_null_surface_state(batch
, surface
,
1379 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
]);
1382 if (params
->src
.enabled
) {
1383 blorp_emit_surface_state(batch
, ¶ms
->src
,
1384 surface_maps
[BLORP_TEXTURE_BT_INDEX
],
1385 surface_offsets
[BLORP_TEXTURE_BT_INDEX
],
1387 if (params
->src
.clear_color_addr
.buffer
!= NULL
)
1388 has_indirect_clear_color
= true;
1392 #if GEN_GEN >= 7 && GEN_GEN <= 10
1393 if (has_indirect_clear_color
) {
1394 /* Updating a surface state object may require that the state cache be
1395 * invalidated. From the SKL PRM, Shared Functions -> State -> State
1398 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
1399 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
1400 * modified [...], the L1 state cache must be invalidated to ensure
1401 * the new surface or sampler state is fetched from system memory.
1403 blorp_emit(batch
, GENX(PIPE_CONTROL
), pipe
) {
1404 pipe
.StateCacheInvalidationEnable
= true;
1410 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), bt
);
1411 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_HS
), bt
);
1412 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_DS
), bt
);
1413 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_GS
), bt
);
1415 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS
), bt
) {
1416 bt
.PointertoPSBindingTable
= bind_offset
;
1419 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1420 bt
.PSBindingTableChange
= true;
1421 bt
.PointertoPSBindingTable
= bind_offset
;
1424 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1425 bt
.PointertoPSBindingTable
= bind_offset
;
1431 blorp_emit_depth_stencil_config(struct blorp_batch
*batch
,
1432 const struct blorp_params
*params
)
1434 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1436 uint32_t *dw
= blorp_emit_dwords(batch
, isl_dev
->ds
.size
/ 4);
1440 struct isl_depth_stencil_hiz_emit_info info
= { };
1442 if (params
->depth
.enabled
) {
1443 info
.view
= ¶ms
->depth
.view
;
1444 info
.mocs
= params
->depth
.addr
.mocs
;
1445 } else if (params
->stencil
.enabled
) {
1446 info
.view
= ¶ms
->stencil
.view
;
1447 info
.mocs
= params
->stencil
.addr
.mocs
;
1450 if (params
->depth
.enabled
) {
1451 info
.depth_surf
= ¶ms
->depth
.surf
;
1453 info
.depth_address
=
1454 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.depth_offset
/ 4,
1455 params
->depth
.addr
, 0);
1457 info
.hiz_usage
= params
->depth
.aux_usage
;
1458 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
1459 info
.hiz_surf
= ¶ms
->depth
.aux_surf
;
1461 struct blorp_address hiz_address
= params
->depth
.aux_addr
;
1463 /* Sandy bridge hardware does not technically support mipmapped HiZ.
1464 * However, we have a special layout that allows us to make it work
1465 * anyway by manually offsetting to the specified miplevel.
1467 assert(info
.hiz_surf
->dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
1469 isl_surf_get_image_offset_B_tile_sa(info
.hiz_surf
,
1470 info
.view
->base_level
, 0, 0,
1471 &offset_B
, NULL
, NULL
);
1472 hiz_address
.offset
+= offset_B
;
1476 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.hiz_offset
/ 4,
1479 info
.depth_clear_value
= params
->depth
.clear_color
.f32
[0];
1483 if (params
->stencil
.enabled
) {
1484 info
.stencil_surf
= ¶ms
->stencil
.surf
;
1486 struct blorp_address stencil_address
= params
->stencil
.addr
;
1488 /* Sandy bridge hardware does not technically support mipmapped stencil.
1489 * However, we have a special layout that allows us to make it work
1490 * anyway by manually offsetting to the specified miplevel.
1492 assert(info
.stencil_surf
->dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
1494 isl_surf_get_image_offset_B_tile_sa(info
.stencil_surf
,
1495 info
.view
->base_level
, 0, 0,
1496 &offset_B
, NULL
, NULL
);
1497 stencil_address
.offset
+= offset_B
;
1500 info
.stencil_address
=
1501 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.stencil_offset
/ 4,
1502 stencil_address
, 0);
1505 isl_emit_depth_stencil_hiz_s(isl_dev
, dw
, &info
);
1509 /* Emits the Optimized HiZ sequence specified in the BDW+ PRMs. The
1510 * depth/stencil buffer extents are ignored to handle APIs which perform
1511 * clearing operations without such information.
1514 blorp_emit_gen8_hiz_op(struct blorp_batch
*batch
,
1515 const struct blorp_params
*params
)
1517 /* We should be performing an operation on a depth or stencil buffer.
1519 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1521 /* The stencil buffer should only be enabled if a fast clear operation is
1524 if (params
->stencil
.enabled
)
1525 assert(params
->hiz_op
== BLORP_HIZ_OP_DEPTH_CLEAR
);
1527 /* From the BDW PRM Volume 2, 3DSTATE_WM_HZ_OP:
1529 * 3DSTATE_MULTISAMPLE packet must be used prior to this packet to change
1530 * the Number of Multisamples. This packet must not be used to change
1531 * Number of Multisamples in a rendering sequence.
1533 * Since HIZ may be the first thing in a batch buffer, play safe and always
1534 * emit 3DSTATE_MULTISAMPLE.
1536 blorp_emit_3dstate_multisample(batch
, params
);
1538 /* If we can't alter the depth stencil config and multiple layers are
1539 * involved, the HiZ op will fail. This is because the op requires that a
1540 * new config is emitted for each additional layer.
1542 if (batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
) {
1543 assert(params
->num_layers
<= 1);
1545 blorp_emit_depth_stencil_config(batch
, params
);
1548 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
) {
1549 switch (params
->hiz_op
) {
1550 case BLORP_HIZ_OP_DEPTH_CLEAR
:
1551 hzp
.StencilBufferClearEnable
= params
->stencil
.enabled
;
1552 hzp
.DepthBufferClearEnable
= params
->depth
.enabled
;
1553 hzp
.StencilClearValue
= params
->stencil_ref
;
1554 hzp
.FullSurfaceDepthandStencilClear
= params
->full_surface_hiz_op
;
1556 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
1557 assert(params
->full_surface_hiz_op
);
1558 hzp
.DepthBufferResolveEnable
= true;
1560 case BLORP_HIZ_OP_HIZ_RESOLVE
:
1561 assert(params
->full_surface_hiz_op
);
1562 hzp
.HierarchicalDepthBufferResolveEnable
= true;
1564 case BLORP_HIZ_OP_NONE
:
1565 unreachable("Invalid HIZ op");
1568 hzp
.NumberofMultisamples
= ffs(params
->num_samples
) - 1;
1569 hzp
.SampleMask
= 0xFFFF;
1571 /* Due to a hardware issue, this bit MBZ */
1572 assert(hzp
.ScissorRectangleEnable
== false);
1574 /* Contrary to the HW docs both fields are inclusive */
1575 hzp
.ClearRectangleXMin
= params
->x0
;
1576 hzp
.ClearRectangleYMin
= params
->y0
;
1578 /* Contrary to the HW docs both fields are exclusive */
1579 hzp
.ClearRectangleXMax
= params
->x1
;
1580 hzp
.ClearRectangleYMax
= params
->y1
;
1583 /* PIPE_CONTROL w/ all bits clear except for “Post-Sync Operation” must set
1584 * to “Write Immediate Data” enabled.
1586 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1587 pc
.PostSyncOperation
= WriteImmediateData
;
1588 pc
.Address
= blorp_get_workaround_page(batch
);
1591 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
);
1596 * \brief Execute a blit or render pass operation.
1598 * To execute the operation, this function manually constructs and emits a
1599 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1600 * constructing and after emitting the batch.
1602 * This function alters no GL state.
1605 blorp_exec(struct blorp_batch
*batch
, const struct blorp_params
*params
)
1608 if (params
->hiz_op
!= BLORP_HIZ_OP_NONE
) {
1609 blorp_emit_gen8_hiz_op(batch
, params
);
1614 blorp_emit_vertex_buffers(batch
, params
);
1615 blorp_emit_vertex_elements(batch
, params
);
1617 blorp_emit_pipeline(batch
, params
);
1619 blorp_emit_surface_states(batch
, params
);
1621 if (!(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
))
1622 blorp_emit_depth_stencil_config(batch
, params
);
1624 blorp_emit(batch
, GENX(3DPRIMITIVE
), prim
) {
1625 prim
.VertexAccessType
= SEQUENTIAL
;
1626 prim
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
1628 prim
.PredicateEnable
= batch
->flags
& BLORP_BATCH_PREDICATE_ENABLE
;
1630 prim
.VertexCountPerInstance
= 3;
1631 prim
.InstanceCount
= params
->num_layers
;
1635 #endif /* BLORP_GENX_EXEC_H */