2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BLORP_GENX_EXEC_H
25 #define BLORP_GENX_EXEC_H
27 #include "blorp_priv.h"
28 #include "dev/gen_device_info.h"
29 #include "common/gen_sample_positions.h"
30 #include "genxml/gen_macros.h"
33 * This file provides the blorp pipeline setup and execution functionality.
34 * It defines the following function:
37 * blorp_exec(struct blorp_context *blorp, void *batch_data,
38 * const struct blorp_params *params);
40 * It is the job of whoever includes this header to wrap this in something
41 * to get an externally visible symbol.
43 * In order for the blorp_exec function to work, the driver must provide
44 * implementations of the following static helper functions.
48 blorp_emit_dwords(struct blorp_batch
*batch
, unsigned n
);
51 blorp_emit_reloc(struct blorp_batch
*batch
,
52 void *location
, struct blorp_address address
, uint32_t delta
);
55 blorp_alloc_dynamic_state(struct blorp_batch
*batch
,
60 blorp_alloc_vertex_buffer(struct blorp_batch
*batch
, uint32_t size
,
61 struct blorp_address
*addr
);
64 static struct blorp_address
65 blorp_get_workaround_page(struct blorp_batch
*batch
);
69 blorp_alloc_binding_table(struct blorp_batch
*batch
, unsigned num_entries
,
70 unsigned state_size
, unsigned state_alignment
,
71 uint32_t *bt_offset
, uint32_t *surface_offsets
,
75 blorp_flush_range(struct blorp_batch
*batch
, void *start
, size_t size
);
78 blorp_surface_reloc(struct blorp_batch
*batch
, uint32_t ss_offset
,
79 struct blorp_address address
, uint32_t delta
);
81 #if GEN_GEN >= 7 && GEN_GEN < 10
82 static struct blorp_address
83 blorp_get_surface_base_address(struct blorp_batch
*batch
);
87 blorp_emit_urb_config(struct blorp_batch
*batch
,
88 unsigned vs_entry_size
, unsigned sf_entry_size
);
91 blorp_emit_pipeline(struct blorp_batch
*batch
,
92 const struct blorp_params
*params
);
94 /***** BEGIN blorp_exec implementation ******/
97 _blorp_combine_address(struct blorp_batch
*batch
, void *location
,
98 struct blorp_address address
, uint32_t delta
)
100 if (address
.buffer
== NULL
) {
101 return address
.offset
+ delta
;
103 return blorp_emit_reloc(batch
, location
, address
, delta
);
107 #define __gen_address_type struct blorp_address
108 #define __gen_user_data struct blorp_batch
109 #define __gen_combine_address _blorp_combine_address
111 #include "genxml/genX_pack.h"
113 #define _blorp_cmd_length(cmd) cmd ## _length
114 #define _blorp_cmd_length_bias(cmd) cmd ## _length_bias
115 #define _blorp_cmd_header(cmd) cmd ## _header
116 #define _blorp_cmd_pack(cmd) cmd ## _pack
118 #define blorp_emit(batch, cmd, name) \
119 for (struct cmd name = { _blorp_cmd_header(cmd) }, \
120 *_dst = blorp_emit_dwords(batch, _blorp_cmd_length(cmd)); \
121 __builtin_expect(_dst != NULL, 1); \
122 _blorp_cmd_pack(cmd)(batch, (void *)_dst, &name), \
125 #define blorp_emitn(batch, cmd, n) ({ \
126 uint32_t *_dw = blorp_emit_dwords(batch, n); \
128 struct cmd template = { \
129 _blorp_cmd_header(cmd), \
130 .DWordLength = n - _blorp_cmd_length_bias(cmd), \
132 _blorp_cmd_pack(cmd)(batch, _dw, &template); \
134 _dw ? _dw + 1 : NULL; /* Array starts at dw[1] */ \
137 #define STRUCT_ZERO(S) ({ struct S t; memset(&t, 0, sizeof(t)); t; })
139 #define blorp_emit_dynamic(batch, state, name, align, offset) \
140 for (struct state name = STRUCT_ZERO(state), \
141 *_dst = blorp_alloc_dynamic_state(batch, \
142 _blorp_cmd_length(state) * 4, \
144 __builtin_expect(_dst != NULL, 1); \
145 _blorp_cmd_pack(state)(batch, (void *)_dst, &name), \
146 blorp_flush_range(batch, _dst, _blorp_cmd_length(state) * 4), \
155 * Assign the entire URB to the VS. Even though the VS disabled, URB space
156 * is still needed because the clipper loads the VUE's from the URB. From
157 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
158 * Dword 1.15:0 "VS Number of URB Entries":
159 * This field is always used (even if VS Function Enable is DISABLED).
161 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
162 * safely ignore it because this batch contains only one draw call.
163 * Because of URB corruption caused by allocating a previous GS unit
164 * URB entry to the VS unit, software is required to send a “GS NULL
165 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
166 * plus a dummy DRAW call before any case where VS will be taking over
169 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
170 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
172 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
173 * programmed in order for the programming of this state to be
177 emit_urb_config(struct blorp_batch
*batch
,
178 const struct blorp_params
*params
)
180 /* Once vertex fetcher has written full VUE entries with complete
181 * header the space requirement is as follows per vertex (in bytes):
183 * Header Position Program constants
184 * +--------+------------+-------------------+
185 * | 16 | 16 | n x 16 |
186 * +--------+------------+-------------------+
188 * where 'n' stands for number of varying inputs expressed as vec4s.
190 const unsigned num_varyings
=
191 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
192 const unsigned total_needed
= 16 + 16 + num_varyings
* 16;
194 /* The URB size is expressed in units of 64 bytes (512 bits) */
195 const unsigned vs_entry_size
= DIV_ROUND_UP(total_needed
, 64);
197 const unsigned sf_entry_size
=
198 params
->sf_prog_data
? params
->sf_prog_data
->urb_entry_size
: 0;
200 blorp_emit_urb_config(batch
, vs_entry_size
, sf_entry_size
);
205 blorp_emit_memcpy(struct blorp_batch
*batch
,
206 struct blorp_address dst
,
207 struct blorp_address src
,
212 blorp_emit_vertex_data(struct blorp_batch
*batch
,
213 const struct blorp_params
*params
,
214 struct blorp_address
*addr
,
217 const float vertices
[] = {
218 /* v0 */ (float)params
->x1
, (float)params
->y1
, params
->z
,
219 /* v1 */ (float)params
->x0
, (float)params
->y1
, params
->z
,
220 /* v2 */ (float)params
->x0
, (float)params
->y0
, params
->z
,
223 void *data
= blorp_alloc_vertex_buffer(batch
, sizeof(vertices
), addr
);
224 memcpy(data
, vertices
, sizeof(vertices
));
225 *size
= sizeof(vertices
);
226 blorp_flush_range(batch
, data
, *size
);
230 blorp_emit_input_varying_data(struct blorp_batch
*batch
,
231 const struct blorp_params
*params
,
232 struct blorp_address
*addr
,
235 const unsigned vec4_size_in_bytes
= 4 * sizeof(float);
236 const unsigned max_num_varyings
=
237 DIV_ROUND_UP(sizeof(params
->wm_inputs
), vec4_size_in_bytes
);
238 const unsigned num_varyings
=
239 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
241 *size
= 16 + num_varyings
* vec4_size_in_bytes
;
243 const uint32_t *const inputs_src
= (const uint32_t *)¶ms
->wm_inputs
;
244 void *data
= blorp_alloc_vertex_buffer(batch
, *size
, addr
);
245 uint32_t *inputs
= data
;
247 /* Copy in the VS inputs */
248 assert(sizeof(params
->vs_inputs
) == 16);
249 memcpy(inputs
, ¶ms
->vs_inputs
, sizeof(params
->vs_inputs
));
252 if (params
->wm_prog_data
) {
253 /* Walk over the attribute slots, determine if the attribute is used by
254 * the program and when necessary copy the values from the input storage
255 * to the vertex data buffer.
257 for (unsigned i
= 0; i
< max_num_varyings
; i
++) {
258 const gl_varying_slot attr
= VARYING_SLOT_VAR0
+ i
;
260 const int input_index
= params
->wm_prog_data
->urb_setup
[attr
];
264 memcpy(inputs
, inputs_src
+ i
* 4, vec4_size_in_bytes
);
270 blorp_flush_range(batch
, data
, *size
);
272 if (params
->dst_clear_color_as_input
) {
274 /* In this case, the clear color isn't known statically and instead
275 * comes in through an indirect which we have to copy into the vertex
276 * buffer before we execute the 3DPRIMITIVE. We already copied the
277 * value of params->wm_inputs.clear_color into the vertex buffer in the
278 * loop above. Now we emit code to stomp it from the GPU with the
279 * actual clear color value.
281 assert(num_varyings
== 1);
283 /* The clear color is the first thing after the header */
284 struct blorp_address clear_color_input_addr
= *addr
;
285 clear_color_input_addr
.offset
+= 16;
287 const unsigned clear_color_size
=
288 GEN_GEN
< 10 ? batch
->blorp
->isl_dev
->ss
.clear_value_size
: 4 * 4;
289 blorp_emit_memcpy(batch
, clear_color_input_addr
,
290 params
->dst
.clear_color_addr
,
293 unreachable("MCS partial resolve is not a thing on SNB and earlier");
299 blorp_fill_vertex_buffer_state(struct blorp_batch
*batch
,
300 struct GENX(VERTEX_BUFFER_STATE
) *vb
,
302 struct blorp_address addr
, uint32_t size
,
305 vb
[idx
].VertexBufferIndex
= idx
;
306 vb
[idx
].BufferStartingAddress
= addr
;
307 vb
[idx
].BufferPitch
= stride
;
310 vb
[idx
].VertexBufferMOCS
= addr
.mocs
;
314 vb
[idx
].AddressModifyEnable
= true;
318 vb
[idx
].BufferSize
= size
;
320 vb
[idx
].BufferAccessType
= stride
> 0 ? VERTEXDATA
: INSTANCEDATA
;
321 vb
[idx
].EndAddress
= vb
[idx
].BufferStartingAddress
;
322 vb
[idx
].EndAddress
.offset
+= size
- 1;
324 vb
[idx
].BufferAccessType
= stride
> 0 ? VERTEXDATA
: INSTANCEDATA
;
325 vb
[idx
].MaxIndex
= stride
> 0 ? size
/ stride
: 0;
330 blorp_emit_vertex_buffers(struct blorp_batch
*batch
,
331 const struct blorp_params
*params
)
333 struct GENX(VERTEX_BUFFER_STATE
) vb
[3];
334 uint32_t num_vbs
= 2;
335 memset(vb
, 0, sizeof(vb
));
337 struct blorp_address addr
;
339 blorp_emit_vertex_data(batch
, params
, &addr
, &size
);
340 blorp_fill_vertex_buffer_state(batch
, vb
, 0, addr
, size
, 3 * sizeof(float));
342 blorp_emit_input_varying_data(batch
, params
, &addr
, &size
);
343 blorp_fill_vertex_buffer_state(batch
, vb
, 1, addr
, size
, 0);
345 const unsigned num_dwords
= 1 + num_vbs
* GENX(VERTEX_BUFFER_STATE_length
);
346 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), num_dwords
);
350 for (unsigned i
= 0; i
< num_vbs
; i
++) {
351 GENX(VERTEX_BUFFER_STATE_pack
)(batch
, dw
, &vb
[i
]);
352 dw
+= GENX(VERTEX_BUFFER_STATE_length
);
357 blorp_emit_vertex_elements(struct blorp_batch
*batch
,
358 const struct blorp_params
*params
)
360 const unsigned num_varyings
=
361 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
362 bool need_ndc
= batch
->blorp
->compiler
->devinfo
->gen
<= 5;
363 const unsigned num_elements
= 2 + need_ndc
+ num_varyings
;
365 struct GENX(VERTEX_ELEMENT_STATE
) ve
[num_elements
];
366 memset(ve
, 0, num_elements
* sizeof(*ve
));
368 /* Setup VBO for the rectangle primitive..
370 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
371 * vertices. The vertices reside in screen space with DirectX
372 * coordinates (that is, (0, 0) is the upper left corner).
379 * Since the VS is disabled, the clipper loads each VUE directly from
380 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
381 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
382 * dw0: Reserved, MBZ.
383 * dw1: Render Target Array Index. Below vertex fetcher gets programmed
384 * to assign this with primitive instance identifier which will be
385 * used for layered clears. All other renders have only one instance
386 * and therefore the value will be effectively zero.
387 * dw2: Viewport Index. The HiZ op disables viewport mapping and
388 * scissoring, so set the dword to 0.
389 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive,
390 * so set the dword to 0.
391 * dw4: Vertex Position X.
392 * dw5: Vertex Position Y.
393 * dw6: Vertex Position Z.
394 * dw7: Vertex Position W.
396 * dw8: Flat vertex input 0
397 * dw9: Flat vertex input 1
399 * dwn: Flat vertex input n - 8
401 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
402 * "Vertex URB Entry (VUE) Formats".
404 * Only vertex position X and Y are going to be variable, Z is fixed to
405 * zero and W to one. Header words dw0,2,3 are zero. There is no need to
406 * include the fixed values in the vertex buffer. Vertex fetcher can be
407 * instructed to fill vertex elements with constant values of one and zero
408 * instead of reading them from the buffer.
409 * Flat inputs are program constants that are not interpolated. Moreover
410 * their values will be the same between vertices.
412 * See the vertex element setup below.
416 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
417 .VertexBufferIndex
= 1,
419 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
420 .SourceElementOffset
= 0,
421 .Component0Control
= VFCOMP_STORE_SRC
,
423 /* From Gen8 onwards hardware is no more instructed to overwrite
424 * components using an element specifier. Instead one has separate
425 * 3DSTATE_VF_SGVS (System Generated Value Setup) state packet for it.
428 .Component1Control
= VFCOMP_STORE_0
,
430 .Component1Control
= VFCOMP_STORE_IID
,
432 .Component1Control
= VFCOMP_STORE_0
,
434 .Component2Control
= VFCOMP_STORE_0
,
435 .Component3Control
= VFCOMP_STORE_0
,
437 .DestinationElementOffset
= slot
* 4,
443 /* On Iron Lake and earlier, a native device coordinates version of the
444 * position goes right after the normal VUE header and before position.
445 * Since w == 1 for all of our coordinates, this is just a copy of the
448 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
449 .VertexBufferIndex
= 0,
451 .SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
,
452 .SourceElementOffset
= 0,
453 .Component0Control
= VFCOMP_STORE_SRC
,
454 .Component1Control
= VFCOMP_STORE_SRC
,
455 .Component2Control
= VFCOMP_STORE_SRC
,
456 .Component3Control
= VFCOMP_STORE_1_FP
,
457 .DestinationElementOffset
= slot
* 4,
462 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
463 .VertexBufferIndex
= 0,
465 .SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
,
466 .SourceElementOffset
= 0,
467 .Component0Control
= VFCOMP_STORE_SRC
,
468 .Component1Control
= VFCOMP_STORE_SRC
,
469 .Component2Control
= VFCOMP_STORE_SRC
,
470 .Component3Control
= VFCOMP_STORE_1_FP
,
472 .DestinationElementOffset
= slot
* 4,
477 for (unsigned i
= 0; i
< num_varyings
; ++i
) {
478 ve
[slot
] = (struct GENX(VERTEX_ELEMENT_STATE
)) {
479 .VertexBufferIndex
= 1,
481 .SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
,
482 .SourceElementOffset
= 16 + i
* 4 * sizeof(float),
483 .Component0Control
= VFCOMP_STORE_SRC
,
484 .Component1Control
= VFCOMP_STORE_SRC
,
485 .Component2Control
= VFCOMP_STORE_SRC
,
486 .Component3Control
= VFCOMP_STORE_SRC
,
488 .DestinationElementOffset
= slot
* 4,
494 const unsigned num_dwords
=
495 1 + GENX(VERTEX_ELEMENT_STATE_length
) * num_elements
;
496 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_ELEMENTS
), num_dwords
);
500 for (unsigned i
= 0; i
< num_elements
; i
++) {
501 GENX(VERTEX_ELEMENT_STATE_pack
)(batch
, dw
, &ve
[i
]);
502 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
506 /* Overwrite Render Target Array Index (2nd dword) in the VUE header with
507 * primitive instance identifier. This is used for layered clears.
509 blorp_emit(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
510 sgvs
.InstanceIDEnable
= true;
511 sgvs
.InstanceIDComponentNumber
= COMP_1
;
512 sgvs
.InstanceIDElementOffset
= 0;
515 for (unsigned i
= 0; i
< num_elements
; i
++) {
516 blorp_emit(batch
, GENX(3DSTATE_VF_INSTANCING
), vf
) {
517 vf
.VertexElementIndex
= i
;
518 vf
.InstancingEnable
= false;
522 blorp_emit(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
523 topo
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
528 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
530 blorp_emit_cc_viewport(struct blorp_batch
*batch
)
532 uint32_t cc_vp_offset
;
533 blorp_emit_dynamic(batch
, GENX(CC_VIEWPORT
), vp
, 32, &cc_vp_offset
) {
534 vp
.MinimumDepth
= 0.0;
535 vp
.MaximumDepth
= 1.0;
539 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), vsp
) {
540 vsp
.CCViewportPointer
= cc_vp_offset
;
543 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vsp
) {
544 vsp
.CCViewportStateChange
= true;
545 vsp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
553 blorp_emit_sampler_state(struct blorp_batch
*batch
)
556 blorp_emit_dynamic(batch
, GENX(SAMPLER_STATE
), sampler
, 32, &offset
) {
557 sampler
.MipModeFilter
= MIPFILTER_NONE
;
558 sampler
.MagModeFilter
= MAPFILTER_LINEAR
;
559 sampler
.MinModeFilter
= MAPFILTER_LINEAR
;
562 sampler
.TCXAddressControlMode
= TCM_CLAMP
;
563 sampler
.TCYAddressControlMode
= TCM_CLAMP
;
564 sampler
.TCZAddressControlMode
= TCM_CLAMP
;
565 sampler
.MaximumAnisotropy
= RATIO21
;
566 sampler
.RAddressMinFilterRoundingEnable
= true;
567 sampler
.RAddressMagFilterRoundingEnable
= true;
568 sampler
.VAddressMinFilterRoundingEnable
= true;
569 sampler
.VAddressMagFilterRoundingEnable
= true;
570 sampler
.UAddressMinFilterRoundingEnable
= true;
571 sampler
.UAddressMagFilterRoundingEnable
= true;
573 sampler
.NonnormalizedCoordinateEnable
= true;
578 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS
), ssp
) {
579 ssp
.PointertoPSSamplerState
= offset
;
582 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS
), ssp
) {
583 ssp
.VSSamplerStateChange
= true;
584 ssp
.GSSamplerStateChange
= true;
585 ssp
.PSSamplerStateChange
= true;
586 ssp
.PointertoPSSamplerState
= offset
;
593 /* What follows is the code for setting up a "pipeline" on Sandy Bridge and
594 * later hardware. This file will be included by i965 for gen4-5 as well, so
595 * this code is guarded by GEN_GEN >= 6.
600 blorp_emit_vs_config(struct blorp_batch
*batch
,
601 const struct blorp_params
*params
)
603 struct brw_vs_prog_data
*vs_prog_data
= params
->vs_prog_data
;
604 assert(!vs_prog_data
|| GEN_GEN
< 11 ||
605 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
);
607 blorp_emit(batch
, GENX(3DSTATE_VS
), vs
) {
611 vs
.KernelStartPointer
= params
->vs_prog_kernel
;
613 vs
.DispatchGRFStartRegisterForURBData
=
614 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
615 vs
.VertexURBEntryReadLength
=
616 vs_prog_data
->base
.urb_read_length
;
617 vs
.VertexURBEntryReadOffset
= 0;
619 vs
.MaximumNumberofThreads
=
620 batch
->blorp
->isl_dev
->info
->max_vs_threads
- 1;
623 vs
.SIMD8DispatchEnable
=
624 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
631 blorp_emit_sf_config(struct blorp_batch
*batch
,
632 const struct blorp_params
*params
)
634 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
638 * Disable ViewportTransformEnable (dw2.1)
640 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
641 * Primitives Overview":
642 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
643 * use of screen- space coordinates).
645 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
646 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
648 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
649 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
650 * SOLID: Any triangle or rectangle object found to be front-facing
651 * is rendered as a solid object. This setting is required when
652 * (rendering rectangle (RECTLIST) objects.
657 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
);
659 blorp_emit(batch
, GENX(3DSTATE_RASTER
), raster
) {
660 raster
.CullMode
= CULLMODE_NONE
;
663 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
664 sbe
.VertexURBEntryReadOffset
= 1;
666 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
667 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
668 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
670 sbe
.NumberofSFOutputAttributes
= 0;
671 sbe
.VertexURBEntryReadLength
= 1;
673 sbe
.ForceVertexURBEntryReadLength
= true;
674 sbe
.ForceVertexURBEntryReadOffset
= true;
677 for (unsigned i
= 0; i
< 32; i
++)
678 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
684 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
685 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
686 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
688 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
689 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
692 sf
.DepthBufferSurfaceFormat
= params
->depth_format
;
696 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
697 sbe
.VertexURBEntryReadOffset
= 1;
699 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
700 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
701 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
703 sbe
.NumberofSFOutputAttributes
= 0;
704 sbe
.VertexURBEntryReadLength
= 1;
708 #else /* GEN_GEN <= 6 */
710 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
711 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
712 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
714 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
715 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
717 sf
.VertexURBEntryReadOffset
= 1;
719 sf
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
720 sf
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
721 sf
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
723 sf
.NumberofSFOutputAttributes
= 0;
724 sf
.VertexURBEntryReadLength
= 1;
732 blorp_emit_ps_config(struct blorp_batch
*batch
,
733 const struct blorp_params
*params
)
735 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
737 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
738 * nonzero to prevent the GPU from hanging. While the documentation doesn't
739 * mention this explicitly, it notes that the valid range for the field is
740 * [1,39] = [2,40] threads, which excludes zero.
742 * To be safe (and to minimize extraneous code) we go ahead and fully
743 * configure the WM state whether or not there is a WM program.
748 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
750 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
751 if (params
->src
.enabled
) {
752 ps
.SamplerCount
= 1; /* Up to 4 samplers */
753 ps
.BindingTableEntryCount
= 2;
755 ps
.BindingTableEntryCount
= 1;
759 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
760 prog_data
->base
.dispatch_grf_start_reg
;
761 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
762 prog_data
->dispatch_grf_start_reg_2
;
764 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
765 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
767 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
768 ps
.KernelStartPointer2
=
769 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
772 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64
773 * for pre Gen11 and 128 for gen11+; On gen11+ If a programmed value is
774 * k, it implies 2(k+1) threads. It implicitly scales for different GT
775 * levels (which have some # of PSDs).
777 * In Gen8 the format is U8-2 whereas in Gen9+ it is U9-1.
780 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
782 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
784 switch (params
->fast_clear_op
) {
785 case ISL_AUX_OP_NONE
:
788 case ISL_AUX_OP_PARTIAL_RESOLVE
:
789 ps
.RenderTargetResolveType
= RESOLVE_PARTIAL
;
791 case ISL_AUX_OP_FULL_RESOLVE
:
792 ps
.RenderTargetResolveType
= RESOLVE_FULL
;
795 case ISL_AUX_OP_FULL_RESOLVE
:
796 ps
.RenderTargetResolveEnable
= true;
799 case ISL_AUX_OP_FAST_CLEAR
:
800 ps
.RenderTargetFastClearEnable
= true;
803 unreachable("Invalid fast clear op");
807 blorp_emit(batch
, GENX(3DSTATE_PS_EXTRA
), psx
) {
809 psx
.PixelShaderValid
= true;
810 psx
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
811 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
814 if (params
->src
.enabled
)
815 psx
.PixelShaderKillsPixel
= true;
820 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
821 switch (params
->hiz_op
) {
822 case ISL_AUX_OP_FAST_CLEAR
:
823 wm
.DepthBufferClear
= true;
825 case ISL_AUX_OP_FULL_RESOLVE
:
826 wm
.DepthBufferResolveEnable
= true;
828 case ISL_AUX_OP_AMBIGUATE
:
829 wm
.HierarchicalDepthBufferResolveEnable
= true;
831 case ISL_AUX_OP_NONE
:
834 unreachable("not reached");
838 wm
.ThreadDispatchEnable
= true;
840 if (params
->src
.enabled
)
841 wm
.PixelShaderKillsPixel
= true;
843 if (params
->num_samples
> 1) {
844 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
845 wm
.MultisampleDispatchMode
=
846 (prog_data
&& prog_data
->persample_dispatch
) ?
847 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
849 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
850 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
854 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
855 ps
.MaximumNumberofThreads
=
856 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
863 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
864 prog_data
->base
.dispatch_grf_start_reg
;
865 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
866 prog_data
->dispatch_grf_start_reg_2
;
868 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
869 ps
.KernelStartPointer2
=
870 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
872 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
873 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
875 ps
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
877 /* Gen7 hardware gets angry if we don't enable at least one dispatch
878 * mode, so just enable 16-pixel dispatch if we don't have a program.
880 ps
._16PixelDispatchEnable
= true;
883 if (params
->src
.enabled
)
884 ps
.SamplerCount
= 1; /* Up to 4 samplers */
886 switch (params
->fast_clear_op
) {
887 case ISL_AUX_OP_NONE
:
889 case ISL_AUX_OP_FULL_RESOLVE
:
890 ps
.RenderTargetResolveEnable
= true;
892 case ISL_AUX_OP_FAST_CLEAR
:
893 ps
.RenderTargetFastClearEnable
= true;
896 unreachable("Invalid fast clear op");
900 #else /* GEN_GEN <= 6 */
902 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
903 wm
.MaximumNumberofThreads
=
904 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
906 switch (params
->hiz_op
) {
907 case ISL_AUX_OP_FAST_CLEAR
:
908 wm
.DepthBufferClear
= true;
910 case ISL_AUX_OP_FULL_RESOLVE
:
911 wm
.DepthBufferResolveEnable
= true;
913 case ISL_AUX_OP_AMBIGUATE
:
914 wm
.HierarchicalDepthBufferResolveEnable
= true;
916 case ISL_AUX_OP_NONE
:
919 unreachable("not reached");
923 wm
.ThreadDispatchEnable
= true;
925 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
926 prog_data
->base
.dispatch_grf_start_reg
;
927 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
928 prog_data
->dispatch_grf_start_reg_2
;
930 wm
.KernelStartPointer0
= params
->wm_prog_kernel
;
931 wm
.KernelStartPointer2
=
932 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
934 wm
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
935 wm
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
937 wm
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
940 if (params
->src
.enabled
) {
941 wm
.SamplerCount
= 1; /* Up to 4 samplers */
942 wm
.PixelShaderKillsPixel
= true; /* TODO: temporarily smash on */
945 if (params
->num_samples
> 1) {
946 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
947 wm
.MultisampleDispatchMode
=
948 (prog_data
&& prog_data
->persample_dispatch
) ?
949 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
951 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
952 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
960 blorp_emit_blend_state(struct blorp_batch
*batch
,
961 const struct blorp_params
*params
)
963 struct GENX(BLEND_STATE
) blend
;
964 memset(&blend
, 0, sizeof(blend
));
967 int size
= GENX(BLEND_STATE_length
) * 4;
968 size
+= GENX(BLEND_STATE_ENTRY_length
) * 4 * params
->num_draw_buffers
;
969 uint32_t *state
= blorp_alloc_dynamic_state(batch
, size
, 64, &offset
);
970 uint32_t *pos
= state
;
972 GENX(BLEND_STATE_pack
)(NULL
, pos
, &blend
);
973 pos
+= GENX(BLEND_STATE_length
);
975 for (unsigned i
= 0; i
< params
->num_draw_buffers
; ++i
) {
976 struct GENX(BLEND_STATE_ENTRY
) entry
= {
977 .PreBlendColorClampEnable
= true,
978 .PostBlendColorClampEnable
= true,
979 .ColorClampRange
= COLORCLAMP_RTFORMAT
,
981 .WriteDisableRed
= params
->color_write_disable
[0],
982 .WriteDisableGreen
= params
->color_write_disable
[1],
983 .WriteDisableBlue
= params
->color_write_disable
[2],
984 .WriteDisableAlpha
= params
->color_write_disable
[3],
986 GENX(BLEND_STATE_ENTRY_pack
)(NULL
, pos
, &entry
);
987 pos
+= GENX(BLEND_STATE_ENTRY_length
);
990 blorp_flush_range(batch
, state
, size
);
993 blorp_emit(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), sp
) {
994 sp
.BlendStatePointer
= offset
;
996 sp
.BlendStatePointerValid
= true;
1002 blorp_emit(batch
, GENX(3DSTATE_PS_BLEND
), ps_blend
) {
1003 ps_blend
.HasWriteableRT
= true;
1011 blorp_emit_color_calc_state(struct blorp_batch
*batch
,
1012 MAYBE_UNUSED
const struct blorp_params
*params
)
1015 blorp_emit_dynamic(batch
, GENX(COLOR_CALC_STATE
), cc
, 64, &offset
) {
1017 cc
.StencilReferenceValue
= params
->stencil_ref
;
1022 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), sp
) {
1023 sp
.ColorCalcStatePointer
= offset
;
1025 sp
.ColorCalcStatePointerValid
= true;
1034 blorp_emit_depth_stencil_state(struct blorp_batch
*batch
,
1035 const struct blorp_params
*params
)
1038 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) ds
= {
1039 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
1042 struct GENX(DEPTH_STENCIL_STATE
) ds
= { 0 };
1045 if (params
->depth
.enabled
) {
1046 ds
.DepthBufferWriteEnable
= true;
1048 switch (params
->hiz_op
) {
1049 case ISL_AUX_OP_NONE
:
1050 ds
.DepthTestEnable
= true;
1051 ds
.DepthTestFunction
= COMPAREFUNCTION_ALWAYS
;
1054 /* See the following sections of the Sandy Bridge PRM, Volume 2, Part1:
1055 * - 7.5.3.1 Depth Buffer Clear
1056 * - 7.5.3.2 Depth Buffer Resolve
1057 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
1059 case ISL_AUX_OP_FULL_RESOLVE
:
1060 ds
.DepthTestEnable
= true;
1061 ds
.DepthTestFunction
= COMPAREFUNCTION_NEVER
;
1064 case ISL_AUX_OP_FAST_CLEAR
:
1065 case ISL_AUX_OP_AMBIGUATE
:
1066 ds
.DepthTestEnable
= false;
1068 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1069 unreachable("Invalid HIZ op");
1073 if (params
->stencil
.enabled
) {
1074 ds
.StencilBufferWriteEnable
= true;
1075 ds
.StencilTestEnable
= true;
1076 ds
.DoubleSidedStencilEnable
= false;
1078 ds
.StencilTestFunction
= COMPAREFUNCTION_ALWAYS
;
1079 ds
.StencilPassDepthPassOp
= STENCILOP_REPLACE
;
1081 ds
.StencilWriteMask
= params
->stencil_mask
;
1083 ds
.StencilReferenceValue
= params
->stencil_ref
;
1088 uint32_t offset
= 0;
1089 uint32_t *dw
= blorp_emit_dwords(batch
,
1090 GENX(3DSTATE_WM_DEPTH_STENCIL_length
));
1094 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dw
, &ds
);
1097 void *state
= blorp_alloc_dynamic_state(batch
,
1098 GENX(DEPTH_STENCIL_STATE_length
) * 4,
1100 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, state
, &ds
);
1101 blorp_flush_range(batch
, state
, GENX(DEPTH_STENCIL_STATE_length
) * 4);
1105 blorp_emit(batch
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), sp
) {
1106 sp
.PointertoDEPTH_STENCIL_STATE
= offset
;
1114 blorp_emit_3dstate_multisample(struct blorp_batch
*batch
,
1115 const struct blorp_params
*params
)
1117 blorp_emit(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1118 ms
.NumberofMultisamples
= __builtin_ffs(params
->num_samples
) - 1;
1121 /* The PRM says that this bit is valid only for DX9:
1123 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
1124 * should not have any effect by setting or not setting this bit.
1126 ms
.PixelPositionOffsetEnable
= false;
1129 switch (params
->num_samples
) {
1131 GEN_SAMPLE_POS_1X(ms
.Sample
);
1134 GEN_SAMPLE_POS_2X(ms
.Sample
);
1137 GEN_SAMPLE_POS_4X(ms
.Sample
);
1140 GEN_SAMPLE_POS_8X(ms
.Sample
);
1146 GEN_SAMPLE_POS_4X(ms
.Sample
);
1148 ms
.PixelLocation
= CENTER
;
1153 blorp_emit_pipeline(struct blorp_batch
*batch
,
1154 const struct blorp_params
*params
)
1156 uint32_t blend_state_offset
= 0;
1157 uint32_t color_calc_state_offset
;
1158 uint32_t depth_stencil_state_offset
;
1160 emit_urb_config(batch
, params
);
1162 if (params
->wm_prog_data
) {
1163 blend_state_offset
= blorp_emit_blend_state(batch
, params
);
1165 color_calc_state_offset
= blorp_emit_color_calc_state(batch
, params
);
1166 depth_stencil_state_offset
= blorp_emit_depth_stencil_state(batch
, params
);
1169 /* 3DSTATE_CC_STATE_POINTERS
1171 * The pointer offsets are relative to
1172 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
1174 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
1176 * The dynamic state emit helpers emit their own STATE_POINTERS packets on
1177 * gen7+. However, on gen6 and earlier, they're all lumpped together in
1178 * one CC_STATE_POINTERS packet so we have to emit that here.
1180 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), cc
) {
1181 cc
.BLEND_STATEChange
= true;
1182 cc
.ColorCalcStatePointerValid
= true;
1183 cc
.DEPTH_STENCIL_STATEChange
= true;
1184 cc
.PointertoBLEND_STATE
= blend_state_offset
;
1185 cc
.ColorCalcStatePointer
= color_calc_state_offset
;
1186 cc
.PointertoDEPTH_STENCIL_STATE
= depth_stencil_state_offset
;
1189 (void)blend_state_offset
;
1190 (void)color_calc_state_offset
;
1191 (void)depth_stencil_state_offset
;
1194 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_VS
), vs
);
1196 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_HS
), hs
);
1197 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_DS
), DS
);
1199 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_GS
), gs
);
1200 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_PS
), ps
);
1202 if (params
->src
.enabled
)
1203 blorp_emit_sampler_state(batch
);
1205 blorp_emit_3dstate_multisample(batch
, params
);
1207 blorp_emit(batch
, GENX(3DSTATE_SAMPLE_MASK
), mask
) {
1208 mask
.SampleMask
= (1 << params
->num_samples
) - 1;
1211 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1212 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1214 * [DevSNB] A pipeline flush must be programmed prior to a
1215 * 3DSTATE_VS command that causes the VS Function Enable to
1216 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
1217 * command with CS stall bit set and a post sync operation.
1219 * We've already done one at the start of the BLORP operation.
1221 blorp_emit_vs_config(batch
, params
);
1223 blorp_emit(batch
, GENX(3DSTATE_HS
), hs
);
1224 blorp_emit(batch
, GENX(3DSTATE_TE
), te
);
1225 blorp_emit(batch
, GENX(3DSTATE_DS
), DS
);
1226 blorp_emit(batch
, GENX(3DSTATE_STREAMOUT
), so
);
1228 blorp_emit(batch
, GENX(3DSTATE_GS
), gs
);
1230 blorp_emit(batch
, GENX(3DSTATE_CLIP
), clip
) {
1231 clip
.PerspectiveDivideDisable
= true;
1234 blorp_emit_sf_config(batch
, params
);
1235 blorp_emit_ps_config(batch
, params
);
1237 blorp_emit_cc_viewport(batch
);
1240 /******** This is the end of the pipeline setup code ********/
1242 #endif /* GEN_GEN >= 6 */
1246 blorp_emit_memcpy(struct blorp_batch
*batch
,
1247 struct blorp_address dst
,
1248 struct blorp_address src
,
1251 assert(size
% 4 == 0);
1253 for (unsigned dw
= 0; dw
< size
; dw
+= 4) {
1255 blorp_emit(batch
, GENX(MI_COPY_MEM_MEM
), cp
) {
1256 cp
.DestinationMemoryAddress
= dst
;
1257 cp
.SourceMemoryAddress
= src
;
1260 /* IVB does not have a general purpose register for command streamer
1261 * commands. Therefore, we use an alternate temporary register.
1263 #define BLORP_TEMP_REG 0x2440 /* GEN7_3DPRIM_BASE_VERTEX */
1264 blorp_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), load
) {
1265 load
.RegisterAddress
= BLORP_TEMP_REG
;
1266 load
.MemoryAddress
= src
;
1268 blorp_emit(batch
, GENX(MI_STORE_REGISTER_MEM
), store
) {
1269 store
.RegisterAddress
= BLORP_TEMP_REG
;
1270 store
.MemoryAddress
= dst
;
1272 #undef BLORP_TEMP_REG
1281 blorp_emit_surface_state(struct blorp_batch
*batch
,
1282 const struct brw_blorp_surface_info
*surface
,
1284 void *state
, uint32_t state_offset
,
1285 const bool color_write_disables
[4],
1286 bool is_render_target
)
1288 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1289 struct isl_surf surf
= surface
->surf
;
1291 if (surf
.dim
== ISL_SURF_DIM_1D
&&
1292 surf
.dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
) {
1293 assert(surf
.logical_level0_px
.height
== 1);
1294 surf
.dim
= ISL_SURF_DIM_2D
;
1297 /* Blorp doesn't support HiZ in any of the blit or slow-clear paths */
1298 enum isl_aux_usage aux_usage
= surface
->aux_usage
;
1299 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
1300 aux_usage
= ISL_AUX_USAGE_NONE
;
1302 isl_channel_mask_t write_disable_mask
= 0;
1303 if (is_render_target
&& GEN_GEN
<= 5) {
1304 if (color_write_disables
[0])
1305 write_disable_mask
|= ISL_CHANNEL_RED_BIT
;
1306 if (color_write_disables
[1])
1307 write_disable_mask
|= ISL_CHANNEL_GREEN_BIT
;
1308 if (color_write_disables
[2])
1309 write_disable_mask
|= ISL_CHANNEL_BLUE_BIT
;
1310 if (color_write_disables
[3])
1311 write_disable_mask
|= ISL_CHANNEL_ALPHA_BIT
;
1314 const bool use_clear_address
=
1315 GEN_GEN
>= 10 && (surface
->clear_color_addr
.buffer
!= NULL
);
1317 isl_surf_fill_state(batch
->blorp
->isl_dev
, state
,
1318 .surf
= &surf
, .view
= &surface
->view
,
1319 .aux_surf
= &surface
->aux_surf
, .aux_usage
= aux_usage
,
1320 .mocs
= surface
->addr
.mocs
,
1321 .clear_color
= surface
->clear_color
,
1322 .use_clear_address
= use_clear_address
,
1323 .write_disables
= write_disable_mask
);
1325 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.addr_offset
,
1328 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1329 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1330 * used to store other information. This should be ok, however, because
1331 * surface buffer addresses are always 4K page alinged.
1333 assert((surface
->aux_addr
.offset
& 0xfff) == 0);
1334 uint32_t *aux_addr
= state
+ isl_dev
->ss
.aux_addr_offset
;
1335 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.aux_addr_offset
,
1336 surface
->aux_addr
, *aux_addr
);
1339 if (surface
->clear_color_addr
.buffer
) {
1341 assert((surface
->clear_color_addr
.offset
& 0x3f) == 0);
1342 uint32_t *clear_addr
= state
+ isl_dev
->ss
.clear_color_state_offset
;
1343 blorp_surface_reloc(batch
, state_offset
+
1344 isl_dev
->ss
.clear_color_state_offset
,
1345 surface
->clear_color_addr
, *clear_addr
);
1347 if (op
== ISL_AUX_OP_FULL_RESOLVE
|| op
== ISL_AUX_OP_PARTIAL_RESOLVE
) {
1348 struct blorp_address dst_addr
= blorp_get_surface_base_address(batch
);
1349 dst_addr
.offset
+= state_offset
+ isl_dev
->ss
.clear_value_offset
;
1350 blorp_emit_memcpy(batch
, dst_addr
, surface
->clear_color_addr
,
1351 isl_dev
->ss
.clear_value_size
);
1354 unreachable("Fast clears are only supported on gen7+");
1358 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1362 blorp_emit_null_surface_state(struct blorp_batch
*batch
,
1363 const struct brw_blorp_surface_info
*surface
,
1366 struct GENX(RENDER_SURFACE_STATE
) ss
= {
1367 .SurfaceType
= SURFTYPE_NULL
,
1368 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
1369 .Width
= surface
->surf
.logical_level0_px
.width
- 1,
1370 .Height
= surface
->surf
.logical_level0_px
.height
- 1,
1371 .MIPCountLOD
= surface
->view
.base_level
,
1372 .MinimumArrayElement
= surface
->view
.base_array_layer
,
1373 .Depth
= surface
->view
.array_len
- 1,
1374 .RenderTargetViewExtent
= surface
->view
.array_len
- 1,
1376 .NumberofMultisamples
= ffs(surface
->surf
.samples
) - 1,
1380 .SurfaceArray
= surface
->surf
.dim
!= ISL_SURF_DIM_3D
,
1386 .TiledSurface
= true,
1390 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &ss
);
1392 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1396 blorp_emit_surface_states(struct blorp_batch
*batch
,
1397 const struct blorp_params
*params
)
1399 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1400 uint32_t bind_offset
= 0, surface_offsets
[2];
1401 void *surface_maps
[2];
1403 MAYBE_UNUSED
bool has_indirect_clear_color
= false;
1404 if (params
->use_pre_baked_binding_table
) {
1405 bind_offset
= params
->pre_baked_binding_table_offset
;
1407 unsigned num_surfaces
= 1 + params
->src
.enabled
;
1408 blorp_alloc_binding_table(batch
, num_surfaces
,
1409 isl_dev
->ss
.size
, isl_dev
->ss
.align
,
1410 &bind_offset
, surface_offsets
, surface_maps
);
1412 if (params
->dst
.enabled
) {
1413 blorp_emit_surface_state(batch
, ¶ms
->dst
,
1414 params
->fast_clear_op
,
1415 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
],
1416 surface_offsets
[BLORP_RENDERBUFFER_BT_INDEX
],
1417 params
->color_write_disable
, true);
1418 if (params
->dst
.clear_color_addr
.buffer
!= NULL
)
1419 has_indirect_clear_color
= true;
1421 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1422 const struct brw_blorp_surface_info
*surface
=
1423 params
->depth
.enabled
? ¶ms
->depth
: ¶ms
->stencil
;
1424 blorp_emit_null_surface_state(batch
, surface
,
1425 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
]);
1428 if (params
->src
.enabled
) {
1429 blorp_emit_surface_state(batch
, ¶ms
->src
,
1430 params
->fast_clear_op
,
1431 surface_maps
[BLORP_TEXTURE_BT_INDEX
],
1432 surface_offsets
[BLORP_TEXTURE_BT_INDEX
],
1434 if (params
->src
.clear_color_addr
.buffer
!= NULL
)
1435 has_indirect_clear_color
= true;
1440 if (has_indirect_clear_color
) {
1441 /* Updating a surface state object may require that the state cache be
1442 * invalidated. From the SKL PRM, Shared Functions -> State -> State
1445 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
1446 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
1447 * modified [...], the L1 state cache must be invalidated to ensure
1448 * the new surface or sampler state is fetched from system memory.
1450 blorp_emit(batch
, GENX(PIPE_CONTROL
), pipe
) {
1451 pipe
.StateCacheInvalidationEnable
= true;
1457 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), bt
);
1458 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_HS
), bt
);
1459 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_DS
), bt
);
1460 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_GS
), bt
);
1462 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS
), bt
) {
1463 bt
.PointertoPSBindingTable
= bind_offset
;
1466 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1467 bt
.PSBindingTableChange
= true;
1468 bt
.PointertoPSBindingTable
= bind_offset
;
1471 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1472 bt
.PointertoPSBindingTable
= bind_offset
;
1478 blorp_emit_depth_stencil_config(struct blorp_batch
*batch
,
1479 const struct blorp_params
*params
)
1481 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1483 uint32_t *dw
= blorp_emit_dwords(batch
, isl_dev
->ds
.size
/ 4);
1487 struct isl_depth_stencil_hiz_emit_info info
= { };
1489 if (params
->depth
.enabled
) {
1490 info
.view
= ¶ms
->depth
.view
;
1491 info
.mocs
= params
->depth
.addr
.mocs
;
1492 } else if (params
->stencil
.enabled
) {
1493 info
.view
= ¶ms
->stencil
.view
;
1494 info
.mocs
= params
->stencil
.addr
.mocs
;
1497 if (params
->depth
.enabled
) {
1498 info
.depth_surf
= ¶ms
->depth
.surf
;
1500 info
.depth_address
=
1501 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.depth_offset
/ 4,
1502 params
->depth
.addr
, 0);
1504 info
.hiz_usage
= params
->depth
.aux_usage
;
1505 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
1506 info
.hiz_surf
= ¶ms
->depth
.aux_surf
;
1508 struct blorp_address hiz_address
= params
->depth
.aux_addr
;
1510 /* Sandy bridge hardware does not technically support mipmapped HiZ.
1511 * However, we have a special layout that allows us to make it work
1512 * anyway by manually offsetting to the specified miplevel.
1514 assert(info
.hiz_surf
->dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
1516 isl_surf_get_image_offset_B_tile_sa(info
.hiz_surf
,
1517 info
.view
->base_level
, 0, 0,
1518 &offset_B
, NULL
, NULL
);
1519 hiz_address
.offset
+= offset_B
;
1523 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.hiz_offset
/ 4,
1526 info
.depth_clear_value
= params
->depth
.clear_color
.f32
[0];
1530 if (params
->stencil
.enabled
) {
1531 info
.stencil_surf
= ¶ms
->stencil
.surf
;
1533 struct blorp_address stencil_address
= params
->stencil
.addr
;
1535 /* Sandy bridge hardware does not technically support mipmapped stencil.
1536 * However, we have a special layout that allows us to make it work
1537 * anyway by manually offsetting to the specified miplevel.
1539 assert(info
.stencil_surf
->dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
1541 isl_surf_get_image_offset_B_tile_sa(info
.stencil_surf
,
1542 info
.view
->base_level
, 0, 0,
1543 &offset_B
, NULL
, NULL
);
1544 stencil_address
.offset
+= offset_B
;
1547 info
.stencil_address
=
1548 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.stencil_offset
/ 4,
1549 stencil_address
, 0);
1552 isl_emit_depth_stencil_hiz_s(isl_dev
, dw
, &info
);
1556 /* Emits the Optimized HiZ sequence specified in the BDW+ PRMs. The
1557 * depth/stencil buffer extents are ignored to handle APIs which perform
1558 * clearing operations without such information.
1561 blorp_emit_gen8_hiz_op(struct blorp_batch
*batch
,
1562 const struct blorp_params
*params
)
1564 /* We should be performing an operation on a depth or stencil buffer.
1566 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1568 /* The stencil buffer should only be enabled if a fast clear operation is
1571 if (params
->stencil
.enabled
)
1572 assert(params
->hiz_op
== ISL_AUX_OP_FAST_CLEAR
);
1574 /* From the BDW PRM Volume 2, 3DSTATE_WM_HZ_OP:
1576 * 3DSTATE_MULTISAMPLE packet must be used prior to this packet to change
1577 * the Number of Multisamples. This packet must not be used to change
1578 * Number of Multisamples in a rendering sequence.
1580 * Since HIZ may be the first thing in a batch buffer, play safe and always
1581 * emit 3DSTATE_MULTISAMPLE.
1583 blorp_emit_3dstate_multisample(batch
, params
);
1585 /* If we can't alter the depth stencil config and multiple layers are
1586 * involved, the HiZ op will fail. This is because the op requires that a
1587 * new config is emitted for each additional layer.
1589 if (batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
) {
1590 assert(params
->num_layers
<= 1);
1592 blorp_emit_depth_stencil_config(batch
, params
);
1595 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
) {
1596 switch (params
->hiz_op
) {
1597 case ISL_AUX_OP_FAST_CLEAR
:
1598 hzp
.StencilBufferClearEnable
= params
->stencil
.enabled
;
1599 hzp
.DepthBufferClearEnable
= params
->depth
.enabled
;
1600 hzp
.StencilClearValue
= params
->stencil_ref
;
1601 hzp
.FullSurfaceDepthandStencilClear
= params
->full_surface_hiz_op
;
1603 case ISL_AUX_OP_FULL_RESOLVE
:
1604 assert(params
->full_surface_hiz_op
);
1605 hzp
.DepthBufferResolveEnable
= true;
1607 case ISL_AUX_OP_AMBIGUATE
:
1608 assert(params
->full_surface_hiz_op
);
1609 hzp
.HierarchicalDepthBufferResolveEnable
= true;
1611 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1612 case ISL_AUX_OP_NONE
:
1613 unreachable("Invalid HIZ op");
1616 hzp
.NumberofMultisamples
= ffs(params
->num_samples
) - 1;
1617 hzp
.SampleMask
= 0xFFFF;
1619 /* Due to a hardware issue, this bit MBZ */
1620 assert(hzp
.ScissorRectangleEnable
== false);
1622 /* Contrary to the HW docs both fields are inclusive */
1623 hzp
.ClearRectangleXMin
= params
->x0
;
1624 hzp
.ClearRectangleYMin
= params
->y0
;
1626 /* Contrary to the HW docs both fields are exclusive */
1627 hzp
.ClearRectangleXMax
= params
->x1
;
1628 hzp
.ClearRectangleYMax
= params
->y1
;
1631 /* PIPE_CONTROL w/ all bits clear except for “Post-Sync Operation” must set
1632 * to “Write Immediate Data” enabled.
1634 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1635 pc
.PostSyncOperation
= WriteImmediateData
;
1636 pc
.Address
= blorp_get_workaround_page(batch
);
1639 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
);
1644 blorp_update_clear_color(struct blorp_batch
*batch
,
1645 const struct brw_blorp_surface_info
*info
,
1648 if (info
->clear_color_addr
.buffer
&& op
== ISL_AUX_OP_FAST_CLEAR
) {
1650 for (int i
= 0; i
< 4; i
++) {
1651 blorp_emit(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
1652 sdi
.Address
= info
->clear_color_addr
;
1653 sdi
.Address
.offset
+= i
* 4;
1654 sdi
.ImmediateData
= info
->clear_color
.u32
[i
];
1658 blorp_emit(batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
1659 sdi
.Address
= info
->clear_color_addr
;
1660 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
1661 ISL_CHANNEL_SELECT_GREEN
<< 22 |
1662 ISL_CHANNEL_SELECT_BLUE
<< 19 |
1663 ISL_CHANNEL_SELECT_ALPHA
<< 16;
1664 if (isl_format_has_int_channel(info
->view
.format
)) {
1665 for (unsigned i
= 0; i
< 4; i
++) {
1666 assert(info
->clear_color
.u32
[i
] == 0 ||
1667 info
->clear_color
.u32
[i
] == 1);
1669 sdi
.ImmediateData
|= (info
->clear_color
.u32
[0] != 0) << 31;
1670 sdi
.ImmediateData
|= (info
->clear_color
.u32
[1] != 0) << 30;
1671 sdi
.ImmediateData
|= (info
->clear_color
.u32
[2] != 0) << 29;
1672 sdi
.ImmediateData
|= (info
->clear_color
.u32
[3] != 0) << 28;
1674 for (unsigned i
= 0; i
< 4; i
++) {
1675 assert(info
->clear_color
.f32
[i
] == 0.0f
||
1676 info
->clear_color
.f32
[i
] == 1.0f
);
1678 sdi
.ImmediateData
|= (info
->clear_color
.f32
[0] != 0.0f
) << 31;
1679 sdi
.ImmediateData
|= (info
->clear_color
.f32
[1] != 0.0f
) << 30;
1680 sdi
.ImmediateData
|= (info
->clear_color
.f32
[2] != 0.0f
) << 29;
1681 sdi
.ImmediateData
|= (info
->clear_color
.f32
[3] != 0.0f
) << 28;
1689 * \brief Execute a blit or render pass operation.
1691 * To execute the operation, this function manually constructs and emits a
1692 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1693 * constructing and after emitting the batch.
1695 * This function alters no GL state.
1698 blorp_exec(struct blorp_batch
*batch
, const struct blorp_params
*params
)
1700 if (!(batch
->flags
& BLORP_BATCH_NO_UPDATE_CLEAR_COLOR
)) {
1701 blorp_update_clear_color(batch
, ¶ms
->dst
, params
->fast_clear_op
);
1702 blorp_update_clear_color(batch
, ¶ms
->depth
, params
->hiz_op
);
1706 if (params
->hiz_op
!= ISL_AUX_OP_NONE
) {
1707 blorp_emit_gen8_hiz_op(batch
, params
);
1712 blorp_emit_vertex_buffers(batch
, params
);
1713 blorp_emit_vertex_elements(batch
, params
);
1715 blorp_emit_pipeline(batch
, params
);
1717 blorp_emit_surface_states(batch
, params
);
1719 if (!(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
))
1720 blorp_emit_depth_stencil_config(batch
, params
);
1722 blorp_emit(batch
, GENX(3DPRIMITIVE
), prim
) {
1723 prim
.VertexAccessType
= SEQUENTIAL
;
1724 prim
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
1726 prim
.PredicateEnable
= batch
->flags
& BLORP_BATCH_PREDICATE_ENABLE
;
1728 prim
.VertexCountPerInstance
= 3;
1729 prim
.InstanceCount
= params
->num_layers
;
1733 #endif /* BLORP_GENX_EXEC_H */