2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BLORP_GENX_EXEC_H
25 #define BLORP_GENX_EXEC_H
27 #include "blorp_priv.h"
28 #include "common/gen_device_info.h"
29 #include "common/gen_sample_positions.h"
30 #include "intel_aub.h"
33 * This file provides the blorp pipeline setup and execution functionality.
34 * It defines the following function:
37 * blorp_exec(struct blorp_context *blorp, void *batch_data,
38 * const struct blorp_params *params);
40 * It is the job of whoever includes this header to wrap this in something
41 * to get an externally visible symbol.
43 * In order for the blorp_exec function to work, the driver must provide
44 * implementations of the following static helper functions.
48 blorp_emit_dwords(struct blorp_batch
*batch
, unsigned n
);
51 blorp_emit_reloc(struct blorp_batch
*batch
,
52 void *location
, struct blorp_address address
, uint32_t delta
);
55 blorp_alloc_dynamic_state(struct blorp_batch
*batch
,
56 enum aub_state_struct_type type
,
61 blorp_alloc_vertex_buffer(struct blorp_batch
*batch
, uint32_t size
,
62 struct blorp_address
*addr
);
65 blorp_alloc_binding_table(struct blorp_batch
*batch
, unsigned num_entries
,
66 unsigned state_size
, unsigned state_alignment
,
67 uint32_t *bt_offset
, uint32_t *surface_offsets
,
70 blorp_surface_reloc(struct blorp_batch
*batch
, uint32_t ss_offset
,
71 struct blorp_address address
, uint32_t delta
);
74 blorp_emit_urb_config(struct blorp_batch
*batch
, unsigned vs_entry_size
);
76 /***** BEGIN blorp_exec implementation ******/
78 #include "genxml/gen_macros.h"
81 _blorp_combine_address(struct blorp_batch
*batch
, void *location
,
82 struct blorp_address address
, uint32_t delta
)
84 if (address
.buffer
== NULL
) {
85 return address
.offset
+ delta
;
87 return blorp_emit_reloc(batch
, location
, address
, delta
);
91 #define __gen_address_type struct blorp_address
92 #define __gen_user_data struct blorp_batch
93 #define __gen_combine_address _blorp_combine_address
95 #include "genxml/genX_pack.h"
97 #define _blorp_cmd_length(cmd) cmd ## _length
98 #define _blorp_cmd_length_bias(cmd) cmd ## _length_bias
99 #define _blorp_cmd_header(cmd) cmd ## _header
100 #define _blorp_cmd_pack(cmd) cmd ## _pack
102 #define blorp_emit(batch, cmd, name) \
103 for (struct cmd name = { _blorp_cmd_header(cmd) }, \
104 *_dst = blorp_emit_dwords(batch, _blorp_cmd_length(cmd)); \
105 __builtin_expect(_dst != NULL, 1); \
106 _blorp_cmd_pack(cmd)(batch, (void *)_dst, &name), \
109 #define blorp_emitn(batch, cmd, n) ({ \
110 uint32_t *_dw = blorp_emit_dwords(batch, n); \
111 struct cmd template = { \
112 _blorp_cmd_header(cmd), \
113 .DWordLength = n - _blorp_cmd_length_bias(cmd), \
115 _blorp_cmd_pack(cmd)(batch, _dw, &template); \
116 _dw + 1; /* Array starts at dw[1] */ \
125 * Assign the entire URB to the VS. Even though the VS disabled, URB space
126 * is still needed because the clipper loads the VUE's from the URB. From
127 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
128 * Dword 1.15:0 "VS Number of URB Entries":
129 * This field is always used (even if VS Function Enable is DISABLED).
131 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
132 * safely ignore it because this batch contains only one draw call.
133 * Because of URB corruption caused by allocating a previous GS unit
134 * URB entry to the VS unit, software is required to send a “GS NULL
135 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
136 * plus a dummy DRAW call before any case where VS will be taking over
139 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
140 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
142 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
143 * programmed in order for the programming of this state to be
147 emit_urb_config(struct blorp_batch
*batch
,
148 const struct blorp_params
*params
)
150 /* Once vertex fetcher has written full VUE entries with complete
151 * header the space requirement is as follows per vertex (in bytes):
153 * Header Position Program constants
154 * +--------+------------+-------------------+
155 * | 16 | 16 | n x 16 |
156 * +--------+------------+-------------------+
158 * where 'n' stands for number of varying inputs expressed as vec4s.
160 const unsigned num_varyings
=
161 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
162 const unsigned total_needed
= 16 + 16 + num_varyings
* 16;
164 /* The URB size is expressed in units of 64 bytes (512 bits) */
165 const unsigned vs_entry_size
= DIV_ROUND_UP(total_needed
, 64);
167 blorp_emit_urb_config(batch
, vs_entry_size
);
171 blorp_emit_vertex_data(struct blorp_batch
*batch
,
172 const struct blorp_params
*params
,
173 struct blorp_address
*addr
,
176 const float vertices
[] = {
177 /* v0 */ (float)params
->x1
, (float)params
->y1
, params
->z
,
178 /* v1 */ (float)params
->x0
, (float)params
->y1
, params
->z
,
179 /* v2 */ (float)params
->x0
, (float)params
->y0
, params
->z
,
182 void *data
= blorp_alloc_vertex_buffer(batch
, sizeof(vertices
), addr
);
183 memcpy(data
, vertices
, sizeof(vertices
));
184 *size
= sizeof(vertices
);
188 blorp_emit_input_varying_data(struct blorp_batch
*batch
,
189 const struct blorp_params
*params
,
190 struct blorp_address
*addr
,
193 const unsigned vec4_size_in_bytes
= 4 * sizeof(float);
194 const unsigned max_num_varyings
=
195 DIV_ROUND_UP(sizeof(params
->wm_inputs
), vec4_size_in_bytes
);
196 const unsigned num_varyings
= params
->wm_prog_data
->num_varying_inputs
;
198 *size
= num_varyings
* vec4_size_in_bytes
;
200 const float *const inputs_src
= (const float *)¶ms
->wm_inputs
;
201 float *inputs
= blorp_alloc_vertex_buffer(batch
, *size
, addr
);
203 /* Walk over the attribute slots, determine if the attribute is used by
204 * the program and when necessary copy the values from the input storage to
205 * the vertex data buffer.
207 for (unsigned i
= 0; i
< max_num_varyings
; i
++) {
208 const gl_varying_slot attr
= VARYING_SLOT_VAR0
+ i
;
210 if (!(params
->wm_prog_data
->inputs_read
& (1ull << attr
)))
213 memcpy(inputs
, inputs_src
+ i
* 4, vec4_size_in_bytes
);
220 blorp_emit_vertex_buffers(struct blorp_batch
*batch
,
221 const struct blorp_params
*params
)
223 struct GENX(VERTEX_BUFFER_STATE
) vb
[2];
224 memset(vb
, 0, sizeof(vb
));
226 unsigned num_buffers
= 1;
229 blorp_emit_vertex_data(batch
, params
, &vb
[0].BufferStartingAddress
, &size
);
230 vb
[0].VertexBufferIndex
= 0;
231 vb
[0].BufferPitch
= 3 * sizeof(float);
232 vb
[0].VertexBufferMOCS
= batch
->blorp
->mocs
.vb
;
234 vb
[0].AddressModifyEnable
= true;
237 vb
[0].BufferSize
= size
;
239 vb
[0].BufferAccessType
= VERTEXDATA
;
240 vb
[0].EndAddress
= vb
[0].BufferStartingAddress
;
241 vb
[0].EndAddress
.offset
+= size
- 1;
244 if (params
->wm_prog_data
&& params
->wm_prog_data
->num_varying_inputs
) {
245 blorp_emit_input_varying_data(batch
, params
,
246 &vb
[1].BufferStartingAddress
, &size
);
247 vb
[1].VertexBufferIndex
= 1;
248 vb
[1].BufferPitch
= 0;
249 vb
[1].VertexBufferMOCS
= batch
->blorp
->mocs
.vb
;
251 vb
[1].AddressModifyEnable
= true;
254 vb
[1].BufferSize
= size
;
256 vb
[1].BufferAccessType
= INSTANCEDATA
;
257 vb
[1].EndAddress
= vb
[1].BufferStartingAddress
;
258 vb
[1].EndAddress
.offset
+= size
- 1;
263 const unsigned num_dwords
=
264 1 + GENX(VERTEX_BUFFER_STATE_length
) * num_buffers
;
265 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), num_dwords
);
267 for (unsigned i
= 0; i
< num_buffers
; i
++) {
268 GENX(VERTEX_BUFFER_STATE_pack
)(batch
, dw
, &vb
[i
]);
269 dw
+= GENX(VERTEX_BUFFER_STATE_length
);
274 blorp_emit_vertex_elements(struct blorp_batch
*batch
,
275 const struct blorp_params
*params
)
277 const unsigned num_varyings
=
278 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
279 const unsigned num_elements
= 2 + num_varyings
;
281 struct GENX(VERTEX_ELEMENT_STATE
) ve
[num_elements
];
282 memset(ve
, 0, num_elements
* sizeof(*ve
));
284 /* Setup VBO for the rectangle primitive..
286 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
287 * vertices. The vertices reside in screen space with DirectX
288 * coordinates (that is, (0, 0) is the upper left corner).
295 * Since the VS is disabled, the clipper loads each VUE directly from
296 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
297 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
298 * dw0: Reserved, MBZ.
299 * dw1: Render Target Array Index. Below vertex fetcher gets programmed
300 * to assign this with primitive instance identifier which will be
301 * used for layered clears. All other renders have only one instance
302 * and therefore the value will be effectively zero.
303 * dw2: Viewport Index. The HiZ op disables viewport mapping and
304 * scissoring, so set the dword to 0.
305 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive,
306 * so set the dword to 0.
307 * dw4: Vertex Position X.
308 * dw5: Vertex Position Y.
309 * dw6: Vertex Position Z.
310 * dw7: Vertex Position W.
312 * dw8: Flat vertex input 0
313 * dw9: Flat vertex input 1
315 * dwn: Flat vertex input n - 8
317 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
318 * "Vertex URB Entry (VUE) Formats".
320 * Only vertex position X and Y are going to be variable, Z is fixed to
321 * zero and W to one. Header words dw0,2,3 are zero. There is no need to
322 * include the fixed values in the vertex buffer. Vertex fetcher can be
323 * instructed to fill vertex elements with constant values of one and zero
324 * instead of reading them from the buffer.
325 * Flat inputs are program constants that are not interpolated. Moreover
326 * their values will be the same between vertices.
328 * See the vertex element setup below.
330 ve
[0].VertexBufferIndex
= 0;
332 ve
[0].SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
333 ve
[0].SourceElementOffset
= 0;
334 ve
[0].Component0Control
= VFCOMP_STORE_0
;
336 /* From Gen8 onwards hardware is no more instructed to overwrite components
337 * using an element specifier. Instead one has separate 3DSTATE_VF_SGVS
338 * (System Generated Value Setup) state packet for it.
341 ve
[0].Component1Control
= VFCOMP_STORE_0
;
343 ve
[0].Component1Control
= VFCOMP_STORE_IID
;
345 ve
[0].Component2Control
= VFCOMP_STORE_0
;
346 ve
[0].Component3Control
= VFCOMP_STORE_0
;
348 ve
[1].VertexBufferIndex
= 0;
350 ve
[1].SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
;
351 ve
[1].SourceElementOffset
= 0;
352 ve
[1].Component0Control
= VFCOMP_STORE_SRC
;
353 ve
[1].Component1Control
= VFCOMP_STORE_SRC
;
354 ve
[1].Component2Control
= VFCOMP_STORE_SRC
;
355 ve
[1].Component3Control
= VFCOMP_STORE_1_FP
;
357 for (unsigned i
= 0; i
< num_varyings
; ++i
) {
358 ve
[i
+ 2].VertexBufferIndex
= 1;
359 ve
[i
+ 2].Valid
= true;
360 ve
[i
+ 2].SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
361 ve
[i
+ 2].SourceElementOffset
= i
* 4 * sizeof(float);
362 ve
[i
+ 2].Component0Control
= VFCOMP_STORE_SRC
;
363 ve
[i
+ 2].Component1Control
= VFCOMP_STORE_SRC
;
364 ve
[i
+ 2].Component2Control
= VFCOMP_STORE_SRC
;
365 ve
[i
+ 2].Component3Control
= VFCOMP_STORE_SRC
;
368 const unsigned num_dwords
=
369 1 + GENX(VERTEX_ELEMENT_STATE_length
) * num_elements
;
370 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_ELEMENTS
), num_dwords
);
372 for (unsigned i
= 0; i
< num_elements
; i
++) {
373 GENX(VERTEX_ELEMENT_STATE_pack
)(batch
, dw
, &ve
[i
]);
374 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
378 /* Overwrite Render Target Array Index (2nd dword) in the VUE header with
379 * primitive instance identifier. This is used for layered clears.
381 blorp_emit(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
382 sgvs
.InstanceIDEnable
= true;
383 sgvs
.InstanceIDComponentNumber
= COMP_1
;
384 sgvs
.InstanceIDElementOffset
= 0;
387 for (unsigned i
= 0; i
< num_elements
; i
++) {
388 blorp_emit(batch
, GENX(3DSTATE_VF_INSTANCING
), vf
) {
389 vf
.VertexElementIndex
= i
;
390 vf
.InstancingEnable
= false;
394 blorp_emit(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
395 topo
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
401 blorp_emit_sf_config(struct blorp_batch
*batch
,
402 const struct blorp_params
*params
)
404 const struct brw_blorp_prog_data
*prog_data
= params
->wm_prog_data
;
408 * Disable ViewportTransformEnable (dw2.1)
410 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
411 * Primitives Overview":
412 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
413 * use of screen- space coordinates).
415 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
416 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
418 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
419 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
420 * SOLID: Any triangle or rectangle object found to be front-facing
421 * is rendered as a solid object. This setting is required when
422 * (rendering rectangle (RECTLIST) objects.
427 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
);
429 blorp_emit(batch
, GENX(3DSTATE_RASTER
), raster
) {
430 raster
.CullMode
= CULLMODE_NONE
;
433 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
434 sbe
.VertexURBEntryReadOffset
= 1;
435 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
436 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
437 sbe
.ForceVertexURBEntryReadLength
= true;
438 sbe
.ForceVertexURBEntryReadOffset
= true;
439 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
442 for (unsigned i
= 0; i
< 32; i
++)
443 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
449 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
450 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
451 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
453 sf
.MultisampleRasterizationMode
= params
->dst
.surf
.samples
> 1 ?
454 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
457 sf
.DepthBufferSurfaceFormat
= params
->depth_format
;
461 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
462 sbe
.VertexURBEntryReadOffset
= 1;
464 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
465 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
466 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
468 sbe
.NumberofSFOutputAttributes
= 0;
469 sbe
.VertexURBEntryReadLength
= 1;
473 #else /* GEN_GEN <= 6 */
475 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
476 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
477 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
479 sf
.MultisampleRasterizationMode
= params
->dst
.surf
.samples
> 1 ?
480 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
482 sf
.VertexURBEntryReadOffset
= 1;
484 sf
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
485 sf
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
486 sf
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
488 sf
.NumberofSFOutputAttributes
= 0;
489 sf
.VertexURBEntryReadLength
= 1;
497 blorp_emit_ps_config(struct blorp_batch
*batch
,
498 const struct blorp_params
*params
)
500 const struct brw_blorp_prog_data
*prog_data
= params
->wm_prog_data
;
502 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
503 * nonzero to prevent the GPU from hanging. While the documentation doesn't
504 * mention this explicitly, it notes that the valid range for the field is
505 * [1,39] = [2,40] threads, which excludes zero.
507 * To be safe (and to minimize extraneous code) we go ahead and fully
508 * configure the WM state whether or not there is a WM program.
513 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
515 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
516 if (params
->src
.enabled
) {
517 ps
.SamplerCount
= 1; /* Up to 4 samplers */
518 ps
.BindingTableEntryCount
= 2;
520 ps
.BindingTableEntryCount
= 1;
523 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
524 prog_data
->first_curbe_grf_0
;
525 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
526 prog_data
->first_curbe_grf_2
;
528 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
529 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
531 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
532 ps
.KernelStartPointer2
=
533 params
->wm_prog_kernel
+ prog_data
->ksp_offset_2
;
535 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
536 * it implicitly scales for different GT levels (which have some # of
539 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
542 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
544 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
546 switch (params
->fast_clear_op
) {
547 case BLORP_FAST_CLEAR_OP_NONE
:
550 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
551 ps
.RenderTargetResolveType
= RESOLVE_PARTIAL
;
553 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
554 ps
.RenderTargetResolveType
= RESOLVE_FULL
;
557 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
558 ps
.RenderTargetResolveEnable
= true;
561 case BLORP_FAST_CLEAR_OP_CLEAR
:
562 ps
.RenderTargetFastClearEnable
= true;
565 unreachable("Invalid fast clear op");
569 blorp_emit(batch
, GENX(3DSTATE_PS_EXTRA
), psx
) {
570 psx
.PixelShaderValid
= true;
572 if (params
->src
.enabled
)
573 psx
.PixelShaderKillsPixel
= true;
575 psx
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
577 if (prog_data
&& prog_data
->persample_msaa_dispatch
)
578 psx
.PixelShaderIsPerSample
= true;
583 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
584 switch (params
->hiz_op
) {
585 case BLORP_HIZ_OP_DEPTH_CLEAR
:
586 wm
.DepthBufferClear
= true;
588 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
589 wm
.DepthBufferResolveEnable
= true;
591 case BLORP_HIZ_OP_HIZ_RESOLVE
:
592 wm
.HierarchicalDepthBufferResolveEnable
= true;
594 case BLORP_HIZ_OP_NONE
:
597 unreachable("not reached");
601 wm
.ThreadDispatchEnable
= true;
603 if (params
->src
.enabled
)
604 wm
.PixelShaderKillPixel
= true;
606 if (params
->dst
.surf
.samples
> 1) {
607 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
608 wm
.MultisampleDispatchMode
=
609 (prog_data
&& prog_data
->persample_msaa_dispatch
) ?
610 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
612 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
613 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
617 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
618 ps
.MaximumNumberofThreads
=
619 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
626 ps
.DispatchGRFStartRegisterforConstantSetupData0
=
627 prog_data
->first_curbe_grf_0
;
628 ps
.DispatchGRFStartRegisterforConstantSetupData2
=
629 prog_data
->first_curbe_grf_2
;
631 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
632 ps
.KernelStartPointer2
=
633 params
->wm_prog_kernel
+ prog_data
->ksp_offset_2
;
635 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
636 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
638 ps
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
640 /* Gen7 hardware gets angry if we don't enable at least one dispatch
641 * mode, so just enable 16-pixel dispatch if we don't have a program.
643 ps
._16PixelDispatchEnable
= true;
646 if (params
->src
.enabled
)
647 ps
.SamplerCount
= 1; /* Up to 4 samplers */
649 switch (params
->fast_clear_op
) {
650 case BLORP_FAST_CLEAR_OP_NONE
:
652 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
653 ps
.RenderTargetResolveEnable
= true;
655 case BLORP_FAST_CLEAR_OP_CLEAR
:
656 ps
.RenderTargetFastClearEnable
= true;
659 unreachable("Invalid fast clear op");
663 #else /* GEN_GEN <= 6 */
665 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
666 wm
.MaximumNumberofThreads
=
667 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
669 switch (params
->hiz_op
) {
670 case BLORP_HIZ_OP_DEPTH_CLEAR
:
671 wm
.DepthBufferClear
= true;
673 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
674 wm
.DepthBufferResolveEnable
= true;
676 case BLORP_HIZ_OP_HIZ_RESOLVE
:
677 wm
.HierarchicalDepthBufferResolveEnable
= true;
679 case BLORP_HIZ_OP_NONE
:
682 unreachable("not reached");
686 wm
.ThreadDispatchEnable
= true;
688 wm
.DispatchGRFStartRegisterforConstantSetupData0
=
689 prog_data
->first_curbe_grf_0
;
690 wm
.DispatchGRFStartRegisterforConstantSetupData2
=
691 prog_data
->first_curbe_grf_2
;
693 wm
.KernelStartPointer0
= params
->wm_prog_kernel
;
694 wm
.KernelStartPointer2
=
695 params
->wm_prog_kernel
+ prog_data
->ksp_offset_2
;
697 wm
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
698 wm
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
700 wm
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
703 if (params
->src
.enabled
) {
704 wm
.SamplerCount
= 1; /* Up to 4 samplers */
705 wm
.PixelShaderKillPixel
= true; /* TODO: temporarily smash on */
708 if (params
->dst
.surf
.samples
> 1) {
709 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
710 wm
.MultisampleDispatchMode
=
711 (prog_data
&& prog_data
->persample_msaa_dispatch
) ?
712 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
714 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
715 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
722 static const uint32_t isl_to_gen_ds_surftype
[] = {
724 /* From the SKL PRM, "3DSTATE_DEPTH_STENCIL::SurfaceType":
726 * "If depth/stencil is enabled with 1D render target, depth/stencil
727 * surface type needs to be set to 2D surface type and height set to 1.
728 * Depth will use (legacy) TileY and stencil will use TileW. For this
729 * case only, the Surface Type of the depth buffer can be 2D while the
730 * Surface Type of the render target(s) are 1D, representing an
731 * exception to a programming note above.
733 [ISL_SURF_DIM_1D
] = SURFTYPE_2D
,
735 [ISL_SURF_DIM_1D
] = SURFTYPE_1D
,
737 [ISL_SURF_DIM_2D
] = SURFTYPE_2D
,
738 [ISL_SURF_DIM_3D
] = SURFTYPE_3D
,
742 blorp_emit_depth_stencil_config(struct blorp_batch
*batch
,
743 const struct blorp_params
*params
)
746 const uint32_t mocs
= 1; /* GEN7_MOCS_L3 */
748 const uint32_t mocs
= 0;
751 blorp_emit(batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
753 db
.DepthWriteEnable
= params
->depth
.enabled
;
754 db
.StencilWriteEnable
= params
->stencil
.enabled
;
758 db
.SeparateStencilBufferEnable
= true;
761 if (params
->depth
.enabled
) {
762 db
.SurfaceFormat
= params
->depth_format
;
763 db
.SurfaceType
= isl_to_gen_ds_surftype
[params
->depth
.surf
.dim
];
766 db
.TiledSurface
= true;
767 db
.TileWalk
= TILEWALK_YMAJOR
;
768 db
.MIPMapLayoutMode
= MIPLAYOUT_BELOW
;
771 db
.HierarchicalDepthBufferEnable
=
772 params
->depth
.aux_usage
== ISL_AUX_USAGE_HIZ
;
774 db
.Width
= params
->depth
.surf
.logical_level0_px
.width
- 1;
775 db
.Height
= params
->depth
.surf
.logical_level0_px
.height
- 1;
776 db
.RenderTargetViewExtent
= db
.Depth
=
777 params
->depth
.view
.array_len
- 1;
779 db
.LOD
= params
->depth
.view
.base_level
;
780 db
.MinimumArrayElement
= params
->depth
.view
.base_array_layer
;
782 db
.SurfacePitch
= params
->depth
.surf
.row_pitch
- 1;
785 isl_surf_get_array_pitch_el_rows(¶ms
->depth
.surf
) >> 2,
788 db
.SurfaceBaseAddress
= params
->depth
.addr
;
789 db
.DepthBufferMOCS
= mocs
;
790 } else if (params
->stencil
.enabled
) {
791 db
.SurfaceFormat
= D32_FLOAT
;
792 db
.SurfaceType
= isl_to_gen_ds_surftype
[params
->stencil
.surf
.dim
];
794 db
.Width
= params
->stencil
.surf
.logical_level0_px
.width
- 1;
795 db
.Height
= params
->stencil
.surf
.logical_level0_px
.height
- 1;
796 db
.RenderTargetViewExtent
= db
.Depth
=
797 params
->stencil
.view
.array_len
- 1;
799 db
.LOD
= params
->stencil
.view
.base_level
;
800 db
.MinimumArrayElement
= params
->stencil
.view
.base_array_layer
;
802 db
.SurfaceType
= SURFTYPE_NULL
;
803 db
.SurfaceFormat
= D32_FLOAT
;
807 blorp_emit(batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hiz
) {
808 if (params
->depth
.aux_usage
== ISL_AUX_USAGE_HIZ
) {
809 hiz
.SurfacePitch
= params
->depth
.aux_surf
.row_pitch
- 1;
810 hiz
.SurfaceBaseAddress
= params
->depth
.aux_addr
;
811 hiz
.HierarchicalDepthBufferMOCS
= mocs
;
814 isl_surf_get_array_pitch_sa_rows(¶ms
->depth
.aux_surf
) >> 2;
819 blorp_emit(batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
) {
820 if (params
->stencil
.enabled
) {
821 #if GEN_GEN >= 8 || GEN_IS_HASWELL
822 sb
.StencilBufferEnable
= true;
825 sb
.SurfacePitch
= params
->stencil
.surf
.row_pitch
- 1,
828 isl_surf_get_array_pitch_el_rows(¶ms
->stencil
.surf
) >> 2,
831 sb
.SurfaceBaseAddress
= params
->stencil
.addr
;
832 sb
.StencilBufferMOCS
= batch
->blorp
->mocs
.tex
;
836 /* 3DSTATE_CLEAR_PARAMS
838 * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS:
839 * [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE
840 * packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
842 blorp_emit(batch
, GENX(3DSTATE_CLEAR_PARAMS
), clear
) {
843 clear
.DepthClearValueValid
= true;
844 clear
.DepthClearValue
= params
->depth
.clear_color
.u32
[0];
849 blorp_emit_blend_state(struct blorp_batch
*batch
,
850 const struct blorp_params
*params
)
852 struct GENX(BLEND_STATE
) blend
;
853 memset(&blend
, 0, sizeof(blend
));
855 for (unsigned i
= 0; i
< params
->num_draw_buffers
; ++i
) {
856 blend
.Entry
[i
].PreBlendColorClampEnable
= true;
857 blend
.Entry
[i
].PostBlendColorClampEnable
= true;
858 blend
.Entry
[i
].ColorClampRange
= COLORCLAMP_RTFORMAT
;
860 blend
.Entry
[i
].WriteDisableRed
= params
->color_write_disable
[0];
861 blend
.Entry
[i
].WriteDisableGreen
= params
->color_write_disable
[1];
862 blend
.Entry
[i
].WriteDisableBlue
= params
->color_write_disable
[2];
863 blend
.Entry
[i
].WriteDisableAlpha
= params
->color_write_disable
[3];
867 void *state
= blorp_alloc_dynamic_state(batch
, AUB_TRACE_BLEND_STATE
,
868 GENX(BLEND_STATE_length
) * 4,
870 GENX(BLEND_STATE_pack
)(NULL
, state
, &blend
);
873 blorp_emit(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), sp
) {
874 sp
.BlendStatePointer
= offset
;
876 sp
.BlendStatePointerValid
= true;
882 blorp_emit(batch
, GENX(3DSTATE_PS_BLEND
), ps_blend
) {
883 ps_blend
.HasWriteableRT
= true;
891 blorp_emit_color_calc_state(struct blorp_batch
*batch
,
892 const struct blorp_params
*params
)
894 struct GENX(COLOR_CALC_STATE
) cc
= { 0 };
897 cc
.StencilReferenceValue
= params
->stencil_ref
;
901 void *state
= blorp_alloc_dynamic_state(batch
, AUB_TRACE_CC_STATE
,
902 GENX(COLOR_CALC_STATE_length
) * 4,
904 GENX(COLOR_CALC_STATE_pack
)(NULL
, state
, &cc
);
907 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), sp
) {
908 sp
.ColorCalcStatePointer
= offset
;
910 sp
.ColorCalcStatePointerValid
= true;
919 blorp_emit_depth_stencil_state(struct blorp_batch
*batch
,
920 const struct blorp_params
*params
)
923 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) ds
= {
924 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
927 struct GENX(DEPTH_STENCIL_STATE
) ds
= { 0 };
930 if (params
->depth
.enabled
) {
931 ds
.DepthBufferWriteEnable
= true;
933 switch (params
->hiz_op
) {
934 case BLORP_HIZ_OP_NONE
:
935 ds
.DepthTestEnable
= true;
936 ds
.DepthTestFunction
= COMPAREFUNCTION_ALWAYS
;
939 /* See the following sections of the Sandy Bridge PRM, Volume 2, Part1:
940 * - 7.5.3.1 Depth Buffer Clear
941 * - 7.5.3.2 Depth Buffer Resolve
942 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
944 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
945 ds
.DepthTestEnable
= true;
946 ds
.DepthTestFunction
= COMPAREFUNCTION_NEVER
;
949 case BLORP_HIZ_OP_DEPTH_CLEAR
:
950 case BLORP_HIZ_OP_HIZ_RESOLVE
:
951 ds
.DepthTestEnable
= false;
956 if (params
->stencil
.enabled
) {
957 ds
.StencilBufferWriteEnable
= true;
958 ds
.StencilTestEnable
= true;
959 ds
.DoubleSidedStencilEnable
= false;
961 ds
.StencilTestFunction
= COMPAREFUNCTION_ALWAYS
;
962 ds
.StencilPassDepthPassOp
= STENCILOP_REPLACE
;
964 ds
.StencilWriteMask
= params
->stencil_mask
;
966 ds
.StencilReferenceValue
= params
->stencil_ref
;
972 uint32_t *dw
= blorp_emit_dwords(batch
,
973 GENX(3DSTATE_WM_DEPTH_STENCIL_length
));
974 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dw
, &ds
);
977 void *state
= blorp_alloc_dynamic_state(batch
, AUB_TRACE_DEPTH_STENCIL_STATE
,
978 GENX(DEPTH_STENCIL_STATE_length
) * 4,
980 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, state
, &ds
);
984 blorp_emit(batch
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), sp
) {
985 sp
.PointertoDEPTH_STENCIL_STATE
= offset
;
992 struct surface_state_info
{
994 unsigned ss_align
; /* Required alignment of RENDER_SURFACE_STATE in bytes */
996 unsigned aux_reloc_dw
;
999 static const struct surface_state_info surface_state_infos
[] = {
1000 [6] = {6, 32, 1, 0},
1001 [7] = {8, 32, 1, 6},
1002 [8] = {13, 64, 8, 10},
1003 [9] = {16, 64, 8, 10},
1007 blorp_emit_surface_state(struct blorp_batch
*batch
,
1008 const struct brw_blorp_surface_info
*surface
,
1009 uint32_t *state
, uint32_t state_offset
,
1010 bool is_render_target
)
1012 const struct surface_state_info ss_info
= surface_state_infos
[GEN_GEN
];
1014 struct isl_surf surf
= surface
->surf
;
1016 if (surf
.dim
== ISL_SURF_DIM_1D
&&
1017 surf
.dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
) {
1018 assert(surf
.logical_level0_px
.height
== 1);
1019 surf
.dim
= ISL_SURF_DIM_2D
;
1022 /* Blorp doesn't support HiZ in any of the blit or slow-clear paths */
1023 enum isl_aux_usage aux_usage
= surface
->aux_usage
;
1024 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
1025 aux_usage
= ISL_AUX_USAGE_NONE
;
1027 const uint32_t mocs
=
1028 is_render_target
? batch
->blorp
->mocs
.rb
: batch
->blorp
->mocs
.tex
;
1030 isl_surf_fill_state(batch
->blorp
->isl_dev
, state
,
1031 .surf
= &surf
, .view
= &surface
->view
,
1032 .aux_surf
= &surface
->aux_surf
, .aux_usage
= aux_usage
,
1033 .mocs
= mocs
, .clear_color
= surface
->clear_color
);
1035 blorp_surface_reloc(batch
, state_offset
+ ss_info
.reloc_dw
* 4,
1038 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1039 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1040 * used to store other information. This should be ok, however, because
1041 * surface buffer addresses are always 4K page alinged.
1043 assert((surface
->aux_addr
.offset
& 0xfff) == 0);
1044 blorp_surface_reloc(batch
, state_offset
+ ss_info
.aux_reloc_dw
* 4,
1045 surface
->aux_addr
, state
[ss_info
.aux_reloc_dw
]);
1050 blorp_emit_surface_states(struct blorp_batch
*batch
,
1051 const struct blorp_params
*params
)
1053 uint32_t bind_offset
, surface_offsets
[2];
1054 void *surface_maps
[2];
1056 const unsigned ss_size
= GENX(RENDER_SURFACE_STATE_length
) * 4;
1057 const unsigned ss_align
= GENX(RENDER_SURFACE_STATE_length
) > 8 ? 64 : 32;
1059 unsigned num_surfaces
= 1 + params
->src
.enabled
;
1060 blorp_alloc_binding_table(batch
, num_surfaces
, ss_size
, ss_align
,
1061 &bind_offset
, surface_offsets
, surface_maps
);
1063 blorp_emit_surface_state(batch
, ¶ms
->dst
,
1064 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
],
1065 surface_offsets
[BLORP_RENDERBUFFER_BT_INDEX
], true);
1066 if (params
->src
.enabled
) {
1067 blorp_emit_surface_state(batch
, ¶ms
->src
,
1068 surface_maps
[BLORP_TEXTURE_BT_INDEX
],
1069 surface_offsets
[BLORP_TEXTURE_BT_INDEX
], false);
1073 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS
), bt
) {
1074 bt
.PointertoPSBindingTable
= bind_offset
;
1077 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1078 bt
.PSBindingTableChange
= true;
1079 bt
.PointertoPSBindingTable
= bind_offset
;
1085 blorp_emit_sampler_state(struct blorp_batch
*batch
,
1086 const struct blorp_params
*params
)
1088 struct GENX(SAMPLER_STATE
) sampler
= {
1089 .MipModeFilter
= MIPFILTER_NONE
,
1090 .MagModeFilter
= MAPFILTER_LINEAR
,
1091 .MinModeFilter
= MAPFILTER_LINEAR
,
1094 .TCXAddressControlMode
= TCM_CLAMP
,
1095 .TCYAddressControlMode
= TCM_CLAMP
,
1096 .TCZAddressControlMode
= TCM_CLAMP
,
1097 .MaximumAnisotropy
= RATIO21
,
1098 .RAddressMinFilterRoundingEnable
= true,
1099 .RAddressMagFilterRoundingEnable
= true,
1100 .VAddressMinFilterRoundingEnable
= true,
1101 .VAddressMagFilterRoundingEnable
= true,
1102 .UAddressMinFilterRoundingEnable
= true,
1103 .UAddressMagFilterRoundingEnable
= true,
1104 .NonnormalizedCoordinateEnable
= true,
1108 void *state
= blorp_alloc_dynamic_state(batch
, AUB_TRACE_SAMPLER_STATE
,
1109 GENX(SAMPLER_STATE_length
) * 4,
1111 GENX(SAMPLER_STATE_pack
)(NULL
, state
, &sampler
);
1114 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS
), ssp
) {
1115 ssp
.PointertoPSSamplerState
= offset
;
1118 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS
), ssp
) {
1119 ssp
.VSSamplerStateChange
= true;
1120 ssp
.GSSamplerStateChange
= true;
1121 ssp
.PSSamplerStateChange
= true;
1122 ssp
.PointertoPSSamplerState
= offset
;
1128 blorp_emit_3dstate_multisample(struct blorp_batch
*batch
,
1129 const struct blorp_params
*params
)
1131 const unsigned samples
= params
->dst
.surf
.samples
;
1133 blorp_emit(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1134 ms
.NumberofMultisamples
= __builtin_ffs(samples
) - 1;
1137 /* The PRM says that this bit is valid only for DX9:
1139 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
1140 * should not have any effect by setting or not setting this bit.
1142 ms
.PixelPositionOffsetEnable
= false;
1143 ms
.PixelLocation
= CENTER
;
1145 ms
.PixelLocation
= PIXLOC_CENTER
;
1149 GEN_SAMPLE_POS_1X(ms
.Sample
);
1152 GEN_SAMPLE_POS_2X(ms
.Sample
);
1155 GEN_SAMPLE_POS_4X(ms
.Sample
);
1158 GEN_SAMPLE_POS_8X(ms
.Sample
);
1164 ms
.PixelLocation
= PIXLOC_CENTER
;
1165 GEN_SAMPLE_POS_4X(ms
.Sample
);
1170 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
1172 blorp_emit_viewport_state(struct blorp_batch
*batch
,
1173 const struct blorp_params
*params
)
1175 uint32_t cc_vp_offset
;
1177 void *state
= blorp_alloc_dynamic_state(batch
, AUB_TRACE_CC_VP_STATE
,
1178 GENX(CC_VIEWPORT_length
) * 4, 32,
1181 GENX(CC_VIEWPORT_pack
)(batch
, state
,
1182 &(struct GENX(CC_VIEWPORT
)) {
1183 .MinimumDepth
= 0.0,
1184 .MaximumDepth
= 1.0,
1188 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), vsp
) {
1189 vsp
.CCViewportPointer
= cc_vp_offset
;
1192 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vsp
) {
1193 vsp
.CCViewportStateChange
= true;
1194 vsp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
1201 * \brief Execute a blit or render pass operation.
1203 * To execute the operation, this function manually constructs and emits a
1204 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1205 * constructing and after emitting the batch.
1207 * This function alters no GL state.
1210 blorp_exec(struct blorp_batch
*batch
, const struct blorp_params
*params
)
1212 uint32_t blend_state_offset
= 0;
1213 uint32_t color_calc_state_offset
= 0;
1214 uint32_t depth_stencil_state_offset
;
1216 blorp_emit_vertex_buffers(batch
, params
);
1217 blorp_emit_vertex_elements(batch
, params
);
1219 emit_urb_config(batch
, params
);
1221 if (params
->wm_prog_data
) {
1222 blend_state_offset
= blorp_emit_blend_state(batch
, params
);
1224 color_calc_state_offset
= blorp_emit_color_calc_state(batch
, params
);
1225 depth_stencil_state_offset
= blorp_emit_depth_stencil_state(batch
, params
);
1228 /* 3DSTATE_CC_STATE_POINTERS
1230 * The pointer offsets are relative to
1231 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
1233 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
1235 * The dynamic state emit helpers emit their own STATE_POINTERS packets on
1236 * gen7+. However, on gen6 and earlier, they're all lumpped together in
1237 * one CC_STATE_POINTERS packet so we have to emit that here.
1239 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), cc
) {
1240 cc
.BLEND_STATEChange
= true;
1241 cc
.COLOR_CALC_STATEChange
= true;
1242 cc
.DEPTH_STENCIL_STATEChange
= true;
1243 cc
.PointertoBLEND_STATE
= blend_state_offset
;
1244 cc
.PointertoCOLOR_CALC_STATE
= color_calc_state_offset
;
1245 cc
.PointertoDEPTH_STENCIL_STATE
= depth_stencil_state_offset
;
1248 (void)blend_state_offset
;
1249 (void)color_calc_state_offset
;
1250 (void)depth_stencil_state_offset
;
1253 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_VS
), vs
);
1255 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_HS
), hs
);
1256 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_DS
), DS
);
1258 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_GS
), gs
);
1259 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_PS
), ps
);
1261 if (params
->wm_prog_data
)
1262 blorp_emit_surface_states(batch
, params
);
1264 if (params
->src
.enabled
)
1265 blorp_emit_sampler_state(batch
, params
);
1267 blorp_emit_3dstate_multisample(batch
, params
);
1269 blorp_emit(batch
, GENX(3DSTATE_SAMPLE_MASK
), mask
) {
1270 mask
.SampleMask
= (1 << params
->dst
.surf
.samples
) - 1;
1273 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1274 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1276 * [DevSNB] A pipeline flush must be programmed prior to a
1277 * 3DSTATE_VS command that causes the VS Function Enable to
1278 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
1279 * command with CS stall bit set and a post sync operation.
1281 * We've already done one at the start of the BLORP operation.
1283 blorp_emit(batch
, GENX(3DSTATE_VS
), vs
);
1285 blorp_emit(batch
, GENX(3DSTATE_HS
), hs
);
1286 blorp_emit(batch
, GENX(3DSTATE_TE
), te
);
1287 blorp_emit(batch
, GENX(3DSTATE_DS
), DS
);
1288 blorp_emit(batch
, GENX(3DSTATE_STREAMOUT
), so
);
1290 blorp_emit(batch
, GENX(3DSTATE_GS
), gs
);
1292 blorp_emit(batch
, GENX(3DSTATE_CLIP
), clip
) {
1293 clip
.PerspectiveDivideDisable
= true;
1296 blorp_emit_sf_config(batch
, params
);
1297 blorp_emit_ps_config(batch
, params
);
1299 blorp_emit_viewport_state(batch
, params
);
1301 blorp_emit_depth_stencil_config(batch
, params
);
1303 blorp_emit(batch
, GENX(3DPRIMITIVE
), prim
) {
1304 prim
.VertexAccessType
= SEQUENTIAL
;
1305 prim
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
1306 prim
.VertexCountPerInstance
= 3;
1307 prim
.InstanceCount
= params
->num_layers
;
1311 #endif /* BLORP_GENX_EXEC_H */