2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BLORP_GENX_EXEC_H
25 #define BLORP_GENX_EXEC_H
27 #include "blorp_priv.h"
28 #include "common/gen_device_info.h"
29 #include "common/gen_sample_positions.h"
32 * This file provides the blorp pipeline setup and execution functionality.
33 * It defines the following function:
36 * blorp_exec(struct blorp_context *blorp, void *batch_data,
37 * const struct blorp_params *params);
39 * It is the job of whoever includes this header to wrap this in something
40 * to get an externally visible symbol.
42 * In order for the blorp_exec function to work, the driver must provide
43 * implementations of the following static helper functions.
47 blorp_emit_dwords(struct blorp_batch
*batch
, unsigned n
);
50 blorp_emit_reloc(struct blorp_batch
*batch
,
51 void *location
, struct blorp_address address
, uint32_t delta
);
54 blorp_alloc_dynamic_state(struct blorp_batch
*batch
,
59 blorp_alloc_vertex_buffer(struct blorp_batch
*batch
, uint32_t size
,
60 struct blorp_address
*addr
);
63 blorp_alloc_binding_table(struct blorp_batch
*batch
, unsigned num_entries
,
64 unsigned state_size
, unsigned state_alignment
,
65 uint32_t *bt_offset
, uint32_t *surface_offsets
,
69 blorp_flush_range(struct blorp_batch
*batch
, void *start
, size_t size
);
72 blorp_surface_reloc(struct blorp_batch
*batch
, uint32_t ss_offset
,
73 struct blorp_address address
, uint32_t delta
);
76 blorp_emit_urb_config(struct blorp_batch
*batch
, unsigned vs_entry_size
);
78 /***** BEGIN blorp_exec implementation ******/
80 #include "genxml/gen_macros.h"
83 _blorp_combine_address(struct blorp_batch
*batch
, void *location
,
84 struct blorp_address address
, uint32_t delta
)
86 if (address
.buffer
== NULL
) {
87 return address
.offset
+ delta
;
89 return blorp_emit_reloc(batch
, location
, address
, delta
);
93 #define __gen_address_type struct blorp_address
94 #define __gen_user_data struct blorp_batch
95 #define __gen_combine_address _blorp_combine_address
97 #include "genxml/genX_pack.h"
99 #define _blorp_cmd_length(cmd) cmd ## _length
100 #define _blorp_cmd_length_bias(cmd) cmd ## _length_bias
101 #define _blorp_cmd_header(cmd) cmd ## _header
102 #define _blorp_cmd_pack(cmd) cmd ## _pack
104 #define blorp_emit(batch, cmd, name) \
105 for (struct cmd name = { _blorp_cmd_header(cmd) }, \
106 *_dst = blorp_emit_dwords(batch, _blorp_cmd_length(cmd)); \
107 __builtin_expect(_dst != NULL, 1); \
108 _blorp_cmd_pack(cmd)(batch, (void *)_dst, &name), \
111 #define blorp_emitn(batch, cmd, n) ({ \
112 uint32_t *_dw = blorp_emit_dwords(batch, n); \
114 struct cmd template = { \
115 _blorp_cmd_header(cmd), \
116 .DWordLength = n - _blorp_cmd_length_bias(cmd), \
118 _blorp_cmd_pack(cmd)(batch, _dw, &template); \
120 _dw ? _dw + 1 : NULL; /* Array starts at dw[1] */ \
129 * Assign the entire URB to the VS. Even though the VS disabled, URB space
130 * is still needed because the clipper loads the VUE's from the URB. From
131 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE,
132 * Dword 1.15:0 "VS Number of URB Entries":
133 * This field is always used (even if VS Function Enable is DISABLED).
135 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can
136 * safely ignore it because this batch contains only one draw call.
137 * Because of URB corruption caused by allocating a previous GS unit
138 * URB entry to the VS unit, software is required to send a “GS NULL
139 * Fence” (Send URB fence with VS URB size == 1 and GS URB size == 0)
140 * plus a dummy DRAW call before any case where VS will be taking over
143 * If the 3DSTATE_URB_VS is emitted, than the others must be also.
144 * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
146 * 3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
147 * programmed in order for the programming of this state to be
151 emit_urb_config(struct blorp_batch
*batch
,
152 const struct blorp_params
*params
)
154 /* Once vertex fetcher has written full VUE entries with complete
155 * header the space requirement is as follows per vertex (in bytes):
157 * Header Position Program constants
158 * +--------+------------+-------------------+
159 * | 16 | 16 | n x 16 |
160 * +--------+------------+-------------------+
162 * where 'n' stands for number of varying inputs expressed as vec4s.
164 const unsigned num_varyings
=
165 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
166 const unsigned total_needed
= 16 + 16 + num_varyings
* 16;
168 /* The URB size is expressed in units of 64 bytes (512 bits) */
169 const unsigned vs_entry_size
= DIV_ROUND_UP(total_needed
, 64);
171 blorp_emit_urb_config(batch
, vs_entry_size
);
175 blorp_emit_vertex_data(struct blorp_batch
*batch
,
176 const struct blorp_params
*params
,
177 struct blorp_address
*addr
,
180 const float vertices
[] = {
181 /* v0 */ (float)params
->x1
, (float)params
->y1
, params
->z
,
182 /* v1 */ (float)params
->x0
, (float)params
->y1
, params
->z
,
183 /* v2 */ (float)params
->x0
, (float)params
->y0
, params
->z
,
186 void *data
= blorp_alloc_vertex_buffer(batch
, sizeof(vertices
), addr
);
187 memcpy(data
, vertices
, sizeof(vertices
));
188 *size
= sizeof(vertices
);
189 blorp_flush_range(batch
, data
, *size
);
193 blorp_emit_input_varying_data(struct blorp_batch
*batch
,
194 const struct blorp_params
*params
,
195 struct blorp_address
*addr
,
198 const unsigned vec4_size_in_bytes
= 4 * sizeof(float);
199 const unsigned max_num_varyings
=
200 DIV_ROUND_UP(sizeof(params
->wm_inputs
), vec4_size_in_bytes
);
201 const unsigned num_varyings
=
202 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
204 *size
= 16 + num_varyings
* vec4_size_in_bytes
;
206 const uint32_t *const inputs_src
= (const uint32_t *)¶ms
->wm_inputs
;
207 void *data
= blorp_alloc_vertex_buffer(batch
, *size
, addr
);
208 uint32_t *inputs
= data
;
210 /* Copy in the VS inputs */
211 assert(sizeof(params
->vs_inputs
) == 16);
212 memcpy(inputs
, ¶ms
->vs_inputs
, sizeof(params
->vs_inputs
));
215 if (params
->wm_prog_data
) {
216 /* Walk over the attribute slots, determine if the attribute is used by
217 * the program and when necessary copy the values from the input storage
218 * to the vertex data buffer.
220 for (unsigned i
= 0; i
< max_num_varyings
; i
++) {
221 const gl_varying_slot attr
= VARYING_SLOT_VAR0
+ i
;
223 const int input_index
= params
->wm_prog_data
->urb_setup
[attr
];
227 memcpy(inputs
, inputs_src
+ i
* 4, vec4_size_in_bytes
);
233 blorp_flush_range(batch
, data
, *size
);
237 blorp_emit_vertex_buffers(struct blorp_batch
*batch
,
238 const struct blorp_params
*params
)
240 struct GENX(VERTEX_BUFFER_STATE
) vb
[2];
241 memset(vb
, 0, sizeof(vb
));
244 blorp_emit_vertex_data(batch
, params
, &vb
[0].BufferStartingAddress
, &size
);
245 vb
[0].VertexBufferIndex
= 0;
246 vb
[0].BufferPitch
= 3 * sizeof(float);
247 vb
[0].VertexBufferMOCS
= batch
->blorp
->mocs
.vb
;
249 vb
[0].AddressModifyEnable
= true;
252 vb
[0].BufferSize
= size
;
254 vb
[0].BufferAccessType
= VERTEXDATA
;
255 vb
[0].EndAddress
= vb
[0].BufferStartingAddress
;
256 vb
[0].EndAddress
.offset
+= size
- 1;
259 blorp_emit_input_varying_data(batch
, params
,
260 &vb
[1].BufferStartingAddress
, &size
);
261 vb
[1].VertexBufferIndex
= 1;
262 vb
[1].BufferPitch
= 0;
263 vb
[1].VertexBufferMOCS
= batch
->blorp
->mocs
.vb
;
265 vb
[1].AddressModifyEnable
= true;
268 vb
[1].BufferSize
= size
;
270 vb
[1].BufferAccessType
= INSTANCEDATA
;
271 vb
[1].EndAddress
= vb
[1].BufferStartingAddress
;
272 vb
[1].EndAddress
.offset
+= size
- 1;
275 const unsigned num_dwords
= 1 + GENX(VERTEX_BUFFER_STATE_length
) * 2;
276 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_BUFFERS
), num_dwords
);
280 for (unsigned i
= 0; i
< 2; i
++) {
281 GENX(VERTEX_BUFFER_STATE_pack
)(batch
, dw
, &vb
[i
]);
282 dw
+= GENX(VERTEX_BUFFER_STATE_length
);
287 blorp_emit_vertex_elements(struct blorp_batch
*batch
,
288 const struct blorp_params
*params
)
290 const unsigned num_varyings
=
291 params
->wm_prog_data
? params
->wm_prog_data
->num_varying_inputs
: 0;
292 const unsigned num_elements
= 2 + num_varyings
;
294 struct GENX(VERTEX_ELEMENT_STATE
) ve
[num_elements
];
295 memset(ve
, 0, num_elements
* sizeof(*ve
));
297 /* Setup VBO for the rectangle primitive..
299 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
300 * vertices. The vertices reside in screen space with DirectX
301 * coordinates (that is, (0, 0) is the upper left corner).
308 * Since the VS is disabled, the clipper loads each VUE directly from
309 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
310 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
311 * dw0: Reserved, MBZ.
312 * dw1: Render Target Array Index. Below vertex fetcher gets programmed
313 * to assign this with primitive instance identifier which will be
314 * used for layered clears. All other renders have only one instance
315 * and therefore the value will be effectively zero.
316 * dw2: Viewport Index. The HiZ op disables viewport mapping and
317 * scissoring, so set the dword to 0.
318 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive,
319 * so set the dword to 0.
320 * dw4: Vertex Position X.
321 * dw5: Vertex Position Y.
322 * dw6: Vertex Position Z.
323 * dw7: Vertex Position W.
325 * dw8: Flat vertex input 0
326 * dw9: Flat vertex input 1
328 * dwn: Flat vertex input n - 8
330 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
331 * "Vertex URB Entry (VUE) Formats".
333 * Only vertex position X and Y are going to be variable, Z is fixed to
334 * zero and W to one. Header words dw0,2,3 are zero. There is no need to
335 * include the fixed values in the vertex buffer. Vertex fetcher can be
336 * instructed to fill vertex elements with constant values of one and zero
337 * instead of reading them from the buffer.
338 * Flat inputs are program constants that are not interpolated. Moreover
339 * their values will be the same between vertices.
341 * See the vertex element setup below.
343 ve
[0].VertexBufferIndex
= 1;
345 ve
[0].SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
346 ve
[0].SourceElementOffset
= 0;
347 ve
[0].Component0Control
= VFCOMP_STORE_SRC
;
349 /* From Gen8 onwards hardware is no more instructed to overwrite components
350 * using an element specifier. Instead one has separate 3DSTATE_VF_SGVS
351 * (System Generated Value Setup) state packet for it.
354 ve
[0].Component1Control
= VFCOMP_STORE_0
;
356 ve
[0].Component1Control
= VFCOMP_STORE_IID
;
358 ve
[0].Component2Control
= VFCOMP_STORE_SRC
;
359 ve
[0].Component3Control
= VFCOMP_STORE_SRC
;
361 ve
[1].VertexBufferIndex
= 0;
363 ve
[1].SourceElementFormat
= ISL_FORMAT_R32G32B32_FLOAT
;
364 ve
[1].SourceElementOffset
= 0;
365 ve
[1].Component0Control
= VFCOMP_STORE_SRC
;
366 ve
[1].Component1Control
= VFCOMP_STORE_SRC
;
367 ve
[1].Component2Control
= VFCOMP_STORE_SRC
;
368 ve
[1].Component3Control
= VFCOMP_STORE_1_FP
;
370 for (unsigned i
= 0; i
< num_varyings
; ++i
) {
371 ve
[i
+ 2].VertexBufferIndex
= 1;
372 ve
[i
+ 2].Valid
= true;
373 ve
[i
+ 2].SourceElementFormat
= ISL_FORMAT_R32G32B32A32_FLOAT
;
374 ve
[i
+ 2].SourceElementOffset
= 16 + i
* 4 * sizeof(float);
375 ve
[i
+ 2].Component0Control
= VFCOMP_STORE_SRC
;
376 ve
[i
+ 2].Component1Control
= VFCOMP_STORE_SRC
;
377 ve
[i
+ 2].Component2Control
= VFCOMP_STORE_SRC
;
378 ve
[i
+ 2].Component3Control
= VFCOMP_STORE_SRC
;
381 const unsigned num_dwords
=
382 1 + GENX(VERTEX_ELEMENT_STATE_length
) * num_elements
;
383 uint32_t *dw
= blorp_emitn(batch
, GENX(3DSTATE_VERTEX_ELEMENTS
), num_dwords
);
387 for (unsigned i
= 0; i
< num_elements
; i
++) {
388 GENX(VERTEX_ELEMENT_STATE_pack
)(batch
, dw
, &ve
[i
]);
389 dw
+= GENX(VERTEX_ELEMENT_STATE_length
);
393 /* Overwrite Render Target Array Index (2nd dword) in the VUE header with
394 * primitive instance identifier. This is used for layered clears.
396 blorp_emit(batch
, GENX(3DSTATE_VF_SGVS
), sgvs
) {
397 sgvs
.InstanceIDEnable
= true;
398 sgvs
.InstanceIDComponentNumber
= COMP_1
;
399 sgvs
.InstanceIDElementOffset
= 0;
402 for (unsigned i
= 0; i
< num_elements
; i
++) {
403 blorp_emit(batch
, GENX(3DSTATE_VF_INSTANCING
), vf
) {
404 vf
.VertexElementIndex
= i
;
405 vf
.InstancingEnable
= false;
409 blorp_emit(batch
, GENX(3DSTATE_VF_TOPOLOGY
), topo
) {
410 topo
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
416 blorp_emit_vs_config(struct blorp_batch
*batch
,
417 const struct blorp_params
*params
)
419 struct brw_vs_prog_data
*vs_prog_data
= params
->vs_prog_data
;
421 blorp_emit(batch
, GENX(3DSTATE_VS
), vs
) {
423 vs
.FunctionEnable
= true;
425 vs
.KernelStartPointer
= params
->vs_prog_kernel
;
427 vs
.DispatchGRFStartRegisterForURBData
=
428 vs_prog_data
->base
.base
.dispatch_grf_start_reg
;
429 vs
.VertexURBEntryReadLength
=
430 vs_prog_data
->base
.urb_read_length
;
431 vs
.VertexURBEntryReadOffset
= 0;
433 vs
.MaximumNumberofThreads
=
434 batch
->blorp
->isl_dev
->info
->max_vs_threads
- 1;
437 vs
.SIMD8DispatchEnable
=
438 vs_prog_data
->base
.dispatch_mode
== DISPATCH_MODE_SIMD8
;
445 blorp_emit_sf_config(struct blorp_batch
*batch
,
446 const struct blorp_params
*params
)
448 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
452 * Disable ViewportTransformEnable (dw2.1)
454 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
455 * Primitives Overview":
456 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
457 * use of screen- space coordinates).
459 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3)
460 * and BackFaceFillMode (dw2.5:6) to SOLID(0).
462 * From the Sandy Bridge PRM, Volume 2, Part 1, Section
463 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
464 * SOLID: Any triangle or rectangle object found to be front-facing
465 * is rendered as a solid object. This setting is required when
466 * (rendering rectangle (RECTLIST) objects.
471 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
);
473 blorp_emit(batch
, GENX(3DSTATE_RASTER
), raster
) {
474 raster
.CullMode
= CULLMODE_NONE
;
477 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
478 sbe
.VertexURBEntryReadOffset
= 1;
480 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
481 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
482 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
484 sbe
.NumberofSFOutputAttributes
= 0;
485 sbe
.VertexURBEntryReadLength
= 1;
487 sbe
.ForceVertexURBEntryReadLength
= true;
488 sbe
.ForceVertexURBEntryReadOffset
= true;
491 for (unsigned i
= 0; i
< 32; i
++)
492 sbe
.AttributeActiveComponentFormat
[i
] = ACF_XYZW
;
498 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
499 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
500 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
502 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
503 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
506 sf
.DepthBufferSurfaceFormat
= params
->depth_format
;
510 blorp_emit(batch
, GENX(3DSTATE_SBE
), sbe
) {
511 sbe
.VertexURBEntryReadOffset
= 1;
513 sbe
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
514 sbe
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
515 sbe
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
517 sbe
.NumberofSFOutputAttributes
= 0;
518 sbe
.VertexURBEntryReadLength
= 1;
522 #else /* GEN_GEN <= 6 */
524 blorp_emit(batch
, GENX(3DSTATE_SF
), sf
) {
525 sf
.FrontFaceFillMode
= FILL_MODE_SOLID
;
526 sf
.BackFaceFillMode
= FILL_MODE_SOLID
;
528 sf
.MultisampleRasterizationMode
= params
->num_samples
> 1 ?
529 MSRASTMODE_ON_PATTERN
: MSRASTMODE_OFF_PIXEL
;
531 sf
.VertexURBEntryReadOffset
= 1;
533 sf
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
534 sf
.VertexURBEntryReadLength
= brw_blorp_get_urb_length(prog_data
);
535 sf
.ConstantInterpolationEnable
= prog_data
->flat_inputs
;
537 sf
.NumberofSFOutputAttributes
= 0;
538 sf
.VertexURBEntryReadLength
= 1;
546 blorp_emit_ps_config(struct blorp_batch
*batch
,
547 const struct blorp_params
*params
)
549 const struct brw_wm_prog_data
*prog_data
= params
->wm_prog_data
;
551 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be
552 * nonzero to prevent the GPU from hanging. While the documentation doesn't
553 * mention this explicitly, it notes that the valid range for the field is
554 * [1,39] = [2,40] threads, which excludes zero.
556 * To be safe (and to minimize extraneous code) we go ahead and fully
557 * configure the WM state whether or not there is a WM program.
562 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
);
564 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
565 if (params
->src
.enabled
) {
566 ps
.SamplerCount
= 1; /* Up to 4 samplers */
567 ps
.BindingTableEntryCount
= 2;
569 ps
.BindingTableEntryCount
= 1;
573 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
574 prog_data
->base
.dispatch_grf_start_reg
;
575 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
576 prog_data
->dispatch_grf_start_reg_2
;
578 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
579 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
581 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
582 ps
.KernelStartPointer2
=
583 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
586 /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
587 * it implicitly scales for different GT levels (which have some # of
590 * In Gen8 the format is U8-2 whereas in Gen9 it is U8-1.
593 ps
.MaximumNumberofThreadsPerPSD
= 64 - 1;
595 ps
.MaximumNumberofThreadsPerPSD
= 64 - 2;
597 switch (params
->fast_clear_op
) {
598 case BLORP_FAST_CLEAR_OP_NONE
:
601 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
602 ps
.RenderTargetResolveType
= RESOLVE_PARTIAL
;
604 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
605 ps
.RenderTargetResolveType
= RESOLVE_FULL
;
608 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
609 ps
.RenderTargetResolveEnable
= true;
612 case BLORP_FAST_CLEAR_OP_CLEAR
:
613 ps
.RenderTargetFastClearEnable
= true;
616 unreachable("Invalid fast clear op");
620 blorp_emit(batch
, GENX(3DSTATE_PS_EXTRA
), psx
) {
622 psx
.PixelShaderValid
= true;
623 psx
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
624 psx
.PixelShaderIsPerSample
= prog_data
->persample_dispatch
;
627 if (params
->src
.enabled
)
628 psx
.PixelShaderKillsPixel
= true;
633 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
634 switch (params
->hiz_op
) {
635 case BLORP_HIZ_OP_DEPTH_CLEAR
:
636 wm
.DepthBufferClear
= true;
638 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
639 wm
.DepthBufferResolveEnable
= true;
641 case BLORP_HIZ_OP_HIZ_RESOLVE
:
642 wm
.HierarchicalDepthBufferResolveEnable
= true;
644 case BLORP_HIZ_OP_NONE
:
647 unreachable("not reached");
651 wm
.ThreadDispatchEnable
= true;
653 if (params
->src
.enabled
)
654 wm
.PixelShaderKillsPixel
= true;
656 if (params
->num_samples
> 1) {
657 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
658 wm
.MultisampleDispatchMode
=
659 (prog_data
&& prog_data
->persample_dispatch
) ?
660 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
662 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
663 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
667 blorp_emit(batch
, GENX(3DSTATE_PS
), ps
) {
668 ps
.MaximumNumberofThreads
=
669 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
676 ps
.DispatchGRFStartRegisterForConstantSetupData0
=
677 prog_data
->base
.dispatch_grf_start_reg
;
678 ps
.DispatchGRFStartRegisterForConstantSetupData2
=
679 prog_data
->dispatch_grf_start_reg_2
;
681 ps
.KernelStartPointer0
= params
->wm_prog_kernel
;
682 ps
.KernelStartPointer2
=
683 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
685 ps
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
686 ps
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
688 ps
.AttributeEnable
= prog_data
->num_varying_inputs
> 0;
690 /* Gen7 hardware gets angry if we don't enable at least one dispatch
691 * mode, so just enable 16-pixel dispatch if we don't have a program.
693 ps
._16PixelDispatchEnable
= true;
696 if (params
->src
.enabled
)
697 ps
.SamplerCount
= 1; /* Up to 4 samplers */
699 switch (params
->fast_clear_op
) {
700 case BLORP_FAST_CLEAR_OP_NONE
:
702 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
703 ps
.RenderTargetResolveEnable
= true;
705 case BLORP_FAST_CLEAR_OP_CLEAR
:
706 ps
.RenderTargetFastClearEnable
= true;
709 unreachable("Invalid fast clear op");
713 #else /* GEN_GEN <= 6 */
715 blorp_emit(batch
, GENX(3DSTATE_WM
), wm
) {
716 wm
.MaximumNumberofThreads
=
717 batch
->blorp
->isl_dev
->info
->max_wm_threads
- 1;
719 switch (params
->hiz_op
) {
720 case BLORP_HIZ_OP_DEPTH_CLEAR
:
721 wm
.DepthBufferClear
= true;
723 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
724 wm
.DepthBufferResolveEnable
= true;
726 case BLORP_HIZ_OP_HIZ_RESOLVE
:
727 wm
.HierarchicalDepthBufferResolveEnable
= true;
729 case BLORP_HIZ_OP_NONE
:
732 unreachable("not reached");
736 wm
.ThreadDispatchEnable
= true;
738 wm
.DispatchGRFStartRegisterForConstantSetupData0
=
739 prog_data
->base
.dispatch_grf_start_reg
;
740 wm
.DispatchGRFStartRegisterForConstantSetupData2
=
741 prog_data
->dispatch_grf_start_reg_2
;
743 wm
.KernelStartPointer0
= params
->wm_prog_kernel
;
744 wm
.KernelStartPointer2
=
745 params
->wm_prog_kernel
+ prog_data
->prog_offset_2
;
747 wm
._8PixelDispatchEnable
= prog_data
->dispatch_8
;
748 wm
._16PixelDispatchEnable
= prog_data
->dispatch_16
;
750 wm
.NumberofSFOutputAttributes
= prog_data
->num_varying_inputs
;
753 if (params
->src
.enabled
) {
754 wm
.SamplerCount
= 1; /* Up to 4 samplers */
755 wm
.PixelShaderKillsPixel
= true; /* TODO: temporarily smash on */
758 if (params
->num_samples
> 1) {
759 wm
.MultisampleRasterizationMode
= MSRASTMODE_ON_PATTERN
;
760 wm
.MultisampleDispatchMode
=
761 (prog_data
&& prog_data
->persample_dispatch
) ?
762 MSDISPMODE_PERSAMPLE
: MSDISPMODE_PERPIXEL
;
764 wm
.MultisampleRasterizationMode
= MSRASTMODE_OFF_PIXEL
;
765 wm
.MultisampleDispatchMode
= MSDISPMODE_PERSAMPLE
;
772 static const uint32_t isl_to_gen_ds_surftype
[] = {
774 /* From the SKL PRM, "3DSTATE_DEPTH_STENCIL::SurfaceType":
776 * "If depth/stencil is enabled with 1D render target, depth/stencil
777 * surface type needs to be set to 2D surface type and height set to 1.
778 * Depth will use (legacy) TileY and stencil will use TileW. For this
779 * case only, the Surface Type of the depth buffer can be 2D while the
780 * Surface Type of the render target(s) are 1D, representing an
781 * exception to a programming note above.
783 [ISL_SURF_DIM_1D
] = SURFTYPE_2D
,
785 [ISL_SURF_DIM_1D
] = SURFTYPE_1D
,
787 [ISL_SURF_DIM_2D
] = SURFTYPE_2D
,
788 [ISL_SURF_DIM_3D
] = SURFTYPE_3D
,
792 blorp_emit_depth_stencil_config(struct blorp_batch
*batch
,
793 const struct blorp_params
*params
)
795 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
797 uint32_t *dw
= blorp_emit_dwords(batch
, isl_dev
->ds
.size
/ 4);
801 struct isl_depth_stencil_hiz_emit_info info
= {
803 .mocs
= 1, /* GEN7_MOCS_L3 */
809 if (params
->depth
.enabled
) {
810 info
.view
= ¶ms
->depth
.view
;
811 } else if (params
->stencil
.enabled
) {
812 info
.view
= ¶ms
->stencil
.view
;
815 if (params
->depth
.enabled
) {
816 info
.depth_surf
= ¶ms
->depth
.surf
;
819 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.depth_offset
/ 4,
820 params
->depth
.addr
, 0);
822 info
.hiz_usage
= params
->depth
.aux_usage
;
823 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
824 info
.hiz_surf
= ¶ms
->depth
.aux_surf
;
827 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.hiz_offset
/ 4,
828 params
->depth
.aux_addr
, 0);
830 info
.depth_clear_value
= params
->depth
.clear_color
.u32
[0];
834 if (params
->stencil
.enabled
) {
835 info
.stencil_surf
= ¶ms
->stencil
.surf
;
837 info
.stencil_address
=
838 blorp_emit_reloc(batch
, dw
+ isl_dev
->ds
.stencil_offset
/ 4,
839 params
->stencil
.addr
, 0);
842 isl_emit_depth_stencil_hiz_s(isl_dev
, dw
, &info
);
846 blorp_emit_blend_state(struct blorp_batch
*batch
,
847 const struct blorp_params
*params
)
849 struct GENX(BLEND_STATE
) blend
;
850 memset(&blend
, 0, sizeof(blend
));
852 for (unsigned i
= 0; i
< params
->num_draw_buffers
; ++i
) {
853 blend
.Entry
[i
].PreBlendColorClampEnable
= true;
854 blend
.Entry
[i
].PostBlendColorClampEnable
= true;
855 blend
.Entry
[i
].ColorClampRange
= COLORCLAMP_RTFORMAT
;
857 blend
.Entry
[i
].WriteDisableRed
= params
->color_write_disable
[0];
858 blend
.Entry
[i
].WriteDisableGreen
= params
->color_write_disable
[1];
859 blend
.Entry
[i
].WriteDisableBlue
= params
->color_write_disable
[2];
860 blend
.Entry
[i
].WriteDisableAlpha
= params
->color_write_disable
[3];
864 void *state
= blorp_alloc_dynamic_state(batch
,
865 GENX(BLEND_STATE_length
) * 4,
867 GENX(BLEND_STATE_pack
)(NULL
, state
, &blend
);
868 blorp_flush_range(batch
, state
, GENX(BLEND_STATE_length
) * 4);
871 blorp_emit(batch
, GENX(3DSTATE_BLEND_STATE_POINTERS
), sp
) {
872 sp
.BlendStatePointer
= offset
;
874 sp
.BlendStatePointerValid
= true;
880 blorp_emit(batch
, GENX(3DSTATE_PS_BLEND
), ps_blend
) {
881 ps_blend
.HasWriteableRT
= true;
889 blorp_emit_color_calc_state(struct blorp_batch
*batch
,
890 const struct blorp_params
*params
)
892 struct GENX(COLOR_CALC_STATE
) cc
= { 0 };
895 cc
.StencilReferenceValue
= params
->stencil_ref
;
899 void *state
= blorp_alloc_dynamic_state(batch
,
900 GENX(COLOR_CALC_STATE_length
) * 4,
902 GENX(COLOR_CALC_STATE_pack
)(NULL
, state
, &cc
);
903 blorp_flush_range(batch
, state
, GENX(COLOR_CALC_STATE_length
) * 4);
906 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), sp
) {
907 sp
.ColorCalcStatePointer
= offset
;
909 sp
.ColorCalcStatePointerValid
= true;
918 blorp_emit_depth_stencil_state(struct blorp_batch
*batch
,
919 const struct blorp_params
*params
)
922 struct GENX(3DSTATE_WM_DEPTH_STENCIL
) ds
= {
923 GENX(3DSTATE_WM_DEPTH_STENCIL_header
),
926 struct GENX(DEPTH_STENCIL_STATE
) ds
= { 0 };
929 if (params
->depth
.enabled
) {
930 ds
.DepthBufferWriteEnable
= true;
932 switch (params
->hiz_op
) {
933 case BLORP_HIZ_OP_NONE
:
934 ds
.DepthTestEnable
= true;
935 ds
.DepthTestFunction
= COMPAREFUNCTION_ALWAYS
;
938 /* See the following sections of the Sandy Bridge PRM, Volume 2, Part1:
939 * - 7.5.3.1 Depth Buffer Clear
940 * - 7.5.3.2 Depth Buffer Resolve
941 * - 7.5.3.3 Hierarchical Depth Buffer Resolve
943 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
944 ds
.DepthTestEnable
= true;
945 ds
.DepthTestFunction
= COMPAREFUNCTION_NEVER
;
948 case BLORP_HIZ_OP_DEPTH_CLEAR
:
949 case BLORP_HIZ_OP_HIZ_RESOLVE
:
950 ds
.DepthTestEnable
= false;
955 if (params
->stencil
.enabled
) {
956 ds
.StencilBufferWriteEnable
= true;
957 ds
.StencilTestEnable
= true;
958 ds
.DoubleSidedStencilEnable
= false;
960 ds
.StencilTestFunction
= COMPAREFUNCTION_ALWAYS
;
961 ds
.StencilPassDepthPassOp
= STENCILOP_REPLACE
;
963 ds
.StencilWriteMask
= params
->stencil_mask
;
965 ds
.StencilReferenceValue
= params
->stencil_ref
;
971 uint32_t *dw
= blorp_emit_dwords(batch
,
972 GENX(3DSTATE_WM_DEPTH_STENCIL_length
));
976 GENX(3DSTATE_WM_DEPTH_STENCIL_pack
)(NULL
, dw
, &ds
);
979 void *state
= blorp_alloc_dynamic_state(batch
,
980 GENX(DEPTH_STENCIL_STATE_length
) * 4,
982 GENX(DEPTH_STENCIL_STATE_pack
)(NULL
, state
, &ds
);
983 blorp_flush_range(batch
, state
, GENX(DEPTH_STENCIL_STATE_length
) * 4);
987 blorp_emit(batch
, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS
), sp
) {
988 sp
.PointertoDEPTH_STENCIL_STATE
= offset
;
996 blorp_emit_surface_state(struct blorp_batch
*batch
,
997 const struct brw_blorp_surface_info
*surface
,
998 void *state
, uint32_t state_offset
,
999 bool is_render_target
)
1001 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1002 struct isl_surf surf
= surface
->surf
;
1004 if (surf
.dim
== ISL_SURF_DIM_1D
&&
1005 surf
.dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
) {
1006 assert(surf
.logical_level0_px
.height
== 1);
1007 surf
.dim
= ISL_SURF_DIM_2D
;
1010 /* Blorp doesn't support HiZ in any of the blit or slow-clear paths */
1011 enum isl_aux_usage aux_usage
= surface
->aux_usage
;
1012 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
1013 aux_usage
= ISL_AUX_USAGE_NONE
;
1015 const uint32_t mocs
=
1016 is_render_target
? batch
->blorp
->mocs
.rb
: batch
->blorp
->mocs
.tex
;
1018 isl_surf_fill_state(batch
->blorp
->isl_dev
, state
,
1019 .surf
= &surf
, .view
= &surface
->view
,
1020 .aux_surf
= &surface
->aux_surf
, .aux_usage
= aux_usage
,
1021 .mocs
= mocs
, .clear_color
= surface
->clear_color
);
1023 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.addr_offset
,
1026 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1027 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1028 * used to store other information. This should be ok, however, because
1029 * surface buffer addresses are always 4K page alinged.
1031 assert((surface
->aux_addr
.offset
& 0xfff) == 0);
1032 uint32_t *aux_addr
= state
+ isl_dev
->ss
.aux_addr_offset
;
1033 blorp_surface_reloc(batch
, state_offset
+ isl_dev
->ss
.aux_addr_offset
,
1034 surface
->aux_addr
, *aux_addr
);
1037 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1041 blorp_emit_null_surface_state(struct blorp_batch
*batch
,
1042 const struct brw_blorp_surface_info
*surface
,
1045 struct GENX(RENDER_SURFACE_STATE
) ss
= {
1046 .SurfaceType
= SURFTYPE_NULL
,
1047 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
1048 .Width
= surface
->surf
.logical_level0_px
.width
- 1,
1049 .Height
= surface
->surf
.logical_level0_px
.height
- 1,
1050 .MIPCountLOD
= surface
->view
.base_level
,
1051 .MinimumArrayElement
= surface
->view
.base_array_layer
,
1052 .Depth
= surface
->view
.array_len
- 1,
1053 .RenderTargetViewExtent
= surface
->view
.array_len
- 1,
1054 .NumberofMultisamples
= ffs(surface
->surf
.samples
) - 1,
1057 .SurfaceArray
= surface
->surf
.dim
!= ISL_SURF_DIM_3D
,
1063 .TiledSurface
= true,
1067 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &ss
);
1069 blorp_flush_range(batch
, state
, GENX(RENDER_SURFACE_STATE_length
) * 4);
1073 blorp_emit_surface_states(struct blorp_batch
*batch
,
1074 const struct blorp_params
*params
)
1076 const struct isl_device
*isl_dev
= batch
->blorp
->isl_dev
;
1077 uint32_t bind_offset
, surface_offsets
[2];
1078 void *surface_maps
[2];
1080 if (params
->use_pre_baked_binding_table
) {
1081 bind_offset
= params
->pre_baked_binding_table_offset
;
1083 unsigned num_surfaces
= 1 + params
->src
.enabled
;
1084 blorp_alloc_binding_table(batch
, num_surfaces
,
1085 isl_dev
->ss
.size
, isl_dev
->ss
.align
,
1086 &bind_offset
, surface_offsets
, surface_maps
);
1088 if (params
->dst
.enabled
) {
1089 blorp_emit_surface_state(batch
, ¶ms
->dst
,
1090 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
],
1091 surface_offsets
[BLORP_RENDERBUFFER_BT_INDEX
],
1094 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1095 const struct brw_blorp_surface_info
*surface
=
1096 params
->depth
.enabled
? ¶ms
->depth
: ¶ms
->stencil
;
1097 blorp_emit_null_surface_state(batch
, surface
,
1098 surface_maps
[BLORP_RENDERBUFFER_BT_INDEX
]);
1101 if (params
->src
.enabled
) {
1102 blorp_emit_surface_state(batch
, ¶ms
->src
,
1103 surface_maps
[BLORP_TEXTURE_BT_INDEX
],
1104 surface_offsets
[BLORP_TEXTURE_BT_INDEX
], false);
1109 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), bt
);
1110 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_HS
), bt
);
1111 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_DS
), bt
);
1112 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_GS
), bt
);
1114 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS
), bt
) {
1115 bt
.PointertoPSBindingTable
= bind_offset
;
1118 blorp_emit(batch
, GENX(3DSTATE_BINDING_TABLE_POINTERS
), bt
) {
1119 bt
.PSBindingTableChange
= true;
1120 bt
.PointertoPSBindingTable
= bind_offset
;
1126 blorp_emit_sampler_state(struct blorp_batch
*batch
,
1127 const struct blorp_params
*params
)
1129 struct GENX(SAMPLER_STATE
) sampler
= {
1130 .MipModeFilter
= MIPFILTER_NONE
,
1131 .MagModeFilter
= MAPFILTER_LINEAR
,
1132 .MinModeFilter
= MAPFILTER_LINEAR
,
1135 .TCXAddressControlMode
= TCM_CLAMP
,
1136 .TCYAddressControlMode
= TCM_CLAMP
,
1137 .TCZAddressControlMode
= TCM_CLAMP
,
1138 .MaximumAnisotropy
= RATIO21
,
1139 .RAddressMinFilterRoundingEnable
= true,
1140 .RAddressMagFilterRoundingEnable
= true,
1141 .VAddressMinFilterRoundingEnable
= true,
1142 .VAddressMagFilterRoundingEnable
= true,
1143 .UAddressMinFilterRoundingEnable
= true,
1144 .UAddressMagFilterRoundingEnable
= true,
1145 .NonnormalizedCoordinateEnable
= true,
1149 void *state
= blorp_alloc_dynamic_state(batch
,
1150 GENX(SAMPLER_STATE_length
) * 4,
1152 GENX(SAMPLER_STATE_pack
)(NULL
, state
, &sampler
);
1153 blorp_flush_range(batch
, state
, GENX(SAMPLER_STATE_length
) * 4);
1156 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS
), ssp
) {
1157 ssp
.PointertoPSSamplerState
= offset
;
1160 blorp_emit(batch
, GENX(3DSTATE_SAMPLER_STATE_POINTERS
), ssp
) {
1161 ssp
.VSSamplerStateChange
= true;
1162 ssp
.GSSamplerStateChange
= true;
1163 ssp
.PSSamplerStateChange
= true;
1164 ssp
.PointertoPSSamplerState
= offset
;
1170 blorp_emit_3dstate_multisample(struct blorp_batch
*batch
,
1171 const struct blorp_params
*params
)
1173 blorp_emit(batch
, GENX(3DSTATE_MULTISAMPLE
), ms
) {
1174 ms
.NumberofMultisamples
= __builtin_ffs(params
->num_samples
) - 1;
1177 /* The PRM says that this bit is valid only for DX9:
1179 * SW can choose to set this bit only for DX9 API. DX10/OGL API's
1180 * should not have any effect by setting or not setting this bit.
1182 ms
.PixelPositionOffsetEnable
= false;
1183 ms
.PixelLocation
= CENTER
;
1185 ms
.PixelLocation
= PIXLOC_CENTER
;
1187 switch (params
->num_samples
) {
1189 GEN_SAMPLE_POS_1X(ms
.Sample
);
1192 GEN_SAMPLE_POS_2X(ms
.Sample
);
1195 GEN_SAMPLE_POS_4X(ms
.Sample
);
1198 GEN_SAMPLE_POS_8X(ms
.Sample
);
1204 ms
.PixelLocation
= PIXLOC_CENTER
;
1205 GEN_SAMPLE_POS_4X(ms
.Sample
);
1211 /* Emits the Optimized HiZ sequence specified in the BDW+ PRMs. The
1212 * depth/stencil buffer extents are ignored to handle APIs which perform
1213 * clearing operations without such information.
1216 blorp_emit_gen8_hiz_op(struct blorp_batch
*batch
,
1217 const struct blorp_params
*params
)
1219 /* We should be performing an operation on a depth or stencil buffer.
1221 assert(params
->depth
.enabled
|| params
->stencil
.enabled
);
1223 /* The stencil buffer should only be enabled if a fast clear operation is
1226 if (params
->stencil
.enabled
)
1227 assert(params
->hiz_op
== BLORP_HIZ_OP_DEPTH_CLEAR
);
1229 /* If we can't alter the depth stencil config and multiple layers are
1230 * involved, the HiZ op will fail. This is because the op requires that a
1231 * new config is emitted for each additional layer.
1233 if (batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
) {
1234 assert(params
->num_layers
<= 1);
1236 blorp_emit_depth_stencil_config(batch
, params
);
1239 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
) {
1240 switch (params
->hiz_op
) {
1241 case BLORP_HIZ_OP_DEPTH_CLEAR
:
1242 hzp
.StencilBufferClearEnable
= params
->stencil
.enabled
;
1243 hzp
.DepthBufferClearEnable
= params
->depth
.enabled
;
1244 hzp
.StencilClearValue
= params
->stencil_ref
;
1246 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
1247 hzp
.DepthBufferResolveEnable
= true;
1249 case BLORP_HIZ_OP_HIZ_RESOLVE
:
1250 hzp
.HierarchicalDepthBufferResolveEnable
= true;
1252 case BLORP_HIZ_OP_NONE
:
1253 unreachable("Invalid HIZ op");
1256 hzp
.NumberofMultisamples
= ffs(params
->num_samples
) - 1;
1257 hzp
.SampleMask
= 0xFFFF;
1259 /* Due to a hardware issue, this bit MBZ */
1260 assert(hzp
.ScissorRectangleEnable
== false);
1262 /* Contrary to the HW docs both fields are inclusive */
1263 hzp
.ClearRectangleXMin
= params
->x0
;
1264 hzp
.ClearRectangleYMin
= params
->y0
;
1266 /* Contrary to the HW docs both fields are exclusive */
1267 hzp
.ClearRectangleXMax
= params
->x1
;
1268 hzp
.ClearRectangleYMax
= params
->y1
;
1271 /* PIPE_CONTROL w/ all bits clear except for “Post-Sync Operation” must set
1272 * to “Write Immediate Data” enabled.
1274 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1275 pc
.PostSyncOperation
= WriteImmediateData
;
1278 blorp_emit(batch
, GENX(3DSTATE_WM_HZ_OP
), hzp
);
1280 /* Perform depth clear specific flushing */
1281 if (params
->hiz_op
== BLORP_HIZ_OP_DEPTH_CLEAR
&& params
->depth
.enabled
) {
1282 blorp_emit(batch
, GENX(PIPE_CONTROL
), pc
) {
1283 pc
.DepthStallEnable
= true;
1284 pc
.DepthCacheFlushEnable
= true;
1290 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
1292 blorp_emit_viewport_state(struct blorp_batch
*batch
,
1293 const struct blorp_params
*params
)
1295 uint32_t cc_vp_offset
;
1297 void *state
= blorp_alloc_dynamic_state(batch
,
1298 GENX(CC_VIEWPORT_length
) * 4, 32,
1301 GENX(CC_VIEWPORT_pack
)(batch
, state
,
1302 &(struct GENX(CC_VIEWPORT
)) {
1303 .MinimumDepth
= 0.0,
1304 .MaximumDepth
= 1.0,
1306 blorp_flush_range(batch
, state
, GENX(CC_VIEWPORT_length
) * 4);
1309 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC
), vsp
) {
1310 vsp
.CCViewportPointer
= cc_vp_offset
;
1313 blorp_emit(batch
, GENX(3DSTATE_VIEWPORT_STATE_POINTERS
), vsp
) {
1314 vsp
.CCViewportStateChange
= true;
1315 vsp
.PointertoCC_VIEWPORT
= cc_vp_offset
;
1322 * \brief Execute a blit or render pass operation.
1324 * To execute the operation, this function manually constructs and emits a
1325 * batch to draw a rectangle primitive. The batchbuffer is flushed before
1326 * constructing and after emitting the batch.
1328 * This function alters no GL state.
1331 blorp_exec(struct blorp_batch
*batch
, const struct blorp_params
*params
)
1333 uint32_t blend_state_offset
= 0;
1334 uint32_t color_calc_state_offset
= 0;
1335 uint32_t depth_stencil_state_offset
;
1338 if (params
->hiz_op
!= BLORP_HIZ_OP_NONE
) {
1339 blorp_emit_gen8_hiz_op(batch
, params
);
1344 blorp_emit_vertex_buffers(batch
, params
);
1345 blorp_emit_vertex_elements(batch
, params
);
1347 emit_urb_config(batch
, params
);
1349 if (params
->wm_prog_data
) {
1350 blend_state_offset
= blorp_emit_blend_state(batch
, params
);
1352 color_calc_state_offset
= blorp_emit_color_calc_state(batch
, params
);
1353 depth_stencil_state_offset
= blorp_emit_depth_stencil_state(batch
, params
);
1356 /* 3DSTATE_CC_STATE_POINTERS
1358 * The pointer offsets are relative to
1359 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
1361 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE.
1363 * The dynamic state emit helpers emit their own STATE_POINTERS packets on
1364 * gen7+. However, on gen6 and earlier, they're all lumpped together in
1365 * one CC_STATE_POINTERS packet so we have to emit that here.
1367 blorp_emit(batch
, GENX(3DSTATE_CC_STATE_POINTERS
), cc
) {
1368 cc
.BLEND_STATEChange
= true;
1369 cc
.COLOR_CALC_STATEChange
= true;
1370 cc
.DEPTH_STENCIL_STATEChange
= true;
1371 cc
.PointertoBLEND_STATE
= blend_state_offset
;
1372 cc
.PointertoCOLOR_CALC_STATE
= color_calc_state_offset
;
1373 cc
.PointertoDEPTH_STENCIL_STATE
= depth_stencil_state_offset
;
1376 (void)blend_state_offset
;
1377 (void)color_calc_state_offset
;
1378 (void)depth_stencil_state_offset
;
1381 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_VS
), vs
);
1383 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_HS
), hs
);
1384 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_DS
), DS
);
1386 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_GS
), gs
);
1387 blorp_emit(batch
, GENX(3DSTATE_CONSTANT_PS
), ps
);
1389 blorp_emit_surface_states(batch
, params
);
1391 if (params
->src
.enabled
)
1392 blorp_emit_sampler_state(batch
, params
);
1394 blorp_emit_3dstate_multisample(batch
, params
);
1396 blorp_emit(batch
, GENX(3DSTATE_SAMPLE_MASK
), mask
) {
1397 mask
.SampleMask
= (1 << params
->num_samples
) - 1;
1400 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
1401 * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
1403 * [DevSNB] A pipeline flush must be programmed prior to a
1404 * 3DSTATE_VS command that causes the VS Function Enable to
1405 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
1406 * command with CS stall bit set and a post sync operation.
1408 * We've already done one at the start of the BLORP operation.
1410 blorp_emit_vs_config(batch
, params
);
1412 blorp_emit(batch
, GENX(3DSTATE_HS
), hs
);
1413 blorp_emit(batch
, GENX(3DSTATE_TE
), te
);
1414 blorp_emit(batch
, GENX(3DSTATE_DS
), DS
);
1415 blorp_emit(batch
, GENX(3DSTATE_STREAMOUT
), so
);
1417 blorp_emit(batch
, GENX(3DSTATE_GS
), gs
);
1419 blorp_emit(batch
, GENX(3DSTATE_CLIP
), clip
) {
1420 clip
.PerspectiveDivideDisable
= true;
1423 blorp_emit_sf_config(batch
, params
);
1424 blorp_emit_ps_config(batch
, params
);
1426 blorp_emit_viewport_state(batch
, params
);
1428 if (!(batch
->flags
& BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
))
1429 blorp_emit_depth_stencil_config(batch
, params
);
1431 blorp_emit(batch
, GENX(3DPRIMITIVE
), prim
) {
1432 prim
.VertexAccessType
= SEQUENTIAL
;
1433 prim
.PrimitiveTopologyType
= _3DPRIM_RECTLIST
;
1434 prim
.VertexCountPerInstance
= 3;
1435 prim
.InstanceCount
= params
->num_layers
;
1439 #endif /* BLORP_GENX_EXEC_H */