intel/blorp: Add support for vertex shaders
[mesa.git] / src / intel / blorp / blorp_priv.h
1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef BLORP_PRIV_H
25 #define BLORP_PRIV_H
26
27 #include <stdint.h>
28
29 #include "compiler/nir/nir.h"
30 #include "brw_compiler.h"
31
32 #include "blorp.h"
33
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37
38 /**
39 * Binding table indices used by BLORP.
40 */
41 enum {
42 BLORP_RENDERBUFFER_BT_INDEX,
43 BLORP_TEXTURE_BT_INDEX,
44 BLORP_NUM_BT_ENTRIES
45 };
46
47 enum blorp_fast_clear_op {
48 BLORP_FAST_CLEAR_OP_NONE = 0,
49 BLORP_FAST_CLEAR_OP_CLEAR,
50 BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL,
51 BLORP_FAST_CLEAR_OP_RESOLVE_FULL,
52 };
53
54 struct brw_blorp_surface_info
55 {
56 bool enabled;
57
58 struct isl_surf surf;
59 struct blorp_address addr;
60
61 struct isl_surf aux_surf;
62 struct blorp_address aux_addr;
63 enum isl_aux_usage aux_usage;
64
65 union isl_color_value clear_color;
66
67 struct isl_view view;
68
69 /* Z offset into a 3-D texture or slice of a 2-D array texture. */
70 uint32_t z_offset;
71
72 uint32_t tile_x_sa, tile_y_sa;
73 };
74
75 void
76 brw_blorp_surface_info_init(struct blorp_context *blorp,
77 struct brw_blorp_surface_info *info,
78 const struct blorp_surf *surf,
79 unsigned int level, unsigned int layer,
80 enum isl_format format, bool is_render_target);
81
82
83 struct brw_blorp_coord_transform
84 {
85 float multiplier;
86 float offset;
87 };
88
89 /**
90 * Bounding rectangle telling pixel discard which pixels are not to be
91 * touched. This is needed in when surfaces are configured as something else
92 * what they really are:
93 *
94 * - writing W-tiled stencil as Y-tiled
95 * - writing interleaved multisampled as single sampled.
96 *
97 * See blorp_nir_discard_if_outside_rect().
98 */
99 struct brw_blorp_discard_rect
100 {
101 uint32_t x0;
102 uint32_t x1;
103 uint32_t y0;
104 uint32_t y1;
105 };
106
107 /**
108 * Grid needed for blended and scaled blits of integer formats, see
109 * blorp_nir_manual_blend_bilinear().
110 */
111 struct brw_blorp_rect_grid
112 {
113 float x1;
114 float y1;
115 float pad[2];
116 };
117
118 struct blorp_surf_offset {
119 uint32_t x;
120 uint32_t y;
121 };
122
123 struct brw_blorp_wm_inputs
124 {
125 uint32_t clear_color[4];
126
127 struct brw_blorp_discard_rect discard_rect;
128 struct brw_blorp_rect_grid rect_grid;
129 struct brw_blorp_coord_transform coord_transform[2];
130
131 struct blorp_surf_offset src_offset;
132 struct blorp_surf_offset dst_offset;
133
134 /* Minimum layer setting works for all the textures types but texture_3d
135 * for which the setting has no effect. Use the z-coordinate instead.
136 */
137 uint32_t src_z;
138
139 /* Pad out to an integral number of registers */
140 uint32_t pad[1];
141 };
142
143 #define BLORP_CREATE_NIR_INPUT(shader, name, type) ({ \
144 nir_variable *input = nir_variable_create((shader), nir_var_shader_in, \
145 type, #name); \
146 if ((shader)->stage == MESA_SHADER_FRAGMENT) \
147 input->data.interpolation = INTERP_MODE_FLAT; \
148 input->data.location = VARYING_SLOT_VAR0 + \
149 offsetof(struct brw_blorp_wm_inputs, name) / (4 * sizeof(float)); \
150 input->data.location_frac = \
151 (offsetof(struct brw_blorp_wm_inputs, name) / sizeof(float)) % 4; \
152 input; \
153 })
154
155 struct blorp_vs_inputs {
156 uint32_t base_layer;
157 uint32_t _instance_id; /* Set in hardware by SGVS */
158 uint32_t pad[2];
159 };
160
161 static inline unsigned
162 brw_blorp_get_urb_length(const struct brw_wm_prog_data *prog_data)
163 {
164 if (prog_data == NULL)
165 return 1;
166
167 /* From the BSpec: 3D Pipeline - Strips and Fans - 3DSTATE_SBE
168 *
169 * read_length = ceiling((max_source_attr+1)/2)
170 */
171 return MAX2((prog_data->num_varying_inputs + 1) / 2, 1);
172 }
173
174 struct blorp_params
175 {
176 uint32_t x0;
177 uint32_t y0;
178 uint32_t x1;
179 uint32_t y1;
180 float z;
181 uint8_t stencil_mask;
182 uint8_t stencil_ref;
183 struct brw_blorp_surface_info depth;
184 struct brw_blorp_surface_info stencil;
185 uint32_t depth_format;
186 struct brw_blorp_surface_info src;
187 struct brw_blorp_surface_info dst;
188 enum blorp_hiz_op hiz_op;
189 enum blorp_fast_clear_op fast_clear_op;
190 bool color_write_disable[4];
191 struct brw_blorp_wm_inputs wm_inputs;
192 struct blorp_vs_inputs vs_inputs;
193 unsigned num_samples;
194 unsigned num_draw_buffers;
195 unsigned num_layers;
196 uint32_t vs_prog_kernel;
197 struct brw_vs_prog_data *vs_prog_data;
198 uint32_t wm_prog_kernel;
199 struct brw_wm_prog_data *wm_prog_data;
200 };
201
202 void blorp_params_init(struct blorp_params *params);
203
204 enum blorp_shader_type {
205 BLORP_SHADER_TYPE_BLIT,
206 BLORP_SHADER_TYPE_CLEAR,
207 };
208
209 struct brw_blorp_blit_prog_key
210 {
211 enum blorp_shader_type shader_type; /* Must be BLORP_SHADER_TYPE_BLIT */
212
213 /* Number of samples per pixel that have been configured in the surface
214 * state for texturing from.
215 */
216 unsigned tex_samples;
217
218 /* MSAA layout that has been configured in the surface state for texturing
219 * from.
220 */
221 enum isl_msaa_layout tex_layout;
222
223 enum isl_aux_usage tex_aux_usage;
224
225 /* Actual number of samples per pixel in the source image. */
226 unsigned src_samples;
227
228 /* Actual MSAA layout used by the source image. */
229 enum isl_msaa_layout src_layout;
230
231 /* Number of samples per pixel that have been configured in the render
232 * target.
233 */
234 unsigned rt_samples;
235
236 /* MSAA layout that has been configured in the render target. */
237 enum isl_msaa_layout rt_layout;
238
239 /* Actual number of samples per pixel in the destination image. */
240 unsigned dst_samples;
241
242 /* Actual MSAA layout used by the destination image. */
243 enum isl_msaa_layout dst_layout;
244
245 /* Type of the data to be read from the texture (one of
246 * nir_type_(int|uint|float)).
247 */
248 nir_alu_type texture_data_type;
249
250 /* True if the source image is W tiled. If true, the surface state for the
251 * source image must be configured as Y tiled, and tex_samples must be 0.
252 */
253 bool src_tiled_w;
254
255 /* True if the destination image is W tiled. If true, the surface state
256 * for the render target must be configured as Y tiled, and rt_samples must
257 * be 0.
258 */
259 bool dst_tiled_w;
260
261 /* True if the destination is an RGB format. If true, the surface state
262 * for the render target must be configured as red with three times the
263 * normal width. We need to do this because you cannot render to
264 * non-power-of-two formats.
265 */
266 bool dst_rgb;
267
268 /* True if all source samples should be blended together to produce each
269 * destination pixel. If true, src_tiled_w must be false, tex_samples must
270 * equal src_samples, and tex_samples must be nonzero.
271 */
272 bool blend;
273
274 /* True if the rectangle being sent through the rendering pipeline might be
275 * larger than the destination rectangle, so the WM program should kill any
276 * pixels that are outside the destination rectangle.
277 */
278 bool use_kill;
279
280 /**
281 * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
282 * than one sample per pixel.
283 */
284 bool persample_msaa_dispatch;
285
286 /* True for scaled blitting. */
287 bool blit_scaled;
288
289 /* True if this blit operation may involve intratile offsets on the source.
290 * In this case, we need to add the offset before texturing.
291 */
292 bool need_src_offset;
293
294 /* True if this blit operation may involve intratile offsets on the
295 * destination. In this case, we need to add the offset to gl_FragCoord.
296 */
297 bool need_dst_offset;
298
299 /* Scale factors between the pixel grid and the grid of samples. We're
300 * using grid of samples for bilinear filetring in multisample scaled blits.
301 */
302 float x_scale;
303 float y_scale;
304
305 /* True for blits with filter = GL_LINEAR. */
306 bool bilinear_filter;
307 };
308
309 /**
310 * \name BLORP internals
311 * \{
312 *
313 * Used internally by gen6_blorp_exec() and gen7_blorp_exec().
314 */
315
316 void brw_blorp_init_wm_prog_key(struct brw_wm_prog_key *wm_key);
317
318 const unsigned *
319 blorp_compile_fs(struct blorp_context *blorp, void *mem_ctx,
320 struct nir_shader *nir,
321 const struct brw_wm_prog_key *wm_key,
322 bool use_repclear,
323 struct brw_wm_prog_data *wm_prog_data,
324 unsigned *program_size);
325
326 const unsigned *
327 blorp_compile_vs(struct blorp_context *blorp, void *mem_ctx,
328 struct nir_shader *nir,
329 struct brw_vs_prog_data *vs_prog_data,
330 unsigned *program_size);
331
332 /** \} */
333
334 #ifdef __cplusplus
335 } /* end extern "C" */
336 #endif /* __cplusplus */
337
338 #endif /* BLORP_PRIV_H */