src/intel/common/gen_device_info.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdio.h>
  25 #include <stdlib.h>
  26 #include "gen_device_info.h"
  27
  28 static const struct gen_device_info gen_device_info_i965 = {
  29    .gen = 4,
  30    .has_negative_rhw_bug = true,
  31    .num_slices = 1,
  32    .max_vs_threads = 16,
  33    .max_gs_threads = 2,
  34    .max_wm_threads = 8 * 4,
  35    .urb = {
  36       .size = 256,
  37    },
  38 };
  39
  40 static const struct gen_device_info gen_device_info_g4x = {
  41    .gen = 4,
  42    .has_pln = true,
  43    .has_compr4 = true,
  44    .has_surface_tile_offset = true,
  45    .is_g4x = true,
  46    .num_slices = 1,
  47    .max_vs_threads = 32,
  48    .max_gs_threads = 2,
  49    .max_wm_threads = 10 * 5,
  50    .urb = {
  51       .size = 384,
  52    },
  53 };
  54
  55 static const struct gen_device_info gen_device_info_ilk = {
  56    .gen = 5,
  57    .has_pln = true,
  58    .has_compr4 = true,
  59    .has_surface_tile_offset = true,
  60    .num_slices = 1,
  61    .max_vs_threads = 72,
  62    .max_gs_threads = 32,
  63    .max_wm_threads = 12 * 6,
  64    .urb = {
  65       .size = 1024,
  66    },
  67 };
  68
  69 static const struct gen_device_info gen_device_info_snb_gt1 = {
  70    .gen = 6,
  71    .gt = 1,
  72    .has_hiz_and_separate_stencil = true,
  73    .has_llc = true,
  74    .has_pln = true,
  75    .has_surface_tile_offset = true,
  76    .needs_unlit_centroid_workaround = true,
  77    .num_slices = 1,
  78    .max_vs_threads = 24,
  79    .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
  80    .max_wm_threads = 40,
  81    .urb = {
  82       .size = 32,
  83       .min_vs_entries = 24,
  84       .max_vs_entries = 256,
  85       .max_gs_entries = 256,
  86    },
  87 };
  88
  89 static const struct gen_device_info gen_device_info_snb_gt2 = {
  90    .gen = 6,
  91    .gt = 2,
  92    .has_hiz_and_separate_stencil = true,
  93    .has_llc = true,
  94    .has_pln = true,
  95    .has_surface_tile_offset = true,
  96    .needs_unlit_centroid_workaround = true,
  97    .num_slices = 1,
  98    .max_vs_threads = 60,
  99    .max_gs_threads = 60,
 100    .max_wm_threads = 80,
 101    .urb = {
 102       .size = 64,
 103       .min_vs_entries = 24,
 104       .max_vs_entries = 256,
 105       .max_gs_entries = 256,
 106    },
 107 };
 108
 109 #define GEN7_FEATURES                               \
 110    .gen = 7,                                        \
 111    .has_hiz_and_separate_stencil = true,            \
 112    .must_use_separate_stencil = true,               \
 113    .has_llc = true,                                 \
 114    .has_pln = true,                                 \
 115    .has_surface_tile_offset = true
 116
 117 static const struct gen_device_info gen_device_info_ivb_gt1 = {
 118    GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
 119    .num_slices = 1,
 120    .max_vs_threads = 36,
 121    .max_tcs_threads = 36,
 122    .max_tes_threads = 36,
 123    .max_gs_threads = 36,
 124    .max_wm_threads = 48,
 125    .max_cs_threads = 36,
 126    .urb = {
 127       .size = 128,
 128       .min_vs_entries = 32,
 129       .max_vs_entries = 512,
 130       .max_tcs_entries = 32,
 131       .min_ds_entries = 10,
 132       .max_tes_entries = 288,
 133       .max_gs_entries = 192,
 134    },
 135 };
 136
 137 static const struct gen_device_info gen_device_info_ivb_gt2 = {
 138    GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
 139    .num_slices = 1,
 140    .max_vs_threads = 128,
 141    .max_tcs_threads = 128,
 142    .max_tes_threads = 128,
 143    .max_gs_threads = 128,
 144    .max_wm_threads = 172,
 145    .max_cs_threads = 64,
 146    .urb = {
 147       .size = 256,
 148       .min_vs_entries = 32,
 149       .max_vs_entries = 704,
 150       .max_tcs_entries = 64,
 151       .min_ds_entries = 10,
 152       .max_tes_entries = 448,
 153       .max_gs_entries = 320,
 154    },
 155 };
 156
 157 static const struct gen_device_info gen_device_info_byt = {
 158    GEN7_FEATURES, .is_baytrail = true, .gt = 1,
 159    .num_slices = 1,
 160    .has_llc = false,
 161    .max_vs_threads = 36,
 162    .max_tcs_threads = 36,
 163    .max_tes_threads = 36,
 164    .max_gs_threads = 36,
 165    .max_wm_threads = 48,
 166    .max_cs_threads = 32,
 167    .urb = {
 168       .size = 128,
 169       .min_vs_entries = 32,
 170       .max_vs_entries = 512,
 171       .max_tcs_entries = 32,
 172       .min_ds_entries = 10,
 173       .max_tes_entries = 288,
 174       .max_gs_entries = 192,
 175    },
 176 };
 177
 178 #define HSW_FEATURES             \
 179    GEN7_FEATURES,                \
 180    .is_haswell = true,           \
 181    .supports_simd16_3src = true, \
 182    .has_resource_streamer = true
 183
 184 static const struct gen_device_info gen_device_info_hsw_gt1 = {
 185    HSW_FEATURES, .gt = 1,
 186    .num_slices = 1,
 187    .max_vs_threads = 70,
 188    .max_tcs_threads = 70,
 189    .max_tes_threads = 70,
 190    .max_gs_threads = 70,
 191    .max_wm_threads = 102,
 192    .max_cs_threads = 70,
 193    .urb = {
 194       .size = 128,
 195       .min_vs_entries = 32,
 196       .max_vs_entries = 640,
 197       .max_tcs_entries = 64,
 198       .min_ds_entries = 10,
 199       .max_tes_entries = 384,
 200       .max_gs_entries = 256,
 201    },
 202 };
 203
 204 static const struct gen_device_info gen_device_info_hsw_gt2 = {
 205    HSW_FEATURES, .gt = 2,
 206    .num_slices = 1,
 207    .max_vs_threads = 280,
 208    .max_tcs_threads = 256,
 209    .max_tes_threads = 280,
 210    .max_gs_threads = 256,
 211    .max_wm_threads = 204,
 212    .max_cs_threads = 70,
 213    .urb = {
 214       .size = 256,
 215       .min_vs_entries = 64,
 216       .max_vs_entries = 1664,
 217       .max_tcs_entries = 128,
 218       .min_ds_entries = 10,
 219       .max_tes_entries = 960,
 220       .max_gs_entries = 640,
 221    },
 222 };
 223
 224 static const struct gen_device_info gen_device_info_hsw_gt3 = {
 225    HSW_FEATURES, .gt = 3,
 226    .num_slices = 2,
 227    .max_vs_threads = 280,
 228    .max_tcs_threads = 256,
 229    .max_tes_threads = 280,
 230    .max_gs_threads = 256,
 231    .max_wm_threads = 408,
 232    .max_cs_threads = 70,
 233    .urb = {
 234       .size = 512,
 235       .min_vs_entries = 64,
 236       .max_vs_entries = 1664,
 237       .max_tcs_entries = 128,
 238       .min_ds_entries = 10,
 239       .max_tes_entries = 960,
 240       .max_gs_entries = 640,
 241    },
 242 };
 243
 244 #define GEN8_FEATURES                               \
 245    .gen = 8,                                        \
 246    .has_hiz_and_separate_stencil = true,            \
 247    .has_resource_streamer = true,                   \
 248    .must_use_separate_stencil = true,               \
 249    .has_llc = true,                                 \
 250    .has_pln = true,                                 \
 251    .supports_simd16_3src = true,                    \
 252    .has_surface_tile_offset = true,                 \
 253    .max_vs_threads = 504,                           \
 254    .max_tcs_threads = 504,                          \
 255    .max_tes_threads = 504,                          \
 256    .max_gs_threads = 504,                           \
 257    .max_wm_threads = 384
 258
 259 static const struct gen_device_info gen_device_info_bdw_gt1 = {
 260    GEN8_FEATURES, .gt = 1,
 261    .num_slices = 1,
 262    .max_cs_threads = 42,
 263    .urb = {
 264       .size = 192,
 265       .min_vs_entries = 64,
 266       .max_vs_entries = 2560,
 267       .max_tcs_entries = 504,
 268       .min_ds_entries = 34,
 269       .max_tes_entries = 1536,
 270       .max_gs_entries = 960,
 271    }
 272 };
 273
 274 static const struct gen_device_info gen_device_info_bdw_gt2 = {
 275    GEN8_FEATURES, .gt = 2,
 276    .num_slices = 1,
 277    .max_cs_threads = 56,
 278    .urb = {
 279       .size = 384,
 280       .min_vs_entries = 64,
 281       .max_vs_entries = 2560,
 282       .max_tcs_entries = 504,
 283       .min_ds_entries = 34,
 284       .max_tes_entries = 1536,
 285       .max_gs_entries = 960,
 286    }
 287 };
 288
 289 static const struct gen_device_info gen_device_info_bdw_gt3 = {
 290    GEN8_FEATURES, .gt = 3,
 291    .num_slices = 2,
 292    .max_cs_threads = 56,
 293    .urb = {
 294       .size = 384,
 295       .min_vs_entries = 64,
 296       .max_vs_entries = 2560,
 297       .max_tcs_entries = 504,
 298       .min_ds_entries = 34,
 299       .max_tes_entries = 1536,
 300       .max_gs_entries = 960,
 301    }
 302 };
 303
 304 static const struct gen_device_info gen_device_info_chv = {
 305    GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
 306    .has_llc = false,
 307    .num_slices = 1,
 308    .max_vs_threads = 80,
 309    .max_tcs_threads = 80,
 310    .max_tes_threads = 80,
 311    .max_gs_threads = 80,
 312    .max_wm_threads = 128,
 313    .max_cs_threads = 6 * 7,
 314    .urb = {
 315       .size = 192,
 316       .min_vs_entries = 34,
 317       .max_vs_entries = 640,
 318       .max_tcs_entries = 80,
 319       .min_ds_entries = 34,
 320       .max_tes_entries = 384,
 321       .max_gs_entries = 256,
 322    }
 323 };
 324
 325 #define GEN9_FEATURES                               \
 326    .gen = 9,                                        \
 327    .has_hiz_and_separate_stencil = true,            \
 328    .has_resource_streamer = true,                   \
 329    .must_use_separate_stencil = true,               \
 330    .has_llc = true,                                 \
 331    .has_pln = true,                                 \
 332    .supports_simd16_3src = true,                    \
 333    .has_surface_tile_offset = true,                 \
 334    .max_vs_threads = 336,                           \
 335    .max_gs_threads = 336,                           \
 336    .max_tcs_threads = 336,                          \
 337    .max_tes_threads = 336,                          \
 338    .max_cs_threads = 56,                            \
 339    .urb = {                                         \
 340       .size = 384,                                  \
 341       .min_vs_entries = 64,                         \
 342       .max_vs_entries = 1856,                       \
 343       .max_tcs_entries = 672,                       \
 344       .min_ds_entries = 34,                         \
 345       .max_tes_entries = 1120,                      \
 346       .max_gs_entries = 640,                        \
 347    }
 348
 349 static const struct gen_device_info gen_device_info_skl_gt1 = {
 350    GEN9_FEATURES, .gt = 1,
 351    .num_slices = 1,
 352    .urb.size = 192,
 353 };
 354
 355 static const struct gen_device_info gen_device_info_skl_gt2 = {
 356    GEN9_FEATURES, .gt = 2,
 357    .num_slices = 1,
 358 };
 359
 360 static const struct gen_device_info gen_device_info_skl_gt3 = {
 361    GEN9_FEATURES, .gt = 3,
 362    .num_slices = 2,
 363 };
 364
 365 static const struct gen_device_info gen_device_info_skl_gt4 = {
 366    GEN9_FEATURES, .gt = 4,
 367    .num_slices = 3,
 368    /* From the "L3 Allocation and Programming" documentation:
 369     *
 370     * "URB is limited to 1008KB due to programming restrictions.  This is not a
 371     * restriction of the L3 implementation, but of the FF and other clients.
 372     * Therefore, in a GT4 implementation it is possible for the programmed
 373     * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
 374     * only 1008KB of this will be used."
 375     */
 376    .urb.size = 1008 / 3,
 377 };
 378
 379 static const struct gen_device_info gen_device_info_bxt = {
 380    GEN9_FEATURES,
 381    .is_broxton = 1,
 382    .gt = 1,
 383    .has_llc = false,
 384
 385    .num_slices = 1,
 386    .max_vs_threads = 112,
 387    .max_tcs_threads = 112,
 388    .max_tes_threads = 112,
 389    .max_gs_threads = 112,
 390    .max_cs_threads = 6 * 6,
 391    .urb = {
 392       .size = 192,
 393       .min_vs_entries = 34,
 394       .min_ds_entries = 34,
 395       .max_vs_entries = 704,
 396       .max_tcs_entries = 256,
 397       .max_tes_entries = 416,
 398       .max_gs_entries = 256,
 399    }
 400 };
 401
 402 static const struct gen_device_info gen_device_info_bxt_2x6 = {
 403    GEN9_FEATURES,
 404    .is_broxton = 1,
 405    .gt = 1,
 406    .has_llc = false,
 407
 408    .num_slices = 1,
 409    .max_vs_threads = 56, /* XXX: guess */
 410    .max_tcs_threads = 56, /* XXX: guess */
 411    .max_tes_threads = 56,
 412    .max_gs_threads = 56,
 413    .max_cs_threads = 6 * 6,
 414    .urb = {
 415       .size = 128,
 416       .min_vs_entries = 34,
 417       .min_ds_entries = 34,
 418       .max_vs_entries = 352,
 419       .max_tcs_entries = 128,
 420       .max_tes_entries = 208,
 421       .max_gs_entries = 128,
 422    }
 423 };
 424 /*
 425  * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
 426  * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
 427  */
 428
 429 static const struct gen_device_info gen_device_info_kbl_gt1 = {
 430    GEN9_FEATURES,
 431    .gt = 1,
 432
 433    .max_cs_threads = 7 * 6,
 434    .urb.size = 192,
 435    .num_slices = 1,
 436 };
 437
 438 static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
 439    GEN9_FEATURES,
 440    .gt = 1,
 441
 442    .max_cs_threads = 7 * 6,
 443    .num_slices = 1,
 444 };
 445
 446 static const struct gen_device_info gen_device_info_kbl_gt2 = {
 447    GEN9_FEATURES,
 448    .gt = 2,
 449
 450    .num_slices = 1,
 451 };
 452
 453 static const struct gen_device_info gen_device_info_kbl_gt3 = {
 454    GEN9_FEATURES,
 455    .gt = 3,
 456
 457    .num_slices = 2,
 458 };
 459
 460 static const struct gen_device_info gen_device_info_kbl_gt4 = {
 461    GEN9_FEATURES,
 462    .gt = 4,
 463
 464    /*
 465     * From the "L3 Allocation and Programming" documentation:
 466     *
 467     * "URB is limited to 1008KB due to programming restrictions.  This
 468     *  is not a restriction of the L3 implementation, but of the FF and
 469     *  other clients.  Therefore, in a GT4 implementation it is
 470     *  possible for the programmed allocation of the L3 data array to
 471     *  provide 3*384KB=1152KB for URB, but only 1008KB of this
 472     *  will be used."
 473     */
 474    .urb.size = 1008 / 3,
 475    .num_slices = 3,
 476 };
 477
 478 bool
 479 gen_get_device_info(int devid, struct gen_device_info *devinfo)
 480 {
 481    switch (devid) {
 482 #undef CHIPSET
 483 #define CHIPSET(id, family, name) \
 484       case id: *devinfo = gen_device_info_##family; break;
 485 #include "pci_ids/i965_pci_ids.h"
 486    default:
 487       fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid);
 488       return false;
 489    }
 490
 491    /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
 492     *
 493     * "Scratch Space per slice is computed based on 4 sub-slices.  SW must
 494     *  allocate scratch space enough so that each slice has 4 slices allowed."
 495     *
 496     * The equivalent internal documentation says that this programming note
 497     * applies to all Gen9+ platforms.
 498     *
 499     * The hardware typically calculates the scratch space pointer by taking
 500     * the base address, and adding per-thread-scratch-space * thread ID.
 501     * Extra padding can be necessary depending how the thread IDs are
 502     * calculated for a particular shader stage.
 503     */
 504    if (devinfo->gen >= 9) {
 505       devinfo->max_wm_threads = 64 /* threads-per-PSD */
 506                               * devinfo->num_slices
 507                               * 4; /* effective subslices per slice */
 508    }
 509
 510    return true;
 511 }
 512
 513 const char *
 514 gen_get_device_name(int devid)
 515 {
 516    switch (devid) {
 517 #undef CHIPSET
 518 #define CHIPSET(id, family, name) case id: return name;
 519 #include "pci_ids/i965_pci_ids.h"
 520    default:
 521       return NULL;
 522    }
 523 }