src/intel/common/gen_device_info.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdio.h>
  25 #include <stdlib.h>
  26 #include "gen_device_info.h"
  27 #include "compiler/shader_enums.h"
  28
  29 static const struct gen_device_info gen_device_info_i965 = {
  30    .gen = 4,
  31    .has_negative_rhw_bug = true,
  32    .num_slices = 1,
  33    .max_vs_threads = 16,
  34    .max_gs_threads = 2,
  35    .max_wm_threads = 8 * 4,
  36    .urb = {
  37       .size = 256,
  38    },
  39 };
  40
  41 static const struct gen_device_info gen_device_info_g4x = {
  42    .gen = 4,
  43    .has_pln = true,
  44    .has_compr4 = true,
  45    .has_surface_tile_offset = true,
  46    .is_g4x = true,
  47    .num_slices = 1,
  48    .max_vs_threads = 32,
  49    .max_gs_threads = 2,
  50    .max_wm_threads = 10 * 5,
  51    .urb = {
  52       .size = 384,
  53    },
  54 };
  55
  56 static const struct gen_device_info gen_device_info_ilk = {
  57    .gen = 5,
  58    .has_pln = true,
  59    .has_compr4 = true,
  60    .has_surface_tile_offset = true,
  61    .num_slices = 1,
  62    .max_vs_threads = 72,
  63    .max_gs_threads = 32,
  64    .max_wm_threads = 12 * 6,
  65    .urb = {
  66       .size = 1024,
  67    },
  68 };
  69
  70 static const struct gen_device_info gen_device_info_snb_gt1 = {
  71    .gen = 6,
  72    .gt = 1,
  73    .has_hiz_and_separate_stencil = true,
  74    .has_llc = true,
  75    .has_pln = true,
  76    .has_surface_tile_offset = true,
  77    .needs_unlit_centroid_workaround = true,
  78    .num_slices = 1,
  79    .max_vs_threads = 24,
  80    .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
  81    .max_wm_threads = 40,
  82    .urb = {
  83       .size = 32,
  84       .min_vs_entries = 24,
  85       .max_entries = {
  86          [MESA_SHADER_VERTEX]   = 256,
  87          [MESA_SHADER_GEOMETRY] = 256,
  88       },
  89    },
  90 };
  91
  92 static const struct gen_device_info gen_device_info_snb_gt2 = {
  93    .gen = 6,
  94    .gt = 2,
  95    .has_hiz_and_separate_stencil = true,
  96    .has_llc = true,
  97    .has_pln = true,
  98    .has_surface_tile_offset = true,
  99    .needs_unlit_centroid_workaround = true,
 100    .num_slices = 1,
 101    .max_vs_threads = 60,
 102    .max_gs_threads = 60,
 103    .max_wm_threads = 80,
 104    .urb = {
 105       .size = 64,
 106       .min_vs_entries = 24,
 107       .max_entries = {
 108          [MESA_SHADER_VERTEX]   = 256,
 109          [MESA_SHADER_GEOMETRY] = 256,
 110       },
 111    },
 112 };
 113
 114 #define GEN7_FEATURES                               \
 115    .gen = 7,                                        \
 116    .has_hiz_and_separate_stencil = true,            \
 117    .must_use_separate_stencil = true,               \
 118    .has_llc = true,                                 \
 119    .has_pln = true,                                 \
 120    .has_surface_tile_offset = true
 121
 122 static const struct gen_device_info gen_device_info_ivb_gt1 = {
 123    GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
 124    .num_slices = 1,
 125    .max_vs_threads = 36,
 126    .max_tcs_threads = 36,
 127    .max_tes_threads = 36,
 128    .max_gs_threads = 36,
 129    .max_wm_threads = 48,
 130    .max_cs_threads = 36,
 131    .urb = {
 132       .size = 128,
 133       .min_vs_entries = 32,
 134       .min_ds_entries = 10,
 135       .max_entries = {
 136          [MESA_SHADER_VERTEX]    = 512,
 137          [MESA_SHADER_TESS_CTRL] = 32,
 138          [MESA_SHADER_TESS_EVAL] = 288,
 139          [MESA_SHADER_GEOMETRY]  = 192,
 140       },
 141    },
 142 };
 143
 144 static const struct gen_device_info gen_device_info_ivb_gt2 = {
 145    GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
 146    .num_slices = 1,
 147    .max_vs_threads = 128,
 148    .max_tcs_threads = 128,
 149    .max_tes_threads = 128,
 150    .max_gs_threads = 128,
 151    .max_wm_threads = 172,
 152    .max_cs_threads = 64,
 153    .urb = {
 154       .size = 256,
 155       .min_vs_entries = 32,
 156       .min_ds_entries = 10,
 157       .max_entries = {
 158          [MESA_SHADER_VERTEX]    = 704,
 159          [MESA_SHADER_TESS_CTRL] = 64,
 160          [MESA_SHADER_TESS_EVAL] = 448,
 161          [MESA_SHADER_GEOMETRY]  = 320,
 162       },
 163    },
 164 };
 165
 166 static const struct gen_device_info gen_device_info_byt = {
 167    GEN7_FEATURES, .is_baytrail = true, .gt = 1,
 168    .num_slices = 1,
 169    .has_llc = false,
 170    .max_vs_threads = 36,
 171    .max_tcs_threads = 36,
 172    .max_tes_threads = 36,
 173    .max_gs_threads = 36,
 174    .max_wm_threads = 48,
 175    .max_cs_threads = 32,
 176    .urb = {
 177       .size = 128,
 178       .min_vs_entries = 32,
 179       .min_ds_entries = 10,
 180       .max_entries = {
 181          [MESA_SHADER_VERTEX]    = 512,
 182          [MESA_SHADER_TESS_CTRL] = 32,
 183          [MESA_SHADER_TESS_EVAL] = 288,
 184          [MESA_SHADER_GEOMETRY]  = 192,
 185       },
 186    },
 187 };
 188
 189 #define HSW_FEATURES             \
 190    GEN7_FEATURES,                \
 191    .is_haswell = true,           \
 192    .supports_simd16_3src = true, \
 193    .has_resource_streamer = true
 194
 195 static const struct gen_device_info gen_device_info_hsw_gt1 = {
 196    HSW_FEATURES, .gt = 1,
 197    .num_slices = 1,
 198    .max_vs_threads = 70,
 199    .max_tcs_threads = 70,
 200    .max_tes_threads = 70,
 201    .max_gs_threads = 70,
 202    .max_wm_threads = 102,
 203    .max_cs_threads = 70,
 204    .urb = {
 205       .size = 128,
 206       .min_vs_entries = 32,
 207       .min_ds_entries = 10,
 208       .max_entries = {
 209          [MESA_SHADER_VERTEX]    = 640,
 210          [MESA_SHADER_TESS_CTRL] = 64,
 211          [MESA_SHADER_TESS_EVAL] = 384,
 212          [MESA_SHADER_GEOMETRY]  = 256,
 213       },
 214    },
 215 };
 216
 217 static const struct gen_device_info gen_device_info_hsw_gt2 = {
 218    HSW_FEATURES, .gt = 2,
 219    .num_slices = 1,
 220    .max_vs_threads = 280,
 221    .max_tcs_threads = 256,
 222    .max_tes_threads = 280,
 223    .max_gs_threads = 256,
 224    .max_wm_threads = 204,
 225    .max_cs_threads = 70,
 226    .urb = {
 227       .size = 256,
 228       .min_vs_entries = 64,
 229       .min_ds_entries = 10,
 230       .max_entries = {
 231          [MESA_SHADER_VERTEX]    = 1664,
 232          [MESA_SHADER_TESS_CTRL] = 128,
 233          [MESA_SHADER_TESS_EVAL] = 960,
 234          [MESA_SHADER_GEOMETRY]  = 640,
 235       },
 236    },
 237 };
 238
 239 static const struct gen_device_info gen_device_info_hsw_gt3 = {
 240    HSW_FEATURES, .gt = 3,
 241    .num_slices = 2,
 242    .max_vs_threads = 280,
 243    .max_tcs_threads = 256,
 244    .max_tes_threads = 280,
 245    .max_gs_threads = 256,
 246    .max_wm_threads = 408,
 247    .max_cs_threads = 70,
 248    .urb = {
 249       .size = 512,
 250       .min_vs_entries = 64,
 251       .min_ds_entries = 10,
 252       .max_entries = {
 253          [MESA_SHADER_VERTEX]    = 1664,
 254          [MESA_SHADER_TESS_CTRL] = 128,
 255          [MESA_SHADER_TESS_EVAL] = 960,
 256          [MESA_SHADER_GEOMETRY]  = 640,
 257       },
 258    },
 259 };
 260
 261 #define GEN8_FEATURES                               \
 262    .gen = 8,                                        \
 263    .has_hiz_and_separate_stencil = true,            \
 264    .has_resource_streamer = true,                   \
 265    .must_use_separate_stencil = true,               \
 266    .has_llc = true,                                 \
 267    .has_pln = true,                                 \
 268    .supports_simd16_3src = true,                    \
 269    .has_surface_tile_offset = true,                 \
 270    .max_vs_threads = 504,                           \
 271    .max_tcs_threads = 504,                          \
 272    .max_tes_threads = 504,                          \
 273    .max_gs_threads = 504,                           \
 274    .max_wm_threads = 384
 275
 276 static const struct gen_device_info gen_device_info_bdw_gt1 = {
 277    GEN8_FEATURES, .gt = 1,
 278    .num_slices = 1,
 279    .max_cs_threads = 42,
 280    .urb = {
 281       .size = 192,
 282       .min_vs_entries = 64,
 283       .min_ds_entries = 34,
 284       .max_entries = {
 285          [MESA_SHADER_VERTEX]    = 2560,
 286          [MESA_SHADER_TESS_CTRL] = 504,
 287          [MESA_SHADER_TESS_EVAL] = 1536,
 288          [MESA_SHADER_GEOMETRY]  = 960,
 289       },
 290    }
 291 };
 292
 293 static const struct gen_device_info gen_device_info_bdw_gt2 = {
 294    GEN8_FEATURES, .gt = 2,
 295    .num_slices = 1,
 296    .max_cs_threads = 56,
 297    .urb = {
 298       .size = 384,
 299       .min_vs_entries = 64,
 300       .min_ds_entries = 34,
 301       .max_entries = {
 302          [MESA_SHADER_VERTEX]    = 2560,
 303          [MESA_SHADER_TESS_CTRL] = 504,
 304          [MESA_SHADER_TESS_EVAL] = 1536,
 305          [MESA_SHADER_GEOMETRY]  = 960,
 306       },
 307    }
 308 };
 309
 310 static const struct gen_device_info gen_device_info_bdw_gt3 = {
 311    GEN8_FEATURES, .gt = 3,
 312    .num_slices = 2,
 313    .max_cs_threads = 56,
 314    .urb = {
 315       .size = 384,
 316       .min_vs_entries = 64,
 317       .min_ds_entries = 34,
 318       .max_entries = {
 319          [MESA_SHADER_VERTEX]    = 2560,
 320          [MESA_SHADER_TESS_CTRL] = 504,
 321          [MESA_SHADER_TESS_EVAL] = 1536,
 322          [MESA_SHADER_GEOMETRY]  = 960,
 323       },
 324    }
 325 };
 326
 327 static const struct gen_device_info gen_device_info_chv = {
 328    GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
 329    .has_llc = false,
 330    .num_slices = 1,
 331    .max_vs_threads = 80,
 332    .max_tcs_threads = 80,
 333    .max_tes_threads = 80,
 334    .max_gs_threads = 80,
 335    .max_wm_threads = 128,
 336    .max_cs_threads = 6 * 7,
 337    .urb = {
 338       .size = 192,
 339       .min_vs_entries = 34,
 340       .min_ds_entries = 34,
 341       .max_entries = {
 342          [MESA_SHADER_VERTEX]    = 640,
 343          [MESA_SHADER_TESS_CTRL] = 80,
 344          [MESA_SHADER_TESS_EVAL] = 384,
 345          [MESA_SHADER_GEOMETRY]  = 256,
 346       },
 347    }
 348 };
 349
 350 #define GEN9_FEATURES                               \
 351    .gen = 9,                                        \
 352    .has_hiz_and_separate_stencil = true,            \
 353    .has_resource_streamer = true,                   \
 354    .must_use_separate_stencil = true,               \
 355    .has_llc = true,                                 \
 356    .has_pln = true,                                 \
 357    .supports_simd16_3src = true,                    \
 358    .has_surface_tile_offset = true,                 \
 359    .max_vs_threads = 336,                           \
 360    .max_gs_threads = 336,                           \
 361    .max_tcs_threads = 336,                          \
 362    .max_tes_threads = 336,                          \
 363    .max_cs_threads = 56,                            \
 364    .urb = {                                         \
 365       .size = 384,                                  \
 366       .min_vs_entries = 64,                         \
 367       .min_ds_entries = 34,                         \
 368       .max_entries = {                              \
 369          [MESA_SHADER_VERTEX]    = 1856,            \
 370          [MESA_SHADER_TESS_CTRL] = 672,             \
 371          [MESA_SHADER_TESS_EVAL] = 1120,            \
 372          [MESA_SHADER_GEOMETRY]  = 640,             \
 373       },                                            \
 374    }
 375
 376 #define GEN9_LP_FEATURES                           \
 377    GEN9_FEATURES,                                  \
 378    .is_broxton = 1,                                \
 379    .gt = 1,                                        \
 380    .has_llc = false,                               \
 381    .num_slices = 1,                                \
 382    .max_vs_threads = 112,                          \
 383    .max_tcs_threads = 112,                         \
 384    .max_tes_threads = 112,                         \
 385    .max_gs_threads = 112,                          \
 386    .max_cs_threads = 6 * 6,                        \
 387    .urb = {                                        \
 388       .size = 192,                                 \
 389       .min_vs_entries = 34,                        \
 390       .min_ds_entries = 34,                        \
 391       .max_entries = {                             \
 392          [MESA_SHADER_VERTEX]    = 704,            \
 393          [MESA_SHADER_TESS_CTRL] = 256,            \
 394          [MESA_SHADER_TESS_EVAL] = 416,            \
 395          [MESA_SHADER_GEOMETRY]  = 256,            \
 396       },                                           \
 397    }
 398
 399 #define GEN9_LP_FEATURES_2X6                       \
 400    GEN9_LP_FEATURES,                               \
 401    .max_vs_threads = 56,                           \
 402    .max_tcs_threads = 56,                          \
 403    .max_tes_threads = 56,                          \
 404    .max_gs_threads = 56,                           \
 405    .max_cs_threads = 6 * 6,                        \
 406    .urb = {                                        \
 407       .size = 128,                                 \
 408       .min_vs_entries = 34,                        \
 409       .min_ds_entries = 34,                        \
 410       .max_entries = {                             \
 411          [MESA_SHADER_VERTEX]    = 352,            \
 412          [MESA_SHADER_TESS_CTRL] = 128,            \
 413          [MESA_SHADER_TESS_EVAL] = 208,            \
 414          [MESA_SHADER_GEOMETRY]  = 128,            \
 415       },                                           \
 416    }
 417
 418 static const struct gen_device_info gen_device_info_skl_gt1 = {
 419    GEN9_FEATURES, .gt = 1,
 420    .num_slices = 1,
 421    .urb.size = 192,
 422 };
 423
 424 static const struct gen_device_info gen_device_info_skl_gt2 = {
 425    GEN9_FEATURES, .gt = 2,
 426    .num_slices = 1,
 427 };
 428
 429 static const struct gen_device_info gen_device_info_skl_gt3 = {
 430    GEN9_FEATURES, .gt = 3,
 431    .num_slices = 2,
 432 };
 433
 434 static const struct gen_device_info gen_device_info_skl_gt4 = {
 435    GEN9_FEATURES, .gt = 4,
 436    .num_slices = 3,
 437    /* From the "L3 Allocation and Programming" documentation:
 438     *
 439     * "URB is limited to 1008KB due to programming restrictions.  This is not a
 440     * restriction of the L3 implementation, but of the FF and other clients.
 441     * Therefore, in a GT4 implementation it is possible for the programmed
 442     * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
 443     * only 1008KB of this will be used."
 444     */
 445    .urb.size = 1008 / 3,
 446 };
 447
 448 static const struct gen_device_info gen_device_info_bxt = {
 449    GEN9_LP_FEATURES
 450 };
 451
 452 static const struct gen_device_info gen_device_info_bxt_2x6 = {
 453    GEN9_LP_FEATURES_2X6
 454 };
 455 /*
 456  * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
 457  * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
 458  */
 459
 460 static const struct gen_device_info gen_device_info_kbl_gt1 = {
 461    GEN9_FEATURES,
 462    .gt = 1,
 463
 464    .max_cs_threads = 7 * 6,
 465    .urb.size = 192,
 466    .num_slices = 1,
 467 };
 468
 469 static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
 470    GEN9_FEATURES,
 471    .gt = 1,
 472
 473    .max_cs_threads = 7 * 6,
 474    .num_slices = 1,
 475 };
 476
 477 static const struct gen_device_info gen_device_info_kbl_gt2 = {
 478    GEN9_FEATURES,
 479    .gt = 2,
 480
 481    .num_slices = 1,
 482 };
 483
 484 static const struct gen_device_info gen_device_info_kbl_gt3 = {
 485    GEN9_FEATURES,
 486    .gt = 3,
 487
 488    .num_slices = 2,
 489 };
 490
 491 static const struct gen_device_info gen_device_info_kbl_gt4 = {
 492    GEN9_FEATURES,
 493    .gt = 4,
 494
 495    /*
 496     * From the "L3 Allocation and Programming" documentation:
 497     *
 498     * "URB is limited to 1008KB due to programming restrictions.  This
 499     *  is not a restriction of the L3 implementation, but of the FF and
 500     *  other clients.  Therefore, in a GT4 implementation it is
 501     *  possible for the programmed allocation of the L3 data array to
 502     *  provide 3*384KB=1152KB for URB, but only 1008KB of this
 503     *  will be used."
 504     */
 505    .urb.size = 1008 / 3,
 506    .num_slices = 3,
 507 };
 508
 509 static const struct gen_device_info gen_device_info_glk = {
 510    GEN9_LP_FEATURES
 511 };
 512
 513 static const struct gen_device_info gen_device_info_glk_2x6 = {
 514    GEN9_LP_FEATURES_2X6
 515 };
 516
 517 bool
 518 gen_get_device_info(int devid, struct gen_device_info *devinfo)
 519 {
 520    switch (devid) {
 521 #undef CHIPSET
 522 #define CHIPSET(id, family, name) \
 523       case id: *devinfo = gen_device_info_##family; break;
 524 #include "pci_ids/i965_pci_ids.h"
 525    default:
 526       fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid);
 527       return false;
 528    }
 529
 530    /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
 531     *
 532     * "Scratch Space per slice is computed based on 4 sub-slices.  SW must
 533     *  allocate scratch space enough so that each slice has 4 slices allowed."
 534     *
 535     * The equivalent internal documentation says that this programming note
 536     * applies to all Gen9+ platforms.
 537     *
 538     * The hardware typically calculates the scratch space pointer by taking
 539     * the base address, and adding per-thread-scratch-space * thread ID.
 540     * Extra padding can be necessary depending how the thread IDs are
 541     * calculated for a particular shader stage.
 542     */
 543    if (devinfo->gen >= 9) {
 544       devinfo->max_wm_threads = 64 /* threads-per-PSD */
 545                               * devinfo->num_slices
 546                               * 4; /* effective subslices per slice */
 547    }
 548
 549    return true;
 550 }
 551
 552 const char *
 553 gen_get_device_name(int devid)
 554 {
 555    switch (devid) {
 556 #undef CHIPSET
 557 #define CHIPSET(id, family, name) case id: return name;
 558 #include "pci_ids/i965_pci_ids.h"
 559    default:
 560       return NULL;
 561    }
 562 }