src/intel/common/gen_device_info.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdio.h>
  25 #include <stdlib.h>
  26 #include "gen_device_info.h"
  27 #include "compiler/shader_enums.h"
  28
  29 static const struct gen_device_info gen_device_info_i965 = {
  30    .gen = 4,
  31    .has_negative_rhw_bug = true,
  32    .num_slices = 1,
  33    .max_vs_threads = 16,
  34    .max_gs_threads = 2,
  35    .max_wm_threads = 8 * 4,
  36    .urb = {
  37       .size = 256,
  38    },
  39    .timebase_scale = 80,
  40 };
  41
  42 static const struct gen_device_info gen_device_info_g4x = {
  43    .gen = 4,
  44    .has_pln = true,
  45    .has_compr4 = true,
  46    .has_surface_tile_offset = true,
  47    .is_g4x = true,
  48    .num_slices = 1,
  49    .max_vs_threads = 32,
  50    .max_gs_threads = 2,
  51    .max_wm_threads = 10 * 5,
  52    .urb = {
  53       .size = 384,
  54    },
  55    .timebase_scale = 80,
  56 };
  57
  58 static const struct gen_device_info gen_device_info_ilk = {
  59    .gen = 5,
  60    .has_pln = true,
  61    .has_compr4 = true,
  62    .has_surface_tile_offset = true,
  63    .num_slices = 1,
  64    .max_vs_threads = 72,
  65    .max_gs_threads = 32,
  66    .max_wm_threads = 12 * 6,
  67    .urb = {
  68       .size = 1024,
  69    },
  70    .timebase_scale = 80,
  71 };
  72
  73 static const struct gen_device_info gen_device_info_snb_gt1 = {
  74    .gen = 6,
  75    .gt = 1,
  76    .has_hiz_and_separate_stencil = true,
  77    .has_llc = true,
  78    .has_pln = true,
  79    .has_surface_tile_offset = true,
  80    .needs_unlit_centroid_workaround = true,
  81    .num_slices = 1,
  82    .max_vs_threads = 24,
  83    .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
  84    .max_wm_threads = 40,
  85    .urb = {
  86       .size = 32,
  87       .min_entries = {
  88          [MESA_SHADER_VERTEX]   = 24,
  89       },
  90       .max_entries = {
  91          [MESA_SHADER_VERTEX]   = 256,
  92          [MESA_SHADER_GEOMETRY] = 256,
  93       },
  94    },
  95    .timebase_scale = 80,
  96 };
  97
  98 static const struct gen_device_info gen_device_info_snb_gt2 = {
  99    .gen = 6,
 100    .gt = 2,
 101    .has_hiz_and_separate_stencil = true,
 102    .has_llc = true,
 103    .has_pln = true,
 104    .has_surface_tile_offset = true,
 105    .needs_unlit_centroid_workaround = true,
 106    .num_slices = 1,
 107    .max_vs_threads = 60,
 108    .max_gs_threads = 60,
 109    .max_wm_threads = 80,
 110    .urb = {
 111       .size = 64,
 112       .min_entries = {
 113          [MESA_SHADER_VERTEX]   = 24,
 114       },
 115       .max_entries = {
 116          [MESA_SHADER_VERTEX]   = 256,
 117          [MESA_SHADER_GEOMETRY] = 256,
 118       },
 119    },
 120    .timebase_scale = 80,
 121 };
 122
 123 #define GEN7_FEATURES                               \
 124    .gen = 7,                                        \
 125    .has_hiz_and_separate_stencil = true,            \
 126    .must_use_separate_stencil = true,               \
 127    .has_llc = true,                                 \
 128    .has_pln = true,                                 \
 129    .has_surface_tile_offset = true,                 \
 130    .timebase_scale = 80
 131
 132 static const struct gen_device_info gen_device_info_ivb_gt1 = {
 133    GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
 134    .num_slices = 1,
 135    .l3_banks = 2,
 136    .max_vs_threads = 36,
 137    .max_tcs_threads = 36,
 138    .max_tes_threads = 36,
 139    .max_gs_threads = 36,
 140    .max_wm_threads = 48,
 141    .max_cs_threads = 36,
 142    .urb = {
 143       .size = 128,
 144       .min_entries = {
 145          [MESA_SHADER_VERTEX]    = 32,
 146          [MESA_SHADER_TESS_EVAL] = 10,
 147       },
 148       .max_entries = {
 149          [MESA_SHADER_VERTEX]    = 512,
 150          [MESA_SHADER_TESS_CTRL] = 32,
 151          [MESA_SHADER_TESS_EVAL] = 288,
 152          [MESA_SHADER_GEOMETRY]  = 192,
 153       },
 154    },
 155 };
 156
 157 static const struct gen_device_info gen_device_info_ivb_gt2 = {
 158    GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
 159    .num_slices = 1,
 160    .l3_banks = 4,
 161    .max_vs_threads = 128,
 162    .max_tcs_threads = 128,
 163    .max_tes_threads = 128,
 164    .max_gs_threads = 128,
 165    .max_wm_threads = 172,
 166    .max_cs_threads = 64,
 167    .urb = {
 168       .size = 256,
 169       .min_entries = {
 170          [MESA_SHADER_VERTEX]    = 32,
 171          [MESA_SHADER_TESS_EVAL] = 10,
 172       },
 173       .max_entries = {
 174          [MESA_SHADER_VERTEX]    = 704,
 175          [MESA_SHADER_TESS_CTRL] = 64,
 176          [MESA_SHADER_TESS_EVAL] = 448,
 177          [MESA_SHADER_GEOMETRY]  = 320,
 178       },
 179    },
 180 };
 181
 182 static const struct gen_device_info gen_device_info_byt = {
 183    GEN7_FEATURES, .is_baytrail = true, .gt = 1,
 184    .num_slices = 1,
 185    .l3_banks = 1,
 186    .has_llc = false,
 187    .max_vs_threads = 36,
 188    .max_tcs_threads = 36,
 189    .max_tes_threads = 36,
 190    .max_gs_threads = 36,
 191    .max_wm_threads = 48,
 192    .max_cs_threads = 32,
 193    .urb = {
 194       .size = 128,
 195       .min_entries = {
 196          [MESA_SHADER_VERTEX]    = 32,
 197          [MESA_SHADER_TESS_EVAL] = 10,
 198       },
 199       .max_entries = {
 200          [MESA_SHADER_VERTEX]    = 512,
 201          [MESA_SHADER_TESS_CTRL] = 32,
 202          [MESA_SHADER_TESS_EVAL] = 288,
 203          [MESA_SHADER_GEOMETRY]  = 192,
 204       },
 205    },
 206 };
 207
 208 #define HSW_FEATURES             \
 209    GEN7_FEATURES,                \
 210    .is_haswell = true,           \
 211    .supports_simd16_3src = true, \
 212    .has_resource_streamer = true
 213
 214 static const struct gen_device_info gen_device_info_hsw_gt1 = {
 215    HSW_FEATURES, .gt = 1,
 216    .num_slices = 1,
 217    .l3_banks = 2,
 218    .max_vs_threads = 70,
 219    .max_tcs_threads = 70,
 220    .max_tes_threads = 70,
 221    .max_gs_threads = 70,
 222    .max_wm_threads = 102,
 223    .max_cs_threads = 70,
 224    .urb = {
 225       .size = 128,
 226       .min_entries = {
 227          [MESA_SHADER_VERTEX]    = 32,
 228          [MESA_SHADER_TESS_EVAL] = 10,
 229       },
 230       .max_entries = {
 231          [MESA_SHADER_VERTEX]    = 640,
 232          [MESA_SHADER_TESS_CTRL] = 64,
 233          [MESA_SHADER_TESS_EVAL] = 384,
 234          [MESA_SHADER_GEOMETRY]  = 256,
 235       },
 236    },
 237 };
 238
 239 static const struct gen_device_info gen_device_info_hsw_gt2 = {
 240    HSW_FEATURES, .gt = 2,
 241    .num_slices = 1,
 242    .l3_banks = 4,
 243    .max_vs_threads = 280,
 244    .max_tcs_threads = 256,
 245    .max_tes_threads = 280,
 246    .max_gs_threads = 256,
 247    .max_wm_threads = 204,
 248    .max_cs_threads = 70,
 249    .urb = {
 250       .size = 256,
 251       .min_entries = {
 252          [MESA_SHADER_VERTEX]    = 64,
 253          [MESA_SHADER_TESS_EVAL] = 10,
 254       },
 255       .max_entries = {
 256          [MESA_SHADER_VERTEX]    = 1664,
 257          [MESA_SHADER_TESS_CTRL] = 128,
 258          [MESA_SHADER_TESS_EVAL] = 960,
 259          [MESA_SHADER_GEOMETRY]  = 640,
 260       },
 261    },
 262 };
 263
 264 static const struct gen_device_info gen_device_info_hsw_gt3 = {
 265    HSW_FEATURES, .gt = 3,
 266    .num_slices = 2,
 267    .l3_banks = 8,
 268    .max_vs_threads = 280,
 269    .max_tcs_threads = 256,
 270    .max_tes_threads = 280,
 271    .max_gs_threads = 256,
 272    .max_wm_threads = 408,
 273    .max_cs_threads = 70,
 274    .urb = {
 275       .size = 512,
 276       .min_entries = {
 277          [MESA_SHADER_VERTEX]    = 64,
 278          [MESA_SHADER_TESS_EVAL] = 10,
 279       },
 280       .max_entries = {
 281          [MESA_SHADER_VERTEX]    = 1664,
 282          [MESA_SHADER_TESS_CTRL] = 128,
 283          [MESA_SHADER_TESS_EVAL] = 960,
 284          [MESA_SHADER_GEOMETRY]  = 640,
 285       },
 286    },
 287 };
 288
 289 #define GEN8_FEATURES                               \
 290    .gen = 8,                                        \
 291    .has_hiz_and_separate_stencil = true,            \
 292    .has_resource_streamer = true,                   \
 293    .must_use_separate_stencil = true,               \
 294    .has_llc = true,                                 \
 295    .has_pln = true,                                 \
 296    .supports_simd16_3src = true,                    \
 297    .has_surface_tile_offset = true,                 \
 298    .max_vs_threads = 504,                           \
 299    .max_tcs_threads = 504,                          \
 300    .max_tes_threads = 504,                          \
 301    .max_gs_threads = 504,                           \
 302    .max_wm_threads = 384,                           \
 303    .timebase_scale = 80
 304
 305 static const struct gen_device_info gen_device_info_bdw_gt1 = {
 306    GEN8_FEATURES, .gt = 1,
 307    .is_broadwell = true,
 308    .num_slices = 1,
 309    .l3_banks = 2,
 310    .max_cs_threads = 42,
 311    .urb = {
 312       .size = 192,
 313       .min_entries = {
 314          [MESA_SHADER_VERTEX]    = 64,
 315          [MESA_SHADER_TESS_EVAL] = 34,
 316       },
 317       .max_entries = {
 318          [MESA_SHADER_VERTEX]    = 2560,
 319          [MESA_SHADER_TESS_CTRL] = 504,
 320          [MESA_SHADER_TESS_EVAL] = 1536,
 321          [MESA_SHADER_GEOMETRY]  = 960,
 322       },
 323    }
 324 };
 325
 326 static const struct gen_device_info gen_device_info_bdw_gt2 = {
 327    GEN8_FEATURES, .gt = 2,
 328    .is_broadwell = true,
 329    .num_slices = 1,
 330    .l3_banks = 4,
 331    .max_cs_threads = 56,
 332    .urb = {
 333       .size = 384,
 334       .min_entries = {
 335          [MESA_SHADER_VERTEX]    = 64,
 336          [MESA_SHADER_TESS_EVAL] = 34,
 337       },
 338       .max_entries = {
 339          [MESA_SHADER_VERTEX]    = 2560,
 340          [MESA_SHADER_TESS_CTRL] = 504,
 341          [MESA_SHADER_TESS_EVAL] = 1536,
 342          [MESA_SHADER_GEOMETRY]  = 960,
 343       },
 344    }
 345 };
 346
 347 static const struct gen_device_info gen_device_info_bdw_gt3 = {
 348    GEN8_FEATURES, .gt = 3,
 349    .is_broadwell = true,
 350    .num_slices = 2,
 351    .l3_banks = 8,
 352    .max_cs_threads = 56,
 353    .urb = {
 354       .size = 384,
 355       .min_entries = {
 356          [MESA_SHADER_VERTEX]    = 64,
 357          [MESA_SHADER_TESS_EVAL] = 34,
 358       },
 359       .max_entries = {
 360          [MESA_SHADER_VERTEX]    = 2560,
 361          [MESA_SHADER_TESS_CTRL] = 504,
 362          [MESA_SHADER_TESS_EVAL] = 1536,
 363          [MESA_SHADER_GEOMETRY]  = 960,
 364       },
 365    }
 366 };
 367
 368 static const struct gen_device_info gen_device_info_chv = {
 369    GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
 370    .has_llc = false,
 371    .num_slices = 1,
 372    .l3_banks = 2,
 373    .max_vs_threads = 80,
 374    .max_tcs_threads = 80,
 375    .max_tes_threads = 80,
 376    .max_gs_threads = 80,
 377    .max_wm_threads = 128,
 378    .max_cs_threads = 6 * 7,
 379    .urb = {
 380       .size = 192,
 381       .min_entries = {
 382          [MESA_SHADER_VERTEX]    = 34,
 383          [MESA_SHADER_TESS_EVAL] = 34,
 384       },
 385       .max_entries = {
 386          [MESA_SHADER_VERTEX]    = 640,
 387          [MESA_SHADER_TESS_CTRL] = 80,
 388          [MESA_SHADER_TESS_EVAL] = 384,
 389          [MESA_SHADER_GEOMETRY]  = 256,
 390       },
 391    }
 392 };
 393
 394 #define GEN9_HW_INFO                                \
 395    .gen = 9,                                        \
 396    .max_vs_threads = 336,                           \
 397    .max_gs_threads = 336,                           \
 398    .max_tcs_threads = 336,                          \
 399    .max_tes_threads = 336,                          \
 400    .max_cs_threads = 56,                            \
 401    .timebase_scale = 1000000000.0 / 12000000.0,     \
 402    .urb = {                                         \
 403       .size = 384,                                  \
 404       .min_entries = {                              \
 405          [MESA_SHADER_VERTEX]    = 64,              \
 406          [MESA_SHADER_TESS_EVAL] = 34,              \
 407       },                                            \
 408       .max_entries = {                              \
 409          [MESA_SHADER_VERTEX]    = 1856,            \
 410          [MESA_SHADER_TESS_CTRL] = 672,             \
 411          [MESA_SHADER_TESS_EVAL] = 1120,            \
 412          [MESA_SHADER_GEOMETRY]  = 640,             \
 413       },                                            \
 414    }
 415
 416 #define GEN9_LP_FEATURES                           \
 417    GEN9_FEATURES,                                  \
 418    .gt = 1,                                        \
 419    .has_llc = false,                               \
 420    .num_slices = 1,                                \
 421    .max_vs_threads = 112,                          \
 422    .max_tcs_threads = 112,                         \
 423    .max_tes_threads = 112,                         \
 424    .max_gs_threads = 112,                          \
 425    .max_cs_threads = 6 * 6,                        \
 426    .timebase_scale = 1000000000.0 / 19200123.0,    \
 427    .urb = {                                        \
 428       .size = 192,                                 \
 429       .min_entries = {                             \
 430          [MESA_SHADER_VERTEX]    = 34,             \
 431          [MESA_SHADER_TESS_EVAL] = 34,             \
 432       },                                           \
 433       .max_entries = {                             \
 434          [MESA_SHADER_VERTEX]    = 704,            \
 435          [MESA_SHADER_TESS_CTRL] = 256,            \
 436          [MESA_SHADER_TESS_EVAL] = 416,            \
 437          [MESA_SHADER_GEOMETRY]  = 256,            \
 438       },                                           \
 439    }
 440
 441 #define GEN9_LP_FEATURES_2X6                       \
 442    GEN9_LP_FEATURES,                               \
 443    .max_vs_threads = 56,                           \
 444    .max_tcs_threads = 56,                          \
 445    .max_tes_threads = 56,                          \
 446    .max_gs_threads = 56,                           \
 447    .max_cs_threads = 6 * 6,                        \
 448    .urb = {                                        \
 449       .size = 128,                                 \
 450       .min_entries = {                             \
 451          [MESA_SHADER_VERTEX]    = 34,             \
 452          [MESA_SHADER_TESS_EVAL] = 34,             \
 453       },                                           \
 454       .max_entries = {                             \
 455          [MESA_SHADER_VERTEX]    = 352,            \
 456          [MESA_SHADER_TESS_CTRL] = 128,            \
 457          [MESA_SHADER_TESS_EVAL] = 208,            \
 458          [MESA_SHADER_GEOMETRY]  = 128,            \
 459       },                                           \
 460    }
 461
 462 #define GEN9_FEATURES                               \
 463    GEN8_FEATURES,                                   \
 464    GEN9_HW_INFO
 465
 466 static const struct gen_device_info gen_device_info_skl_gt1 = {
 467    GEN9_FEATURES, .gt = 1,
 468    .is_skylake = true,
 469    .num_slices = 1,
 470    .l3_banks = 2,
 471    .urb.size = 192,
 472 };
 473
 474 static const struct gen_device_info gen_device_info_skl_gt2 = {
 475    GEN9_FEATURES, .gt = 2,
 476    .is_skylake = true,
 477    .num_slices = 1,
 478    .l3_banks = 4,
 479 };
 480
 481 static const struct gen_device_info gen_device_info_skl_gt3 = {
 482    GEN9_FEATURES, .gt = 3,
 483    .is_skylake = true,
 484    .num_slices = 2,
 485    .l3_banks = 8,
 486 };
 487
 488 static const struct gen_device_info gen_device_info_skl_gt4 = {
 489    GEN9_FEATURES, .gt = 4,
 490    .is_skylake = true,
 491    .num_slices = 3,
 492    .l3_banks = 12,
 493    /* From the "L3 Allocation and Programming" documentation:
 494     *
 495     * "URB is limited to 1008KB due to programming restrictions.  This is not a
 496     * restriction of the L3 implementation, but of the FF and other clients.
 497     * Therefore, in a GT4 implementation it is possible for the programmed
 498     * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
 499     * only 1008KB of this will be used."
 500     */
 501    .urb.size = 1008 / 3,
 502 };
 503
 504 static const struct gen_device_info gen_device_info_bxt = {
 505    GEN9_LP_FEATURES,
 506    .is_broxton = true,
 507    .l3_banks = 2,
 508 };
 509
 510 static const struct gen_device_info gen_device_info_bxt_2x6 = {
 511    GEN9_LP_FEATURES_2X6,
 512    .is_broxton = true,
 513    .l3_banks = 1,
 514 };
 515 /*
 516  * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
 517  * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
 518  */
 519
 520 static const struct gen_device_info gen_device_info_kbl_gt1 = {
 521    GEN9_FEATURES,
 522    .is_kabylake = true,
 523    .gt = 1,
 524
 525    .max_cs_threads = 7 * 6,
 526    .urb.size = 192,
 527    .num_slices = 1,
 528    .l3_banks = 2,
 529 };
 530
 531 static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
 532    GEN9_FEATURES,
 533    .is_kabylake = true,
 534    .gt = 1,
 535
 536    .max_cs_threads = 7 * 6,
 537    .num_slices = 1,
 538    .l3_banks = 4,
 539 };
 540
 541 static const struct gen_device_info gen_device_info_kbl_gt2 = {
 542    GEN9_FEATURES,
 543    .is_kabylake = true,
 544    .gt = 2,
 545
 546    .num_slices = 1,
 547    .l3_banks = 4,
 548 };
 549
 550 static const struct gen_device_info gen_device_info_kbl_gt3 = {
 551    GEN9_FEATURES,
 552    .is_kabylake = true,
 553    .gt = 3,
 554
 555    .num_slices = 2,
 556    .l3_banks = 8,
 557 };
 558
 559 static const struct gen_device_info gen_device_info_kbl_gt4 = {
 560    GEN9_FEATURES,
 561    .is_kabylake = true,
 562    .gt = 4,
 563
 564    /*
 565     * From the "L3 Allocation and Programming" documentation:
 566     *
 567     * "URB is limited to 1008KB due to programming restrictions.  This
 568     *  is not a restriction of the L3 implementation, but of the FF and
 569     *  other clients.  Therefore, in a GT4 implementation it is
 570     *  possible for the programmed allocation of the L3 data array to
 571     *  provide 3*384KB=1152KB for URB, but only 1008KB of this
 572     *  will be used."
 573     */
 574    .urb.size = 1008 / 3,
 575    .num_slices = 3,
 576    .l3_banks = 12,
 577 };
 578
 579 static const struct gen_device_info gen_device_info_glk = {
 580    GEN9_LP_FEATURES,
 581    .is_geminilake = true,
 582    .l3_banks = 2,
 583 };
 584
 585 /*TODO: Initialize l3_banks when we know the number. */
 586 static const struct gen_device_info gen_device_info_glk_2x6 = {
 587    GEN9_LP_FEATURES_2X6,
 588    .is_geminilake = true,
 589 };
 590
 591 #define GEN10_HW_INFO                               \
 592    .gen = 10,                                       \
 593    .max_vs_threads = 728,                           \
 594    .max_gs_threads = 432,                           \
 595    .max_tcs_threads = 432,                          \
 596    .max_tes_threads = 624,                          \
 597    .max_cs_threads = 56,                            \
 598    .urb = {                                         \
 599       .size = 256,                                  \
 600       .min_entries = {                              \
 601          [MESA_SHADER_VERTEX]    = 64,              \
 602          [MESA_SHADER_TESS_EVAL] = 34,              \
 603       },                                            \
 604       .max_entries = {                              \
 605       [MESA_SHADER_VERTEX]       = 3936,            \
 606       [MESA_SHADER_TESS_CTRL]    = 896,             \
 607       [MESA_SHADER_TESS_EVAL]    = 2064,            \
 608       [MESA_SHADER_GEOMETRY]     = 832,             \
 609       },                                            \
 610    }
 611
 612 #define GEN10_FEATURES(_gt, _slices, _l3)           \
 613    GEN8_FEATURES,                                   \
 614    GEN10_HW_INFO,                                   \
 615    .gt = _gt, .num_slices = _slices, .l3_banks = _l3
 616
 617 static const struct gen_device_info gen_device_info_cnl_2x8 = {
 618    /* GT0.5 */
 619    GEN10_FEATURES(1, 1, 2),
 620    .is_cannonlake = true,
 621 };
 622
 623 static const struct gen_device_info gen_device_info_cnl_3x8 = {
 624    /* GT1 */
 625    GEN10_FEATURES(1, 1, 3),
 626    .is_cannonlake = true,
 627 };
 628
 629 static const struct gen_device_info gen_device_info_cnl_4x8 = {
 630    /* GT 1.5 */
 631    GEN10_FEATURES(1, 2, 6),
 632    .is_cannonlake = true,
 633 };
 634
 635 static const struct gen_device_info gen_device_info_cnl_5x8 = {
 636    /* GT2 */
 637    GEN10_FEATURES(2, 2, 6),
 638    .is_cannonlake = true,
 639 };
 640
 641 bool
 642 gen_get_device_info(int devid, struct gen_device_info *devinfo)
 643 {
 644    switch (devid) {
 645 #undef CHIPSET
 646 #define CHIPSET(id, family, name) \
 647       case id: *devinfo = gen_device_info_##family; break;
 648 #include "pci_ids/i965_pci_ids.h"
 649    default:
 650       fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid);
 651       return false;
 652    }
 653
 654    /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
 655     *
 656     * "Scratch Space per slice is computed based on 4 sub-slices.  SW must
 657     *  allocate scratch space enough so that each slice has 4 slices allowed."
 658     *
 659     * The equivalent internal documentation says that this programming note
 660     * applies to all Gen9+ platforms.
 661     *
 662     * The hardware typically calculates the scratch space pointer by taking
 663     * the base address, and adding per-thread-scratch-space * thread ID.
 664     * Extra padding can be necessary depending how the thread IDs are
 665     * calculated for a particular shader stage.
 666     */
 667    if (devinfo->gen >= 9) {
 668       devinfo->max_wm_threads = 64 /* threads-per-PSD */
 669                               * devinfo->num_slices
 670                               * 4; /* effective subslices per slice */
 671    }
 672
 673    return true;
 674 }
 675
 676 const char *
 677 gen_get_device_name(int devid)
 678 {
 679    switch (devid) {
 680 #undef CHIPSET
 681 #define CHIPSET(id, family, name) case id: return name;
 682 #include "pci_ids/i965_pci_ids.h"
 683    default:
 684       return NULL;
 685    }
 686 }