2 * Copyright © 2013 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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26 #include "gen_device_info.h"
27 #include "compiler/shader_enums.h"
29 static const struct gen_device_info gen_device_info_i965
= {
31 .has_negative_rhw_bug
= true,
35 .max_wm_threads
= 8 * 4,
42 static const struct gen_device_info gen_device_info_g4x
= {
46 .has_surface_tile_offset
= true,
51 .max_wm_threads
= 10 * 5,
58 static const struct gen_device_info gen_device_info_ilk
= {
62 .has_surface_tile_offset
= true,
66 .max_wm_threads
= 12 * 6,
73 static const struct gen_device_info gen_device_info_snb_gt1
= {
76 .has_hiz_and_separate_stencil
= true,
79 .has_surface_tile_offset
= true,
80 .needs_unlit_centroid_workaround
= true,
83 .max_gs_threads
= 21, /* conservative; 24 if rendering disabled. */
88 [MESA_SHADER_VERTEX
] = 24,
91 [MESA_SHADER_VERTEX
] = 256,
92 [MESA_SHADER_GEOMETRY
] = 256,
98 static const struct gen_device_info gen_device_info_snb_gt2
= {
101 .has_hiz_and_separate_stencil
= true,
104 .has_surface_tile_offset
= true,
105 .needs_unlit_centroid_workaround
= true,
107 .max_vs_threads
= 60,
108 .max_gs_threads
= 60,
109 .max_wm_threads
= 80,
113 [MESA_SHADER_VERTEX
] = 24,
116 [MESA_SHADER_VERTEX
] = 256,
117 [MESA_SHADER_GEOMETRY
] = 256,
120 .timebase_scale
= 80,
123 #define GEN7_FEATURES \
125 .has_hiz_and_separate_stencil = true, \
126 .must_use_separate_stencil = true, \
129 .has_surface_tile_offset = true, \
132 static const struct gen_device_info gen_device_info_ivb_gt1
= {
133 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 1,
136 .max_vs_threads
= 36,
137 .max_tcs_threads
= 36,
138 .max_tes_threads
= 36,
139 .max_gs_threads
= 36,
140 .max_wm_threads
= 48,
141 .max_cs_threads
= 36,
145 [MESA_SHADER_VERTEX
] = 32,
146 [MESA_SHADER_TESS_EVAL
] = 10,
149 [MESA_SHADER_VERTEX
] = 512,
150 [MESA_SHADER_TESS_CTRL
] = 32,
151 [MESA_SHADER_TESS_EVAL
] = 288,
152 [MESA_SHADER_GEOMETRY
] = 192,
157 static const struct gen_device_info gen_device_info_ivb_gt2
= {
158 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 2,
161 .max_vs_threads
= 128,
162 .max_tcs_threads
= 128,
163 .max_tes_threads
= 128,
164 .max_gs_threads
= 128,
165 .max_wm_threads
= 172,
166 .max_cs_threads
= 64,
170 [MESA_SHADER_VERTEX
] = 32,
171 [MESA_SHADER_TESS_EVAL
] = 10,
174 [MESA_SHADER_VERTEX
] = 704,
175 [MESA_SHADER_TESS_CTRL
] = 64,
176 [MESA_SHADER_TESS_EVAL
] = 448,
177 [MESA_SHADER_GEOMETRY
] = 320,
182 static const struct gen_device_info gen_device_info_byt
= {
183 GEN7_FEATURES
, .is_baytrail
= true, .gt
= 1,
187 .max_vs_threads
= 36,
188 .max_tcs_threads
= 36,
189 .max_tes_threads
= 36,
190 .max_gs_threads
= 36,
191 .max_wm_threads
= 48,
192 .max_cs_threads
= 32,
196 [MESA_SHADER_VERTEX
] = 32,
197 [MESA_SHADER_TESS_EVAL
] = 10,
200 [MESA_SHADER_VERTEX
] = 512,
201 [MESA_SHADER_TESS_CTRL
] = 32,
202 [MESA_SHADER_TESS_EVAL
] = 288,
203 [MESA_SHADER_GEOMETRY
] = 192,
208 #define HSW_FEATURES \
210 .is_haswell = true, \
211 .supports_simd16_3src = true, \
212 .has_resource_streamer = true
214 static const struct gen_device_info gen_device_info_hsw_gt1
= {
215 HSW_FEATURES
, .gt
= 1,
218 .max_vs_threads
= 70,
219 .max_tcs_threads
= 70,
220 .max_tes_threads
= 70,
221 .max_gs_threads
= 70,
222 .max_wm_threads
= 102,
223 .max_cs_threads
= 70,
227 [MESA_SHADER_VERTEX
] = 32,
228 [MESA_SHADER_TESS_EVAL
] = 10,
231 [MESA_SHADER_VERTEX
] = 640,
232 [MESA_SHADER_TESS_CTRL
] = 64,
233 [MESA_SHADER_TESS_EVAL
] = 384,
234 [MESA_SHADER_GEOMETRY
] = 256,
239 static const struct gen_device_info gen_device_info_hsw_gt2
= {
240 HSW_FEATURES
, .gt
= 2,
243 .max_vs_threads
= 280,
244 .max_tcs_threads
= 256,
245 .max_tes_threads
= 280,
246 .max_gs_threads
= 256,
247 .max_wm_threads
= 204,
248 .max_cs_threads
= 70,
252 [MESA_SHADER_VERTEX
] = 64,
253 [MESA_SHADER_TESS_EVAL
] = 10,
256 [MESA_SHADER_VERTEX
] = 1664,
257 [MESA_SHADER_TESS_CTRL
] = 128,
258 [MESA_SHADER_TESS_EVAL
] = 960,
259 [MESA_SHADER_GEOMETRY
] = 640,
264 static const struct gen_device_info gen_device_info_hsw_gt3
= {
265 HSW_FEATURES
, .gt
= 3,
268 .max_vs_threads
= 280,
269 .max_tcs_threads
= 256,
270 .max_tes_threads
= 280,
271 .max_gs_threads
= 256,
272 .max_wm_threads
= 408,
273 .max_cs_threads
= 70,
277 [MESA_SHADER_VERTEX
] = 64,
278 [MESA_SHADER_TESS_EVAL
] = 10,
281 [MESA_SHADER_VERTEX
] = 1664,
282 [MESA_SHADER_TESS_CTRL
] = 128,
283 [MESA_SHADER_TESS_EVAL
] = 960,
284 [MESA_SHADER_GEOMETRY
] = 640,
289 #define GEN8_FEATURES \
291 .has_hiz_and_separate_stencil = true, \
292 .has_resource_streamer = true, \
293 .must_use_separate_stencil = true, \
296 .supports_simd16_3src = true, \
297 .has_surface_tile_offset = true, \
298 .max_vs_threads = 504, \
299 .max_tcs_threads = 504, \
300 .max_tes_threads = 504, \
301 .max_gs_threads = 504, \
302 .max_wm_threads = 384, \
305 static const struct gen_device_info gen_device_info_bdw_gt1
= {
306 GEN8_FEATURES
, .gt
= 1,
309 .max_cs_threads
= 42,
313 [MESA_SHADER_VERTEX
] = 64,
314 [MESA_SHADER_TESS_EVAL
] = 34,
317 [MESA_SHADER_VERTEX
] = 2560,
318 [MESA_SHADER_TESS_CTRL
] = 504,
319 [MESA_SHADER_TESS_EVAL
] = 1536,
320 [MESA_SHADER_GEOMETRY
] = 960,
325 static const struct gen_device_info gen_device_info_bdw_gt2
= {
326 GEN8_FEATURES
, .gt
= 2,
329 .max_cs_threads
= 56,
333 [MESA_SHADER_VERTEX
] = 64,
334 [MESA_SHADER_TESS_EVAL
] = 34,
337 [MESA_SHADER_VERTEX
] = 2560,
338 [MESA_SHADER_TESS_CTRL
] = 504,
339 [MESA_SHADER_TESS_EVAL
] = 1536,
340 [MESA_SHADER_GEOMETRY
] = 960,
345 static const struct gen_device_info gen_device_info_bdw_gt3
= {
346 GEN8_FEATURES
, .gt
= 3,
349 .max_cs_threads
= 56,
353 [MESA_SHADER_VERTEX
] = 64,
354 [MESA_SHADER_TESS_EVAL
] = 34,
357 [MESA_SHADER_VERTEX
] = 2560,
358 [MESA_SHADER_TESS_CTRL
] = 504,
359 [MESA_SHADER_TESS_EVAL
] = 1536,
360 [MESA_SHADER_GEOMETRY
] = 960,
365 static const struct gen_device_info gen_device_info_chv
= {
366 GEN8_FEATURES
, .is_cherryview
= 1, .gt
= 1,
370 .max_vs_threads
= 80,
371 .max_tcs_threads
= 80,
372 .max_tes_threads
= 80,
373 .max_gs_threads
= 80,
374 .max_wm_threads
= 128,
375 .max_cs_threads
= 6 * 7,
379 [MESA_SHADER_VERTEX
] = 34,
380 [MESA_SHADER_TESS_EVAL
] = 34,
383 [MESA_SHADER_VERTEX
] = 640,
384 [MESA_SHADER_TESS_CTRL
] = 80,
385 [MESA_SHADER_TESS_EVAL
] = 384,
386 [MESA_SHADER_GEOMETRY
] = 256,
391 #define GEN9_HW_INFO \
393 .max_vs_threads = 336, \
394 .max_gs_threads = 336, \
395 .max_tcs_threads = 336, \
396 .max_tes_threads = 336, \
397 .max_cs_threads = 56, \
398 .timebase_scale = 1000000000.0 / 12000000.0, \
402 [MESA_SHADER_VERTEX] = 64, \
403 [MESA_SHADER_TESS_EVAL] = 34, \
406 [MESA_SHADER_VERTEX] = 1856, \
407 [MESA_SHADER_TESS_CTRL] = 672, \
408 [MESA_SHADER_TESS_EVAL] = 1120, \
409 [MESA_SHADER_GEOMETRY] = 640, \
413 #define GEN9_LP_FEATURES \
419 .max_vs_threads = 112, \
420 .max_tcs_threads = 112, \
421 .max_tes_threads = 112, \
422 .max_gs_threads = 112, \
423 .max_cs_threads = 6 * 6, \
424 .timebase_scale = 1000000000.0 / 19200123.0, \
428 [MESA_SHADER_VERTEX] = 34, \
429 [MESA_SHADER_TESS_EVAL] = 34, \
432 [MESA_SHADER_VERTEX] = 704, \
433 [MESA_SHADER_TESS_CTRL] = 256, \
434 [MESA_SHADER_TESS_EVAL] = 416, \
435 [MESA_SHADER_GEOMETRY] = 256, \
439 #define GEN9_LP_FEATURES_2X6 \
441 .max_vs_threads = 56, \
442 .max_tcs_threads = 56, \
443 .max_tes_threads = 56, \
444 .max_gs_threads = 56, \
445 .max_cs_threads = 6 * 6, \
449 [MESA_SHADER_VERTEX] = 34, \
450 [MESA_SHADER_TESS_EVAL] = 34, \
453 [MESA_SHADER_VERTEX] = 352, \
454 [MESA_SHADER_TESS_CTRL] = 128, \
455 [MESA_SHADER_TESS_EVAL] = 208, \
456 [MESA_SHADER_GEOMETRY] = 128, \
460 #define GEN9_FEATURES \
464 static const struct gen_device_info gen_device_info_skl_gt1
= {
465 GEN9_FEATURES
, .gt
= 1,
471 static const struct gen_device_info gen_device_info_skl_gt2
= {
472 GEN9_FEATURES
, .gt
= 2,
477 static const struct gen_device_info gen_device_info_skl_gt3
= {
478 GEN9_FEATURES
, .gt
= 3,
483 static const struct gen_device_info gen_device_info_skl_gt4
= {
484 GEN9_FEATURES
, .gt
= 4,
487 /* From the "L3 Allocation and Programming" documentation:
489 * "URB is limited to 1008KB due to programming restrictions. This is not a
490 * restriction of the L3 implementation, but of the FF and other clients.
491 * Therefore, in a GT4 implementation it is possible for the programmed
492 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
493 * only 1008KB of this will be used."
495 .urb
.size
= 1008 / 3,
498 static const struct gen_device_info gen_device_info_bxt
= {
503 static const struct gen_device_info gen_device_info_bxt_2x6
= {
504 GEN9_LP_FEATURES_2X6
,
508 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
509 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
512 static const struct gen_device_info gen_device_info_kbl_gt1
= {
517 .max_cs_threads
= 7 * 6,
523 static const struct gen_device_info gen_device_info_kbl_gt1_5
= {
528 .max_cs_threads
= 7 * 6,
533 static const struct gen_device_info gen_device_info_kbl_gt2
= {
542 static const struct gen_device_info gen_device_info_kbl_gt3
= {
551 static const struct gen_device_info gen_device_info_kbl_gt4
= {
557 * From the "L3 Allocation and Programming" documentation:
559 * "URB is limited to 1008KB due to programming restrictions. This
560 * is not a restriction of the L3 implementation, but of the FF and
561 * other clients. Therefore, in a GT4 implementation it is
562 * possible for the programmed allocation of the L3 data array to
563 * provide 3*384KB=1152KB for URB, but only 1008KB of this
566 .urb
.size
= 1008 / 3,
571 static const struct gen_device_info gen_device_info_glk
= {
576 /*TODO: Initialize l3_banks when we know the number. */
577 static const struct gen_device_info gen_device_info_glk_2x6
= {
582 gen_get_device_info(int devid
, struct gen_device_info
*devinfo
)
586 #define CHIPSET(id, family, name) \
587 case id: *devinfo = gen_device_info_##family; break;
588 #include "pci_ids/i965_pci_ids.h"
590 fprintf(stderr
, "i965_dri.so does not support the 0x%x PCI ID.\n", devid
);
594 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
596 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
597 * allocate scratch space enough so that each slice has 4 slices allowed."
599 * The equivalent internal documentation says that this programming note
600 * applies to all Gen9+ platforms.
602 * The hardware typically calculates the scratch space pointer by taking
603 * the base address, and adding per-thread-scratch-space * thread ID.
604 * Extra padding can be necessary depending how the thread IDs are
605 * calculated for a particular shader stage.
607 if (devinfo
->gen
>= 9) {
608 devinfo
->max_wm_threads
= 64 /* threads-per-PSD */
609 * devinfo
->num_slices
610 * 4; /* effective subslices per slice */
617 gen_get_device_name(int devid
)
621 #define CHIPSET(id, family, name) case id: return name;
622 #include "pci_ids/i965_pci_ids.h"