src/intel/common/gen_device_info.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdio.h>
  25 #include <stdlib.h>
  26 #include "gen_device_info.h"
  27 #include "compiler/shader_enums.h"
  28
  29 static const struct gen_device_info gen_device_info_i965 = {
  30    .gen = 4,
  31    .has_negative_rhw_bug = true,
  32    .num_slices = 1,
  33    .max_vs_threads = 16,
  34    .max_gs_threads = 2,
  35    .max_wm_threads = 8 * 4,
  36    .urb = {
  37       .size = 256,
  38    },
  39    .timebase_scale = 80,
  40 };
  41
  42 static const struct gen_device_info gen_device_info_g4x = {
  43    .gen = 4,
  44    .has_pln = true,
  45    .has_compr4 = true,
  46    .has_surface_tile_offset = true,
  47    .is_g4x = true,
  48    .num_slices = 1,
  49    .max_vs_threads = 32,
  50    .max_gs_threads = 2,
  51    .max_wm_threads = 10 * 5,
  52    .urb = {
  53       .size = 384,
  54    },
  55    .timebase_scale = 80,
  56 };
  57
  58 static const struct gen_device_info gen_device_info_ilk = {
  59    .gen = 5,
  60    .has_pln = true,
  61    .has_compr4 = true,
  62    .has_surface_tile_offset = true,
  63    .num_slices = 1,
  64    .max_vs_threads = 72,
  65    .max_gs_threads = 32,
  66    .max_wm_threads = 12 * 6,
  67    .urb = {
  68       .size = 1024,
  69    },
  70    .timebase_scale = 80,
  71 };
  72
  73 static const struct gen_device_info gen_device_info_snb_gt1 = {
  74    .gen = 6,
  75    .gt = 1,
  76    .has_hiz_and_separate_stencil = true,
  77    .has_llc = true,
  78    .has_pln = true,
  79    .has_surface_tile_offset = true,
  80    .needs_unlit_centroid_workaround = true,
  81    .num_slices = 1,
  82    .max_vs_threads = 24,
  83    .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
  84    .max_wm_threads = 40,
  85    .urb = {
  86       .size = 32,
  87       .min_entries = {
  88          [MESA_SHADER_VERTEX]   = 24,
  89       },
  90       .max_entries = {
  91          [MESA_SHADER_VERTEX]   = 256,
  92          [MESA_SHADER_GEOMETRY] = 256,
  93       },
  94    },
  95    .timebase_scale = 80,
  96 };
  97
  98 static const struct gen_device_info gen_device_info_snb_gt2 = {
  99    .gen = 6,
 100    .gt = 2,
 101    .has_hiz_and_separate_stencil = true,
 102    .has_llc = true,
 103    .has_pln = true,
 104    .has_surface_tile_offset = true,
 105    .needs_unlit_centroid_workaround = true,
 106    .num_slices = 1,
 107    .max_vs_threads = 60,
 108    .max_gs_threads = 60,
 109    .max_wm_threads = 80,
 110    .urb = {
 111       .size = 64,
 112       .min_entries = {
 113          [MESA_SHADER_VERTEX]   = 24,
 114       },
 115       .max_entries = {
 116          [MESA_SHADER_VERTEX]   = 256,
 117          [MESA_SHADER_GEOMETRY] = 256,
 118       },
 119    },
 120    .timebase_scale = 80,
 121 };
 122
 123 #define GEN7_FEATURES                               \
 124    .gen = 7,                                        \
 125    .has_hiz_and_separate_stencil = true,            \
 126    .must_use_separate_stencil = true,               \
 127    .has_llc = true,                                 \
 128    .has_pln = true,                                 \
 129    .has_surface_tile_offset = true,                 \
 130    .timebase_scale = 80
 131
 132 static const struct gen_device_info gen_device_info_ivb_gt1 = {
 133    GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
 134    .num_slices = 1,
 135    .l3_banks = 2,
 136    .max_vs_threads = 36,
 137    .max_tcs_threads = 36,
 138    .max_tes_threads = 36,
 139    .max_gs_threads = 36,
 140    .max_wm_threads = 48,
 141    .max_cs_threads = 36,
 142    .urb = {
 143       .size = 128,
 144       .min_entries = {
 145          [MESA_SHADER_VERTEX]    = 32,
 146          [MESA_SHADER_TESS_EVAL] = 10,
 147       },
 148       .max_entries = {
 149          [MESA_SHADER_VERTEX]    = 512,
 150          [MESA_SHADER_TESS_CTRL] = 32,
 151          [MESA_SHADER_TESS_EVAL] = 288,
 152          [MESA_SHADER_GEOMETRY]  = 192,
 153       },
 154    },
 155 };
 156
 157 static const struct gen_device_info gen_device_info_ivb_gt2 = {
 158    GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
 159    .num_slices = 1,
 160    .l3_banks = 4,
 161    .max_vs_threads = 128,
 162    .max_tcs_threads = 128,
 163    .max_tes_threads = 128,
 164    .max_gs_threads = 128,
 165    .max_wm_threads = 172,
 166    .max_cs_threads = 64,
 167    .urb = {
 168       .size = 256,
 169       .min_entries = {
 170          [MESA_SHADER_VERTEX]    = 32,
 171          [MESA_SHADER_TESS_EVAL] = 10,
 172       },
 173       .max_entries = {
 174          [MESA_SHADER_VERTEX]    = 704,
 175          [MESA_SHADER_TESS_CTRL] = 64,
 176          [MESA_SHADER_TESS_EVAL] = 448,
 177          [MESA_SHADER_GEOMETRY]  = 320,
 178       },
 179    },
 180 };
 181
 182 static const struct gen_device_info gen_device_info_byt = {
 183    GEN7_FEATURES, .is_baytrail = true, .gt = 1,
 184    .num_slices = 1,
 185    .l3_banks = 1,
 186    .has_llc = false,
 187    .max_vs_threads = 36,
 188    .max_tcs_threads = 36,
 189    .max_tes_threads = 36,
 190    .max_gs_threads = 36,
 191    .max_wm_threads = 48,
 192    .max_cs_threads = 32,
 193    .urb = {
 194       .size = 128,
 195       .min_entries = {
 196          [MESA_SHADER_VERTEX]    = 32,
 197          [MESA_SHADER_TESS_EVAL] = 10,
 198       },
 199       .max_entries = {
 200          [MESA_SHADER_VERTEX]    = 512,
 201          [MESA_SHADER_TESS_CTRL] = 32,
 202          [MESA_SHADER_TESS_EVAL] = 288,
 203          [MESA_SHADER_GEOMETRY]  = 192,
 204       },
 205    },
 206 };
 207
 208 #define HSW_FEATURES             \
 209    GEN7_FEATURES,                \
 210    .is_haswell = true,           \
 211    .supports_simd16_3src = true, \
 212    .has_resource_streamer = true
 213
 214 static const struct gen_device_info gen_device_info_hsw_gt1 = {
 215    HSW_FEATURES, .gt = 1,
 216    .num_slices = 1,
 217    .l3_banks = 2,
 218    .max_vs_threads = 70,
 219    .max_tcs_threads = 70,
 220    .max_tes_threads = 70,
 221    .max_gs_threads = 70,
 222    .max_wm_threads = 102,
 223    .max_cs_threads = 70,
 224    .urb = {
 225       .size = 128,
 226       .min_entries = {
 227          [MESA_SHADER_VERTEX]    = 32,
 228          [MESA_SHADER_TESS_EVAL] = 10,
 229       },
 230       .max_entries = {
 231          [MESA_SHADER_VERTEX]    = 640,
 232          [MESA_SHADER_TESS_CTRL] = 64,
 233          [MESA_SHADER_TESS_EVAL] = 384,
 234          [MESA_SHADER_GEOMETRY]  = 256,
 235       },
 236    },
 237 };
 238
 239 static const struct gen_device_info gen_device_info_hsw_gt2 = {
 240    HSW_FEATURES, .gt = 2,
 241    .num_slices = 1,
 242    .l3_banks = 4,
 243    .max_vs_threads = 280,
 244    .max_tcs_threads = 256,
 245    .max_tes_threads = 280,
 246    .max_gs_threads = 256,
 247    .max_wm_threads = 204,
 248    .max_cs_threads = 70,
 249    .urb = {
 250       .size = 256,
 251       .min_entries = {
 252          [MESA_SHADER_VERTEX]    = 64,
 253          [MESA_SHADER_TESS_EVAL] = 10,
 254       },
 255       .max_entries = {
 256          [MESA_SHADER_VERTEX]    = 1664,
 257          [MESA_SHADER_TESS_CTRL] = 128,
 258          [MESA_SHADER_TESS_EVAL] = 960,
 259          [MESA_SHADER_GEOMETRY]  = 640,
 260       },
 261    },
 262 };
 263
 264 static const struct gen_device_info gen_device_info_hsw_gt3 = {
 265    HSW_FEATURES, .gt = 3,
 266    .num_slices = 2,
 267    .l3_banks = 8,
 268    .max_vs_threads = 280,
 269    .max_tcs_threads = 256,
 270    .max_tes_threads = 280,
 271    .max_gs_threads = 256,
 272    .max_wm_threads = 408,
 273    .max_cs_threads = 70,
 274    .urb = {
 275       .size = 512,
 276       .min_entries = {
 277          [MESA_SHADER_VERTEX]    = 64,
 278          [MESA_SHADER_TESS_EVAL] = 10,
 279       },
 280       .max_entries = {
 281          [MESA_SHADER_VERTEX]    = 1664,
 282          [MESA_SHADER_TESS_CTRL] = 128,
 283          [MESA_SHADER_TESS_EVAL] = 960,
 284          [MESA_SHADER_GEOMETRY]  = 640,
 285       },
 286    },
 287 };
 288
 289 #define GEN8_FEATURES                               \
 290    .gen = 8,                                        \
 291    .has_hiz_and_separate_stencil = true,            \
 292    .has_resource_streamer = true,                   \
 293    .must_use_separate_stencil = true,               \
 294    .has_llc = true,                                 \
 295    .has_pln = true,                                 \
 296    .supports_simd16_3src = true,                    \
 297    .has_surface_tile_offset = true,                 \
 298    .max_vs_threads = 504,                           \
 299    .max_tcs_threads = 504,                          \
 300    .max_tes_threads = 504,                          \
 301    .max_gs_threads = 504,                           \
 302    .max_wm_threads = 384,                           \
 303    .timebase_scale = 80
 304
 305 static const struct gen_device_info gen_device_info_bdw_gt1 = {
 306    GEN8_FEATURES, .gt = 1,
 307    .num_slices = 1,
 308    .l3_banks = 2,
 309    .max_cs_threads = 42,
 310    .urb = {
 311       .size = 192,
 312       .min_entries = {
 313          [MESA_SHADER_VERTEX]    = 64,
 314          [MESA_SHADER_TESS_EVAL] = 34,
 315       },
 316       .max_entries = {
 317          [MESA_SHADER_VERTEX]    = 2560,
 318          [MESA_SHADER_TESS_CTRL] = 504,
 319          [MESA_SHADER_TESS_EVAL] = 1536,
 320          [MESA_SHADER_GEOMETRY]  = 960,
 321       },
 322    }
 323 };
 324
 325 static const struct gen_device_info gen_device_info_bdw_gt2 = {
 326    GEN8_FEATURES, .gt = 2,
 327    .num_slices = 1,
 328    .l3_banks = 4,
 329    .max_cs_threads = 56,
 330    .urb = {
 331       .size = 384,
 332       .min_entries = {
 333          [MESA_SHADER_VERTEX]    = 64,
 334          [MESA_SHADER_TESS_EVAL] = 34,
 335       },
 336       .max_entries = {
 337          [MESA_SHADER_VERTEX]    = 2560,
 338          [MESA_SHADER_TESS_CTRL] = 504,
 339          [MESA_SHADER_TESS_EVAL] = 1536,
 340          [MESA_SHADER_GEOMETRY]  = 960,
 341       },
 342    }
 343 };
 344
 345 static const struct gen_device_info gen_device_info_bdw_gt3 = {
 346    GEN8_FEATURES, .gt = 3,
 347    .num_slices = 2,
 348    .l3_banks = 8,
 349    .max_cs_threads = 56,
 350    .urb = {
 351       .size = 384,
 352       .min_entries = {
 353          [MESA_SHADER_VERTEX]    = 64,
 354          [MESA_SHADER_TESS_EVAL] = 34,
 355       },
 356       .max_entries = {
 357          [MESA_SHADER_VERTEX]    = 2560,
 358          [MESA_SHADER_TESS_CTRL] = 504,
 359          [MESA_SHADER_TESS_EVAL] = 1536,
 360          [MESA_SHADER_GEOMETRY]  = 960,
 361       },
 362    }
 363 };
 364
 365 static const struct gen_device_info gen_device_info_chv = {
 366    GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
 367    .has_llc = false,
 368    .num_slices = 1,
 369    .l3_banks = 2,
 370    .max_vs_threads = 80,
 371    .max_tcs_threads = 80,
 372    .max_tes_threads = 80,
 373    .max_gs_threads = 80,
 374    .max_wm_threads = 128,
 375    .max_cs_threads = 6 * 7,
 376    .urb = {
 377       .size = 192,
 378       .min_entries = {
 379          [MESA_SHADER_VERTEX]    = 34,
 380          [MESA_SHADER_TESS_EVAL] = 34,
 381       },
 382       .max_entries = {
 383          [MESA_SHADER_VERTEX]    = 640,
 384          [MESA_SHADER_TESS_CTRL] = 80,
 385          [MESA_SHADER_TESS_EVAL] = 384,
 386          [MESA_SHADER_GEOMETRY]  = 256,
 387       },
 388    }
 389 };
 390
 391 #define GEN9_HW_INFO                                \
 392    .gen = 9,                                        \
 393    .max_vs_threads = 336,                           \
 394    .max_gs_threads = 336,                           \
 395    .max_tcs_threads = 336,                          \
 396    .max_tes_threads = 336,                          \
 397    .max_cs_threads = 56,                            \
 398    .timebase_scale = 1000000000.0 / 12000000.0,     \
 399    .urb = {                                         \
 400       .size = 384,                                  \
 401       .min_entries = {                              \
 402          [MESA_SHADER_VERTEX]    = 64,              \
 403          [MESA_SHADER_TESS_EVAL] = 34,              \
 404       },                                            \
 405       .max_entries = {                              \
 406          [MESA_SHADER_VERTEX]    = 1856,            \
 407          [MESA_SHADER_TESS_CTRL] = 672,             \
 408          [MESA_SHADER_TESS_EVAL] = 1120,            \
 409          [MESA_SHADER_GEOMETRY]  = 640,             \
 410       },                                            \
 411    }
 412
 413 #define GEN9_LP_FEATURES                           \
 414    GEN9_FEATURES,                                  \
 415    .is_broxton = 1,                                \
 416    .gt = 1,                                        \
 417    .has_llc = false,                               \
 418    .num_slices = 1,                                \
 419    .max_vs_threads = 112,                          \
 420    .max_tcs_threads = 112,                         \
 421    .max_tes_threads = 112,                         \
 422    .max_gs_threads = 112,                          \
 423    .max_cs_threads = 6 * 6,                        \
 424    .timebase_scale = 1000000000.0 / 19200123.0,    \
 425    .urb = {                                        \
 426       .size = 192,                                 \
 427       .min_entries = {                             \
 428          [MESA_SHADER_VERTEX]    = 34,             \
 429          [MESA_SHADER_TESS_EVAL] = 34,             \
 430       },                                           \
 431       .max_entries = {                             \
 432          [MESA_SHADER_VERTEX]    = 704,            \
 433          [MESA_SHADER_TESS_CTRL] = 256,            \
 434          [MESA_SHADER_TESS_EVAL] = 416,            \
 435          [MESA_SHADER_GEOMETRY]  = 256,            \
 436       },                                           \
 437    }
 438
 439 #define GEN9_LP_FEATURES_2X6                       \
 440    GEN9_LP_FEATURES,                               \
 441    .max_vs_threads = 56,                           \
 442    .max_tcs_threads = 56,                          \
 443    .max_tes_threads = 56,                          \
 444    .max_gs_threads = 56,                           \
 445    .max_cs_threads = 6 * 6,                        \
 446    .urb = {                                        \
 447       .size = 128,                                 \
 448       .min_entries = {                             \
 449          [MESA_SHADER_VERTEX]    = 34,             \
 450          [MESA_SHADER_TESS_EVAL] = 34,             \
 451       },                                           \
 452       .max_entries = {                             \
 453          [MESA_SHADER_VERTEX]    = 352,            \
 454          [MESA_SHADER_TESS_CTRL] = 128,            \
 455          [MESA_SHADER_TESS_EVAL] = 208,            \
 456          [MESA_SHADER_GEOMETRY]  = 128,            \
 457       },                                           \
 458    }
 459
 460 #define GEN9_FEATURES                               \
 461    GEN8_FEATURES,                                   \
 462    GEN9_HW_INFO
 463
 464 static const struct gen_device_info gen_device_info_skl_gt1 = {
 465    GEN9_FEATURES, .gt = 1,
 466    .num_slices = 1,
 467    .l3_banks = 2,
 468    .urb.size = 192,
 469 };
 470
 471 static const struct gen_device_info gen_device_info_skl_gt2 = {
 472    GEN9_FEATURES, .gt = 2,
 473    .num_slices = 1,
 474    .l3_banks = 4,
 475 };
 476
 477 static const struct gen_device_info gen_device_info_skl_gt3 = {
 478    GEN9_FEATURES, .gt = 3,
 479    .num_slices = 2,
 480    .l3_banks = 8,
 481 };
 482
 483 static const struct gen_device_info gen_device_info_skl_gt4 = {
 484    GEN9_FEATURES, .gt = 4,
 485    .num_slices = 3,
 486    .l3_banks = 12,
 487    /* From the "L3 Allocation and Programming" documentation:
 488     *
 489     * "URB is limited to 1008KB due to programming restrictions.  This is not a
 490     * restriction of the L3 implementation, but of the FF and other clients.
 491     * Therefore, in a GT4 implementation it is possible for the programmed
 492     * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
 493     * only 1008KB of this will be used."
 494     */
 495    .urb.size = 1008 / 3,
 496 };
 497
 498 static const struct gen_device_info gen_device_info_bxt = {
 499    GEN9_LP_FEATURES,
 500    .l3_banks = 2,
 501 };
 502
 503 static const struct gen_device_info gen_device_info_bxt_2x6 = {
 504    GEN9_LP_FEATURES_2X6,
 505    .l3_banks = 1,
 506 };
 507 /*
 508  * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
 509  * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
 510  */
 511
 512 static const struct gen_device_info gen_device_info_kbl_gt1 = {
 513    GEN9_FEATURES,
 514    .is_kabylake = true,
 515    .gt = 1,
 516
 517    .max_cs_threads = 7 * 6,
 518    .urb.size = 192,
 519    .num_slices = 1,
 520    .l3_banks = 2,
 521 };
 522
 523 static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
 524    GEN9_FEATURES,
 525    .is_kabylake = true,
 526    .gt = 1,
 527
 528    .max_cs_threads = 7 * 6,
 529    .num_slices = 1,
 530    .l3_banks = 4,
 531 };
 532
 533 static const struct gen_device_info gen_device_info_kbl_gt2 = {
 534    GEN9_FEATURES,
 535    .is_kabylake = true,
 536    .gt = 2,
 537
 538    .num_slices = 1,
 539    .l3_banks = 4,
 540 };
 541
 542 static const struct gen_device_info gen_device_info_kbl_gt3 = {
 543    GEN9_FEATURES,
 544    .is_kabylake = true,
 545    .gt = 3,
 546
 547    .num_slices = 2,
 548    .l3_banks = 8,
 549 };
 550
 551 static const struct gen_device_info gen_device_info_kbl_gt4 = {
 552    GEN9_FEATURES,
 553    .is_kabylake = true,
 554    .gt = 4,
 555
 556    /*
 557     * From the "L3 Allocation and Programming" documentation:
 558     *
 559     * "URB is limited to 1008KB due to programming restrictions.  This
 560     *  is not a restriction of the L3 implementation, but of the FF and
 561     *  other clients.  Therefore, in a GT4 implementation it is
 562     *  possible for the programmed allocation of the L3 data array to
 563     *  provide 3*384KB=1152KB for URB, but only 1008KB of this
 564     *  will be used."
 565     */
 566    .urb.size = 1008 / 3,
 567    .num_slices = 3,
 568    .l3_banks = 12,
 569 };
 570
 571 static const struct gen_device_info gen_device_info_glk = {
 572    GEN9_LP_FEATURES,
 573    .l3_banks = 2,
 574 };
 575
 576 /*TODO: Initialize l3_banks when we know the number. */
 577 static const struct gen_device_info gen_device_info_glk_2x6 = {
 578    GEN9_LP_FEATURES_2X6
 579 };
 580
 581 #define GEN10_HW_INFO                               \
 582    .gen = 10,                                       \
 583    .max_vs_threads = 728,                           \
 584    .max_gs_threads = 432,                           \
 585    .max_tcs_threads = 432,                          \
 586    .max_tes_threads = 624,                          \
 587    .max_cs_threads = 56,                            \
 588    .urb = {                                         \
 589       .size = 256,                                  \
 590       .min_entries = {                              \
 591          [MESA_SHADER_VERTEX]    = 64,              \
 592          [MESA_SHADER_TESS_EVAL] = 34,              \
 593       },                                            \
 594       .max_entries = {                              \
 595       [MESA_SHADER_VERTEX]       = 3936,            \
 596       [MESA_SHADER_TESS_CTRL]    = 896,             \
 597       [MESA_SHADER_TESS_EVAL]    = 2064,            \
 598       [MESA_SHADER_GEOMETRY]     = 832,             \
 599       },                                            \
 600    }
 601
 602 #define GEN10_FEATURES(_gt, _slices, _l3)           \
 603    GEN8_FEATURES,                                   \
 604    GEN10_HW_INFO,                                   \
 605    .gt = _gt, .num_slices = _slices, .l3_banks = _l3
 606
 607 static const struct gen_device_info gen_device_info_cnl_2x8 = {
 608    /* GT0.5 */
 609    GEN10_FEATURES(1, 1, 2)
 610 };
 611
 612 static const struct gen_device_info gen_device_info_cnl_3x8 = {
 613    /* GT1 */
 614    GEN10_FEATURES(1, 1, 3)
 615 };
 616
 617 static const struct gen_device_info gen_device_info_cnl_4x8 = {
 618    /* GT 1.5 */
 619    GEN10_FEATURES(1, 2, 6)
 620 };
 621
 622 static const struct gen_device_info gen_device_info_cnl_5x8 = {
 623    /* GT2 */
 624    GEN10_FEATURES(2, 2, 6)
 625 };
 626
 627 bool
 628 gen_get_device_info(int devid, struct gen_device_info *devinfo)
 629 {
 630    switch (devid) {
 631 #undef CHIPSET
 632 #define CHIPSET(id, family, name) \
 633       case id: *devinfo = gen_device_info_##family; break;
 634 #include "pci_ids/i965_pci_ids.h"
 635    default:
 636       fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid);
 637       return false;
 638    }
 639
 640    /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
 641     *
 642     * "Scratch Space per slice is computed based on 4 sub-slices.  SW must
 643     *  allocate scratch space enough so that each slice has 4 slices allowed."
 644     *
 645     * The equivalent internal documentation says that this programming note
 646     * applies to all Gen9+ platforms.
 647     *
 648     * The hardware typically calculates the scratch space pointer by taking
 649     * the base address, and adding per-thread-scratch-space * thread ID.
 650     * Extra padding can be necessary depending how the thread IDs are
 651     * calculated for a particular shader stage.
 652     */
 653    if (devinfo->gen >= 9) {
 654       devinfo->max_wm_threads = 64 /* threads-per-PSD */
 655                               * devinfo->num_slices
 656                               * 4; /* effective subslices per slice */
 657    }
 658
 659    return true;
 660 }
 661
 662 const char *
 663 gen_get_device_name(int devid)
 664 {
 665    switch (devid) {
 666 #undef CHIPSET
 667 #define CHIPSET(id, family, name) case id: return name;
 668 #include "pci_ids/i965_pci_ids.h"
 669    default:
 670       return NULL;
 671    }
 672 }