2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "gen_device_info.h"
28 #include "compiler/shader_enums.h"
29 #include "util/macros.h"
31 static const struct gen_device_info gen_device_info_i965
= {
33 .has_negative_rhw_bug
= true,
35 .num_subslices
= { 1, },
36 .num_thread_per_eu
= 4,
39 .max_wm_threads
= 8 * 4,
43 .timestamp_frequency
= 12500000,
46 static const struct gen_device_info gen_device_info_g4x
= {
50 .has_surface_tile_offset
= true,
53 .num_subslices
= { 1, },
54 .num_thread_per_eu
= 5,
57 .max_wm_threads
= 10 * 5,
61 .timestamp_frequency
= 12500000,
64 static const struct gen_device_info gen_device_info_ilk
= {
68 .has_surface_tile_offset
= true,
70 .num_subslices
= { 1, },
71 .num_thread_per_eu
= 6,
74 .max_wm_threads
= 12 * 6,
78 .timestamp_frequency
= 12500000,
81 static const struct gen_device_info gen_device_info_snb_gt1
= {
84 .has_hiz_and_separate_stencil
= true,
87 .has_surface_tile_offset
= true,
88 .needs_unlit_centroid_workaround
= true,
90 .num_subslices
= { 1, },
91 .num_thread_per_eu
= 6, /* Not confirmed */
93 .max_gs_threads
= 21, /* conservative; 24 if rendering disabled. */
98 [MESA_SHADER_VERTEX
] = 24,
101 [MESA_SHADER_VERTEX
] = 256,
102 [MESA_SHADER_GEOMETRY
] = 256,
105 .timestamp_frequency
= 12500000,
108 static const struct gen_device_info gen_device_info_snb_gt2
= {
111 .has_hiz_and_separate_stencil
= true,
114 .has_surface_tile_offset
= true,
115 .needs_unlit_centroid_workaround
= true,
117 .num_subslices
= { 1, },
118 .num_thread_per_eu
= 6, /* Not confirmed */
119 .max_vs_threads
= 60,
120 .max_gs_threads
= 60,
121 .max_wm_threads
= 80,
125 [MESA_SHADER_VERTEX
] = 24,
128 [MESA_SHADER_VERTEX
] = 256,
129 [MESA_SHADER_GEOMETRY
] = 256,
132 .timestamp_frequency
= 12500000,
135 #define GEN7_FEATURES \
137 .has_hiz_and_separate_stencil = true, \
138 .must_use_separate_stencil = true, \
141 .has_surface_tile_offset = true, \
142 .timestamp_frequency = 12500000
144 static const struct gen_device_info gen_device_info_ivb_gt1
= {
145 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 1,
147 .num_subslices
= { 1, },
148 .num_thread_per_eu
= 6,
150 .max_vs_threads
= 36,
151 .max_tcs_threads
= 36,
152 .max_tes_threads
= 36,
153 .max_gs_threads
= 36,
154 .max_wm_threads
= 48,
155 .max_cs_threads
= 36,
159 [MESA_SHADER_VERTEX
] = 32,
160 [MESA_SHADER_TESS_EVAL
] = 10,
163 [MESA_SHADER_VERTEX
] = 512,
164 [MESA_SHADER_TESS_CTRL
] = 32,
165 [MESA_SHADER_TESS_EVAL
] = 288,
166 [MESA_SHADER_GEOMETRY
] = 192,
171 static const struct gen_device_info gen_device_info_ivb_gt2
= {
172 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 2,
174 .num_subslices
= { 1, },
175 .num_thread_per_eu
= 8, /* Not sure why this isn't a multiple of
176 * @max_wm_threads ... */
178 .max_vs_threads
= 128,
179 .max_tcs_threads
= 128,
180 .max_tes_threads
= 128,
181 .max_gs_threads
= 128,
182 .max_wm_threads
= 172,
183 .max_cs_threads
= 64,
187 [MESA_SHADER_VERTEX
] = 32,
188 [MESA_SHADER_TESS_EVAL
] = 10,
191 [MESA_SHADER_VERTEX
] = 704,
192 [MESA_SHADER_TESS_CTRL
] = 64,
193 [MESA_SHADER_TESS_EVAL
] = 448,
194 [MESA_SHADER_GEOMETRY
] = 320,
199 static const struct gen_device_info gen_device_info_byt
= {
200 GEN7_FEATURES
, .is_baytrail
= true, .gt
= 1,
202 .num_subslices
= { 1, },
203 .num_thread_per_eu
= 8,
206 .max_vs_threads
= 36,
207 .max_tcs_threads
= 36,
208 .max_tes_threads
= 36,
209 .max_gs_threads
= 36,
210 .max_wm_threads
= 48,
211 .max_cs_threads
= 32,
215 [MESA_SHADER_VERTEX
] = 32,
216 [MESA_SHADER_TESS_EVAL
] = 10,
219 [MESA_SHADER_VERTEX
] = 512,
220 [MESA_SHADER_TESS_CTRL
] = 32,
221 [MESA_SHADER_TESS_EVAL
] = 288,
222 [MESA_SHADER_GEOMETRY
] = 192,
227 #define HSW_FEATURES \
229 .is_haswell = true, \
230 .supports_simd16_3src = true, \
231 .has_resource_streamer = true
233 static const struct gen_device_info gen_device_info_hsw_gt1
= {
234 HSW_FEATURES
, .gt
= 1,
236 .num_subslices
= { 1, },
237 .num_thread_per_eu
= 7,
239 .max_vs_threads
= 70,
240 .max_tcs_threads
= 70,
241 .max_tes_threads
= 70,
242 .max_gs_threads
= 70,
243 .max_wm_threads
= 102,
244 .max_cs_threads
= 70,
248 [MESA_SHADER_VERTEX
] = 32,
249 [MESA_SHADER_TESS_EVAL
] = 10,
252 [MESA_SHADER_VERTEX
] = 640,
253 [MESA_SHADER_TESS_CTRL
] = 64,
254 [MESA_SHADER_TESS_EVAL
] = 384,
255 [MESA_SHADER_GEOMETRY
] = 256,
260 static const struct gen_device_info gen_device_info_hsw_gt2
= {
261 HSW_FEATURES
, .gt
= 2,
263 .num_subslices
= { 2, },
264 .num_thread_per_eu
= 7,
266 .max_vs_threads
= 280,
267 .max_tcs_threads
= 256,
268 .max_tes_threads
= 280,
269 .max_gs_threads
= 256,
270 .max_wm_threads
= 204,
271 .max_cs_threads
= 70,
275 [MESA_SHADER_VERTEX
] = 64,
276 [MESA_SHADER_TESS_EVAL
] = 10,
279 [MESA_SHADER_VERTEX
] = 1664,
280 [MESA_SHADER_TESS_CTRL
] = 128,
281 [MESA_SHADER_TESS_EVAL
] = 960,
282 [MESA_SHADER_GEOMETRY
] = 640,
287 static const struct gen_device_info gen_device_info_hsw_gt3
= {
288 HSW_FEATURES
, .gt
= 3,
290 .num_subslices
= { 2, },
291 .num_thread_per_eu
= 7,
293 .max_vs_threads
= 280,
294 .max_tcs_threads
= 256,
295 .max_tes_threads
= 280,
296 .max_gs_threads
= 256,
297 .max_wm_threads
= 408,
298 .max_cs_threads
= 70,
302 [MESA_SHADER_VERTEX
] = 64,
303 [MESA_SHADER_TESS_EVAL
] = 10,
306 [MESA_SHADER_VERTEX
] = 1664,
307 [MESA_SHADER_TESS_CTRL
] = 128,
308 [MESA_SHADER_TESS_EVAL
] = 960,
309 [MESA_SHADER_GEOMETRY
] = 640,
314 #define GEN8_FEATURES \
316 .has_hiz_and_separate_stencil = true, \
317 .has_resource_streamer = true, \
318 .must_use_separate_stencil = true, \
321 .supports_simd16_3src = true, \
322 .has_surface_tile_offset = true, \
323 .max_vs_threads = 504, \
324 .max_tcs_threads = 504, \
325 .max_tes_threads = 504, \
326 .max_gs_threads = 504, \
327 .max_wm_threads = 384, \
328 .timestamp_frequency = 12500000
330 static const struct gen_device_info gen_device_info_bdw_gt1
= {
331 GEN8_FEATURES
, .gt
= 1,
332 .is_broadwell
= true,
334 .num_subslices
= { 2, },
335 .num_thread_per_eu
= 7,
337 .max_cs_threads
= 42,
341 [MESA_SHADER_VERTEX
] = 64,
342 [MESA_SHADER_TESS_EVAL
] = 34,
345 [MESA_SHADER_VERTEX
] = 2560,
346 [MESA_SHADER_TESS_CTRL
] = 504,
347 [MESA_SHADER_TESS_EVAL
] = 1536,
348 [MESA_SHADER_GEOMETRY
] = 960,
353 static const struct gen_device_info gen_device_info_bdw_gt2
= {
354 GEN8_FEATURES
, .gt
= 2,
355 .is_broadwell
= true,
357 .num_subslices
= { 3, },
358 .num_thread_per_eu
= 7,
360 .max_cs_threads
= 56,
364 [MESA_SHADER_VERTEX
] = 64,
365 [MESA_SHADER_TESS_EVAL
] = 34,
368 [MESA_SHADER_VERTEX
] = 2560,
369 [MESA_SHADER_TESS_CTRL
] = 504,
370 [MESA_SHADER_TESS_EVAL
] = 1536,
371 [MESA_SHADER_GEOMETRY
] = 960,
376 static const struct gen_device_info gen_device_info_bdw_gt3
= {
377 GEN8_FEATURES
, .gt
= 3,
378 .is_broadwell
= true,
380 .num_subslices
= { 3, 3, },
381 .num_thread_per_eu
= 7,
383 .max_cs_threads
= 56,
387 [MESA_SHADER_VERTEX
] = 64,
388 [MESA_SHADER_TESS_EVAL
] = 34,
391 [MESA_SHADER_VERTEX
] = 2560,
392 [MESA_SHADER_TESS_CTRL
] = 504,
393 [MESA_SHADER_TESS_EVAL
] = 1536,
394 [MESA_SHADER_GEOMETRY
] = 960,
399 static const struct gen_device_info gen_device_info_chv
= {
400 GEN8_FEATURES
, .is_cherryview
= 1, .gt
= 1,
403 .num_subslices
= { 2, },
404 .num_thread_per_eu
= 7,
406 .max_vs_threads
= 80,
407 .max_tcs_threads
= 80,
408 .max_tes_threads
= 80,
409 .max_gs_threads
= 80,
410 .max_wm_threads
= 128,
411 .max_cs_threads
= 6 * 7,
415 [MESA_SHADER_VERTEX
] = 34,
416 [MESA_SHADER_TESS_EVAL
] = 34,
419 [MESA_SHADER_VERTEX
] = 640,
420 [MESA_SHADER_TESS_CTRL
] = 80,
421 [MESA_SHADER_TESS_EVAL
] = 384,
422 [MESA_SHADER_GEOMETRY
] = 256,
427 #define GEN9_HW_INFO \
429 .max_vs_threads = 336, \
430 .max_gs_threads = 336, \
431 .max_tcs_threads = 336, \
432 .max_tes_threads = 336, \
433 .max_cs_threads = 56, \
434 .timestamp_frequency = 12000000, \
438 [MESA_SHADER_VERTEX] = 64, \
439 [MESA_SHADER_TESS_EVAL] = 34, \
442 [MESA_SHADER_VERTEX] = 1856, \
443 [MESA_SHADER_TESS_CTRL] = 672, \
444 [MESA_SHADER_TESS_EVAL] = 1120, \
445 [MESA_SHADER_GEOMETRY] = 640, \
449 #define GEN9_LP_FEATURES \
455 .num_thread_per_eu = 6, \
456 .max_vs_threads = 112, \
457 .max_tcs_threads = 112, \
458 .max_tes_threads = 112, \
459 .max_gs_threads = 112, \
460 .max_cs_threads = 6 * 6, \
461 .timestamp_frequency = 19200000, \
465 [MESA_SHADER_VERTEX] = 34, \
466 [MESA_SHADER_TESS_EVAL] = 34, \
469 [MESA_SHADER_VERTEX] = 704, \
470 [MESA_SHADER_TESS_CTRL] = 256, \
471 [MESA_SHADER_TESS_EVAL] = 416, \
472 [MESA_SHADER_GEOMETRY] = 256, \
476 #define GEN9_LP_FEATURES_3X6 \
478 .num_subslices = { 3, }
480 #define GEN9_LP_FEATURES_2X6 \
482 .num_subslices = { 2, }, \
483 .max_vs_threads = 56, \
484 .max_tcs_threads = 56, \
485 .max_tes_threads = 56, \
486 .max_gs_threads = 56, \
487 .max_cs_threads = 6 * 6, \
491 [MESA_SHADER_VERTEX] = 34, \
492 [MESA_SHADER_TESS_EVAL] = 34, \
495 [MESA_SHADER_VERTEX] = 352, \
496 [MESA_SHADER_TESS_CTRL] = 128, \
497 [MESA_SHADER_TESS_EVAL] = 208, \
498 [MESA_SHADER_GEOMETRY] = 128, \
502 #define GEN9_FEATURES \
505 .num_thread_per_eu = 7
507 static const struct gen_device_info gen_device_info_skl_gt1
= {
508 GEN9_FEATURES
, .gt
= 1,
511 .num_subslices
= { 2, },
516 static const struct gen_device_info gen_device_info_skl_gt2
= {
517 GEN9_FEATURES
, .gt
= 2,
520 .num_subslices
= { 3, },
524 static const struct gen_device_info gen_device_info_skl_gt3
= {
525 GEN9_FEATURES
, .gt
= 3,
528 .num_subslices
= { 3, 3, },
532 static const struct gen_device_info gen_device_info_skl_gt4
= {
533 GEN9_FEATURES
, .gt
= 4,
536 .num_subslices
= { 3, 3, 3, },
538 /* From the "L3 Allocation and Programming" documentation:
540 * "URB is limited to 1008KB due to programming restrictions. This is not a
541 * restriction of the L3 implementation, but of the FF and other clients.
542 * Therefore, in a GT4 implementation it is possible for the programmed
543 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
544 * only 1008KB of this will be used."
546 .urb
.size
= 1008 / 3,
549 static const struct gen_device_info gen_device_info_bxt
= {
550 GEN9_LP_FEATURES_3X6
,
555 static const struct gen_device_info gen_device_info_bxt_2x6
= {
556 GEN9_LP_FEATURES_2X6
,
561 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
562 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
565 static const struct gen_device_info gen_device_info_kbl_gt1
= {
570 .max_cs_threads
= 7 * 6,
573 .num_subslices
= { 2, },
577 static const struct gen_device_info gen_device_info_kbl_gt1_5
= {
582 .max_cs_threads
= 7 * 6,
584 .num_subslices
= { 3, },
588 static const struct gen_device_info gen_device_info_kbl_gt2
= {
594 .num_subslices
= { 3, },
598 static const struct gen_device_info gen_device_info_kbl_gt3
= {
604 .num_subslices
= { 3, 3, },
608 static const struct gen_device_info gen_device_info_kbl_gt4
= {
614 * From the "L3 Allocation and Programming" documentation:
616 * "URB is limited to 1008KB due to programming restrictions. This
617 * is not a restriction of the L3 implementation, but of the FF and
618 * other clients. Therefore, in a GT4 implementation it is
619 * possible for the programmed allocation of the L3 data array to
620 * provide 3*384KB=1152KB for URB, but only 1008KB of this
623 .urb
.size
= 1008 / 3,
625 .num_subslices
= { 3, 3, 3, },
629 static const struct gen_device_info gen_device_info_glk
= {
630 GEN9_LP_FEATURES_3X6
,
631 .is_geminilake
= true,
635 /*TODO: Initialize l3_banks when we know the number. */
636 static const struct gen_device_info gen_device_info_glk_2x6
= {
637 GEN9_LP_FEATURES_2X6
,
638 .is_geminilake
= true,
641 static const struct gen_device_info gen_device_info_cfl_gt1
= {
643 .is_coffeelake
= true,
647 .num_subslices
= { 2, },
650 static const struct gen_device_info gen_device_info_cfl_gt2
= {
652 .is_coffeelake
= true,
656 .num_subslices
= { 3, },
660 static const struct gen_device_info gen_device_info_cfl_gt3
= {
662 .is_coffeelake
= true,
666 .num_subslices
= { 3, 3, },
670 #define GEN10_HW_INFO \
672 .num_thread_per_eu = 7, \
673 .max_vs_threads = 728, \
674 .max_gs_threads = 432, \
675 .max_tcs_threads = 432, \
676 .max_tes_threads = 624, \
677 .max_cs_threads = 56, \
678 .timestamp_frequency = 19200000, \
682 [MESA_SHADER_VERTEX] = 64, \
683 [MESA_SHADER_TESS_EVAL] = 34, \
686 [MESA_SHADER_VERTEX] = 3936, \
687 [MESA_SHADER_TESS_CTRL] = 896, \
688 [MESA_SHADER_TESS_EVAL] = 2064, \
689 [MESA_SHADER_GEOMETRY] = 832, \
693 #define subslices(args...) { args, }
695 #define GEN10_FEATURES(_gt, _slices, _subslices, _l3) \
699 .num_slices = _slices, \
700 .num_subslices = _subslices, \
703 static const struct gen_device_info gen_device_info_cnl_2x8
= {
705 GEN10_FEATURES(1, 1, subslices(2), 2),
706 .is_cannonlake
= true,
709 static const struct gen_device_info gen_device_info_cnl_3x8
= {
711 GEN10_FEATURES(1, 1, subslices(3), 3),
712 .is_cannonlake
= true,
715 static const struct gen_device_info gen_device_info_cnl_4x8
= {
717 GEN10_FEATURES(1, 2, subslices(2, 2), 6),
718 .is_cannonlake
= true,
721 static const struct gen_device_info gen_device_info_cnl_5x8
= {
723 GEN10_FEATURES(2, 2, subslices(3, 2), 6),
724 .is_cannonlake
= true,
728 gen_get_device_info(int devid
, struct gen_device_info
*devinfo
)
732 #define CHIPSET(id, family, name) \
733 case id: *devinfo = gen_device_info_##family; break;
734 #include "pci_ids/i965_pci_ids.h"
736 fprintf(stderr
, "i965_dri.so does not support the 0x%x PCI ID.\n", devid
);
740 /* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer:
742 * "Scratch Space per slice is computed based on 4 sub-slices. SW must
743 * allocate scratch space enough so that each slice has 4 slices allowed."
745 * The equivalent internal documentation says that this programming note
746 * applies to all Gen9+ platforms.
748 * The hardware typically calculates the scratch space pointer by taking
749 * the base address, and adding per-thread-scratch-space * thread ID.
750 * Extra padding can be necessary depending how the thread IDs are
751 * calculated for a particular shader stage.
753 if (devinfo
->gen
>= 9) {
754 devinfo
->max_wm_threads
= 64 /* threads-per-PSD */
755 * devinfo
->num_slices
756 * 4; /* effective subslices per slice */
759 assert(devinfo
->num_slices
<= ARRAY_SIZE(devinfo
->num_subslices
));
765 gen_get_device_name(int devid
)
769 #define CHIPSET(id, family, name) case id: return name;
770 #include "pci_ids/i965_pci_ids.h"