src/intel/common/gen_device_info.h

   1  /*
   2   * Copyright © 2013 Intel Corporation
   3   *
   4   * Permission is hereby granted, free of charge, to any person obtaining a
   5   * copy of this software and associated documentation files (the "Software"),
   6   * to deal in the Software without restriction, including without limitation
   7   * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8   * and/or sell copies of the Software, and to permit persons to whom the
   9   * Software is furnished to do so, subject to the following conditions:
  10   *
  11   * The above copyright notice and this permission notice (including the next
  12   * paragraph) shall be included in all copies or substantial portions of the
  13   * Software.
  14   *
  15   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18   * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19   * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20   * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21   * IN THE SOFTWARE.
  22   *
  23   */
  24
  25 #pragma once
  26 #include <stdbool.h>
  27
  28 /**
  29  * Intel hardware information and quirks
  30  */
  31 struct gen_device_info
  32 {
  33    int gen; /**< Generation number: 4, 5, 6, 7, ... */
  34    int gt;
  35
  36    bool is_g4x;
  37    bool is_ivybridge;
  38    bool is_baytrail;
  39    bool is_haswell;
  40    bool is_cherryview;
  41    bool is_broxton;
  42
  43    bool has_hiz_and_separate_stencil;
  44    bool must_use_separate_stencil;
  45
  46    bool has_llc;
  47
  48    bool has_pln;
  49    bool has_compr4;
  50    bool has_surface_tile_offset;
  51    bool supports_simd16_3src;
  52    bool has_resource_streamer;
  53
  54    /**
  55     * \name Intel hardware quirks
  56     *  @{
  57     */
  58    bool has_negative_rhw_bug;
  59
  60    /**
  61     * Some versions of Gen hardware don't do centroid interpolation correctly
  62     * on unlit pixels, causing incorrect values for derivatives near triangle
  63     * edges.  Enabling this flag causes the fragment shader to use
  64     * non-centroid interpolation for unlit pixels, at the expense of two extra
  65     * fragment shader instructions.
  66     */
  67    bool needs_unlit_centroid_workaround;
  68    /** @} */
  69
  70    /**
  71     * \name GPU hardware limits
  72     *
  73     * In general, you can find shader thread maximums by looking at the "Maximum
  74     * Number of Threads" field in the Intel PRM description of the 3DSTATE_VS,
  75     * 3DSTATE_GS, 3DSTATE_HS, 3DSTATE_DS, and 3DSTATE_PS commands. URB entry
  76     * limits come from the "Number of URB Entries" field in the
  77     * 3DSTATE_URB_VS command and friends.
  78     *
  79     * These fields are used to calculate the scratch space to allocate.  The
  80     * amount of scratch space can be larger without being harmful on modern
  81     * GPUs, however, prior to Haswell, programming the maximum number of threads
  82     * to greater than the hardware maximum would cause GPU performance to tank.
  83     *
  84     *  @{
  85     */
  86    /**
  87     * Total number of slices present on the device whether or not they've been
  88     * fused off.
  89     *
  90     * XXX: CS thread counts are limited by the inability to do cross subslice
  91     * communication. It is the effectively the number of logical threads which
  92     * can be executed in a subslice. Fuse configurations may cause this number
  93     * to change, so we program @max_cs_threads as the lower maximum.
  94     */
  95    unsigned num_slices;
  96    unsigned max_vs_threads;   /**< Maximum Vertex Shader threads */
  97    unsigned max_hs_threads;   /**< Maximum Hull Shader threads */
  98    unsigned max_ds_threads;   /**< Maximum Domain Shader threads */
  99    unsigned max_gs_threads;   /**< Maximum Geometry Shader threads. */
 100    /**
 101     * Theoretical maximum number of Pixel Shader threads.
 102     *
 103     * PSD means Pixel Shader Dispatcher. On modern Intel GPUs, hardware will
 104     * automatically scale pixel shader thread count, based on a single value
 105     * programmed into 3DSTATE_PS.
 106     *
 107     * To calculate the maximum number of threads for Gen8 beyond (which have
 108     * multiple Pixel Shader Dispatchers):
 109     *
 110     * - Look up 3DSTATE_PS and find "Maximum Number of Threads Per PSD"
 111     * - Usually there's only one PSD per subslice, so use the number of
 112     *   subslices for number of PSDs.
 113     * - For max_wm_threads, the total should be PSD threads * #PSDs.
 114     */
 115    unsigned max_wm_threads;
 116
 117    /**
 118     * Maximum Compute Shader threads.
 119     *
 120     * Thread count * number of EUs per subslice
 121     */
 122    unsigned max_cs_threads;
 123
 124    struct {
 125       /**
 126        * Hardware default URB size.
 127        *
 128        * The units this is expressed in are somewhat inconsistent: 512b units
 129        * on Gen4-5, KB on Gen6-7, and KB times the slice count on Gen8+.
 130        *
 131        * Look up "URB Size" in the "Device Attributes" page, and take the
 132        * maximum.  Look up the slice count for each GT SKU on the same page.
 133        * urb.size = URB Size (kbytes) / slice count
 134        */
 135       unsigned size;
 136       unsigned min_vs_entries;
 137       unsigned max_vs_entries;
 138       unsigned max_hs_entries;
 139       unsigned min_ds_entries;
 140       unsigned max_ds_entries;
 141       unsigned max_gs_entries;
 142    } urb;
 143    /** @} */
 144 };
 145
 146 const bool gen_get_device_info(int devid, struct gen_device_info *devinfo);
 147 const char *gen_get_device_name(int devid);