2 * Copyright (c) 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "util/macros.h"
28 #include "main/macros.h"
30 #include "gen_l3_config.h"
33 * IVB/HSW validated L3 configurations. The first entry will be used as
34 * default by gen7_restore_default_l3_config(), otherwise the ordering is
37 static const struct gen_l3_config ivb_l3_configs
[] = {
38 /* SLM URB ALL DC RO IS C T */
39 {{ 0, 32, 0, 0, 32, 0, 0, 0 }},
40 {{ 0, 32, 0, 16, 16, 0, 0, 0 }},
41 {{ 0, 32, 0, 4, 0, 8, 4, 16 }},
42 {{ 0, 28, 0, 8, 0, 8, 4, 16 }},
43 {{ 0, 28, 0, 16, 0, 8, 4, 8 }},
44 {{ 0, 28, 0, 8, 0, 16, 4, 8 }},
45 {{ 0, 28, 0, 0, 0, 16, 4, 16 }},
46 {{ 0, 32, 0, 0, 0, 16, 0, 16 }},
47 {{ 0, 28, 0, 4, 32, 0, 0, 0 }},
48 {{ 16, 16, 0, 16, 16, 0, 0, 0 }},
49 {{ 16, 16, 0, 8, 0, 8, 8, 8 }},
50 {{ 16, 16, 0, 4, 0, 8, 4, 16 }},
51 {{ 16, 16, 0, 4, 0, 16, 4, 8 }},
52 {{ 16, 16, 0, 0, 32, 0, 0, 0 }},
57 * VLV validated L3 configurations. \sa ivb_l3_configs.
59 static const struct gen_l3_config vlv_l3_configs
[] = {
60 /* SLM URB ALL DC RO IS C T */
61 {{ 0, 64, 0, 0, 32, 0, 0, 0 }},
62 {{ 0, 80, 0, 0, 16, 0, 0, 0 }},
63 {{ 0, 80, 0, 8, 8, 0, 0, 0 }},
64 {{ 0, 64, 0, 16, 16, 0, 0, 0 }},
65 {{ 0, 60, 0, 4, 32, 0, 0, 0 }},
66 {{ 32, 32, 0, 16, 16, 0, 0, 0 }},
67 {{ 32, 40, 0, 8, 16, 0, 0, 0 }},
68 {{ 32, 40, 0, 16, 8, 0, 0, 0 }},
73 * BDW validated L3 configurations. \sa ivb_l3_configs.
75 static const struct gen_l3_config bdw_l3_configs
[] = {
76 /* SLM URB ALL DC RO IS C T */
77 {{ 0, 48, 48, 0, 0, 0, 0, 0 }},
78 {{ 0, 48, 0, 16, 32, 0, 0, 0 }},
79 {{ 0, 32, 0, 16, 48, 0, 0, 0 }},
80 {{ 0, 32, 0, 0, 64, 0, 0, 0 }},
81 {{ 0, 32, 64, 0, 0, 0, 0, 0 }},
82 {{ 24, 16, 48, 0, 0, 0, 0, 0 }},
83 {{ 24, 16, 0, 16, 32, 0, 0, 0 }},
84 {{ 24, 16, 0, 32, 16, 0, 0, 0 }},
89 * CHV/SKL validated L3 configurations. \sa ivb_l3_configs.
91 static const struct gen_l3_config chv_l3_configs
[] = {
92 /* SLM URB ALL DC RO IS C T */
93 {{ 0, 48, 48, 0, 0, 0, 0, 0 }},
94 {{ 0, 48, 0, 16, 32, 0, 0, 0 }},
95 {{ 0, 32, 0, 16, 48, 0, 0, 0 }},
96 {{ 0, 32, 0, 0, 64, 0, 0, 0 }},
97 {{ 0, 32, 64, 0, 0, 0, 0, 0 }},
98 {{ 32, 16, 48, 0, 0, 0, 0, 0 }},
99 {{ 32, 16, 0, 16, 32, 0, 0, 0 }},
100 {{ 32, 16, 0, 32, 16, 0, 0, 0 }},
105 * BXT 2x6 validated L3 configurations. \sa ivb_l3_configs.
107 static const struct gen_l3_config bxt_2x6_l3_configs
[] = {
108 /* SLM URB ALL DC RO IS C T */
109 {{ 0, 32, 48, 0, 0, 0, 0, 0 }},
110 {{ 0, 32, 0, 8, 40, 0, 0, 0 }},
111 {{ 0, 32, 0, 32, 16, 0, 0, 0 }},
112 {{ 16, 16, 48, 0, 0, 0, 0, 0 }},
113 {{ 16, 16, 0, 40, 8, 0, 0, 0 }},
114 {{ 16, 16, 0, 16, 32, 0, 0, 0 }},
119 * CNL validated L3 configurations. \sa ivb_l3_configs.
121 static const struct gen_l3_config cnl_l3_configs
[] = {
122 /* SLM URB ALL DC RO IS C T */
123 {{ 0, 64, 64, 0, 0, 0, 0, 0 }},
124 {{ 0, 64, 0, 16, 48, 0, 0, 0 }},
125 {{ 0, 48, 0, 16, 64, 0, 0, 0 }},
126 {{ 0, 32, 0, 0, 96, 0, 0, 0 }},
127 {{ 0, 32, 96, 0, 0, 0, 0, 0 }},
128 {{ 0, 32, 0, 16, 80, 0, 0, 0 }},
129 {{ 32, 16, 80, 0, 0, 0, 0, 0 }},
130 {{ 32, 16, 0, 64, 16, 0, 0, 0 }},
131 {{ 32, 0, 96, 0, 0, 0, 0, 0 }},
136 * ICL validated L3 configurations. \sa icl_l3_configs.
137 * Zeroth entry in below table has been commented out intentionally
138 * due to known issues with this configuration. Many other entries
139 * suggested by h/w specification aren't added here because they
140 * do under allocation of L3 cache with below partitioning.
142 static const struct gen_l3_config icl_l3_configs
[] = {
143 /* SLM URB ALL DC RO IS C T */
144 /*{{ 0, 16, 80, 0, 0, 0, 0, 0 }},*/
145 {{ 0, 32, 64, 0, 0, 0, 0, 0 }},
151 * Return a zero-terminated array of validated L3 configurations for the
154 static const struct gen_l3_config
*
155 get_l3_configs(const struct gen_device_info
*devinfo
)
157 switch (devinfo
->gen
) {
159 return (devinfo
->is_baytrail
? vlv_l3_configs
: ivb_l3_configs
);
162 return (devinfo
->is_cherryview
? chv_l3_configs
: bdw_l3_configs
);
165 if (devinfo
->l3_banks
== 1)
166 return bxt_2x6_l3_configs
;
167 return chv_l3_configs
;
170 return cnl_l3_configs
;
173 return icl_l3_configs
;
176 unreachable("Not implemented");
181 * L1-normalize a vector of L3 partition weights.
183 static struct gen_l3_weights
184 norm_l3_weights(struct gen_l3_weights w
)
188 for (unsigned i
= 0; i
< GEN_NUM_L3P
; i
++)
191 for (unsigned i
= 0; i
< GEN_NUM_L3P
; i
++)
198 * Get the relative partition weights of the specified L3 configuration.
200 struct gen_l3_weights
201 gen_get_l3_config_weights(const struct gen_l3_config
*cfg
)
204 struct gen_l3_weights w
;
206 for (unsigned i
= 0; i
< GEN_NUM_L3P
; i
++)
209 return norm_l3_weights(w
);
211 const struct gen_l3_weights w
= { { 0 } };
217 * Distance between two L3 configurations represented as vectors of weights.
218 * Usually just the L1 metric except when the two configurations are
219 * considered incompatible in which case the distance will be infinite. Note
220 * that the compatibility condition is asymmetric -- They will be considered
221 * incompatible whenever the reference configuration \p w0 requires SLM, DC,
222 * or URB but \p w1 doesn't provide it.
225 gen_diff_l3_weights(struct gen_l3_weights w0
, struct gen_l3_weights w1
)
227 if ((w0
.w
[GEN_L3P_SLM
] && !w1
.w
[GEN_L3P_SLM
]) ||
228 (w0
.w
[GEN_L3P_DC
] && !w1
.w
[GEN_L3P_DC
] && !w1
.w
[GEN_L3P_ALL
]) ||
229 (w0
.w
[GEN_L3P_URB
] && !w1
.w
[GEN_L3P_URB
])) {
235 for (unsigned i
= 0; i
< GEN_NUM_L3P
; i
++)
236 dw
+= fabs(w0
.w
[i
] - w1
.w
[i
]);
243 * Return a reasonable default L3 configuration for the specified device based
244 * on whether SLM and DC are required. In the non-SLM non-DC case the result
245 * is intended to approximately resemble the hardware defaults.
247 struct gen_l3_weights
248 gen_get_default_l3_weights(const struct gen_device_info
*devinfo
,
249 bool needs_dc
, bool needs_slm
)
251 struct gen_l3_weights w
= {{ 0 }};
253 w
.w
[GEN_L3P_SLM
] = devinfo
->gen
< 11 && needs_slm
;
254 w
.w
[GEN_L3P_URB
] = 1.0;
256 if (devinfo
->gen
>= 8) {
257 w
.w
[GEN_L3P_ALL
] = 1.0;
259 w
.w
[GEN_L3P_DC
] = needs_dc
? 0.1 : 0;
260 w
.w
[GEN_L3P_RO
] = devinfo
->is_baytrail
? 0.5 : 1.0;
263 return norm_l3_weights(w
);
267 * Get the default L3 configuration
269 const struct gen_l3_config
*
270 gen_get_default_l3_config(const struct gen_device_info
*devinfo
)
272 /* For efficiency assume that the first entry of the array matches the
273 * default configuration.
275 const struct gen_l3_config
*const cfg
= get_l3_configs(devinfo
);
276 assert(cfg
== gen_get_l3_config(devinfo
,
277 gen_get_default_l3_weights(devinfo
, false, false)));
282 * Return the closest validated L3 configuration for the specified device and
285 const struct gen_l3_config
*
286 gen_get_l3_config(const struct gen_device_info
*devinfo
,
287 struct gen_l3_weights w0
)
289 const struct gen_l3_config
*const cfgs
= get_l3_configs(devinfo
);
290 const struct gen_l3_config
*cfg_best
= NULL
;
291 float dw_best
= HUGE_VALF
;
293 for (const struct gen_l3_config
*cfg
= cfgs
; cfg
->n
[GEN_L3P_URB
]; cfg
++) {
294 const float dw
= gen_diff_l3_weights(w0
, gen_get_l3_config_weights(cfg
));
306 * Return the size of an L3 way in KB.
309 get_l3_way_size(const struct gen_device_info
*devinfo
)
311 const unsigned way_size_per_bank
=
312 (devinfo
->gen
>= 9 && devinfo
->l3_banks
== 1) || devinfo
->gen
== 11 ?
315 assert(devinfo
->l3_banks
);
316 return way_size_per_bank
* devinfo
->l3_banks
;
320 * Return the unit brw_context::urb::size is expressed in, in KB. \sa
321 * gen_device_info::urb::size.
324 get_urb_size_scale(const struct gen_device_info
*devinfo
)
326 return (devinfo
->gen
>= 8 ? devinfo
->num_slices
: 1);
330 gen_get_l3_config_urb_size(const struct gen_device_info
*devinfo
,
331 const struct gen_l3_config
*cfg
)
333 /* From the SKL "L3 Allocation and Programming" documentation:
335 * "URB is limited to 1008KB due to programming restrictions. This is not
336 * a restriction of the L3 implementation, but of the FF and other clients.
337 * Therefore, in a GT4 implementation it is possible for the programmed
338 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
339 * only 1008KB of this will be used."
341 const unsigned max
= (devinfo
->gen
== 9 ? 1008 : ~0);
342 return MIN2(max
, cfg
->n
[GEN_L3P_URB
] * get_l3_way_size(devinfo
)) /
343 get_urb_size_scale(devinfo
);
347 * Print out the specified L3 configuration.
350 gen_dump_l3_config(const struct gen_l3_config
*cfg
, FILE *fp
)
352 fprintf(stderr
, "SLM=%d URB=%d ALL=%d DC=%d RO=%d IS=%d C=%d T=%d\n",
353 cfg
->n
[GEN_L3P_SLM
], cfg
->n
[GEN_L3P_URB
], cfg
->n
[GEN_L3P_ALL
],
354 cfg
->n
[GEN_L3P_DC
], cfg
->n
[GEN_L3P_RO
],
355 cfg
->n
[GEN_L3P_IS
], cfg
->n
[GEN_L3P_C
], cfg
->n
[GEN_L3P_T
]);