2 * Copyright © 2015-2016 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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24 #include "brw_compiler.h"
25 #include "brw_shader.h"
27 #include "common/gen_debug.h"
28 #include "compiler/nir/nir.h"
29 #include "main/errors.h"
30 #include "util/debug.h"
32 #define COMMON_OPTIONS \
36 .lower_fmod32 = true, \
37 .lower_fmod64 = false, \
38 .lower_bitfield_extract = true, \
39 .lower_bitfield_insert = true, \
40 .lower_uadd_carry = true, \
41 .lower_usub_borrow = true, \
43 .lower_flrp64 = true, \
44 .native_integers = true, \
45 .use_interpolated_input_intrinsics = true, \
46 .vertex_id_zero_based = true
48 static const struct nir_shader_compiler_options scalar_nir_options
= {
50 .lower_pack_half_2x16
= true,
51 .lower_pack_snorm_2x16
= true,
52 .lower_pack_snorm_4x8
= true,
53 .lower_pack_unorm_2x16
= true,
54 .lower_pack_unorm_4x8
= true,
55 .lower_unpack_half_2x16
= true,
56 .lower_unpack_snorm_2x16
= true,
57 .lower_unpack_snorm_4x8
= true,
58 .lower_unpack_unorm_2x16
= true,
59 .lower_unpack_unorm_4x8
= true,
60 .lower_subgroup_masks
= true,
61 .max_subgroup_size
= 32,
62 .max_unroll_iterations
= 32,
65 static const struct nir_shader_compiler_options vector_nir_options
= {
68 /* In the vec4 backend, our dpN instruction replicates its result to all the
69 * components of a vec4. We would like NIR to give us replicated fdot
70 * instructions because it can optimize better for us.
72 .fdot_replicates
= true,
74 /* Prior to Gen6, there are no three source operations for SIMD4x2. */
77 .lower_pack_snorm_2x16
= true,
78 .lower_pack_unorm_2x16
= true,
79 .lower_unpack_snorm_2x16
= true,
80 .lower_unpack_unorm_2x16
= true,
81 .lower_extract_byte
= true,
82 .lower_extract_word
= true,
83 .lower_vote_trivial
= true,
84 .max_unroll_iterations
= 32,
87 static const struct nir_shader_compiler_options vector_nir_options_gen6
= {
90 /* In the vec4 backend, our dpN instruction replicates its result to all the
91 * components of a vec4. We would like NIR to give us replicated fdot
92 * instructions because it can optimize better for us.
94 .fdot_replicates
= true,
96 .lower_pack_snorm_2x16
= true,
97 .lower_pack_unorm_2x16
= true,
98 .lower_unpack_snorm_2x16
= true,
99 .lower_unpack_unorm_2x16
= true,
100 .lower_extract_byte
= true,
101 .lower_extract_word
= true,
102 .lower_vote_trivial
= true,
103 .max_unroll_iterations
= 32,
106 struct brw_compiler
*
107 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
)
109 struct brw_compiler
*compiler
= rzalloc(mem_ctx
, struct brw_compiler
);
111 compiler
->devinfo
= devinfo
;
113 brw_fs_alloc_reg_sets(compiler
);
114 brw_vec4_alloc_reg_set(compiler
);
115 brw_init_compaction_tables(devinfo
);
117 compiler
->precise_trig
= env_var_as_boolean("INTEL_PRECISE_TRIG", false);
119 if (devinfo
->gen
>= 10) {
120 /* We don't support vec4 mode on Cannonlake. */
121 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_STAGES
; i
++)
122 compiler
->scalar_stage
[i
] = true;
124 compiler
->scalar_stage
[MESA_SHADER_VERTEX
] =
125 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_VS", true);
126 compiler
->scalar_stage
[MESA_SHADER_TESS_CTRL
] =
127 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", true);
128 compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
] =
129 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
130 compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
] =
131 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
132 compiler
->scalar_stage
[MESA_SHADER_FRAGMENT
] = true;
133 compiler
->scalar_stage
[MESA_SHADER_COMPUTE
] = true;
136 /* We want the GLSL compiler to emit code that uses condition codes */
137 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
138 compiler
->glsl_compiler_options
[i
].MaxUnrollIterations
= 0;
139 compiler
->glsl_compiler_options
[i
].MaxIfDepth
=
140 devinfo
->gen
< 6 ? 16 : UINT_MAX
;
142 compiler
->glsl_compiler_options
[i
].EmitNoIndirectInput
= true;
143 compiler
->glsl_compiler_options
[i
].EmitNoIndirectUniform
= false;
145 bool is_scalar
= compiler
->scalar_stage
[i
];
147 compiler
->glsl_compiler_options
[i
].EmitNoIndirectOutput
= is_scalar
;
148 compiler
->glsl_compiler_options
[i
].EmitNoIndirectTemp
= is_scalar
;
149 compiler
->glsl_compiler_options
[i
].OptimizeForAOS
= !is_scalar
;
152 compiler
->glsl_compiler_options
[i
].NirOptions
= &scalar_nir_options
;
154 compiler
->glsl_compiler_options
[i
].NirOptions
=
155 devinfo
->gen
< 6 ? &vector_nir_options
: &vector_nir_options_gen6
;
158 compiler
->glsl_compiler_options
[i
].LowerBufferInterfaceBlocks
= true;
159 compiler
->glsl_compiler_options
[i
].ClampBlockIndicesToArrayBounds
= true;
162 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].EmitNoIndirectInput
= false;
163 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_EVAL
].EmitNoIndirectInput
= false;
164 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].EmitNoIndirectOutput
= false;
166 if (compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
])
167 compiler
->glsl_compiler_options
[MESA_SHADER_GEOMETRY
].EmitNoIndirectInput
= false;