2 * Copyright © 2015-2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "brw_compiler.h"
25 #include "brw_shader.h"
27 #include "common/gen_debug.h"
28 #include "compiler/nir/nir.h"
29 #include "main/errors.h"
30 #include "util/debug.h"
32 #define COMMON_OPTIONS \
36 .lower_fmod32 = true, \
37 .lower_fmod64 = false, \
38 .lower_bitfield_extract = true, \
39 .lower_bitfield_insert = true, \
40 .lower_uadd_carry = true, \
41 .lower_usub_borrow = true, \
43 .lower_flrp64 = true, \
44 .lower_isign = true, \
45 .lower_ldexp = true, \
46 .lower_cs_local_id_from_index = true, \
47 .lower_device_index_to_zero = true, \
48 .native_integers = true, \
49 .use_interpolated_input_intrinsics = true, \
50 .vertex_id_zero_based = true, \
51 .lower_base_vertex = true
53 #define COMMON_SCALAR_OPTIONS \
54 .lower_pack_half_2x16 = true, \
55 .lower_pack_snorm_2x16 = true, \
56 .lower_pack_snorm_4x8 = true, \
57 .lower_pack_unorm_2x16 = true, \
58 .lower_pack_unorm_4x8 = true, \
59 .lower_unpack_half_2x16 = true, \
60 .lower_unpack_snorm_2x16 = true, \
61 .lower_unpack_snorm_4x8 = true, \
62 .lower_unpack_unorm_2x16 = true, \
63 .lower_unpack_unorm_4x8 = true, \
64 .max_unroll_iterations = 32
66 static const struct nir_shader_compiler_options scalar_nir_options
= {
68 COMMON_SCALAR_OPTIONS
,
71 static const struct nir_shader_compiler_options scalar_nir_options_gen11
= {
73 COMMON_SCALAR_OPTIONS
,
77 static const struct nir_shader_compiler_options vector_nir_options
= {
80 /* In the vec4 backend, our dpN instruction replicates its result to all the
81 * components of a vec4. We would like NIR to give us replicated fdot
82 * instructions because it can optimize better for us.
84 .fdot_replicates
= true,
86 /* Prior to Gen6, there are no three source operations for SIMD4x2. */
89 .lower_pack_snorm_2x16
= true,
90 .lower_pack_unorm_2x16
= true,
91 .lower_unpack_snorm_2x16
= true,
92 .lower_unpack_unorm_2x16
= true,
93 .lower_extract_byte
= true,
94 .lower_extract_word
= true,
95 .max_unroll_iterations
= 32,
98 static const struct nir_shader_compiler_options vector_nir_options_gen6
= {
101 /* In the vec4 backend, our dpN instruction replicates its result to all the
102 * components of a vec4. We would like NIR to give us replicated fdot
103 * instructions because it can optimize better for us.
105 .fdot_replicates
= true,
107 .lower_pack_snorm_2x16
= true,
108 .lower_pack_unorm_2x16
= true,
109 .lower_unpack_snorm_2x16
= true,
110 .lower_unpack_unorm_2x16
= true,
111 .lower_extract_byte
= true,
112 .lower_extract_word
= true,
113 .max_unroll_iterations
= 32,
116 struct brw_compiler
*
117 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
)
119 struct brw_compiler
*compiler
= rzalloc(mem_ctx
, struct brw_compiler
);
121 compiler
->devinfo
= devinfo
;
123 brw_fs_alloc_reg_sets(compiler
);
124 brw_vec4_alloc_reg_set(compiler
);
125 brw_init_compaction_tables(devinfo
);
127 compiler
->precise_trig
= env_var_as_boolean("INTEL_PRECISE_TRIG", false);
129 if (devinfo
->gen
>= 10) {
130 /* We don't support vec4 mode on Cannonlake. */
131 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_STAGES
; i
++)
132 compiler
->scalar_stage
[i
] = true;
134 compiler
->scalar_stage
[MESA_SHADER_VERTEX
] =
135 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_VS", true);
136 compiler
->scalar_stage
[MESA_SHADER_TESS_CTRL
] =
137 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", true);
138 compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
] =
139 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
140 compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
] =
141 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
142 compiler
->scalar_stage
[MESA_SHADER_FRAGMENT
] = true;
143 compiler
->scalar_stage
[MESA_SHADER_COMPUTE
] = true;
146 /* We want the GLSL compiler to emit code that uses condition codes */
147 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
148 compiler
->glsl_compiler_options
[i
].MaxUnrollIterations
= 0;
149 compiler
->glsl_compiler_options
[i
].MaxIfDepth
=
150 devinfo
->gen
< 6 ? 16 : UINT_MAX
;
152 compiler
->glsl_compiler_options
[i
].EmitNoIndirectInput
= true;
153 compiler
->glsl_compiler_options
[i
].EmitNoIndirectUniform
= false;
155 bool is_scalar
= compiler
->scalar_stage
[i
];
157 compiler
->glsl_compiler_options
[i
].EmitNoIndirectOutput
= is_scalar
;
158 compiler
->glsl_compiler_options
[i
].EmitNoIndirectTemp
= is_scalar
;
159 compiler
->glsl_compiler_options
[i
].OptimizeForAOS
= !is_scalar
;
162 compiler
->glsl_compiler_options
[i
].NirOptions
=
163 devinfo
->gen
< 11 ? &scalar_nir_options
: &scalar_nir_options_gen11
;
165 compiler
->glsl_compiler_options
[i
].NirOptions
=
166 devinfo
->gen
< 6 ? &vector_nir_options
: &vector_nir_options_gen6
;
169 compiler
->glsl_compiler_options
[i
].LowerBufferInterfaceBlocks
= true;
170 compiler
->glsl_compiler_options
[i
].ClampBlockIndicesToArrayBounds
= true;
173 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].EmitNoIndirectInput
= false;
174 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_EVAL
].EmitNoIndirectInput
= false;
175 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].EmitNoIndirectOutput
= false;
177 if (compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
])
178 compiler
->glsl_compiler_options
[MESA_SHADER_GEOMETRY
].EmitNoIndirectInput
= false;
184 insert_u64_bit(uint64_t *val
, bool add
)
186 *val
= (*val
<< 1) | !!add
;
190 brw_get_compiler_config_value(const struct brw_compiler
*compiler
)
193 insert_u64_bit(&config
, compiler
->precise_trig
);
194 if (compiler
->devinfo
->gen
>= 8 && compiler
->devinfo
->gen
< 10) {
195 insert_u64_bit(&config
, compiler
->scalar_stage
[MESA_SHADER_VERTEX
]);
196 insert_u64_bit(&config
, compiler
->scalar_stage
[MESA_SHADER_TESS_CTRL
]);
197 insert_u64_bit(&config
, compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
]);
198 insert_u64_bit(&config
, compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
]);
200 uint64_t debug_bits
= INTEL_DEBUG
;
201 uint64_t mask
= DEBUG_DISK_CACHE_MASK
;
203 const uint64_t bit
= 1ULL << (ffsll(mask
) - 1);
204 insert_u64_bit(&config
, (debug_bits
& bit
) != 0);
211 brw_prog_data_size(gl_shader_stage stage
)
213 STATIC_ASSERT(MESA_SHADER_VERTEX
== 0);
214 STATIC_ASSERT(MESA_SHADER_TESS_CTRL
== 1);
215 STATIC_ASSERT(MESA_SHADER_TESS_EVAL
== 2);
216 STATIC_ASSERT(MESA_SHADER_GEOMETRY
== 3);
217 STATIC_ASSERT(MESA_SHADER_FRAGMENT
== 4);
218 STATIC_ASSERT(MESA_SHADER_COMPUTE
== 5);
219 static const size_t stage_sizes
[] = {
220 sizeof(struct brw_vs_prog_data
),
221 sizeof(struct brw_tcs_prog_data
),
222 sizeof(struct brw_tes_prog_data
),
223 sizeof(struct brw_gs_prog_data
),
224 sizeof(struct brw_wm_prog_data
),
225 sizeof(struct brw_cs_prog_data
),
227 assert((int)stage
>= 0 && stage
< ARRAY_SIZE(stage_sizes
));
228 return stage_sizes
[stage
];
232 brw_prog_key_size(gl_shader_stage stage
)
234 static const size_t stage_sizes
[] = {
235 sizeof(struct brw_vs_prog_key
),
236 sizeof(struct brw_tcs_prog_key
),
237 sizeof(struct brw_tes_prog_key
),
238 sizeof(struct brw_gs_prog_key
),
239 sizeof(struct brw_wm_prog_key
),
240 sizeof(struct brw_cs_prog_key
),
242 assert((int)stage
>= 0 && stage
< ARRAY_SIZE(stage_sizes
));
243 return stage_sizes
[stage
];