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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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24 #include "brw_compiler.h"
25 #include "brw_shader.h"
27 #include "dev/gen_debug.h"
28 #include "compiler/nir/nir.h"
29 #include "main/errors.h"
30 #include "util/debug.h"
32 #define COMMON_OPTIONS \
36 .lower_flrp16 = true, \
38 .lower_bitfield_extract = true, \
39 .lower_bitfield_insert = true, \
40 .lower_uadd_carry = true, \
41 .lower_usub_borrow = true, \
43 .lower_flrp64 = true, \
44 .lower_isign = true, \
45 .lower_ldexp = true, \
46 .lower_device_index_to_zero = true, \
47 .vectorize_io = true, \
48 .use_interpolated_input_intrinsics = true, \
49 .vertex_id_zero_based = true, \
50 .lower_base_vertex = true
52 #define COMMON_SCALAR_OPTIONS \
53 .lower_pack_half_2x16 = true, \
54 .lower_pack_snorm_2x16 = true, \
55 .lower_pack_snorm_4x8 = true, \
56 .lower_pack_unorm_2x16 = true, \
57 .lower_pack_unorm_4x8 = true, \
58 .lower_unpack_half_2x16 = true, \
59 .lower_unpack_snorm_2x16 = true, \
60 .lower_unpack_snorm_4x8 = true, \
61 .lower_unpack_unorm_2x16 = true, \
62 .lower_unpack_unorm_4x8 = true, \
63 .max_unroll_iterations = 32
65 static const struct nir_shader_compiler_options scalar_nir_options
= {
67 COMMON_SCALAR_OPTIONS
,
70 static const struct nir_shader_compiler_options vector_nir_options
= {
73 /* In the vec4 backend, our dpN instruction replicates its result to all the
74 * components of a vec4. We would like NIR to give us replicated fdot
75 * instructions because it can optimize better for us.
77 .fdot_replicates
= true,
79 .lower_pack_snorm_2x16
= true,
80 .lower_pack_unorm_2x16
= true,
81 .lower_unpack_snorm_2x16
= true,
82 .lower_unpack_unorm_2x16
= true,
83 .lower_extract_byte
= true,
84 .lower_extract_word
= true,
86 .max_unroll_iterations
= 32,
90 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
)
92 struct brw_compiler
*compiler
= rzalloc(mem_ctx
, struct brw_compiler
);
94 compiler
->devinfo
= devinfo
;
96 brw_fs_alloc_reg_sets(compiler
);
97 brw_vec4_alloc_reg_set(compiler
);
98 brw_init_compaction_tables(devinfo
);
100 compiler
->precise_trig
= env_var_as_boolean("INTEL_PRECISE_TRIG", false);
102 compiler
->use_tcs_8_patch
=
103 devinfo
->gen
>= 9 && (INTEL_DEBUG
& DEBUG_TCS_EIGHT_PATCH
);
105 if (devinfo
->gen
>= 10) {
106 /* We don't support vec4 mode on Cannonlake. */
107 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_STAGES
; i
++)
108 compiler
->scalar_stage
[i
] = true;
110 compiler
->scalar_stage
[MESA_SHADER_VERTEX
] =
111 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_VS", true);
112 compiler
->scalar_stage
[MESA_SHADER_TESS_CTRL
] =
113 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", true);
114 compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
] =
115 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
116 compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
] =
117 devinfo
->gen
>= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
118 compiler
->scalar_stage
[MESA_SHADER_FRAGMENT
] = true;
119 compiler
->scalar_stage
[MESA_SHADER_COMPUTE
] = true;
122 nir_lower_int64_options int64_options
=
126 nir_lower_imul_high64
;
127 nir_lower_doubles_options fp64_options
=
135 nir_lower_dround_even
|
140 if (!devinfo
->has_64bit_types
|| (INTEL_DEBUG
& DEBUG_SOFT64
)) {
141 int64_options
|= nir_lower_mov64
|
150 fp64_options
|= nir_lower_fp64_full_software
;
153 /* The Bspec's section tittled "Instruction_multiply[DevBDW+]" claims that
154 * destination type can be Quadword and source type Doubleword for Gen8 and
155 * Gen9. So, lower 64 bit multiply instruction on rest of the platforms.
157 if (devinfo
->gen
< 8 || devinfo
->gen
> 9)
158 int64_options
|= nir_lower_imul_2x32_64
;
160 /* We want the GLSL compiler to emit code that uses condition codes */
161 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
162 compiler
->glsl_compiler_options
[i
].MaxUnrollIterations
= 0;
163 compiler
->glsl_compiler_options
[i
].MaxIfDepth
=
164 devinfo
->gen
< 6 ? 16 : UINT_MAX
;
166 compiler
->glsl_compiler_options
[i
].EmitNoIndirectInput
= true;
167 compiler
->glsl_compiler_options
[i
].EmitNoIndirectUniform
= false;
169 bool is_scalar
= compiler
->scalar_stage
[i
];
171 compiler
->glsl_compiler_options
[i
].EmitNoIndirectOutput
= is_scalar
;
172 compiler
->glsl_compiler_options
[i
].EmitNoIndirectTemp
= is_scalar
;
173 compiler
->glsl_compiler_options
[i
].OptimizeForAOS
= !is_scalar
;
175 struct nir_shader_compiler_options
*nir_options
=
176 rzalloc(compiler
, struct nir_shader_compiler_options
);
178 *nir_options
= scalar_nir_options
;
180 *nir_options
= vector_nir_options
;
183 /* Prior to Gen6, there are no three source operations, and Gen11 loses
186 nir_options
->lower_ffma
= devinfo
->gen
< 6;
187 nir_options
->lower_flrp32
= devinfo
->gen
< 6 || devinfo
->gen
>= 11;
189 nir_options
->lower_rotate
= devinfo
->gen
< 11;
191 nir_options
->lower_int64_options
= int64_options
;
192 nir_options
->lower_doubles_options
= fp64_options
;
193 compiler
->glsl_compiler_options
[i
].NirOptions
= nir_options
;
195 compiler
->glsl_compiler_options
[i
].ClampBlockIndicesToArrayBounds
= true;
198 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].EmitNoIndirectInput
= false;
199 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_EVAL
].EmitNoIndirectInput
= false;
200 compiler
->glsl_compiler_options
[MESA_SHADER_TESS_CTRL
].EmitNoIndirectOutput
= false;
202 if (compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
])
203 compiler
->glsl_compiler_options
[MESA_SHADER_GEOMETRY
].EmitNoIndirectInput
= false;
209 insert_u64_bit(uint64_t *val
, bool add
)
211 *val
= (*val
<< 1) | !!add
;
215 brw_get_compiler_config_value(const struct brw_compiler
*compiler
)
218 insert_u64_bit(&config
, compiler
->precise_trig
);
219 if (compiler
->devinfo
->gen
>= 8 && compiler
->devinfo
->gen
< 10) {
220 insert_u64_bit(&config
, compiler
->scalar_stage
[MESA_SHADER_VERTEX
]);
221 insert_u64_bit(&config
, compiler
->scalar_stage
[MESA_SHADER_TESS_CTRL
]);
222 insert_u64_bit(&config
, compiler
->scalar_stage
[MESA_SHADER_TESS_EVAL
]);
223 insert_u64_bit(&config
, compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
]);
225 uint64_t debug_bits
= INTEL_DEBUG
;
226 uint64_t mask
= DEBUG_DISK_CACHE_MASK
;
228 const uint64_t bit
= 1ULL << (ffsll(mask
) - 1);
229 insert_u64_bit(&config
, (debug_bits
& bit
) != 0);
236 brw_prog_data_size(gl_shader_stage stage
)
238 STATIC_ASSERT(MESA_SHADER_VERTEX
== 0);
239 STATIC_ASSERT(MESA_SHADER_TESS_CTRL
== 1);
240 STATIC_ASSERT(MESA_SHADER_TESS_EVAL
== 2);
241 STATIC_ASSERT(MESA_SHADER_GEOMETRY
== 3);
242 STATIC_ASSERT(MESA_SHADER_FRAGMENT
== 4);
243 STATIC_ASSERT(MESA_SHADER_COMPUTE
== 5);
244 static const size_t stage_sizes
[] = {
245 sizeof(struct brw_vs_prog_data
),
246 sizeof(struct brw_tcs_prog_data
),
247 sizeof(struct brw_tes_prog_data
),
248 sizeof(struct brw_gs_prog_data
),
249 sizeof(struct brw_wm_prog_data
),
250 sizeof(struct brw_cs_prog_data
),
252 assert((int)stage
>= 0 && stage
< ARRAY_SIZE(stage_sizes
));
253 return stage_sizes
[stage
];
257 brw_prog_key_size(gl_shader_stage stage
)
259 static const size_t stage_sizes
[] = {
260 sizeof(struct brw_vs_prog_key
),
261 sizeof(struct brw_tcs_prog_key
),
262 sizeof(struct brw_tes_prog_key
),
263 sizeof(struct brw_gs_prog_key
),
264 sizeof(struct brw_wm_prog_key
),
265 sizeof(struct brw_cs_prog_key
),
267 assert((int)stage
>= 0 && stage
< ARRAY_SIZE(stage_sizes
));
268 return stage_sizes
[stage
];