src/intel/compiler/brw_compiler.c

   1 /*
   2  * Copyright © 2015-2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_compiler.h"
  25 #include "brw_shader.h"
  26 #include "brw_eu.h"
  27 #include "common/gen_debug.h"
  28 #include "compiler/nir/nir.h"
  29 #include "main/errors.h"
  30 #include "util/debug.h"
  31
  32 #define COMMON_OPTIONS                                                        \
  33    .lower_sub = true,                                                         \
  34    .lower_fdiv = true,                                                        \
  35    .lower_scmp = true,                                                        \
  36    .lower_fmod32 = true,                                                      \
  37    .lower_fmod64 = false,                                                     \
  38    .lower_bitfield_extract = true,                                            \
  39    .lower_bitfield_insert = true,                                             \
  40    .lower_uadd_carry = true,                                                  \
  41    .lower_usub_borrow = true,                                                 \
  42    .lower_fdiv = true,                                                        \
  43    .lower_flrp64 = true,                                                      \
  44    .lower_ldexp = true,                                                       \
  45    .native_integers = true,                                                   \
  46    .use_interpolated_input_intrinsics = true,                                 \
  47    .vertex_id_zero_based = true
  48
  49 #define COMMON_SCALAR_OPTIONS                                                 \
  50    .lower_pack_half_2x16 = true,                                              \
  51    .lower_pack_snorm_2x16 = true,                                             \
  52    .lower_pack_snorm_4x8 = true,                                              \
  53    .lower_pack_unorm_2x16 = true,                                             \
  54    .lower_pack_unorm_4x8 = true,                                              \
  55    .lower_unpack_half_2x16 = true,                                            \
  56    .lower_unpack_snorm_2x16 = true,                                           \
  57    .lower_unpack_snorm_4x8 = true,                                            \
  58    .lower_unpack_unorm_2x16 = true,                                           \
  59    .lower_unpack_unorm_4x8 = true,                                            \
  60    .vs_inputs_dual_locations = true,                                          \
  61    .max_unroll_iterations = 32
  62
  63 static const struct nir_shader_compiler_options scalar_nir_options = {
  64    COMMON_OPTIONS,
  65    COMMON_SCALAR_OPTIONS,
  66 };
  67
  68 static const struct nir_shader_compiler_options scalar_nir_options_gen11 = {
  69    COMMON_OPTIONS,
  70    COMMON_SCALAR_OPTIONS,
  71    .lower_flrp32 = true,
  72 };
  73
  74 static const struct nir_shader_compiler_options vector_nir_options = {
  75    COMMON_OPTIONS,
  76
  77    /* In the vec4 backend, our dpN instruction replicates its result to all the
  78     * components of a vec4.  We would like NIR to give us replicated fdot
  79     * instructions because it can optimize better for us.
  80     */
  81    .fdot_replicates = true,
  82
  83    /* Prior to Gen6, there are no three source operations for SIMD4x2. */
  84    .lower_flrp32 = true,
  85
  86    .lower_pack_snorm_2x16 = true,
  87    .lower_pack_unorm_2x16 = true,
  88    .lower_unpack_snorm_2x16 = true,
  89    .lower_unpack_unorm_2x16 = true,
  90    .lower_extract_byte = true,
  91    .lower_extract_word = true,
  92    .vs_inputs_dual_locations = true,
  93    .max_unroll_iterations = 32,
  94 };
  95
  96 static const struct nir_shader_compiler_options vector_nir_options_gen6 = {
  97    COMMON_OPTIONS,
  98
  99    /* In the vec4 backend, our dpN instruction replicates its result to all the
 100     * components of a vec4.  We would like NIR to give us replicated fdot
 101     * instructions because it can optimize better for us.
 102     */
 103    .fdot_replicates = true,
 104
 105    .lower_pack_snorm_2x16 = true,
 106    .lower_pack_unorm_2x16 = true,
 107    .lower_unpack_snorm_2x16 = true,
 108    .lower_unpack_unorm_2x16 = true,
 109    .lower_extract_byte = true,
 110    .lower_extract_word = true,
 111    .vs_inputs_dual_locations = true,
 112    .max_unroll_iterations = 32,
 113 };
 114
 115 struct brw_compiler *
 116 brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
 117 {
 118    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
 119
 120    compiler->devinfo = devinfo;
 121
 122    brw_fs_alloc_reg_sets(compiler);
 123    brw_vec4_alloc_reg_set(compiler);
 124    brw_init_compaction_tables(devinfo);
 125
 126    compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
 127
 128    if (devinfo->gen >= 10) {
 129       /* We don't support vec4 mode on Cannonlake. */
 130       for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_STAGES; i++)
 131          compiler->scalar_stage[i] = true;
 132    } else {
 133       compiler->scalar_stage[MESA_SHADER_VERTEX] =
 134          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_VS", true);
 135       compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
 136          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", true);
 137       compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
 138          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
 139       compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
 140          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
 141       compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
 142       compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
 143    }
 144
 145    /* We want the GLSL compiler to emit code that uses condition codes */
 146    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 147       compiler->glsl_compiler_options[i].MaxUnrollIterations = 0;
 148       compiler->glsl_compiler_options[i].MaxIfDepth =
 149          devinfo->gen < 6 ? 16 : UINT_MAX;
 150
 151       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 152       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 153
 154       bool is_scalar = compiler->scalar_stage[i];
 155
 156       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 157       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 158       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 159
 160       if (is_scalar) {
 161          compiler->glsl_compiler_options[i].NirOptions =
 162             devinfo->gen < 11 ? &scalar_nir_options : &scalar_nir_options_gen11;
 163       } else {
 164          compiler->glsl_compiler_options[i].NirOptions =
 165             devinfo->gen < 6 ? &vector_nir_options : &vector_nir_options_gen6;
 166       }
 167
 168       compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
 169       compiler->glsl_compiler_options[i].ClampBlockIndicesToArrayBounds = true;
 170    }
 171
 172    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false;
 173    compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
 174    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectOutput = false;
 175
 176    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 177       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 178
 179    return compiler;
 180 }
 181
 182 unsigned
 183 brw_prog_data_size(gl_shader_stage stage)
 184 {
 185    STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
 186    STATIC_ASSERT(MESA_SHADER_TESS_CTRL == 1);
 187    STATIC_ASSERT(MESA_SHADER_TESS_EVAL == 2);
 188    STATIC_ASSERT(MESA_SHADER_GEOMETRY == 3);
 189    STATIC_ASSERT(MESA_SHADER_FRAGMENT == 4);
 190    STATIC_ASSERT(MESA_SHADER_COMPUTE == 5);
 191    static const size_t stage_sizes[] = {
 192       sizeof(struct brw_vs_prog_data),
 193       sizeof(struct brw_tcs_prog_data),
 194       sizeof(struct brw_tes_prog_data),
 195       sizeof(struct brw_gs_prog_data),
 196       sizeof(struct brw_wm_prog_data),
 197       sizeof(struct brw_cs_prog_data),
 198    };
 199    assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
 200    return stage_sizes[stage];
 201 }
 202
 203 unsigned
 204 brw_prog_key_size(gl_shader_stage stage)
 205 {
 206    static const size_t stage_sizes[] = {
 207       sizeof(struct brw_vs_prog_key),
 208       sizeof(struct brw_tcs_prog_key),
 209       sizeof(struct brw_tes_prog_key),
 210       sizeof(struct brw_gs_prog_key),
 211       sizeof(struct brw_wm_prog_key),
 212       sizeof(struct brw_cs_prog_key),
 213    };
 214    assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
 215    return stage_sizes[stage];
 216 }