src/intel/compiler/brw_compiler.c

   1 /*
   2  * Copyright © 2015-2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_compiler.h"
  25 #include "brw_shader.h"
  26 #include "brw_eu.h"
  27 #include "common/gen_debug.h"
  28 #include "compiler/nir/nir.h"
  29 #include "main/errors.h"
  30 #include "util/debug.h"
  31
  32 #define COMMON_OPTIONS                                                        \
  33    .lower_sub = true,                                                         \
  34    .lower_fdiv = true,                                                        \
  35    .lower_scmp = true,                                                        \
  36    .lower_fmod32 = true,                                                      \
  37    .lower_fmod64 = false,                                                     \
  38    .lower_bitfield_extract = true,                                            \
  39    .lower_bitfield_insert = true,                                             \
  40    .lower_uadd_carry = true,                                                  \
  41    .lower_usub_borrow = true,                                                 \
  42    .lower_fdiv = true,                                                        \
  43    .lower_flrp64 = true,                                                      \
  44    .lower_ldexp = true,                                                       \
  45    .lower_device_index_to_zero = true,                                        \
  46    .native_integers = true,                                                   \
  47    .use_interpolated_input_intrinsics = true,                                 \
  48    .vertex_id_zero_based = true,                                              \
  49    .lower_base_vertex = true
  50
  51 #define COMMON_SCALAR_OPTIONS                                                 \
  52    .lower_pack_half_2x16 = true,                                              \
  53    .lower_pack_snorm_2x16 = true,                                             \
  54    .lower_pack_snorm_4x8 = true,                                              \
  55    .lower_pack_unorm_2x16 = true,                                             \
  56    .lower_pack_unorm_4x8 = true,                                              \
  57    .lower_unpack_half_2x16 = true,                                            \
  58    .lower_unpack_snorm_2x16 = true,                                           \
  59    .lower_unpack_snorm_4x8 = true,                                            \
  60    .lower_unpack_unorm_2x16 = true,                                           \
  61    .lower_unpack_unorm_4x8 = true,                                            \
  62    .max_unroll_iterations = 32
  63
  64 static const struct nir_shader_compiler_options scalar_nir_options = {
  65    COMMON_OPTIONS,
  66    COMMON_SCALAR_OPTIONS,
  67 };
  68
  69 static const struct nir_shader_compiler_options scalar_nir_options_gen11 = {
  70    COMMON_OPTIONS,
  71    COMMON_SCALAR_OPTIONS,
  72    .lower_flrp32 = true,
  73 };
  74
  75 static const struct nir_shader_compiler_options vector_nir_options = {
  76    COMMON_OPTIONS,
  77
  78    /* In the vec4 backend, our dpN instruction replicates its result to all the
  79     * components of a vec4.  We would like NIR to give us replicated fdot
  80     * instructions because it can optimize better for us.
  81     */
  82    .fdot_replicates = true,
  83
  84    /* Prior to Gen6, there are no three source operations for SIMD4x2. */
  85    .lower_flrp32 = true,
  86
  87    .lower_pack_snorm_2x16 = true,
  88    .lower_pack_unorm_2x16 = true,
  89    .lower_unpack_snorm_2x16 = true,
  90    .lower_unpack_unorm_2x16 = true,
  91    .lower_extract_byte = true,
  92    .lower_extract_word = true,
  93    .max_unroll_iterations = 32,
  94 };
  95
  96 static const struct nir_shader_compiler_options vector_nir_options_gen6 = {
  97    COMMON_OPTIONS,
  98
  99    /* In the vec4 backend, our dpN instruction replicates its result to all the
 100     * components of a vec4.  We would like NIR to give us replicated fdot
 101     * instructions because it can optimize better for us.
 102     */
 103    .fdot_replicates = true,
 104
 105    .lower_pack_snorm_2x16 = true,
 106    .lower_pack_unorm_2x16 = true,
 107    .lower_unpack_snorm_2x16 = true,
 108    .lower_unpack_unorm_2x16 = true,
 109    .lower_extract_byte = true,
 110    .lower_extract_word = true,
 111    .max_unroll_iterations = 32,
 112 };
 113
 114 struct brw_compiler *
 115 brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
 116 {
 117    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
 118
 119    compiler->devinfo = devinfo;
 120
 121    brw_fs_alloc_reg_sets(compiler);
 122    brw_vec4_alloc_reg_set(compiler);
 123    brw_init_compaction_tables(devinfo);
 124
 125    compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
 126
 127    if (devinfo->gen >= 10) {
 128       /* We don't support vec4 mode on Cannonlake. */
 129       for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_STAGES; i++)
 130          compiler->scalar_stage[i] = true;
 131    } else {
 132       compiler->scalar_stage[MESA_SHADER_VERTEX] =
 133          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_VS", true);
 134       compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
 135          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", true);
 136       compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
 137          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
 138       compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
 139          devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
 140       compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
 141       compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
 142    }
 143
 144    /* We want the GLSL compiler to emit code that uses condition codes */
 145    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 146       compiler->glsl_compiler_options[i].MaxUnrollIterations = 0;
 147       compiler->glsl_compiler_options[i].MaxIfDepth =
 148          devinfo->gen < 6 ? 16 : UINT_MAX;
 149
 150       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 151       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 152
 153       bool is_scalar = compiler->scalar_stage[i];
 154
 155       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 156       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 157       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 158
 159       if (is_scalar) {
 160          compiler->glsl_compiler_options[i].NirOptions =
 161             devinfo->gen < 11 ? &scalar_nir_options : &scalar_nir_options_gen11;
 162       } else {
 163          compiler->glsl_compiler_options[i].NirOptions =
 164             devinfo->gen < 6 ? &vector_nir_options : &vector_nir_options_gen6;
 165       }
 166
 167       compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
 168       compiler->glsl_compiler_options[i].ClampBlockIndicesToArrayBounds = true;
 169    }
 170
 171    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false;
 172    compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
 173    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectOutput = false;
 174
 175    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 176       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 177
 178    return compiler;
 179 }
 180
 181 static void
 182 insert_u64_bit(uint64_t *val, bool add)
 183 {
 184    *val = (*val << 1) | !!add;
 185 }
 186
 187 uint64_t
 188 brw_get_compiler_config_value(const struct brw_compiler *compiler)
 189 {
 190    uint64_t config = 0;
 191    insert_u64_bit(&config, compiler->precise_trig);
 192    if (compiler->devinfo->gen >= 8 && compiler->devinfo->gen < 10) {
 193       insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_VERTEX]);
 194       insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
 195       insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_TESS_EVAL]);
 196       insert_u64_bit(&config, compiler->scalar_stage[MESA_SHADER_GEOMETRY]);
 197    }
 198    uint64_t debug_bits = INTEL_DEBUG;
 199    uint64_t mask = DEBUG_DISK_CACHE_MASK;
 200    while (mask != 0) {
 201       const uint64_t bit = 1ULL << (ffsll(mask) - 1);
 202       insert_u64_bit(&config, (debug_bits & bit) != 0);
 203       mask &= ~bit;
 204    }
 205    return config;
 206 }
 207
 208 unsigned
 209 brw_prog_data_size(gl_shader_stage stage)
 210 {
 211    STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
 212    STATIC_ASSERT(MESA_SHADER_TESS_CTRL == 1);
 213    STATIC_ASSERT(MESA_SHADER_TESS_EVAL == 2);
 214    STATIC_ASSERT(MESA_SHADER_GEOMETRY == 3);
 215    STATIC_ASSERT(MESA_SHADER_FRAGMENT == 4);
 216    STATIC_ASSERT(MESA_SHADER_COMPUTE == 5);
 217    static const size_t stage_sizes[] = {
 218       sizeof(struct brw_vs_prog_data),
 219       sizeof(struct brw_tcs_prog_data),
 220       sizeof(struct brw_tes_prog_data),
 221       sizeof(struct brw_gs_prog_data),
 222       sizeof(struct brw_wm_prog_data),
 223       sizeof(struct brw_cs_prog_data),
 224    };
 225    assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
 226    return stage_sizes[stage];
 227 }
 228
 229 unsigned
 230 brw_prog_key_size(gl_shader_stage stage)
 231 {
 232    static const size_t stage_sizes[] = {
 233       sizeof(struct brw_vs_prog_key),
 234       sizeof(struct brw_tcs_prog_key),
 235       sizeof(struct brw_tes_prog_key),
 236       sizeof(struct brw_gs_prog_key),
 237       sizeof(struct brw_wm_prog_key),
 238       sizeof(struct brw_cs_prog_key),
 239    };
 240    assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
 241    return stage_sizes[stage];
 242 }