2 * Copyright © 2010 - 2015 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
28 #include "common/gen_device_info.h"
29 #include "main/mtypes.h"
30 #include "main/macros.h"
31 #include "util/ralloc.h"
42 const struct gen_device_info
*devinfo
;
48 * Array of the ra classes for the unaligned contiguous register
54 * Mapping for register-allocated objects in *regs to the first
55 * GRF for that object.
57 uint8_t *ra_reg_to_grf
;
64 * Array of the ra classes for the unaligned contiguous register
65 * block sizes used, indexed by register size.
70 * Mapping from classes to ra_reg ranges. Each of the per-size
71 * classes corresponds to a range of ra_reg nodes. This array stores
72 * those ranges in the form of first ra_reg in each class and the
73 * total number of ra_reg elements in the last array element. This
74 * way the range of the i'th class is given by:
75 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
77 int class_to_ra_reg_range
[17];
80 * Mapping for register-allocated objects in *regs to the first
81 * GRF for that object.
83 uint8_t *ra_reg_to_grf
;
86 * ra class for the aligned pairs we use for PLN, which doesn't
89 int aligned_pairs_class
;
92 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
95 bool scalar_stage
[MESA_SHADER_STAGES
];
96 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
99 * Apply workarounds for SIN and COS output range problems.
100 * This can negatively impact performance.
105 * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State
106 * Base Address? (If not, it's a normal GPU address.)
108 bool constant_buffer_0_is_relative
;
111 * Whether or not the driver supports pull constants. If not, the compiler
112 * will attempt to push everything.
114 bool supports_pull_constants
;
119 * Program key structures.
121 * When drawing, we look for the currently bound shaders in the program
122 * cache. This is essentially a hash table lookup, and these are the keys.
124 * Sometimes OpenGL features specified as state need to be simulated via
125 * shader code, due to a mismatch between the API and the hardware. This
126 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
127 * in the program key so it's considered when searching for a program. If
128 * we haven't seen a particular combination before, we have to recompile a
129 * new specialized version.
131 * Shader compilation should not look up state in gl_context directly, but
132 * instead use the copy in the program key. This guarantees recompiles will
138 enum PACKED gen6_gather_sampler_wa
{
139 WA_SIGN
= 1, /* whether we need to sign extend */
140 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
141 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
145 * Sampler information needed by VS, WM, and GS program cache keys.
147 struct brw_sampler_prog_key_data
{
149 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
151 uint16_t swizzles
[MAX_SAMPLERS
];
153 uint32_t gl_clamp_mask
[3];
156 * For RG32F, gather4's channel select is broken.
158 uint32_t gather_channel_quirk_mask
;
161 * Whether this sampler uses the compressed multisample surface layout.
163 uint32_t compressed_multisample_layout_mask
;
166 * Whether this sampler is using 16x multisampling. If so fetching from
167 * this sampler will be handled with a different instruction, ld2dms_w
173 * For Sandybridge, which shader w/a we need for gather quirks.
175 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
178 * Texture units that have a YUV image bound.
180 uint32_t y_u_v_image_mask
;
181 uint32_t y_uv_image_mask
;
182 uint32_t yx_xuxv_image_mask
;
183 uint32_t xy_uxvx_image_mask
;
187 * The VF can't natively handle certain types of attributes, such as GL_FIXED
188 * or most 10_10_10_2 types. These flags enable various VS workarounds to
189 * "fix" attributes at the beginning of shaders.
191 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
192 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
193 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
194 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
195 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
198 * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range
199 * [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user
200 * input vertex attributes. In Vulkan, we expose up to 28 user vertex input
201 * attributes that are mapped to slots also starting at VERT_ATTRIB_GENERIC0.
203 #define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX
204 #define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28)
206 /** The program key for Vertex Shaders. */
207 struct brw_vs_prog_key
{
208 unsigned program_string_id
;
211 * Per-attribute workaround flags
213 * For each attribute, a combination of BRW_ATTRIB_WA_*.
215 * For OpenGL, where we expose a maximum of 16 user input atttributes
216 * we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
217 * slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
218 * expose up to 28 user input vertex attributes that are mapped to slots
219 * starting at VERT_ATTRIB_GENERIC0, so this array needs to be large
220 * enough to hold this many slots.
222 uint8_t gl_attrib_wa_flags
[MAX2(MAX_GL_VERT_ATTRIB
, MAX_VK_VERT_ATTRIB
)];
224 bool copy_edgeflag
:1;
226 bool clamp_vertex_color
:1;
229 * How many user clipping planes are being uploaded to the vertex shader as
232 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
235 unsigned nr_userclip_plane_consts
:4;
238 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
239 * are going to be replaced with point coordinates (as a consequence of a
240 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
241 * our SF thread requires exact matching between VS outputs and FS inputs,
242 * these texture coordinates will need to be unconditionally included in
243 * the VUE, even if they aren't written by the vertex shader.
245 uint8_t point_coord_replace
;
247 struct brw_sampler_prog_key_data tex
;
250 /** The program key for Tessellation Control Shaders. */
251 struct brw_tcs_prog_key
253 unsigned program_string_id
;
255 GLenum tes_primitive_mode
;
257 unsigned input_vertices
;
259 /** A bitfield of per-patch outputs written. */
260 uint32_t patch_outputs_written
;
262 /** A bitfield of per-vertex outputs written. */
263 uint64_t outputs_written
;
265 bool quads_workaround
;
267 struct brw_sampler_prog_key_data tex
;
270 /** The program key for Tessellation Evaluation Shaders. */
271 struct brw_tes_prog_key
273 unsigned program_string_id
;
275 /** A bitfield of per-patch inputs read. */
276 uint32_t patch_inputs_read
;
278 /** A bitfield of per-vertex inputs read. */
279 uint64_t inputs_read
;
281 struct brw_sampler_prog_key_data tex
;
284 /** The program key for Geometry Shaders. */
285 struct brw_gs_prog_key
287 unsigned program_string_id
;
289 struct brw_sampler_prog_key_data tex
;
292 enum brw_sf_primitive
{
293 BRW_SF_PRIM_POINTS
= 0,
294 BRW_SF_PRIM_LINES
= 1,
295 BRW_SF_PRIM_TRIANGLES
= 2,
296 BRW_SF_PRIM_UNFILLED_TRIS
= 3,
299 struct brw_sf_prog_key
{
301 bool contains_flat_varying
;
302 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
303 uint8_t point_sprite_coord_replace
;
304 enum brw_sf_primitive primitive
:2;
305 bool do_twoside_color
:1;
306 bool frontface_ccw
:1;
307 bool do_point_sprite
:1;
308 bool do_point_coord
:1;
309 bool sprite_origin_lower_left
:1;
310 bool userclip_active
:1;
314 BRW_CLIP_MODE_NORMAL
= 0,
315 BRW_CLIP_MODE_CLIP_ALL
= 1,
316 BRW_CLIP_MODE_CLIP_NON_REJECTED
= 2,
317 BRW_CLIP_MODE_REJECT_ALL
= 3,
318 BRW_CLIP_MODE_ACCEPT_ALL
= 4,
319 BRW_CLIP_MODE_KERNEL_CLIP
= 5,
322 enum brw_clip_fill_mode
{
323 BRW_CLIP_FILL_MODE_LINE
= 0,
324 BRW_CLIP_FILL_MODE_POINT
= 1,
325 BRW_CLIP_FILL_MODE_FILL
= 2,
326 BRW_CLIP_FILL_MODE_CULL
= 3,
329 /* Note that if unfilled primitives are being emitted, we have to fix
330 * up polygon offset and flatshading at this point:
332 struct brw_clip_prog_key
{
334 bool contains_flat_varying
;
335 bool contains_noperspective_varying
;
336 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
337 unsigned primitive
:4;
338 unsigned nr_userclip
:4;
341 enum brw_clip_fill_mode fill_cw
:2; /* includes cull information */
342 enum brw_clip_fill_mode fill_ccw
:2; /* includes cull information */
347 enum brw_clip_mode clip_mode
:3;
354 /* A big lookup table is used to figure out which and how many
355 * additional regs will inserted before the main payload in the WM
356 * program execution. These mainly relate to depth and stencil
357 * processing and the early-depth-test optimization.
359 enum brw_wm_iz_bits
{
360 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
= 0x1,
361 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT
= 0x2,
362 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT
= 0x4,
363 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT
= 0x8,
364 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT
= 0x10,
365 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT
= 0x20,
366 BRW_WM_IZ_BIT_MAX
= 0x40
369 enum brw_wm_aa_enable
{
375 /** The program key for Fragment/Pixel Shaders. */
376 struct brw_wm_prog_key
{
377 /* Some collection of BRW_WM_IZ_* */
381 unsigned nr_color_regions
:5;
382 bool replicate_alpha
:1;
383 bool clamp_fragment_color
:1;
384 bool persample_interp
:1;
385 bool multisample_fbo
:1;
386 bool frag_coord_adds_sample_pos
:1;
387 enum brw_wm_aa_enable line_aa
:2;
388 bool high_quality_derivatives
:1;
389 bool force_dual_color_blend
:1;
390 bool coherent_fb_fetch
:1;
392 uint16_t drawable_height
;
393 uint64_t input_slots_valid
;
394 unsigned program_string_id
;
395 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
396 float alpha_test_ref
;
398 struct brw_sampler_prog_key_data tex
;
401 struct brw_cs_prog_key
{
402 uint32_t program_string_id
;
403 struct brw_sampler_prog_key_data tex
;
407 * Image metadata structure as laid out in the shader parameter
408 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
409 * able to use them. That's okay because the padding and any unused
410 * entries [most of them except when we're doing untyped surface
411 * access] will be removed by the uniform packing pass.
413 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
414 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
415 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
416 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
417 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
418 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
419 #define BRW_IMAGE_PARAM_SIZE 24
421 struct brw_image_param
{
422 /** Surface binding table index. */
423 uint32_t surface_idx
;
425 /** Offset applied to the X and Y surface coordinates. */
428 /** Surface X, Y and Z dimensions. */
431 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
432 * pixels, vertical slice stride in pixels.
436 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
440 * Right shift to apply for bit 6 address swizzling. Two different
441 * swizzles can be specified and will be applied one after the other. The
442 * resulting address will be:
444 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
445 * (addr >> swizzling[1])))
447 * Use \c 0xff if any of the swizzles is not required.
449 uint32_t swizzling
[2];
452 /** Max number of render targets in a shader */
453 #define BRW_MAX_DRAW_BUFFERS 8
456 * Max number of binding table entries used for stream output.
458 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
459 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
461 * On Gen6, the size of transform feedback data is limited not by the number
462 * of components but by the number of binding table entries we set aside. We
463 * use one binding table entry for a float, one entry for a vector, and one
464 * entry per matrix column. Since the only way we can communicate our
465 * transform feedback capabilities to the client is via
466 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
467 * worst case, in which all the varyings are floats, so we use up one binding
468 * table entry per component. Therefore we need to set aside at least 64
469 * binding table entries for use by transform feedback.
471 * Note: since we don't currently pack varyings, it is currently impossible
472 * for the client to actually use up all of these binding table entries--if
473 * all of their varyings were floats, they would run out of varying slots and
474 * fail to link. But that's a bug, so it seems prudent to go ahead and
475 * allocate the number of binding table entries we will need once the bug is
478 #define BRW_MAX_SOL_BINDINGS 64
481 * Binding table index for the first gen6 SOL binding.
483 #define BRW_GEN6_SOL_BINDING_START 0
486 * Stride in bytes between shader_time entries.
488 * We separate entries by a cacheline to reduce traffic between EUs writing to
491 #define BRW_SHADER_TIME_STRIDE 64
500 /* We reserve the first 2^16 values for builtins */
501 #define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0)
503 enum brw_param_builtin
{
504 BRW_PARAM_BUILTIN_ZERO
,
506 BRW_PARAM_BUILTIN_CLIP_PLANE_0_X
,
507 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y
,
508 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z
,
509 BRW_PARAM_BUILTIN_CLIP_PLANE_0_W
,
510 BRW_PARAM_BUILTIN_CLIP_PLANE_1_X
,
511 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y
,
512 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z
,
513 BRW_PARAM_BUILTIN_CLIP_PLANE_1_W
,
514 BRW_PARAM_BUILTIN_CLIP_PLANE_2_X
,
515 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y
,
516 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z
,
517 BRW_PARAM_BUILTIN_CLIP_PLANE_2_W
,
518 BRW_PARAM_BUILTIN_CLIP_PLANE_3_X
,
519 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y
,
520 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z
,
521 BRW_PARAM_BUILTIN_CLIP_PLANE_3_W
,
522 BRW_PARAM_BUILTIN_CLIP_PLANE_4_X
,
523 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y
,
524 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z
,
525 BRW_PARAM_BUILTIN_CLIP_PLANE_4_W
,
526 BRW_PARAM_BUILTIN_CLIP_PLANE_5_X
,
527 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y
,
528 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z
,
529 BRW_PARAM_BUILTIN_CLIP_PLANE_5_W
,
530 BRW_PARAM_BUILTIN_CLIP_PLANE_6_X
,
531 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y
,
532 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z
,
533 BRW_PARAM_BUILTIN_CLIP_PLANE_6_W
,
534 BRW_PARAM_BUILTIN_CLIP_PLANE_7_X
,
535 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y
,
536 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z
,
537 BRW_PARAM_BUILTIN_CLIP_PLANE_7_W
,
539 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
,
540 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
,
541 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z
,
542 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
,
543 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
,
544 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
,
546 BRW_PARAM_BUILTIN_THREAD_LOCAL_ID
,
549 #define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \
550 (BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp))
552 #define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param) \
553 ((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \
554 (param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W)
556 #define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \
557 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2)
559 #define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
560 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
562 struct brw_stage_prog_data
{
564 /** size of our binding table. */
568 * surface indices for the various groups of surfaces
570 uint32_t pull_constants_start
;
571 uint32_t texture_start
;
572 uint32_t gather_texture_start
;
576 uint32_t image_start
;
577 uint32_t shader_time_start
;
578 uint32_t plane_start
[3];
582 struct brw_ubo_range ubo_ranges
[4];
584 GLuint nr_params
; /**< number of float params/constants */
585 GLuint nr_pull_params
;
587 unsigned curb_read_length
;
588 unsigned total_scratch
;
589 unsigned total_shared
;
592 * Register where the thread expects to find input data from the URB
593 * (typically uniforms, followed by vertex or fragment attributes).
595 unsigned dispatch_grf_start_reg
;
597 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
599 /* 32-bit identifiers for all push/pull parameters. These can be anything
600 * the driver wishes them to be; the core of the back-end compiler simply
601 * re-arranges them. The one restriction is that the bottom 2^16 values
602 * are reserved for builtins defined in the brw_param_builtin enum defined
606 uint32_t *pull_param
;
609 static inline uint32_t *
610 brw_stage_prog_data_add_params(struct brw_stage_prog_data
*prog_data
,
611 unsigned nr_new_params
)
613 unsigned old_nr_params
= prog_data
->nr_params
;
614 prog_data
->nr_params
+= nr_new_params
;
615 prog_data
->param
= reralloc(ralloc_parent(prog_data
->param
),
616 prog_data
->param
, uint32_t,
617 prog_data
->nr_params
);
618 return prog_data
->param
+ old_nr_params
;
622 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
625 /* A binding table index is 8 bits and the top 3 values are reserved for
626 * special things (stateless and SLM).
628 assert(surf_index
<= 252);
630 prog_data
->binding_table
.size_bytes
=
631 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
634 enum brw_barycentric_mode
{
635 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
= 0,
636 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
= 1,
637 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
= 2,
638 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL
= 3,
639 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
= 4,
640 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE
= 5,
641 BRW_BARYCENTRIC_MODE_COUNT
= 6
643 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
644 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
645 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
646 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
648 enum brw_pixel_shader_computed_depth_mode
{
649 BRW_PSCDEPTH_OFF
= 0, /* PS does not compute depth */
650 BRW_PSCDEPTH_ON
= 1, /* PS computes depth; no guarantee about value */
651 BRW_PSCDEPTH_ON_GE
= 2, /* PS guarantees output depth >= source depth */
652 BRW_PSCDEPTH_ON_LE
= 3, /* PS guarantees output depth <= source depth */
655 /* Data about a particular attempt to compile a program. Note that
656 * there can be many of these, each in a different GL state
657 * corresponding to a different brw_wm_prog_key struct, with different
660 struct brw_wm_prog_data
{
661 struct brw_stage_prog_data base
;
663 GLuint num_varying_inputs
;
665 uint8_t reg_blocks_0
;
666 uint8_t reg_blocks_2
;
668 uint8_t dispatch_grf_start_reg_2
;
669 uint32_t prog_offset_2
;
673 * surface indices the WM-specific surfaces
675 uint32_t render_target_start
;
676 uint32_t render_target_read_start
;
680 uint8_t computed_depth_mode
;
681 bool computed_stencil
;
683 bool early_fragment_tests
;
684 bool post_depth_coverage
;
689 bool persample_dispatch
;
690 bool uses_pos_offset
;
695 bool uses_sample_mask
;
696 bool has_render_target_reads
;
697 bool has_side_effects
;
700 bool contains_flat_varying
;
701 bool contains_noperspective_varying
;
704 * Mask of which interpolation modes are required by the fragment shader.
705 * Used in hardware setup on gen6+.
707 uint32_t barycentric_interp_modes
;
710 * Mask of which FS inputs are marked flat by the shader source. This is
711 * needed for setting up 3DSTATE_SF/SBE.
713 uint32_t flat_inputs
;
715 /* Mapping of VUE slots to interpolation modes.
716 * Used by the Gen4-5 clip/sf/wm stages.
718 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
721 * Map from gl_varying_slot to the position within the FS setup data
722 * payload where the varying's attribute vertex deltas should be delivered.
723 * For varying slots that are not used by the FS, the value is -1.
725 int urb_setup
[VARYING_SLOT_MAX
];
728 struct brw_push_const_block
{
729 unsigned dwords
; /* Dword count, not reg aligned */
731 unsigned size
; /* Bytes, register aligned */
734 struct brw_cs_prog_data
{
735 struct brw_stage_prog_data base
;
737 GLuint dispatch_grf_start_reg_16
;
738 unsigned local_size
[3];
742 bool uses_num_work_groups
;
745 struct brw_push_const_block cross_thread
;
746 struct brw_push_const_block per_thread
;
747 struct brw_push_const_block total
;
752 * surface indices the CS-specific surfaces
754 uint32_t work_groups_start
;
760 * Enum representing the i965-specific vertex results that don't correspond
761 * exactly to any element of gl_varying_slot. The values of this enum are
762 * assigned such that they don't conflict with gl_varying_slot.
766 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
767 BRW_VARYING_SLOT_PAD
,
769 * Technically this is not a varying but just a placeholder that
770 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
771 * builtin variable to be compiled correctly. see compile_sf_prog() for
774 BRW_VARYING_SLOT_PNTC
,
775 BRW_VARYING_SLOT_COUNT
779 * We always program SF to start reading at an offset of 1 (2 varying slots)
780 * from the start of the vertex URB entry. This causes it to skip:
781 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
782 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
784 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
787 * Bitmask indicating which fragment shader inputs represent varyings (and
788 * hence have to be delivered to the fragment shader by the SF/SBE stage).
790 #define BRW_FS_VARYING_INPUT_MASK \
791 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
792 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
795 * Data structure recording the relationship between the gl_varying_slot enum
796 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
797 * single octaword within the VUE (128 bits).
799 * Note that each BRW register contains 256 bits (2 octawords), so when
800 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
801 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
802 * in a vertex shader), each register corresponds to a single VUE slot, since
803 * it contains data for two separate vertices.
807 * Bitfield representing all varying slots that are (a) stored in this VUE
808 * map, and (b) actually written by the shader. Does not include any of
809 * the additional varying slots defined in brw_varying_slot.
811 uint64_t slots_valid
;
814 * Is this VUE map for a separate shader pipeline?
816 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
817 * without the linker having a chance to dead code eliminate unused varyings.
819 * This means that we have to use a fixed slot layout, based on the output's
820 * location field, rather than assigning slots in a compact contiguous block.
825 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
826 * not stored in a slot (because they are not written, or because
827 * additional processing is applied before storing them in the VUE), the
830 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
833 * Map from VUE slot to gl_varying_slot value. For slots that do not
834 * directly correspond to a gl_varying_slot, the value comes from
837 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
839 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
842 * Total number of VUE slots in use
847 * Number of per-patch VUE slots. Only valid for tessellation control
848 * shader outputs and tessellation evaluation shader inputs.
850 int num_per_patch_slots
;
853 * Number of per-vertex VUE slots. Only valid for tessellation control
854 * shader outputs and tessellation evaluation shader inputs.
856 int num_per_vertex_slots
;
859 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
862 * Convert a VUE slot number into a byte offset within the VUE.
864 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
870 * Convert a vertex output (brw_varying_slot) into a byte offset within the
874 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
876 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
879 void brw_compute_vue_map(const struct gen_device_info
*devinfo
,
880 struct brw_vue_map
*vue_map
,
881 uint64_t slots_valid
,
882 bool separate_shader
);
884 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
885 uint64_t slots_valid
,
888 /* brw_interpolation_map.c */
889 void brw_setup_vue_interpolation(struct brw_vue_map
*vue_map
,
890 struct nir_shader
*nir
,
891 struct brw_wm_prog_data
*prog_data
,
892 const struct gen_device_info
*devinfo
);
894 enum shader_dispatch_mode
{
895 DISPATCH_MODE_4X1_SINGLE
= 0,
896 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
897 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
898 DISPATCH_MODE_SIMD8
= 3,
902 * @defgroup Tessellator parameter enumerations.
904 * These correspond to the hardware values in 3DSTATE_TE, and are provided
905 * as part of the tessellation evaluation shader.
909 enum brw_tess_partitioning
{
910 BRW_TESS_PARTITIONING_INTEGER
= 0,
911 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
912 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
915 enum brw_tess_output_topology
{
916 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
917 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
918 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
919 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
922 enum brw_tess_domain
{
923 BRW_TESS_DOMAIN_QUAD
= 0,
924 BRW_TESS_DOMAIN_TRI
= 1,
925 BRW_TESS_DOMAIN_ISOLINE
= 2,
929 struct brw_vue_prog_data
{
930 struct brw_stage_prog_data base
;
931 struct brw_vue_map vue_map
;
933 /** Should the hardware deliver input VUE handles for URB pull loads? */
934 bool include_vue_handles
;
936 GLuint urb_read_length
;
939 uint32_t clip_distance_mask
;
940 uint32_t cull_distance_mask
;
942 /* Used for calculating urb partitions. In the VS, this is the size of the
943 * URB entry used for both input and output to the thread. In the GS, this
944 * is the size of the URB entry used for output.
946 GLuint urb_entry_size
;
948 enum shader_dispatch_mode dispatch_mode
;
951 struct brw_vs_prog_data
{
952 struct brw_vue_prog_data base
;
954 GLbitfield64 inputs_read
;
955 GLbitfield64 double_inputs_read
;
957 unsigned nr_attributes
;
958 unsigned nr_attribute_slots
;
961 bool uses_instanceid
;
962 bool uses_basevertex
;
963 bool uses_baseinstance
;
967 struct brw_tcs_prog_data
969 struct brw_vue_prog_data base
;
971 /** Number vertices in output patch */
976 struct brw_tes_prog_data
978 struct brw_vue_prog_data base
;
980 enum brw_tess_partitioning partitioning
;
981 enum brw_tess_output_topology output_topology
;
982 enum brw_tess_domain domain
;
985 struct brw_gs_prog_data
987 struct brw_vue_prog_data base
;
989 unsigned vertices_in
;
992 * Size of an output vertex, measured in HWORDS (32 bytes).
994 unsigned output_vertex_size_hwords
;
996 unsigned output_topology
;
999 * Size of the control data (cut bits or StreamID bits), in hwords (32
1000 * bytes). 0 if there is no control data.
1002 unsigned control_data_header_size_hwords
;
1005 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
1006 * if the control data is StreamID bits, or
1007 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
1008 * Ignored if control_data_header_size is 0.
1010 unsigned control_data_format
;
1012 bool include_primitive_id
;
1015 * The number of vertices emitted, if constant - otherwise -1.
1017 int static_vertex_count
;
1022 * Gen6: Provoking vertex convention for odd-numbered triangles
1028 * Gen6: Number of varyings that are output to transform feedback.
1030 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
1033 * Gen6: Map from the index of a transform feedback binding table entry to the
1034 * gl_varying_slot that should be streamed out through that binding table
1037 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
1040 * Gen6: Map from the index of a transform feedback binding table entry to the
1041 * swizzles that should be used when streaming out data through that
1042 * binding table entry.
1044 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
1047 struct brw_sf_prog_data
{
1048 uint32_t urb_read_length
;
1051 /* Each vertex may have upto 12 attributes, 4 components each,
1052 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
1055 * Actually we use 4 for each, so call it 12 rows.
1057 unsigned urb_entry_size
;
1060 struct brw_clip_prog_data
{
1061 uint32_t curb_read_length
; /* user planes? */
1063 uint32_t urb_read_length
;
1067 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
1068 static inline struct brw_##stage##_prog_data * \
1069 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
1071 return (struct brw_##stage##_prog_data *) prog_data; \
1073 DEFINE_PROG_DATA_DOWNCAST(vue
)
1074 DEFINE_PROG_DATA_DOWNCAST(vs
)
1075 DEFINE_PROG_DATA_DOWNCAST(tcs
)
1076 DEFINE_PROG_DATA_DOWNCAST(tes
)
1077 DEFINE_PROG_DATA_DOWNCAST(gs
)
1078 DEFINE_PROG_DATA_DOWNCAST(wm
)
1079 DEFINE_PROG_DATA_DOWNCAST(cs
)
1080 DEFINE_PROG_DATA_DOWNCAST(ff_gs
)
1081 DEFINE_PROG_DATA_DOWNCAST(clip
)
1082 DEFINE_PROG_DATA_DOWNCAST(sf
)
1083 #undef DEFINE_PROG_DATA_DOWNCAST
1087 struct brw_compiler
*
1088 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
);
1091 * Compile a vertex shader.
1093 * Returns the final assembly and the program's size.
1096 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1098 const struct brw_vs_prog_key
*key
,
1099 struct brw_vs_prog_data
*prog_data
,
1100 const struct nir_shader
*shader
,
1101 bool use_legacy_snorm_formula
,
1102 int shader_time_index
,
1103 unsigned *final_assembly_size
,
1107 * Compile a tessellation control shader.
1109 * Returns the final assembly and the program's size.
1112 brw_compile_tcs(const struct brw_compiler
*compiler
,
1115 const struct brw_tcs_prog_key
*key
,
1116 struct brw_tcs_prog_data
*prog_data
,
1117 const struct nir_shader
*nir
,
1118 int shader_time_index
,
1119 unsigned *final_assembly_size
,
1123 * Compile a tessellation evaluation shader.
1125 * Returns the final assembly and the program's size.
1128 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
1130 const struct brw_tes_prog_key
*key
,
1131 const struct brw_vue_map
*input_vue_map
,
1132 struct brw_tes_prog_data
*prog_data
,
1133 const struct nir_shader
*shader
,
1134 struct gl_program
*prog
,
1135 int shader_time_index
,
1136 unsigned *final_assembly_size
,
1140 * Compile a vertex shader.
1142 * Returns the final assembly and the program's size.
1145 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
1147 const struct brw_gs_prog_key
*key
,
1148 struct brw_gs_prog_data
*prog_data
,
1149 const struct nir_shader
*shader
,
1150 struct gl_program
*prog
,
1151 int shader_time_index
,
1152 unsigned *final_assembly_size
,
1156 * Compile a strips and fans shader.
1158 * This is a fixed-function shader determined entirely by the shader key and
1161 * Returns the final assembly and the program's size.
1164 brw_compile_sf(const struct brw_compiler
*compiler
,
1166 const struct brw_sf_prog_key
*key
,
1167 struct brw_sf_prog_data
*prog_data
,
1168 struct brw_vue_map
*vue_map
,
1169 unsigned *final_assembly_size
);
1172 * Compile a clipper shader.
1174 * This is a fixed-function shader determined entirely by the shader key and
1177 * Returns the final assembly and the program's size.
1180 brw_compile_clip(const struct brw_compiler
*compiler
,
1182 const struct brw_clip_prog_key
*key
,
1183 struct brw_clip_prog_data
*prog_data
,
1184 struct brw_vue_map
*vue_map
,
1185 unsigned *final_assembly_size
);
1188 * Compile a fragment shader.
1190 * Returns the final assembly and the program's size.
1193 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
1195 const struct brw_wm_prog_key
*key
,
1196 struct brw_wm_prog_data
*prog_data
,
1197 const struct nir_shader
*shader
,
1198 struct gl_program
*prog
,
1199 int shader_time_index8
,
1200 int shader_time_index16
,
1201 bool allow_spilling
,
1202 bool use_rep_send
, struct brw_vue_map
*vue_map
,
1203 unsigned *final_assembly_size
,
1207 * Compile a compute shader.
1209 * Returns the final assembly and the program's size.
1212 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
1214 const struct brw_cs_prog_key
*key
,
1215 struct brw_cs_prog_data
*prog_data
,
1216 const struct nir_shader
*shader
,
1217 int shader_time_index
,
1218 unsigned *final_assembly_size
,
1221 static inline uint32_t
1222 encode_slm_size(unsigned gen
, uint32_t bytes
)
1224 uint32_t slm_size
= 0;
1226 /* Shared Local Memory is specified as powers of two, and encoded in
1227 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1229 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1230 * -------------------------------------------------------------------
1231 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1232 * -------------------------------------------------------------------
1233 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1235 assert(bytes
<= 64 * 1024);
1238 /* Shared Local Memory Size is specified as powers of two. */
1239 slm_size
= util_next_power_of_two(bytes
);
1242 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1243 slm_size
= ffs(MAX2(slm_size
, 1024)) - 10;
1245 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1246 slm_size
= MAX2(slm_size
, 4096) / 4096;
1254 * Return true if the given shader stage is dispatched contiguously by the
1255 * relevant fixed function starting from channel 0 of the SIMD thread, which
1256 * implies that the dispatch mask of a thread can be assumed to have the form
1257 * '2^n - 1' for some n.
1260 brw_stage_has_packed_dispatch(const struct gen_device_info
*devinfo
,
1261 gl_shader_stage stage
,
1262 const struct brw_stage_prog_data
*prog_data
)
1264 /* The code below makes assumptions about the hardware's thread dispatch
1265 * behavior that could be proven wrong in future generations -- Make sure
1266 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1267 * the NIR front-end before changing this assertion.
1269 assert(devinfo
->gen
<= 10);
1272 case MESA_SHADER_FRAGMENT
: {
1273 /* The PSD discards subspans coming in with no lit samples, which in the
1274 * per-pixel shading case implies that each subspan will either be fully
1275 * lit (due to the VMask being used to allow derivative computations),
1276 * or not dispatched at all. In per-sample dispatch mode individual
1277 * samples from the same subspan have a fixed relative location within
1278 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1279 * general and we should return false.
1281 const struct brw_wm_prog_data
*wm_prog_data
=
1282 (const struct brw_wm_prog_data
*)prog_data
;
1283 return !wm_prog_data
->persample_dispatch
;
1285 case MESA_SHADER_COMPUTE
:
1286 /* Compute shaders will be spawned with either a fully enabled dispatch
1287 * mask or with whatever bottom/right execution mask was given to the
1288 * GPGPU walker command to be used along the workgroup edges -- In both
1289 * cases the dispatch mask is required to be tightly packed for our
1290 * invocation index calculations to work.
1294 /* Most remaining fixed functions are limited to use a packed dispatch
1295 * mask due to the hardware representation of the dispatch mask as a
1296 * single counter representing the number of enabled channels.
1303 * Computes the first varying slot in the URB produced by the previous stage
1304 * that is used in the next stage. We do this by testing the varying slots in
1305 * the previous stage's vue map against the inputs read in the next stage.
1309 * - Each URB offset contains two varying slots and we can only skip a
1310 * full offset if both slots are unused, so the value we return here is always
1311 * rounded down to the closest multiple of two.
1313 * - gl_Layer and gl_ViewportIndex don't have their own varying slots, they are
1314 * part of the vue header, so if these are read we can't skip anything.
1317 brw_compute_first_urb_slot_required(uint64_t inputs_read
,
1318 const struct brw_vue_map
*prev_stage_vue_map
)
1320 if ((inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
)) == 0) {
1321 for (int i
= 0; i
< prev_stage_vue_map
->num_slots
; i
++) {
1322 int varying
= prev_stage_vue_map
->slot_to_varying
[i
];
1323 if (varying
> 0 && (inputs_read
& BITFIELD64_BIT(varying
)) != 0)
1324 return ROUND_DOWN_TO(i
, 2);
1335 #endif /* BRW_COMPILER_H */