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24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
28 #include "common/gen_device_info.h"
29 #include "main/mtypes.h"
30 #include "main/macros.h"
39 union gl_constant_value
;
42 const struct gen_device_info
*devinfo
;
48 * Array of the ra classes for the unaligned contiguous register
54 * Mapping for register-allocated objects in *regs to the first
55 * GRF for that object.
57 uint8_t *ra_reg_to_grf
;
64 * Array of the ra classes for the unaligned contiguous register
65 * block sizes used, indexed by register size.
70 * Mapping from classes to ra_reg ranges. Each of the per-size
71 * classes corresponds to a range of ra_reg nodes. This array stores
72 * those ranges in the form of first ra_reg in each class and the
73 * total number of ra_reg elements in the last array element. This
74 * way the range of the i'th class is given by:
75 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
77 int class_to_ra_reg_range
[17];
80 * Mapping for register-allocated objects in *regs to the first
81 * GRF for that object.
83 uint8_t *ra_reg_to_grf
;
86 * ra class for the aligned pairs we use for PLN, which doesn't
89 int aligned_pairs_class
;
92 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
95 bool scalar_stage
[MESA_SHADER_STAGES
];
96 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
99 * Apply workarounds for SIN and COS output range problems.
100 * This can negatively impact performance.
107 * Program key structures.
109 * When drawing, we look for the currently bound shaders in the program
110 * cache. This is essentially a hash table lookup, and these are the keys.
112 * Sometimes OpenGL features specified as state need to be simulated via
113 * shader code, due to a mismatch between the API and the hardware. This
114 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
115 * in the program key so it's considered when searching for a program. If
116 * we haven't seen a particular combination before, we have to recompile a
117 * new specialized version.
119 * Shader compilation should not look up state in gl_context directly, but
120 * instead use the copy in the program key. This guarantees recompiles will
126 enum PACKED gen6_gather_sampler_wa
{
127 WA_SIGN
= 1, /* whether we need to sign extend */
128 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
129 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
133 * Sampler information needed by VS, WM, and GS program cache keys.
135 struct brw_sampler_prog_key_data
{
137 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
139 uint16_t swizzles
[MAX_SAMPLERS
];
141 uint32_t gl_clamp_mask
[3];
144 * For RG32F, gather4's channel select is broken.
146 uint32_t gather_channel_quirk_mask
;
149 * Whether this sampler uses the compressed multisample surface layout.
151 uint32_t compressed_multisample_layout_mask
;
154 * Whether this sampler is using 16x multisampling. If so fetching from
155 * this sampler will be handled with a different instruction, ld2dms_w
161 * For Sandybridge, which shader w/a we need for gather quirks.
163 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
166 * Texture units that have a YUV image bound.
168 uint32_t y_u_v_image_mask
;
169 uint32_t y_uv_image_mask
;
170 uint32_t yx_xuxv_image_mask
;
174 * The VF can't natively handle certain types of attributes, such as GL_FIXED
175 * or most 10_10_10_2 types. These flags enable various VS workarounds to
176 * "fix" attributes at the beginning of shaders.
178 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
179 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
180 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
181 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
182 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
184 /** The program key for Vertex Shaders. */
185 struct brw_vs_prog_key
{
186 unsigned program_string_id
;
189 * Per-attribute workaround flags
191 * For each attribute, a combination of BRW_ATTRIB_WA_*.
193 uint8_t gl_attrib_wa_flags
[VERT_ATTRIB_MAX
];
195 bool copy_edgeflag
:1;
197 bool clamp_vertex_color
:1;
200 * How many user clipping planes are being uploaded to the vertex shader as
203 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
206 unsigned nr_userclip_plane_consts
:4;
209 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
210 * are going to be replaced with point coordinates (as a consequence of a
211 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
212 * our SF thread requires exact matching between VS outputs and FS inputs,
213 * these texture coordinates will need to be unconditionally included in
214 * the VUE, even if they aren't written by the vertex shader.
216 uint8_t point_coord_replace
;
218 struct brw_sampler_prog_key_data tex
;
221 /** The program key for Tessellation Control Shaders. */
222 struct brw_tcs_prog_key
224 unsigned program_string_id
;
226 GLenum tes_primitive_mode
;
228 unsigned input_vertices
;
230 /** A bitfield of per-patch outputs written. */
231 uint32_t patch_outputs_written
;
233 /** A bitfield of per-vertex outputs written. */
234 uint64_t outputs_written
;
236 bool quads_workaround
;
238 struct brw_sampler_prog_key_data tex
;
241 /** The program key for Tessellation Evaluation Shaders. */
242 struct brw_tes_prog_key
244 unsigned program_string_id
;
246 /** A bitfield of per-patch inputs read. */
247 uint32_t patch_inputs_read
;
249 /** A bitfield of per-vertex inputs read. */
250 uint64_t inputs_read
;
252 struct brw_sampler_prog_key_data tex
;
255 /** The program key for Geometry Shaders. */
256 struct brw_gs_prog_key
258 unsigned program_string_id
;
260 struct brw_sampler_prog_key_data tex
;
263 enum brw_sf_primitive
{
264 BRW_SF_PRIM_POINTS
= 0,
265 BRW_SF_PRIM_LINES
= 1,
266 BRW_SF_PRIM_TRIANGLES
= 2,
267 BRW_SF_PRIM_UNFILLED_TRIS
= 3,
270 struct brw_sf_prog_key
{
272 bool contains_flat_varying
;
273 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
274 uint8_t point_sprite_coord_replace
;
275 enum brw_sf_primitive primitive
:2;
276 bool do_twoside_color
:1;
277 bool frontface_ccw
:1;
278 bool do_point_sprite
:1;
279 bool do_point_coord
:1;
280 bool sprite_origin_lower_left
:1;
281 bool userclip_active
:1;
285 BRW_CLIP_MODE_NORMAL
= 0,
286 BRW_CLIP_MODE_CLIP_ALL
= 1,
287 BRW_CLIP_MODE_CLIP_NON_REJECTED
= 2,
288 BRW_CLIP_MODE_REJECT_ALL
= 3,
289 BRW_CLIP_MODE_ACCEPT_ALL
= 4,
290 BRW_CLIP_MODE_KERNEL_CLIP
= 5,
293 enum brw_clip_fill_mode
{
294 BRW_CLIP_FILL_MODE_LINE
= 0,
295 BRW_CLIP_FILL_MODE_POINT
= 1,
296 BRW_CLIP_FILL_MODE_FILL
= 2,
297 BRW_CLIP_FILL_MODE_CULL
= 3,
300 /* Note that if unfilled primitives are being emitted, we have to fix
301 * up polygon offset and flatshading at this point:
303 struct brw_clip_prog_key
{
305 bool contains_flat_varying
;
306 bool contains_noperspective_varying
;
307 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
308 unsigned primitive
:4;
309 unsigned nr_userclip
:4;
312 enum brw_clip_fill_mode fill_cw
:2; /* includes cull information */
313 enum brw_clip_fill_mode fill_ccw
:2; /* includes cull information */
318 enum brw_clip_mode clip_mode
:3;
325 /* A big lookup table is used to figure out which and how many
326 * additional regs will inserted before the main payload in the WM
327 * program execution. These mainly relate to depth and stencil
328 * processing and the early-depth-test optimization.
330 enum brw_wm_iz_bits
{
331 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
= 0x1,
332 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT
= 0x2,
333 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT
= 0x4,
334 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT
= 0x8,
335 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT
= 0x10,
336 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT
= 0x20,
337 BRW_WM_IZ_BIT_MAX
= 0x40
340 enum brw_wm_aa_enable
{
346 /** The program key for Fragment/Pixel Shaders. */
347 struct brw_wm_prog_key
{
348 /* Some collection of BRW_WM_IZ_* */
352 unsigned nr_color_regions
:5;
353 bool replicate_alpha
:1;
354 bool clamp_fragment_color
:1;
355 bool persample_interp
:1;
356 bool multisample_fbo
:1;
357 bool frag_coord_adds_sample_pos
:1;
358 enum brw_wm_aa_enable line_aa
:2;
359 bool high_quality_derivatives
:1;
360 bool force_dual_color_blend
:1;
361 bool coherent_fb_fetch
:1;
363 uint16_t drawable_height
;
364 uint64_t input_slots_valid
;
365 unsigned program_string_id
;
366 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
367 float alpha_test_ref
;
369 struct brw_sampler_prog_key_data tex
;
372 struct brw_cs_prog_key
{
373 uint32_t program_string_id
;
374 struct brw_sampler_prog_key_data tex
;
378 * Image metadata structure as laid out in the shader parameter
379 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
380 * able to use them. That's okay because the padding and any unused
381 * entries [most of them except when we're doing untyped surface
382 * access] will be removed by the uniform packing pass.
384 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
385 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
386 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
387 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
388 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
389 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
390 #define BRW_IMAGE_PARAM_SIZE 24
392 struct brw_image_param
{
393 /** Surface binding table index. */
394 uint32_t surface_idx
;
396 /** Offset applied to the X and Y surface coordinates. */
399 /** Surface X, Y and Z dimensions. */
402 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
403 * pixels, vertical slice stride in pixels.
407 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
411 * Right shift to apply for bit 6 address swizzling. Two different
412 * swizzles can be specified and will be applied one after the other. The
413 * resulting address will be:
415 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
416 * (addr >> swizzling[1])))
418 * Use \c 0xff if any of the swizzles is not required.
420 uint32_t swizzling
[2];
423 /** Max number of render targets in a shader */
424 #define BRW_MAX_DRAW_BUFFERS 8
427 * Max number of binding table entries used for stream output.
429 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
430 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
432 * On Gen6, the size of transform feedback data is limited not by the number
433 * of components but by the number of binding table entries we set aside. We
434 * use one binding table entry for a float, one entry for a vector, and one
435 * entry per matrix column. Since the only way we can communicate our
436 * transform feedback capabilities to the client is via
437 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
438 * worst case, in which all the varyings are floats, so we use up one binding
439 * table entry per component. Therefore we need to set aside at least 64
440 * binding table entries for use by transform feedback.
442 * Note: since we don't currently pack varyings, it is currently impossible
443 * for the client to actually use up all of these binding table entries--if
444 * all of their varyings were floats, they would run out of varying slots and
445 * fail to link. But that's a bug, so it seems prudent to go ahead and
446 * allocate the number of binding table entries we will need once the bug is
449 #define BRW_MAX_SOL_BINDINGS 64
452 * Binding table index for the first gen6 SOL binding.
454 #define BRW_GEN6_SOL_BINDING_START 0
457 * Stride in bytes between shader_time entries.
459 * We separate entries by a cacheline to reduce traffic between EUs writing to
462 #define BRW_SHADER_TIME_STRIDE 64
464 struct brw_stage_prog_data
{
466 /** size of our binding table. */
470 * surface indices for the various groups of surfaces
472 uint32_t pull_constants_start
;
473 uint32_t texture_start
;
474 uint32_t gather_texture_start
;
478 uint32_t image_start
;
479 uint32_t shader_time_start
;
480 uint32_t plane_start
[3];
484 GLuint nr_params
; /**< number of float params/constants */
485 GLuint nr_pull_params
;
486 unsigned nr_image_params
;
488 unsigned curb_read_length
;
489 unsigned total_scratch
;
490 unsigned total_shared
;
493 * Register where the thread expects to find input data from the URB
494 * (typically uniforms, followed by vertex or fragment attributes).
496 unsigned dispatch_grf_start_reg
;
498 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
500 /* Pointers to tracked values (only valid once
501 * _mesa_load_state_parameters has been called at runtime).
503 const union gl_constant_value
**param
;
504 const union gl_constant_value
**pull_param
;
506 /** Image metadata passed to the shader as uniforms. */
507 struct brw_image_param
*image_param
;
511 brw_mark_surface_used(struct brw_stage_prog_data
*prog_data
,
514 /* A binding table index is 8 bits and the top 3 values are reserved for
515 * special things (stateless and SLM).
517 assert(surf_index
<= 252);
519 prog_data
->binding_table
.size_bytes
=
520 MAX2(prog_data
->binding_table
.size_bytes
, (surf_index
+ 1) * 4);
523 enum brw_barycentric_mode
{
524 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
= 0,
525 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
= 1,
526 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
= 2,
527 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL
= 3,
528 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
= 4,
529 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE
= 5,
530 BRW_BARYCENTRIC_MODE_COUNT
= 6
532 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
533 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
534 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
535 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
537 enum brw_pixel_shader_computed_depth_mode
{
538 BRW_PSCDEPTH_OFF
= 0, /* PS does not compute depth */
539 BRW_PSCDEPTH_ON
= 1, /* PS computes depth; no guarantee about value */
540 BRW_PSCDEPTH_ON_GE
= 2, /* PS guarantees output depth >= source depth */
541 BRW_PSCDEPTH_ON_LE
= 3, /* PS guarantees output depth <= source depth */
544 /* Data about a particular attempt to compile a program. Note that
545 * there can be many of these, each in a different GL state
546 * corresponding to a different brw_wm_prog_key struct, with different
549 struct brw_wm_prog_data
{
550 struct brw_stage_prog_data base
;
552 GLuint num_varying_inputs
;
554 uint8_t reg_blocks_0
;
555 uint8_t reg_blocks_2
;
557 uint8_t dispatch_grf_start_reg_2
;
558 uint32_t prog_offset_2
;
562 * surface indices the WM-specific surfaces
564 uint32_t render_target_start
;
565 uint32_t render_target_read_start
;
569 uint8_t computed_depth_mode
;
570 bool computed_stencil
;
572 bool early_fragment_tests
;
573 bool post_depth_coverage
;
578 bool persample_dispatch
;
579 bool uses_pos_offset
;
584 bool uses_sample_mask
;
585 bool has_side_effects
;
588 bool contains_flat_varying
;
589 bool contains_noperspective_varying
;
592 * Mask of which interpolation modes are required by the fragment shader.
593 * Used in hardware setup on gen6+.
595 uint32_t barycentric_interp_modes
;
598 * Mask of which FS inputs are marked flat by the shader source. This is
599 * needed for setting up 3DSTATE_SF/SBE.
601 uint32_t flat_inputs
;
603 /* Mapping of VUE slots to interpolation modes.
604 * Used by the Gen4-5 clip/sf/wm stages.
606 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
609 * Map from gl_varying_slot to the position within the FS setup data
610 * payload where the varying's attribute vertex deltas should be delivered.
611 * For varying slots that are not used by the FS, the value is -1.
613 int urb_setup
[VARYING_SLOT_MAX
];
616 struct brw_push_const_block
{
617 unsigned dwords
; /* Dword count, not reg aligned */
619 unsigned size
; /* Bytes, register aligned */
622 struct brw_cs_prog_data
{
623 struct brw_stage_prog_data base
;
625 GLuint dispatch_grf_start_reg_16
;
626 unsigned local_size
[3];
630 bool uses_num_work_groups
;
631 int thread_local_id_index
;
634 struct brw_push_const_block cross_thread
;
635 struct brw_push_const_block per_thread
;
636 struct brw_push_const_block total
;
641 * surface indices the CS-specific surfaces
643 uint32_t work_groups_start
;
649 * Enum representing the i965-specific vertex results that don't correspond
650 * exactly to any element of gl_varying_slot. The values of this enum are
651 * assigned such that they don't conflict with gl_varying_slot.
655 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
656 BRW_VARYING_SLOT_PAD
,
658 * Technically this is not a varying but just a placeholder that
659 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
660 * builtin variable to be compiled correctly. see compile_sf_prog() for
663 BRW_VARYING_SLOT_PNTC
,
664 BRW_VARYING_SLOT_COUNT
668 * We always program SF to start reading at an offset of 1 (2 varying slots)
669 * from the start of the vertex URB entry. This causes it to skip:
670 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
671 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
673 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
676 * Bitmask indicating which fragment shader inputs represent varyings (and
677 * hence have to be delivered to the fragment shader by the SF/SBE stage).
679 #define BRW_FS_VARYING_INPUT_MASK \
680 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
681 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
684 * Data structure recording the relationship between the gl_varying_slot enum
685 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
686 * single octaword within the VUE (128 bits).
688 * Note that each BRW register contains 256 bits (2 octawords), so when
689 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
690 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
691 * in a vertex shader), each register corresponds to a single VUE slot, since
692 * it contains data for two separate vertices.
696 * Bitfield representing all varying slots that are (a) stored in this VUE
697 * map, and (b) actually written by the shader. Does not include any of
698 * the additional varying slots defined in brw_varying_slot.
700 uint64_t slots_valid
;
703 * Is this VUE map for a separate shader pipeline?
705 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
706 * without the linker having a chance to dead code eliminate unused varyings.
708 * This means that we have to use a fixed slot layout, based on the output's
709 * location field, rather than assigning slots in a compact contiguous block.
714 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
715 * not stored in a slot (because they are not written, or because
716 * additional processing is applied before storing them in the VUE), the
719 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
722 * Map from VUE slot to gl_varying_slot value. For slots that do not
723 * directly correspond to a gl_varying_slot, the value comes from
726 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
728 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
731 * Total number of VUE slots in use
736 * Number of per-patch VUE slots. Only valid for tessellation control
737 * shader outputs and tessellation evaluation shader inputs.
739 int num_per_patch_slots
;
742 * Number of per-vertex VUE slots. Only valid for tessellation control
743 * shader outputs and tessellation evaluation shader inputs.
745 int num_per_vertex_slots
;
748 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
751 * Convert a VUE slot number into a byte offset within the VUE.
753 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
759 * Convert a vertex output (brw_varying_slot) into a byte offset within the
763 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
765 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
768 void brw_compute_vue_map(const struct gen_device_info
*devinfo
,
769 struct brw_vue_map
*vue_map
,
770 uint64_t slots_valid
,
771 bool separate_shader
);
773 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
774 uint64_t slots_valid
,
777 /* brw_interpolation_map.c */
778 void brw_setup_vue_interpolation(struct brw_vue_map
*vue_map
,
779 struct nir_shader
*nir
,
780 struct brw_wm_prog_data
*prog_data
,
781 const struct gen_device_info
*devinfo
);
783 enum shader_dispatch_mode
{
784 DISPATCH_MODE_4X1_SINGLE
= 0,
785 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
786 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
787 DISPATCH_MODE_SIMD8
= 3,
791 * @defgroup Tessellator parameter enumerations.
793 * These correspond to the hardware values in 3DSTATE_TE, and are provided
794 * as part of the tessellation evaluation shader.
798 enum brw_tess_partitioning
{
799 BRW_TESS_PARTITIONING_INTEGER
= 0,
800 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
801 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
804 enum brw_tess_output_topology
{
805 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
806 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
807 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
808 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
811 enum brw_tess_domain
{
812 BRW_TESS_DOMAIN_QUAD
= 0,
813 BRW_TESS_DOMAIN_TRI
= 1,
814 BRW_TESS_DOMAIN_ISOLINE
= 2,
818 struct brw_vue_prog_data
{
819 struct brw_stage_prog_data base
;
820 struct brw_vue_map vue_map
;
822 /** Should the hardware deliver input VUE handles for URB pull loads? */
823 bool include_vue_handles
;
825 GLuint urb_read_length
;
828 uint32_t clip_distance_mask
;
829 uint32_t cull_distance_mask
;
831 /* Used for calculating urb partitions. In the VS, this is the size of the
832 * URB entry used for both input and output to the thread. In the GS, this
833 * is the size of the URB entry used for output.
835 GLuint urb_entry_size
;
837 enum shader_dispatch_mode dispatch_mode
;
840 struct brw_vs_prog_data
{
841 struct brw_vue_prog_data base
;
843 GLbitfield64 inputs_read
;
844 GLbitfield64 double_inputs_read
;
846 unsigned nr_attributes
;
847 unsigned nr_attribute_slots
;
850 bool uses_instanceid
;
851 bool uses_basevertex
;
852 bool uses_baseinstance
;
856 struct brw_tcs_prog_data
858 struct brw_vue_prog_data base
;
860 /** Number vertices in output patch */
865 struct brw_tes_prog_data
867 struct brw_vue_prog_data base
;
869 enum brw_tess_partitioning partitioning
;
870 enum brw_tess_output_topology output_topology
;
871 enum brw_tess_domain domain
;
874 struct brw_gs_prog_data
876 struct brw_vue_prog_data base
;
878 unsigned vertices_in
;
881 * Size of an output vertex, measured in HWORDS (32 bytes).
883 unsigned output_vertex_size_hwords
;
885 unsigned output_topology
;
888 * Size of the control data (cut bits or StreamID bits), in hwords (32
889 * bytes). 0 if there is no control data.
891 unsigned control_data_header_size_hwords
;
894 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
895 * if the control data is StreamID bits, or
896 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
897 * Ignored if control_data_header_size is 0.
899 unsigned control_data_format
;
901 bool include_primitive_id
;
904 * The number of vertices emitted, if constant - otherwise -1.
906 int static_vertex_count
;
911 * Gen6: Provoking vertex convention for odd-numbered triangles
917 * Gen6: Number of varyings that are output to transform feedback.
919 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
922 * Gen6: Map from the index of a transform feedback binding table entry to the
923 * gl_varying_slot that should be streamed out through that binding table
926 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
929 * Gen6: Map from the index of a transform feedback binding table entry to the
930 * swizzles that should be used when streaming out data through that
931 * binding table entry.
933 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
936 struct brw_sf_prog_data
{
937 uint32_t urb_read_length
;
940 /* Each vertex may have upto 12 attributes, 4 components each,
941 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
944 * Actually we use 4 for each, so call it 12 rows.
946 unsigned urb_entry_size
;
949 struct brw_clip_prog_data
{
950 uint32_t curb_read_length
; /* user planes? */
952 uint32_t urb_read_length
;
956 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
957 static inline struct brw_##stage##_prog_data * \
958 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
960 return (struct brw_##stage##_prog_data *) prog_data; \
962 DEFINE_PROG_DATA_DOWNCAST(vue
)
963 DEFINE_PROG_DATA_DOWNCAST(vs
)
964 DEFINE_PROG_DATA_DOWNCAST(tcs
)
965 DEFINE_PROG_DATA_DOWNCAST(tes
)
966 DEFINE_PROG_DATA_DOWNCAST(gs
)
967 DEFINE_PROG_DATA_DOWNCAST(wm
)
968 DEFINE_PROG_DATA_DOWNCAST(cs
)
969 DEFINE_PROG_DATA_DOWNCAST(ff_gs
)
970 DEFINE_PROG_DATA_DOWNCAST(clip
)
971 DEFINE_PROG_DATA_DOWNCAST(sf
)
972 #undef DEFINE_PROG_DATA_DOWNCAST
976 struct brw_compiler
*
977 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
);
980 * Compile a vertex shader.
982 * Returns the final assembly and the program's size.
985 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
987 const struct brw_vs_prog_key
*key
,
988 struct brw_vs_prog_data
*prog_data
,
989 const struct nir_shader
*shader
,
990 gl_clip_plane
*clip_planes
,
991 bool use_legacy_snorm_formula
,
992 int shader_time_index
,
993 unsigned *final_assembly_size
,
997 * Compile a tessellation control shader.
999 * Returns the final assembly and the program's size.
1002 brw_compile_tcs(const struct brw_compiler
*compiler
,
1005 const struct brw_tcs_prog_key
*key
,
1006 struct brw_tcs_prog_data
*prog_data
,
1007 const struct nir_shader
*nir
,
1008 int shader_time_index
,
1009 unsigned *final_assembly_size
,
1013 * Compile a tessellation evaluation shader.
1015 * Returns the final assembly and the program's size.
1018 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
1020 const struct brw_tes_prog_key
*key
,
1021 const struct brw_vue_map
*input_vue_map
,
1022 struct brw_tes_prog_data
*prog_data
,
1023 const struct nir_shader
*shader
,
1024 struct gl_program
*prog
,
1025 int shader_time_index
,
1026 unsigned *final_assembly_size
,
1030 * Compile a vertex shader.
1032 * Returns the final assembly and the program's size.
1035 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
1037 const struct brw_gs_prog_key
*key
,
1038 struct brw_gs_prog_data
*prog_data
,
1039 const struct nir_shader
*shader
,
1040 struct gl_program
*prog
,
1041 int shader_time_index
,
1042 unsigned *final_assembly_size
,
1046 * Compile a strips and fans shader.
1048 * This is a fixed-function shader determined entirely by the shader key and
1051 * Returns the final assembly and the program's size.
1054 brw_compile_sf(const struct brw_compiler
*compiler
,
1056 const struct brw_sf_prog_key
*key
,
1057 struct brw_sf_prog_data
*prog_data
,
1058 struct brw_vue_map
*vue_map
,
1059 unsigned *final_assembly_size
);
1062 * Compile a clipper shader.
1064 * This is a fixed-function shader determined entirely by the shader key and
1067 * Returns the final assembly and the program's size.
1070 brw_compile_clip(const struct brw_compiler
*compiler
,
1072 const struct brw_clip_prog_key
*key
,
1073 struct brw_clip_prog_data
*prog_data
,
1074 struct brw_vue_map
*vue_map
,
1075 unsigned *final_assembly_size
);
1078 * Compile a fragment shader.
1080 * Returns the final assembly and the program's size.
1083 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
1085 const struct brw_wm_prog_key
*key
,
1086 struct brw_wm_prog_data
*prog_data
,
1087 const struct nir_shader
*shader
,
1088 struct gl_program
*prog
,
1089 int shader_time_index8
,
1090 int shader_time_index16
,
1091 bool allow_spilling
,
1092 bool use_rep_send
, struct brw_vue_map
*vue_map
,
1093 unsigned *final_assembly_size
,
1097 * Compile a compute shader.
1099 * Returns the final assembly and the program's size.
1102 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
1104 const struct brw_cs_prog_key
*key
,
1105 struct brw_cs_prog_data
*prog_data
,
1106 const struct nir_shader
*shader
,
1107 int shader_time_index
,
1108 unsigned *final_assembly_size
,
1111 static inline uint32_t
1112 encode_slm_size(unsigned gen
, uint32_t bytes
)
1114 uint32_t slm_size
= 0;
1116 /* Shared Local Memory is specified as powers of two, and encoded in
1117 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1119 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1120 * -------------------------------------------------------------------
1121 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1122 * -------------------------------------------------------------------
1123 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1125 assert(bytes
<= 64 * 1024);
1128 /* Shared Local Memory Size is specified as powers of two. */
1129 slm_size
= util_next_power_of_two(bytes
);
1132 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1133 slm_size
= ffs(MAX2(slm_size
, 1024)) - 10;
1135 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1136 slm_size
= MAX2(slm_size
, 4096) / 4096;
1144 * Return true if the given shader stage is dispatched contiguously by the
1145 * relevant fixed function starting from channel 0 of the SIMD thread, which
1146 * implies that the dispatch mask of a thread can be assumed to have the form
1147 * '2^n - 1' for some n.
1150 brw_stage_has_packed_dispatch(const struct gen_device_info
*devinfo
,
1151 gl_shader_stage stage
,
1152 const struct brw_stage_prog_data
*prog_data
)
1154 /* The code below makes assumptions about the hardware's thread dispatch
1155 * behavior that could be proven wrong in future generations -- Make sure
1156 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1157 * the NIR front-end before changing this assertion.
1159 assert(devinfo
->gen
<= 10);
1162 case MESA_SHADER_FRAGMENT
: {
1163 /* The PSD discards subspans coming in with no lit samples, which in the
1164 * per-pixel shading case implies that each subspan will either be fully
1165 * lit (due to the VMask being used to allow derivative computations),
1166 * or not dispatched at all. In per-sample dispatch mode individual
1167 * samples from the same subspan have a fixed relative location within
1168 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1169 * general and we should return false.
1171 const struct brw_wm_prog_data
*wm_prog_data
=
1172 (const struct brw_wm_prog_data
*)prog_data
;
1173 return !wm_prog_data
->persample_dispatch
;
1175 case MESA_SHADER_COMPUTE
:
1176 /* Compute shaders will be spawned with either a fully enabled dispatch
1177 * mask or with whatever bottom/right execution mask was given to the
1178 * GPGPU walker command to be used along the workgroup edges -- In both
1179 * cases the dispatch mask is required to be tightly packed for our
1180 * invocation index calculations to work.
1184 /* Most remaining fixed functions are limited to use a packed dispatch
1185 * mask due to the hardware representation of the dispatch mask as a
1186 * single counter representing the number of enabled channels.
1196 #endif /* BRW_COMPILER_H */