2 * Copyright © 2010 - 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #ifndef BRW_COMPILER_H
25 #define BRW_COMPILER_H
28 #include "dev/gen_device_info.h"
29 #include "main/macros.h"
30 #include "main/mtypes.h"
31 #include "util/ralloc.h"
42 const struct gen_device_info
*devinfo
;
48 * Array of the ra classes for the unaligned contiguous register
54 * Mapping for register-allocated objects in *regs to the first
55 * GRF for that object.
57 uint8_t *ra_reg_to_grf
;
64 * Array of the ra classes for the unaligned contiguous register
65 * block sizes used, indexed by register size.
70 * Mapping from classes to ra_reg ranges. Each of the per-size
71 * classes corresponds to a range of ra_reg nodes. This array stores
72 * those ranges in the form of first ra_reg in each class and the
73 * total number of ra_reg elements in the last array element. This
74 * way the range of the i'th class is given by:
75 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
77 int class_to_ra_reg_range
[17];
80 * Mapping for register-allocated objects in *regs to the first
81 * GRF for that object.
83 uint8_t *ra_reg_to_grf
;
86 * ra class for the aligned pairs we use for PLN, which doesn't
89 int aligned_pairs_class
;
92 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
95 bool scalar_stage
[MESA_SHADER_STAGES
];
97 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
100 * Apply workarounds for SIN and COS output range problems.
101 * This can negatively impact performance.
106 * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State
107 * Base Address? (If not, it's a normal GPU address.)
109 bool constant_buffer_0_is_relative
;
112 * Whether or not the driver supports pull constants. If not, the compiler
113 * will attempt to push everything.
115 bool supports_pull_constants
;
118 * Whether or not the driver supports NIR shader constants. This controls
119 * whether nir_opt_large_constants will be run.
121 bool supports_shader_constants
;
125 * We use a constant subgroup size of 32. It really only needs to be a
126 * maximum and, since we do SIMD32 for compute shaders in some cases, it
127 * needs to be at least 32. SIMD8 and SIMD16 shaders will still claim a
128 * subgroup size of 32 but will act as if 16 or 24 of those channels are
131 #define BRW_SUBGROUP_SIZE 32
134 * Program key structures.
136 * When drawing, we look for the currently bound shaders in the program
137 * cache. This is essentially a hash table lookup, and these are the keys.
139 * Sometimes OpenGL features specified as state need to be simulated via
140 * shader code, due to a mismatch between the API and the hardware. This
141 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
142 * in the program key so it's considered when searching for a program. If
143 * we haven't seen a particular combination before, we have to recompile a
144 * new specialized version.
146 * Shader compilation should not look up state in gl_context directly, but
147 * instead use the copy in the program key. This guarantees recompiles will
153 enum PACKED gen6_gather_sampler_wa
{
154 WA_SIGN
= 1, /* whether we need to sign extend */
155 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
156 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
160 * Sampler information needed by VS, WM, and GS program cache keys.
162 struct brw_sampler_prog_key_data
{
164 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
166 uint16_t swizzles
[MAX_SAMPLERS
];
168 uint32_t gl_clamp_mask
[3];
171 * For RG32F, gather4's channel select is broken.
173 uint32_t gather_channel_quirk_mask
;
176 * Whether this sampler uses the compressed multisample surface layout.
178 uint32_t compressed_multisample_layout_mask
;
181 * Whether this sampler is using 16x multisampling. If so fetching from
182 * this sampler will be handled with a different instruction, ld2dms_w
188 * For Sandybridge, which shader w/a we need for gather quirks.
190 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
193 * Texture units that have a YUV image bound.
195 uint32_t y_u_v_image_mask
;
196 uint32_t y_uv_image_mask
;
197 uint32_t yx_xuxv_image_mask
;
198 uint32_t xy_uxvx_image_mask
;
199 uint32_t ayuv_image_mask
;
200 uint32_t xyuv_image_mask
;
202 /* Scale factor for each texture. */
203 float scale_factors
[32];
206 /** An enum representing what kind of input gl_SubgroupSize is. */
207 enum PACKED brw_subgroup_size_type
209 BRW_SUBGROUP_SIZE_API_CONSTANT
, /**< Vulkan behavior */
210 BRW_SUBGROUP_SIZE_UNIFORM
, /**< OpenGL behavior */
211 BRW_SUBGROUP_SIZE_VARYING
, /**< VK_EXT_subgroup_size_control */
214 struct brw_base_prog_key
{
215 unsigned program_string_id
;
217 enum brw_subgroup_size_type subgroup_size_type
;
219 struct brw_sampler_prog_key_data tex
;
223 * The VF can't natively handle certain types of attributes, such as GL_FIXED
224 * or most 10_10_10_2 types. These flags enable various VS workarounds to
225 * "fix" attributes at the beginning of shaders.
227 #define BRW_ATTRIB_WA_COMPONENT_MASK 7 /* mask for GL_FIXED scale channel count */
228 #define BRW_ATTRIB_WA_NORMALIZE 8 /* normalize in shader */
229 #define BRW_ATTRIB_WA_BGRA 16 /* swap r/b channels in shader */
230 #define BRW_ATTRIB_WA_SIGN 32 /* interpret as signed in shader */
231 #define BRW_ATTRIB_WA_SCALE 64 /* interpret as scaled in shader */
234 * OpenGL attribute slots fall in [0, VERT_ATTRIB_MAX - 1] with the range
235 * [VERT_ATTRIB_GENERIC0, VERT_ATTRIB_MAX - 1] reserved for up to 16 user
236 * input vertex attributes. In Vulkan, we expose up to 28 user vertex input
237 * attributes that are mapped to slots also starting at VERT_ATTRIB_GENERIC0.
239 #define MAX_GL_VERT_ATTRIB VERT_ATTRIB_MAX
240 #define MAX_VK_VERT_ATTRIB (VERT_ATTRIB_GENERIC0 + 28)
242 /** The program key for Vertex Shaders. */
243 struct brw_vs_prog_key
{
244 struct brw_base_prog_key base
;
247 * Per-attribute workaround flags
249 * For each attribute, a combination of BRW_ATTRIB_WA_*.
251 * For OpenGL, where we expose a maximum of 16 user input atttributes
252 * we only need up to VERT_ATTRIB_MAX slots, however, in Vulkan
253 * slots preceding VERT_ATTRIB_GENERIC0 are unused and we can
254 * expose up to 28 user input vertex attributes that are mapped to slots
255 * starting at VERT_ATTRIB_GENERIC0, so this array needs to be large
256 * enough to hold this many slots.
258 uint8_t gl_attrib_wa_flags
[MAX2(MAX_GL_VERT_ATTRIB
, MAX_VK_VERT_ATTRIB
)];
260 bool copy_edgeflag
:1;
262 bool clamp_vertex_color
:1;
265 * How many user clipping planes are being uploaded to the vertex shader as
268 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
271 unsigned nr_userclip_plane_consts
:4;
274 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
275 * are going to be replaced with point coordinates (as a consequence of a
276 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
277 * our SF thread requires exact matching between VS outputs and FS inputs,
278 * these texture coordinates will need to be unconditionally included in
279 * the VUE, even if they aren't written by the vertex shader.
281 uint8_t point_coord_replace
;
284 /** The program key for Tessellation Control Shaders. */
285 struct brw_tcs_prog_key
287 struct brw_base_prog_key base
;
289 GLenum tes_primitive_mode
;
291 unsigned input_vertices
;
293 /** A bitfield of per-patch outputs written. */
294 uint32_t patch_outputs_written
;
296 /** A bitfield of per-vertex outputs written. */
297 uint64_t outputs_written
;
299 bool quads_workaround
;
302 /** The program key for Tessellation Evaluation Shaders. */
303 struct brw_tes_prog_key
305 struct brw_base_prog_key base
;
307 /** A bitfield of per-patch inputs read. */
308 uint32_t patch_inputs_read
;
310 /** A bitfield of per-vertex inputs read. */
311 uint64_t inputs_read
;
314 /** The program key for Geometry Shaders. */
315 struct brw_gs_prog_key
317 struct brw_base_prog_key base
;
320 enum brw_sf_primitive
{
321 BRW_SF_PRIM_POINTS
= 0,
322 BRW_SF_PRIM_LINES
= 1,
323 BRW_SF_PRIM_TRIANGLES
= 2,
324 BRW_SF_PRIM_UNFILLED_TRIS
= 3,
327 struct brw_sf_prog_key
{
329 bool contains_flat_varying
;
330 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
331 uint8_t point_sprite_coord_replace
;
332 enum brw_sf_primitive primitive
:2;
333 bool do_twoside_color
:1;
334 bool frontface_ccw
:1;
335 bool do_point_sprite
:1;
336 bool do_point_coord
:1;
337 bool sprite_origin_lower_left
:1;
338 bool userclip_active
:1;
342 BRW_CLIP_MODE_NORMAL
= 0,
343 BRW_CLIP_MODE_CLIP_ALL
= 1,
344 BRW_CLIP_MODE_CLIP_NON_REJECTED
= 2,
345 BRW_CLIP_MODE_REJECT_ALL
= 3,
346 BRW_CLIP_MODE_ACCEPT_ALL
= 4,
347 BRW_CLIP_MODE_KERNEL_CLIP
= 5,
350 enum brw_clip_fill_mode
{
351 BRW_CLIP_FILL_MODE_LINE
= 0,
352 BRW_CLIP_FILL_MODE_POINT
= 1,
353 BRW_CLIP_FILL_MODE_FILL
= 2,
354 BRW_CLIP_FILL_MODE_CULL
= 3,
357 /* Note that if unfilled primitives are being emitted, we have to fix
358 * up polygon offset and flatshading at this point:
360 struct brw_clip_prog_key
{
362 bool contains_flat_varying
;
363 bool contains_noperspective_varying
;
364 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
365 unsigned primitive
:4;
366 unsigned nr_userclip
:4;
369 enum brw_clip_fill_mode fill_cw
:2; /* includes cull information */
370 enum brw_clip_fill_mode fill_ccw
:2; /* includes cull information */
375 enum brw_clip_mode clip_mode
:3;
382 /* A big lookup table is used to figure out which and how many
383 * additional regs will inserted before the main payload in the WM
384 * program execution. These mainly relate to depth and stencil
385 * processing and the early-depth-test optimization.
387 enum brw_wm_iz_bits
{
388 BRW_WM_IZ_PS_KILL_ALPHATEST_BIT
= 0x1,
389 BRW_WM_IZ_PS_COMPUTES_DEPTH_BIT
= 0x2,
390 BRW_WM_IZ_DEPTH_WRITE_ENABLE_BIT
= 0x4,
391 BRW_WM_IZ_DEPTH_TEST_ENABLE_BIT
= 0x8,
392 BRW_WM_IZ_STENCIL_WRITE_ENABLE_BIT
= 0x10,
393 BRW_WM_IZ_STENCIL_TEST_ENABLE_BIT
= 0x20,
394 BRW_WM_IZ_BIT_MAX
= 0x40
397 enum brw_wm_aa_enable
{
403 /** The program key for Fragment/Pixel Shaders. */
404 struct brw_wm_prog_key
{
405 struct brw_base_prog_key base
;
407 /* Some collection of BRW_WM_IZ_* */
411 unsigned nr_color_regions
:5;
412 bool alpha_test_replicate_alpha
:1;
413 bool alpha_to_coverage
:1;
414 bool clamp_fragment_color
:1;
415 bool persample_interp
:1;
416 bool multisample_fbo
:1;
417 bool frag_coord_adds_sample_pos
:1;
418 enum brw_wm_aa_enable line_aa
:2;
419 bool high_quality_derivatives
:1;
420 bool force_dual_color_blend
:1;
421 bool coherent_fb_fetch
:1;
423 uint8_t color_outputs_valid
;
424 uint64_t input_slots_valid
;
425 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
426 float alpha_test_ref
;
429 struct brw_cs_prog_key
{
430 struct brw_base_prog_key base
;
433 /* brw_any_prog_key is any of the keys that map to an API stage */
434 union brw_any_prog_key
{
435 struct brw_base_prog_key base
;
436 struct brw_vs_prog_key vs
;
437 struct brw_tcs_prog_key tcs
;
438 struct brw_tes_prog_key tes
;
439 struct brw_gs_prog_key gs
;
440 struct brw_wm_prog_key wm
;
441 struct brw_cs_prog_key cs
;
445 * Image metadata structure as laid out in the shader parameter
446 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
447 * able to use them. That's okay because the padding and any unused
448 * entries [most of them except when we're doing untyped surface
449 * access] will be removed by the uniform packing pass.
451 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 0
452 #define BRW_IMAGE_PARAM_SIZE_OFFSET 4
453 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 8
454 #define BRW_IMAGE_PARAM_TILING_OFFSET 12
455 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 16
456 #define BRW_IMAGE_PARAM_SIZE 20
458 struct brw_image_param
{
459 /** Offset applied to the X and Y surface coordinates. */
462 /** Surface X, Y and Z dimensions. */
465 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
466 * pixels, vertical slice stride in pixels.
470 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
474 * Right shift to apply for bit 6 address swizzling. Two different
475 * swizzles can be specified and will be applied one after the other. The
476 * resulting address will be:
478 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
479 * (addr >> swizzling[1])))
481 * Use \c 0xff if any of the swizzles is not required.
483 uint32_t swizzling
[2];
486 /** Max number of render targets in a shader */
487 #define BRW_MAX_DRAW_BUFFERS 8
490 * Max number of binding table entries used for stream output.
492 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
493 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
495 * On Gen6, the size of transform feedback data is limited not by the number
496 * of components but by the number of binding table entries we set aside. We
497 * use one binding table entry for a float, one entry for a vector, and one
498 * entry per matrix column. Since the only way we can communicate our
499 * transform feedback capabilities to the client is via
500 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
501 * worst case, in which all the varyings are floats, so we use up one binding
502 * table entry per component. Therefore we need to set aside at least 64
503 * binding table entries for use by transform feedback.
505 * Note: since we don't currently pack varyings, it is currently impossible
506 * for the client to actually use up all of these binding table entries--if
507 * all of their varyings were floats, they would run out of varying slots and
508 * fail to link. But that's a bug, so it seems prudent to go ahead and
509 * allocate the number of binding table entries we will need once the bug is
512 #define BRW_MAX_SOL_BINDINGS 64
515 * Binding table index for the first gen6 SOL binding.
517 #define BRW_GEN6_SOL_BINDING_START 0
520 * Stride in bytes between shader_time entries.
522 * We separate entries by a cacheline to reduce traffic between EUs writing to
525 #define BRW_SHADER_TIME_STRIDE 64
534 /* We reserve the first 2^16 values for builtins */
535 #define BRW_PARAM_IS_BUILTIN(param) (((param) & 0xffff0000) == 0)
537 enum brw_param_builtin
{
538 BRW_PARAM_BUILTIN_ZERO
,
540 BRW_PARAM_BUILTIN_CLIP_PLANE_0_X
,
541 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Y
,
542 BRW_PARAM_BUILTIN_CLIP_PLANE_0_Z
,
543 BRW_PARAM_BUILTIN_CLIP_PLANE_0_W
,
544 BRW_PARAM_BUILTIN_CLIP_PLANE_1_X
,
545 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Y
,
546 BRW_PARAM_BUILTIN_CLIP_PLANE_1_Z
,
547 BRW_PARAM_BUILTIN_CLIP_PLANE_1_W
,
548 BRW_PARAM_BUILTIN_CLIP_PLANE_2_X
,
549 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Y
,
550 BRW_PARAM_BUILTIN_CLIP_PLANE_2_Z
,
551 BRW_PARAM_BUILTIN_CLIP_PLANE_2_W
,
552 BRW_PARAM_BUILTIN_CLIP_PLANE_3_X
,
553 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Y
,
554 BRW_PARAM_BUILTIN_CLIP_PLANE_3_Z
,
555 BRW_PARAM_BUILTIN_CLIP_PLANE_3_W
,
556 BRW_PARAM_BUILTIN_CLIP_PLANE_4_X
,
557 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Y
,
558 BRW_PARAM_BUILTIN_CLIP_PLANE_4_Z
,
559 BRW_PARAM_BUILTIN_CLIP_PLANE_4_W
,
560 BRW_PARAM_BUILTIN_CLIP_PLANE_5_X
,
561 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Y
,
562 BRW_PARAM_BUILTIN_CLIP_PLANE_5_Z
,
563 BRW_PARAM_BUILTIN_CLIP_PLANE_5_W
,
564 BRW_PARAM_BUILTIN_CLIP_PLANE_6_X
,
565 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Y
,
566 BRW_PARAM_BUILTIN_CLIP_PLANE_6_Z
,
567 BRW_PARAM_BUILTIN_CLIP_PLANE_6_W
,
568 BRW_PARAM_BUILTIN_CLIP_PLANE_7_X
,
569 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Y
,
570 BRW_PARAM_BUILTIN_CLIP_PLANE_7_Z
,
571 BRW_PARAM_BUILTIN_CLIP_PLANE_7_W
,
573 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X
,
574 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y
,
575 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Z
,
576 BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W
,
577 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X
,
578 BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y
,
580 BRW_PARAM_BUILTIN_PATCH_VERTICES_IN
,
582 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X
,
583 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y
,
584 BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z
,
585 BRW_PARAM_BUILTIN_SUBGROUP_ID
,
588 #define BRW_PARAM_BUILTIN_CLIP_PLANE(idx, comp) \
589 (BRW_PARAM_BUILTIN_CLIP_PLANE_0_X + ((idx) << 2) + (comp))
591 #define BRW_PARAM_BUILTIN_IS_CLIP_PLANE(param) \
592 ((param) >= BRW_PARAM_BUILTIN_CLIP_PLANE_0_X && \
593 (param) <= BRW_PARAM_BUILTIN_CLIP_PLANE_7_W)
595 #define BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(param) \
596 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) >> 2)
598 #define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
599 (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
601 struct brw_stage_prog_data
{
603 /** size of our binding table. */
607 * surface indices for the various groups of surfaces
609 uint32_t pull_constants_start
;
610 uint32_t texture_start
;
611 uint32_t gather_texture_start
;
614 uint32_t image_start
;
615 uint32_t shader_time_start
;
616 uint32_t plane_start
[3];
620 struct brw_ubo_range ubo_ranges
[4];
622 GLuint nr_params
; /**< number of float params/constants */
623 GLuint nr_pull_params
;
625 unsigned curb_read_length
;
626 unsigned total_scratch
;
627 unsigned total_shared
;
629 unsigned program_size
;
632 * Register where the thread expects to find input data from the URB
633 * (typically uniforms, followed by vertex or fragment attributes).
635 unsigned dispatch_grf_start_reg
;
637 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
639 /* 32-bit identifiers for all push/pull parameters. These can be anything
640 * the driver wishes them to be; the core of the back-end compiler simply
641 * re-arranges them. The one restriction is that the bottom 2^16 values
642 * are reserved for builtins defined in the brw_param_builtin enum defined
646 uint32_t *pull_param
;
649 static inline uint32_t *
650 brw_stage_prog_data_add_params(struct brw_stage_prog_data
*prog_data
,
651 unsigned nr_new_params
)
653 unsigned old_nr_params
= prog_data
->nr_params
;
654 prog_data
->nr_params
+= nr_new_params
;
655 prog_data
->param
= reralloc(ralloc_parent(prog_data
->param
),
656 prog_data
->param
, uint32_t,
657 prog_data
->nr_params
);
658 return prog_data
->param
+ old_nr_params
;
661 enum brw_barycentric_mode
{
662 BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
= 0,
663 BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
= 1,
664 BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
= 2,
665 BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL
= 3,
666 BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
= 4,
667 BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE
= 5,
668 BRW_BARYCENTRIC_MODE_COUNT
= 6
670 #define BRW_BARYCENTRIC_NONPERSPECTIVE_BITS \
671 ((1 << BRW_BARYCENTRIC_NONPERSPECTIVE_PIXEL) | \
672 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID) | \
673 (1 << BRW_BARYCENTRIC_NONPERSPECTIVE_SAMPLE))
675 enum brw_pixel_shader_computed_depth_mode
{
676 BRW_PSCDEPTH_OFF
= 0, /* PS does not compute depth */
677 BRW_PSCDEPTH_ON
= 1, /* PS computes depth; no guarantee about value */
678 BRW_PSCDEPTH_ON_GE
= 2, /* PS guarantees output depth >= source depth */
679 BRW_PSCDEPTH_ON_LE
= 3, /* PS guarantees output depth <= source depth */
682 /* Data about a particular attempt to compile a program. Note that
683 * there can be many of these, each in a different GL state
684 * corresponding to a different brw_wm_prog_key struct, with different
687 struct brw_wm_prog_data
{
688 struct brw_stage_prog_data base
;
690 GLuint num_varying_inputs
;
692 uint8_t reg_blocks_8
;
693 uint8_t reg_blocks_16
;
694 uint8_t reg_blocks_32
;
696 uint8_t dispatch_grf_start_reg_16
;
697 uint8_t dispatch_grf_start_reg_32
;
698 uint32_t prog_offset_16
;
699 uint32_t prog_offset_32
;
703 * surface indices the WM-specific surfaces
705 uint32_t render_target_read_start
;
709 uint8_t computed_depth_mode
;
710 bool computed_stencil
;
712 bool early_fragment_tests
;
713 bool post_depth_coverage
;
719 bool replicate_alpha
;
720 bool persample_dispatch
;
721 bool uses_pos_offset
;
726 bool uses_sample_mask
;
727 bool has_render_target_reads
;
728 bool has_side_effects
;
731 bool contains_flat_varying
;
732 bool contains_noperspective_varying
;
735 * Mask of which interpolation modes are required by the fragment shader.
736 * Used in hardware setup on gen6+.
738 uint32_t barycentric_interp_modes
;
741 * Mask of which FS inputs are marked flat by the shader source. This is
742 * needed for setting up 3DSTATE_SF/SBE.
744 uint32_t flat_inputs
;
746 /* Mapping of VUE slots to interpolation modes.
747 * Used by the Gen4-5 clip/sf/wm stages.
749 unsigned char interp_mode
[65]; /* BRW_VARYING_SLOT_COUNT */
752 * Map from gl_varying_slot to the position within the FS setup data
753 * payload where the varying's attribute vertex deltas should be delivered.
754 * For varying slots that are not used by the FS, the value is -1.
756 int urb_setup
[VARYING_SLOT_MAX
];
759 /** Returns the SIMD width corresponding to a given KSP index
761 * The "Variable Pixel Dispatch" table in the PRM (which can be found, for
762 * example in Vol. 7 of the SKL PRM) has a mapping from dispatch widths to
763 * kernel start pointer (KSP) indices that is based on what dispatch widths
764 * are enabled. This function provides, effectively, the reverse mapping.
766 * If the given KSP is valid with respect to the SIMD8/16/32 enables, a SIMD
767 * width of 8, 16, or 32 is returned. If the KSP is invalid, 0 is returned.
769 static inline unsigned
770 brw_fs_simd_width_for_ksp(unsigned ksp_idx
, bool simd8_enabled
,
771 bool simd16_enabled
, bool simd32_enabled
)
773 /* This function strictly ignores contiguous dispatch */
776 return simd8_enabled
? 8 :
777 (simd16_enabled
&& !simd32_enabled
) ? 16 :
778 (simd32_enabled
&& !simd16_enabled
) ? 32 : 0;
780 return (simd32_enabled
&& (simd16_enabled
|| simd8_enabled
)) ? 32 : 0;
782 return (simd16_enabled
&& (simd32_enabled
|| simd8_enabled
)) ? 16 : 0;
784 unreachable("Invalid KSP index");
788 #define brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx) \
789 brw_fs_simd_width_for_ksp((ksp_idx), (wm_state)._8PixelDispatchEnable, \
790 (wm_state)._16PixelDispatchEnable, \
791 (wm_state)._32PixelDispatchEnable)
793 #define brw_wm_state_has_ksp(wm_state, ksp_idx) \
794 (brw_wm_state_simd_width_for_ksp((wm_state), (ksp_idx)) != 0)
796 static inline uint32_t
797 _brw_wm_prog_data_prog_offset(const struct brw_wm_prog_data
*prog_data
,
800 switch (simd_width
) {
802 case 16: return prog_data
->prog_offset_16
;
803 case 32: return prog_data
->prog_offset_32
;
808 #define brw_wm_prog_data_prog_offset(prog_data, wm_state, ksp_idx) \
809 _brw_wm_prog_data_prog_offset(prog_data, \
810 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
812 static inline uint8_t
813 _brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data
*prog_data
,
816 switch (simd_width
) {
817 case 8: return prog_data
->base
.dispatch_grf_start_reg
;
818 case 16: return prog_data
->dispatch_grf_start_reg_16
;
819 case 32: return prog_data
->dispatch_grf_start_reg_32
;
824 #define brw_wm_prog_data_dispatch_grf_start_reg(prog_data, wm_state, ksp_idx) \
825 _brw_wm_prog_data_dispatch_grf_start_reg(prog_data, \
826 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
828 static inline uint8_t
829 _brw_wm_prog_data_reg_blocks(const struct brw_wm_prog_data
*prog_data
,
832 switch (simd_width
) {
833 case 8: return prog_data
->reg_blocks_8
;
834 case 16: return prog_data
->reg_blocks_16
;
835 case 32: return prog_data
->reg_blocks_32
;
840 #define brw_wm_prog_data_reg_blocks(prog_data, wm_state, ksp_idx) \
841 _brw_wm_prog_data_reg_blocks(prog_data, \
842 brw_wm_state_simd_width_for_ksp(wm_state, ksp_idx))
844 struct brw_push_const_block
{
845 unsigned dwords
; /* Dword count, not reg aligned */
847 unsigned size
; /* Bytes, register aligned */
850 struct brw_cs_prog_data
{
851 struct brw_stage_prog_data base
;
853 unsigned local_size
[3];
857 bool uses_num_work_groups
;
860 struct brw_push_const_block cross_thread
;
861 struct brw_push_const_block per_thread
;
862 struct brw_push_const_block total
;
867 * surface indices the CS-specific surfaces
869 uint32_t work_groups_start
;
875 * Enum representing the i965-specific vertex results that don't correspond
876 * exactly to any element of gl_varying_slot. The values of this enum are
877 * assigned such that they don't conflict with gl_varying_slot.
881 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
882 BRW_VARYING_SLOT_PAD
,
884 * Technically this is not a varying but just a placeholder that
885 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
886 * builtin variable to be compiled correctly. see compile_sf_prog() for
889 BRW_VARYING_SLOT_PNTC
,
890 BRW_VARYING_SLOT_COUNT
894 * We always program SF to start reading at an offset of 1 (2 varying slots)
895 * from the start of the vertex URB entry. This causes it to skip:
896 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
897 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
899 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
902 * Bitmask indicating which fragment shader inputs represent varyings (and
903 * hence have to be delivered to the fragment shader by the SF/SBE stage).
905 #define BRW_FS_VARYING_INPUT_MASK \
906 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
907 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
910 * Data structure recording the relationship between the gl_varying_slot enum
911 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
912 * single octaword within the VUE (128 bits).
914 * Note that each BRW register contains 256 bits (2 octawords), so when
915 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
916 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
917 * in a vertex shader), each register corresponds to a single VUE slot, since
918 * it contains data for two separate vertices.
922 * Bitfield representing all varying slots that are (a) stored in this VUE
923 * map, and (b) actually written by the shader. Does not include any of
924 * the additional varying slots defined in brw_varying_slot.
926 uint64_t slots_valid
;
929 * Is this VUE map for a separate shader pipeline?
931 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
932 * without the linker having a chance to dead code eliminate unused varyings.
934 * This means that we have to use a fixed slot layout, based on the output's
935 * location field, rather than assigning slots in a compact contiguous block.
940 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
941 * not stored in a slot (because they are not written, or because
942 * additional processing is applied before storing them in the VUE), the
945 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
948 * Map from VUE slot to gl_varying_slot value. For slots that do not
949 * directly correspond to a gl_varying_slot, the value comes from
952 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
954 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
957 * Total number of VUE slots in use
962 * Number of per-patch VUE slots. Only valid for tessellation control
963 * shader outputs and tessellation evaluation shader inputs.
965 int num_per_patch_slots
;
968 * Number of per-vertex VUE slots. Only valid for tessellation control
969 * shader outputs and tessellation evaluation shader inputs.
971 int num_per_vertex_slots
;
974 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
977 * Convert a VUE slot number into a byte offset within the VUE.
979 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
985 * Convert a vertex output (brw_varying_slot) into a byte offset within the
989 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
991 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
994 void brw_compute_vue_map(const struct gen_device_info
*devinfo
,
995 struct brw_vue_map
*vue_map
,
996 uint64_t slots_valid
,
997 bool separate_shader
);
999 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
1000 uint64_t slots_valid
,
1003 /* brw_interpolation_map.c */
1004 void brw_setup_vue_interpolation(struct brw_vue_map
*vue_map
,
1005 struct nir_shader
*nir
,
1006 struct brw_wm_prog_data
*prog_data
);
1008 enum shader_dispatch_mode
{
1009 DISPATCH_MODE_4X1_SINGLE
= 0,
1010 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
1011 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
1012 DISPATCH_MODE_SIMD8
= 3,
1014 DISPATCH_MODE_TCS_SINGLE_PATCH
= 0,
1015 DISPATCH_MODE_TCS_8_PATCH
= 2,
1019 * @defgroup Tessellator parameter enumerations.
1021 * These correspond to the hardware values in 3DSTATE_TE, and are provided
1022 * as part of the tessellation evaluation shader.
1026 enum brw_tess_partitioning
{
1027 BRW_TESS_PARTITIONING_INTEGER
= 0,
1028 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
1029 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
1032 enum brw_tess_output_topology
{
1033 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
1034 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
1035 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
1036 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
1039 enum brw_tess_domain
{
1040 BRW_TESS_DOMAIN_QUAD
= 0,
1041 BRW_TESS_DOMAIN_TRI
= 1,
1042 BRW_TESS_DOMAIN_ISOLINE
= 2,
1046 struct brw_vue_prog_data
{
1047 struct brw_stage_prog_data base
;
1048 struct brw_vue_map vue_map
;
1050 /** Should the hardware deliver input VUE handles for URB pull loads? */
1051 bool include_vue_handles
;
1053 GLuint urb_read_length
;
1056 uint32_t clip_distance_mask
;
1057 uint32_t cull_distance_mask
;
1059 /* Used for calculating urb partitions. In the VS, this is the size of the
1060 * URB entry used for both input and output to the thread. In the GS, this
1061 * is the size of the URB entry used for output.
1063 GLuint urb_entry_size
;
1065 enum shader_dispatch_mode dispatch_mode
;
1068 struct brw_vs_prog_data
{
1069 struct brw_vue_prog_data base
;
1071 GLbitfield64 inputs_read
;
1072 GLbitfield64 double_inputs_read
;
1074 unsigned nr_attribute_slots
;
1077 bool uses_instanceid
;
1078 bool uses_is_indexed_draw
;
1079 bool uses_firstvertex
;
1080 bool uses_baseinstance
;
1084 struct brw_tcs_prog_data
1086 struct brw_vue_prog_data base
;
1088 /** Should the non-SINGLE_PATCH payload provide primitive ID? */
1089 bool include_primitive_id
;
1091 /** Number vertices in output patch */
1096 struct brw_tes_prog_data
1098 struct brw_vue_prog_data base
;
1100 enum brw_tess_partitioning partitioning
;
1101 enum brw_tess_output_topology output_topology
;
1102 enum brw_tess_domain domain
;
1105 struct brw_gs_prog_data
1107 struct brw_vue_prog_data base
;
1109 unsigned vertices_in
;
1112 * Size of an output vertex, measured in HWORDS (32 bytes).
1114 unsigned output_vertex_size_hwords
;
1116 unsigned output_topology
;
1119 * Size of the control data (cut bits or StreamID bits), in hwords (32
1120 * bytes). 0 if there is no control data.
1122 unsigned control_data_header_size_hwords
;
1125 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
1126 * if the control data is StreamID bits, or
1127 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
1128 * Ignored if control_data_header_size is 0.
1130 unsigned control_data_format
;
1132 bool include_primitive_id
;
1135 * The number of vertices emitted, if constant - otherwise -1.
1137 int static_vertex_count
;
1142 * Gen6: Provoking vertex convention for odd-numbered triangles
1148 * Gen6: Number of varyings that are output to transform feedback.
1150 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
1153 * Gen6: Map from the index of a transform feedback binding table entry to the
1154 * gl_varying_slot that should be streamed out through that binding table
1157 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
1160 * Gen6: Map from the index of a transform feedback binding table entry to the
1161 * swizzles that should be used when streaming out data through that
1162 * binding table entry.
1164 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
1167 struct brw_sf_prog_data
{
1168 uint32_t urb_read_length
;
1171 /* Each vertex may have upto 12 attributes, 4 components each,
1172 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
1175 * Actually we use 4 for each, so call it 12 rows.
1177 unsigned urb_entry_size
;
1180 struct brw_clip_prog_data
{
1181 uint32_t curb_read_length
; /* user planes? */
1183 uint32_t urb_read_length
;
1187 /* brw_any_prog_data is prog_data for any stage that maps to an API stage */
1188 union brw_any_prog_data
{
1189 struct brw_stage_prog_data base
;
1190 struct brw_vue_prog_data vue
;
1191 struct brw_vs_prog_data vs
;
1192 struct brw_tcs_prog_data tcs
;
1193 struct brw_tes_prog_data tes
;
1194 struct brw_gs_prog_data gs
;
1195 struct brw_wm_prog_data wm
;
1196 struct brw_cs_prog_data cs
;
1199 #define DEFINE_PROG_DATA_DOWNCAST(stage) \
1200 static inline struct brw_##stage##_prog_data * \
1201 brw_##stage##_prog_data(struct brw_stage_prog_data *prog_data) \
1203 return (struct brw_##stage##_prog_data *) prog_data; \
1205 DEFINE_PROG_DATA_DOWNCAST(vue
)
1206 DEFINE_PROG_DATA_DOWNCAST(vs
)
1207 DEFINE_PROG_DATA_DOWNCAST(tcs
)
1208 DEFINE_PROG_DATA_DOWNCAST(tes
)
1209 DEFINE_PROG_DATA_DOWNCAST(gs
)
1210 DEFINE_PROG_DATA_DOWNCAST(wm
)
1211 DEFINE_PROG_DATA_DOWNCAST(cs
)
1212 DEFINE_PROG_DATA_DOWNCAST(ff_gs
)
1213 DEFINE_PROG_DATA_DOWNCAST(clip
)
1214 DEFINE_PROG_DATA_DOWNCAST(sf
)
1215 #undef DEFINE_PROG_DATA_DOWNCAST
1219 struct brw_compiler
*
1220 brw_compiler_create(void *mem_ctx
, const struct gen_device_info
*devinfo
);
1223 * Returns a compiler configuration for use with disk shader cache
1225 * This value only needs to change for settings that can cause different
1226 * program generation between two runs on the same hardware.
1228 * For example, it doesn't need to be different for gen 8 and gen 9 hardware,
1229 * but it does need to be different if INTEL_DEBUG=nocompact is or isn't used.
1232 brw_get_compiler_config_value(const struct brw_compiler
*compiler
);
1235 brw_prog_data_size(gl_shader_stage stage
);
1238 brw_prog_key_size(gl_shader_stage stage
);
1241 brw_prog_key_set_id(union brw_any_prog_key
*key
, gl_shader_stage
, unsigned id
);
1244 * Compile a vertex shader.
1246 * Returns the final assembly and the program's size.
1249 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
1251 const struct brw_vs_prog_key
*key
,
1252 struct brw_vs_prog_data
*prog_data
,
1253 struct nir_shader
*shader
,
1254 int shader_time_index
,
1258 * Compile a tessellation control shader.
1260 * Returns the final assembly and the program's size.
1263 brw_compile_tcs(const struct brw_compiler
*compiler
,
1266 const struct brw_tcs_prog_key
*key
,
1267 struct brw_tcs_prog_data
*prog_data
,
1268 struct nir_shader
*nir
,
1269 int shader_time_index
,
1273 * Compile a tessellation evaluation shader.
1275 * Returns the final assembly and the program's size.
1278 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
1280 const struct brw_tes_prog_key
*key
,
1281 const struct brw_vue_map
*input_vue_map
,
1282 struct brw_tes_prog_data
*prog_data
,
1283 struct nir_shader
*shader
,
1284 struct gl_program
*prog
,
1285 int shader_time_index
,
1289 * Compile a vertex shader.
1291 * Returns the final assembly and the program's size.
1294 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
1296 const struct brw_gs_prog_key
*key
,
1297 struct brw_gs_prog_data
*prog_data
,
1298 struct nir_shader
*shader
,
1299 struct gl_program
*prog
,
1300 int shader_time_index
,
1304 * Compile a strips and fans shader.
1306 * This is a fixed-function shader determined entirely by the shader key and
1309 * Returns the final assembly and the program's size.
1312 brw_compile_sf(const struct brw_compiler
*compiler
,
1314 const struct brw_sf_prog_key
*key
,
1315 struct brw_sf_prog_data
*prog_data
,
1316 struct brw_vue_map
*vue_map
,
1317 unsigned *final_assembly_size
);
1320 * Compile a clipper shader.
1322 * This is a fixed-function shader determined entirely by the shader key and
1325 * Returns the final assembly and the program's size.
1328 brw_compile_clip(const struct brw_compiler
*compiler
,
1330 const struct brw_clip_prog_key
*key
,
1331 struct brw_clip_prog_data
*prog_data
,
1332 struct brw_vue_map
*vue_map
,
1333 unsigned *final_assembly_size
);
1336 * Compile a fragment shader.
1338 * Returns the final assembly and the program's size.
1341 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
1343 const struct brw_wm_prog_key
*key
,
1344 struct brw_wm_prog_data
*prog_data
,
1345 struct nir_shader
*shader
,
1346 struct gl_program
*prog
,
1347 int shader_time_index8
,
1348 int shader_time_index16
,
1349 int shader_time_index32
,
1350 bool allow_spilling
,
1351 bool use_rep_send
, struct brw_vue_map
*vue_map
,
1355 * Compile a compute shader.
1357 * Returns the final assembly and the program's size.
1360 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
1362 const struct brw_cs_prog_key
*key
,
1363 struct brw_cs_prog_data
*prog_data
,
1364 const struct nir_shader
*shader
,
1365 int shader_time_index
,
1368 void brw_debug_key_recompile(const struct brw_compiler
*c
, void *log
,
1369 gl_shader_stage stage
,
1370 const struct brw_base_prog_key
*old_key
,
1371 const struct brw_base_prog_key
*key
);
1373 static inline uint32_t
1374 encode_slm_size(unsigned gen
, uint32_t bytes
)
1376 uint32_t slm_size
= 0;
1378 /* Shared Local Memory is specified as powers of two, and encoded in
1379 * INTERFACE_DESCRIPTOR_DATA with the following representations:
1381 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
1382 * -------------------------------------------------------------------
1383 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
1384 * -------------------------------------------------------------------
1385 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1387 assert(bytes
<= 64 * 1024);
1390 /* Shared Local Memory Size is specified as powers of two. */
1391 slm_size
= util_next_power_of_two(bytes
);
1394 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
1395 slm_size
= ffs(MAX2(slm_size
, 1024)) - 10;
1397 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
1398 slm_size
= MAX2(slm_size
, 4096) / 4096;
1406 * Return true if the given shader stage is dispatched contiguously by the
1407 * relevant fixed function starting from channel 0 of the SIMD thread, which
1408 * implies that the dispatch mask of a thread can be assumed to have the form
1409 * '2^n - 1' for some n.
1412 brw_stage_has_packed_dispatch(MAYBE_UNUSED
const struct gen_device_info
*devinfo
,
1413 gl_shader_stage stage
,
1414 const struct brw_stage_prog_data
*prog_data
)
1416 /* The code below makes assumptions about the hardware's thread dispatch
1417 * behavior that could be proven wrong in future generations -- Make sure
1418 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
1419 * the NIR front-end before changing this assertion.
1421 assert(devinfo
->gen
<= 11);
1424 case MESA_SHADER_FRAGMENT
: {
1425 /* The PSD discards subspans coming in with no lit samples, which in the
1426 * per-pixel shading case implies that each subspan will either be fully
1427 * lit (due to the VMask being used to allow derivative computations),
1428 * or not dispatched at all. In per-sample dispatch mode individual
1429 * samples from the same subspan have a fixed relative location within
1430 * the SIMD thread, so dispatch of unlit samples cannot be avoided in
1431 * general and we should return false.
1433 const struct brw_wm_prog_data
*wm_prog_data
=
1434 (const struct brw_wm_prog_data
*)prog_data
;
1435 return !wm_prog_data
->persample_dispatch
;
1437 case MESA_SHADER_COMPUTE
:
1438 /* Compute shaders will be spawned with either a fully enabled dispatch
1439 * mask or with whatever bottom/right execution mask was given to the
1440 * GPGPU walker command to be used along the workgroup edges -- In both
1441 * cases the dispatch mask is required to be tightly packed for our
1442 * invocation index calculations to work.
1446 /* Most remaining fixed functions are limited to use a packed dispatch
1447 * mask due to the hardware representation of the dispatch mask as a
1448 * single counter representing the number of enabled channels.
1455 * Computes the first varying slot in the URB produced by the previous stage
1456 * that is used in the next stage. We do this by testing the varying slots in
1457 * the previous stage's vue map against the inputs read in the next stage.
1461 * - Each URB offset contains two varying slots and we can only skip a
1462 * full offset if both slots are unused, so the value we return here is always
1463 * rounded down to the closest multiple of two.
1465 * - gl_Layer and gl_ViewportIndex don't have their own varying slots, they are
1466 * part of the vue header, so if these are read we can't skip anything.
1469 brw_compute_first_urb_slot_required(uint64_t inputs_read
,
1470 const struct brw_vue_map
*prev_stage_vue_map
)
1472 if ((inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
)) == 0) {
1473 for (int i
= 0; i
< prev_stage_vue_map
->num_slots
; i
++) {
1474 int varying
= prev_stage_vue_map
->slot_to_varying
[i
];
1475 if (varying
> 0 && (inputs_read
& BITFIELD64_BIT(varying
)) != 0)
1476 return ROUND_DOWN_TO(i
, 2);
1487 #endif /* BRW_COMPILER_H */