src/intel/compiler/brw_eu.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33 #include "brw_eu_defines.h"
  34 #include "brw_eu.h"
  35 #include "brw_shader.h"
  36 #include "dev/gen_debug.h"
  37
  38 #include "util/ralloc.h"
  39
  40 /* Returns a conditional modifier that negates the condition. */
  41 enum brw_conditional_mod
  42 brw_negate_cmod(uint32_t cmod)
  43 {
  44    switch (cmod) {
  45    case BRW_CONDITIONAL_Z:
  46       return BRW_CONDITIONAL_NZ;
  47    case BRW_CONDITIONAL_NZ:
  48       return BRW_CONDITIONAL_Z;
  49    case BRW_CONDITIONAL_G:
  50       return BRW_CONDITIONAL_LE;
  51    case BRW_CONDITIONAL_GE:
  52       return BRW_CONDITIONAL_L;
  53    case BRW_CONDITIONAL_L:
  54       return BRW_CONDITIONAL_GE;
  55    case BRW_CONDITIONAL_LE:
  56       return BRW_CONDITIONAL_G;
  57    default:
  58       return ~0;
  59    }
  60 }
  61
  62 /* Returns the corresponding conditional mod for swapping src0 and
  63  * src1 in e.g. CMP.
  64  */
  65 enum brw_conditional_mod
  66 brw_swap_cmod(uint32_t cmod)
  67 {
  68    switch (cmod) {
  69    case BRW_CONDITIONAL_Z:
  70    case BRW_CONDITIONAL_NZ:
  71       return cmod;
  72    case BRW_CONDITIONAL_G:
  73       return BRW_CONDITIONAL_L;
  74    case BRW_CONDITIONAL_GE:
  75       return BRW_CONDITIONAL_LE;
  76    case BRW_CONDITIONAL_L:
  77       return BRW_CONDITIONAL_G;
  78    case BRW_CONDITIONAL_LE:
  79       return BRW_CONDITIONAL_GE;
  80    default:
  81       return BRW_CONDITIONAL_NONE;
  82    }
  83 }
  84
  85 /**
  86  * Get the least significant bit offset of the i+1-th component of immediate
  87  * type \p type.  For \p i equal to the two's complement of j, return the
  88  * offset of the j-th component starting from the end of the vector.  For
  89  * scalar register types return zero.
  90  */
  91 static unsigned
  92 imm_shift(enum brw_reg_type type, unsigned i)
  93 {
  94    assert(type != BRW_REGISTER_TYPE_UV && type != BRW_REGISTER_TYPE_V &&
  95           "Not implemented.");
  96
  97    if (type == BRW_REGISTER_TYPE_VF)
  98       return 8 * (i & 3);
  99    else
 100       return 0;
 101 }
 102
 103 /**
 104  * Swizzle an arbitrary immediate \p x of the given type according to the
 105  * permutation specified as \p swz.
 106  */
 107 uint32_t
 108 brw_swizzle_immediate(enum brw_reg_type type, uint32_t x, unsigned swz)
 109 {
 110    if (imm_shift(type, 1)) {
 111       const unsigned n = 32 / imm_shift(type, 1);
 112       uint32_t y = 0;
 113
 114       for (unsigned i = 0; i < n; i++) {
 115          /* Shift the specified component all the way to the right and left to
 116           * discard any undesired L/MSBs, then shift it right into component i.
 117           */
 118          y |= x >> imm_shift(type, (i & ~3) + BRW_GET_SWZ(swz, i & 3))
 119                 << imm_shift(type, ~0u)
 120                 >> imm_shift(type, ~0u - i);
 121       }
 122
 123       return y;
 124    } else {
 125       return x;
 126    }
 127 }
 128
 129 unsigned
 130 brw_get_default_exec_size(struct brw_codegen *p)
 131 {
 132    return p->current->exec_size;
 133 }
 134
 135 unsigned
 136 brw_get_default_group(struct brw_codegen *p)
 137 {
 138    return p->current->group;
 139 }
 140
 141 unsigned
 142 brw_get_default_access_mode(struct brw_codegen *p)
 143 {
 144    return p->current->access_mode;
 145 }
 146
 147 void
 148 brw_set_default_exec_size(struct brw_codegen *p, unsigned value)
 149 {
 150    p->current->exec_size = value;
 151 }
 152
 153 void brw_set_default_predicate_control( struct brw_codegen *p, unsigned pc )
 154 {
 155    p->current->predicate = pc;
 156 }
 157
 158 void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse)
 159 {
 160    p->current->pred_inv = predicate_inverse;
 161 }
 162
 163 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg)
 164 {
 165    assert(subreg < 2);
 166    p->current->flag_subreg = reg * 2 + subreg;
 167 }
 168
 169 void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode )
 170 {
 171    p->current->access_mode = access_mode;
 172 }
 173
 174 void
 175 brw_set_default_compression_control(struct brw_codegen *p,
 176                             enum brw_compression compression_control)
 177 {
 178    switch (compression_control) {
 179    case BRW_COMPRESSION_NONE:
 180       /* This is the "use the first set of bits of dmask/vmask/arf
 181        * according to execsize" option.
 182        */
 183       p->current->group = 0;
 184       break;
 185    case BRW_COMPRESSION_2NDHALF:
 186       /* For SIMD8, this is "use the second set of 8 bits." */
 187       p->current->group = 8;
 188       break;
 189    case BRW_COMPRESSION_COMPRESSED:
 190       /* For SIMD16 instruction compression, use the first set of 16 bits
 191        * since we don't do SIMD32 dispatch.
 192        */
 193       p->current->group = 0;
 194       break;
 195    default:
 196       unreachable("not reached");
 197    }
 198
 199    if (p->devinfo->gen <= 6) {
 200       p->current->compressed =
 201          (compression_control == BRW_COMPRESSION_COMPRESSED);
 202    }
 203 }
 204
 205 /**
 206  * Enable or disable instruction compression on the given instruction leaving
 207  * the currently selected channel enable group untouched.
 208  */
 209 void
 210 brw_inst_set_compression(const struct gen_device_info *devinfo,
 211                          brw_inst *inst, bool on)
 212 {
 213    if (devinfo->gen >= 6) {
 214       /* No-op, the EU will figure out for us whether the instruction needs to
 215        * be compressed.
 216        */
 217    } else {
 218       /* The channel group and compression controls are non-orthogonal, there
 219        * are two possible representations for uncompressed instructions and we
 220        * may need to preserve the current one to avoid changing the selected
 221        * channel group inadvertently.
 222        */
 223       if (on)
 224          brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_COMPRESSED);
 225       else if (brw_inst_qtr_control(devinfo, inst)
 226                == BRW_COMPRESSION_COMPRESSED)
 227          brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
 228    }
 229 }
 230
 231 void
 232 brw_set_default_compression(struct brw_codegen *p, bool on)
 233 {
 234    p->current->compressed = on;
 235 }
 236
 237 /**
 238  * Apply the range of channel enable signals given by
 239  * [group, group + exec_size) to the instruction passed as argument.
 240  */
 241 void
 242 brw_inst_set_group(const struct gen_device_info *devinfo,
 243                    brw_inst *inst, unsigned group)
 244 {
 245    if (devinfo->gen >= 7) {
 246       assert(group % 4 == 0 && group < 32);
 247       brw_inst_set_qtr_control(devinfo, inst, group / 8);
 248       brw_inst_set_nib_control(devinfo, inst, (group / 4) % 2);
 249
 250    } else if (devinfo->gen == 6) {
 251       assert(group % 8 == 0 && group < 32);
 252       brw_inst_set_qtr_control(devinfo, inst, group / 8);
 253
 254    } else {
 255       assert(group % 8 == 0 && group < 16);
 256       /* The channel group and compression controls are non-orthogonal, there
 257        * are two possible representations for group zero and we may need to
 258        * preserve the current one to avoid changing the selected compression
 259        * enable inadvertently.
 260        */
 261       if (group == 8)
 262          brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_2NDHALF);
 263       else if (brw_inst_qtr_control(devinfo, inst) == BRW_COMPRESSION_2NDHALF)
 264          brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
 265    }
 266 }
 267
 268 void
 269 brw_set_default_group(struct brw_codegen *p, unsigned group)
 270 {
 271    p->current->group = group;
 272 }
 273
 274 void brw_set_default_mask_control( struct brw_codegen *p, unsigned value )
 275 {
 276    p->current->mask_control = value;
 277 }
 278
 279 void brw_set_default_saturate( struct brw_codegen *p, bool enable )
 280 {
 281    p->current->saturate = enable;
 282 }
 283
 284 void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value)
 285 {
 286    p->current->acc_wr_control = value;
 287 }
 288
 289 void brw_push_insn_state( struct brw_codegen *p )
 290 {
 291    assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
 292    *(p->current + 1) = *p->current;
 293    p->current++;
 294 }
 295
 296 void brw_pop_insn_state( struct brw_codegen *p )
 297 {
 298    assert(p->current != p->stack);
 299    p->current--;
 300 }
 301
 302
 303 /***********************************************************************
 304  */
 305 void
 306 brw_init_codegen(const struct gen_device_info *devinfo,
 307                  struct brw_codegen *p, void *mem_ctx)
 308 {
 309    memset(p, 0, sizeof(*p));
 310
 311    p->devinfo = devinfo;
 312    p->automatic_exec_sizes = true;
 313    /*
 314     * Set the initial instruction store array size to 1024, if found that
 315     * isn't enough, then it will double the store size at brw_next_insn()
 316     * until out of memory.
 317     */
 318    p->store_size = 1024;
 319    p->store = rzalloc_array(mem_ctx, brw_inst, p->store_size);
 320    p->nr_insn = 0;
 321    p->current = p->stack;
 322    memset(p->current, 0, sizeof(p->current[0]));
 323
 324    p->mem_ctx = mem_ctx;
 325
 326    /* Some defaults?
 327     */
 328    brw_set_default_exec_size(p, BRW_EXECUTE_8);
 329    brw_set_default_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
 330    brw_set_default_saturate(p, 0);
 331    brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
 332
 333    /* Set up control flow stack */
 334    p->if_stack_depth = 0;
 335    p->if_stack_array_size = 16;
 336    p->if_stack = rzalloc_array(mem_ctx, int, p->if_stack_array_size);
 337
 338    p->loop_stack_depth = 0;
 339    p->loop_stack_array_size = 16;
 340    p->loop_stack = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 341    p->if_depth_in_loop = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 342 }
 343
 344
 345 const unsigned *brw_get_program( struct brw_codegen *p,
 346                                unsigned *sz )
 347 {
 348    *sz = p->next_insn_offset;
 349    return (const unsigned *)p->store;
 350 }
 351
 352 void
 353 brw_disassemble(const struct gen_device_info *devinfo,
 354                 const void *assembly, int start, int end, FILE *out)
 355 {
 356    bool dump_hex = (INTEL_DEBUG & DEBUG_HEX) != 0;
 357
 358    for (int offset = start; offset < end;) {
 359       const brw_inst *insn = assembly + offset;
 360       brw_inst uncompacted;
 361       bool compacted = brw_inst_cmpt_control(devinfo, insn);
 362       if (0)
 363          fprintf(out, "0x%08x: ", offset);
 364
 365       if (compacted) {
 366          brw_compact_inst *compacted = (void *)insn;
 367          if (dump_hex) {
 368             unsigned char * insn_ptr = ((unsigned char *)&insn[0]);
 369             const unsigned int blank_spaces = 24;
 370             for (int i = 0 ; i < 8; i = i + 4) {
 371                fprintf(out, "%02x %02x %02x %02x ",
 372                        insn_ptr[i],
 373                        insn_ptr[i + 1],
 374                        insn_ptr[i + 2],
 375                        insn_ptr[i + 3]);
 376             }
 377             /* Make compacted instructions hex value output vertically aligned
 378              * with uncompacted instructions hex value
 379              */
 380             fprintf(out, "%*c", blank_spaces, ' ');
 381          }
 382
 383          brw_uncompact_instruction(devinfo, &uncompacted, compacted);
 384          insn = &uncompacted;
 385          offset += 8;
 386       } else {
 387          if (dump_hex) {
 388             unsigned char * insn_ptr = ((unsigned char *)&insn[0]);
 389             for (int i = 0 ; i < 16; i = i + 4) {
 390                fprintf(out, "%02x %02x %02x %02x ",
 391                        insn_ptr[i],
 392                        insn_ptr[i + 1],
 393                        insn_ptr[i + 2],
 394                        insn_ptr[i + 3]);
 395             }
 396          }
 397          offset += 16;
 398       }
 399
 400       brw_disassemble_inst(out, devinfo, insn, compacted);
 401    }
 402 }
 403
 404 enum gen {
 405    GEN4  = (1 << 0),
 406    GEN45 = (1 << 1),
 407    GEN5  = (1 << 2),
 408    GEN6  = (1 << 3),
 409    GEN7  = (1 << 4),
 410    GEN75 = (1 << 5),
 411    GEN8  = (1 << 6),
 412    GEN9  = (1 << 7),
 413    GEN10 = (1 << 8),
 414    GEN11 = (1 << 9),
 415    GEN_ALL = ~0
 416 };
 417
 418 #define GEN_LT(gen) ((gen) - 1)
 419 #define GEN_GE(gen) (~GEN_LT(gen))
 420 #define GEN_LE(gen) (GEN_LT(gen) | (gen))
 421
 422 static const struct opcode_desc opcode_10_descs[] = {
 423    { .name = "dim",   .nsrc = 1, .ndst = 1, .gens = GEN75 },
 424    { .name = "smov",  .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN8) },
 425 };
 426
 427 static const struct opcode_desc opcode_35_descs[] = {
 428    { .name = "iff",   .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 429    { .name = "brc",   .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN7) },
 430 };
 431
 432 static const struct opcode_desc opcode_38_descs[] = {
 433    { .name = "do",    .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 434    { .name = "case",  .nsrc = 0, .ndst = 0, .gens = GEN6 },
 435 };
 436
 437 static const struct opcode_desc opcode_44_descs[] = {
 438    { .name = "msave", .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 439    { .name = "call",  .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN6) },
 440 };
 441
 442 static const struct opcode_desc opcode_45_descs[] = {
 443    { .name = "mrest", .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 444    { .name = "ret",   .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN6) },
 445 };
 446
 447 static const struct opcode_desc opcode_46_descs[] = {
 448    { .name = "push",  .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 449    { .name = "fork",  .nsrc = 0, .ndst = 0, .gens = GEN6 },
 450    { .name = "goto",  .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN8) },
 451 };
 452
 453 static const struct opcode_desc opcode_descs[128] = {
 454    [BRW_OPCODE_ILLEGAL] = {
 455       .name = "illegal", .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 456    },
 457    [BRW_OPCODE_MOV] = {
 458       .name = "mov",     .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 459    },
 460    [BRW_OPCODE_SEL] = {
 461       .name = "sel",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 462    },
 463    [BRW_OPCODE_MOVI] = {
 464       .name = "movi",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN45),
 465    },
 466    [BRW_OPCODE_NOT] = {
 467       .name = "not",     .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 468    },
 469    [BRW_OPCODE_AND] = {
 470       .name = "and",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 471    },
 472    [BRW_OPCODE_OR] = {
 473       .name = "or",      .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 474    },
 475    [BRW_OPCODE_XOR] = {
 476       .name = "xor",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 477    },
 478    [BRW_OPCODE_SHR] = {
 479       .name = "shr",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 480    },
 481    [BRW_OPCODE_SHL] = {
 482       .name = "shl",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 483    },
 484    [10] = {
 485       .table = opcode_10_descs, .size = ARRAY_SIZE(opcode_10_descs),
 486    },
 487    /* Reserved - 11 */
 488    [BRW_OPCODE_ASR] = {
 489       .name = "asr",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 490    },
 491    /* Reserved - 13-15 */
 492    [BRW_OPCODE_CMP] = {
 493       .name = "cmp",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 494    },
 495    [BRW_OPCODE_CMPN] = {
 496       .name = "cmpn",    .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 497    },
 498    [BRW_OPCODE_CSEL] = {
 499       .name = "csel",    .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN8),
 500    },
 501    [BRW_OPCODE_F32TO16] = {
 502       .name = "f32to16", .nsrc = 1, .ndst = 1, .gens = GEN7 | GEN75,
 503    },
 504    [BRW_OPCODE_F16TO32] = {
 505       .name = "f16to32", .nsrc = 1, .ndst = 1, .gens = GEN7 | GEN75,
 506    },
 507    /* Reserved - 21-22 */
 508    [BRW_OPCODE_BFREV] = {
 509       .name = "bfrev",   .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
 510    },
 511    [BRW_OPCODE_BFE] = {
 512       .name = "bfe",     .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN7),
 513    },
 514    [BRW_OPCODE_BFI1] = {
 515       .name = "bfi1",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7),
 516    },
 517    [BRW_OPCODE_BFI2] = {
 518       .name = "bfi2",    .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN7),
 519    },
 520    /* Reserved - 27-31 */
 521    [BRW_OPCODE_JMPI] = {
 522       .name = "jmpi",    .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 523    },
 524    [33] = {
 525       .name = "brd",     .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN7),
 526    },
 527    [BRW_OPCODE_IF] = {
 528       .name = "if",      .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 529    },
 530    [35] = {
 531       .table = opcode_35_descs, .size = ARRAY_SIZE(opcode_35_descs),
 532    },
 533    [BRW_OPCODE_ELSE] = {
 534       .name = "else",    .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 535    },
 536    [BRW_OPCODE_ENDIF] = {
 537       .name = "endif",   .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 538    },
 539    [38] = {
 540       .table = opcode_38_descs, .size = ARRAY_SIZE(opcode_38_descs),
 541    },
 542    [BRW_OPCODE_WHILE] = {
 543       .name = "while",   .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 544    },
 545    [BRW_OPCODE_BREAK] = {
 546       .name = "break",   .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 547    },
 548    [BRW_OPCODE_CONTINUE] = {
 549       .name = "cont",    .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 550    },
 551    [BRW_OPCODE_HALT] = {
 552       .name = "halt",    .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 553    },
 554    [43] = {
 555       .name = "calla",   .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN75),
 556    },
 557    [44] = {
 558       .table = opcode_44_descs, .size = ARRAY_SIZE(opcode_44_descs),
 559    },
 560    [45] = {
 561       .table = opcode_45_descs, .size = ARRAY_SIZE(opcode_45_descs),
 562    },
 563    [46] = {
 564       .table = opcode_46_descs, .size = ARRAY_SIZE(opcode_46_descs),
 565    },
 566    [47] = {
 567       .name = "pop",     .nsrc = 2, .ndst = 0, .gens = GEN_LE(GEN5),
 568    },
 569    [BRW_OPCODE_WAIT] = {
 570       .name = "wait",    .nsrc = 1, .ndst = 0, .gens = GEN_ALL,
 571    },
 572    [BRW_OPCODE_SEND] = {
 573       .name = "send",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 574    },
 575    [BRW_OPCODE_SENDC] = {
 576       .name = "sendc",   .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 577    },
 578    [BRW_OPCODE_SENDS] = {
 579       .name = "sends",   .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN9),
 580    },
 581    [BRW_OPCODE_SENDSC] = {
 582       .name = "sendsc",  .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN9),
 583    },
 584    /* Reserved 53-55 */
 585    [BRW_OPCODE_MATH] = {
 586       .name = "math",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN6),
 587    },
 588    /* Reserved 57-63 */
 589    [BRW_OPCODE_ADD] = {
 590       .name = "add",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 591    },
 592    [BRW_OPCODE_MUL] = {
 593       .name = "mul",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 594    },
 595    [BRW_OPCODE_AVG] = {
 596       .name = "avg",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 597    },
 598    [BRW_OPCODE_FRC] = {
 599       .name = "frc",     .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 600    },
 601    [BRW_OPCODE_RNDU] = {
 602       .name = "rndu",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 603    },
 604    [BRW_OPCODE_RNDD] = {
 605       .name = "rndd",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 606    },
 607    [BRW_OPCODE_RNDE] = {
 608       .name = "rnde",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 609    },
 610    [BRW_OPCODE_RNDZ] = {
 611       .name = "rndz",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 612    },
 613    [BRW_OPCODE_MAC] = {
 614       .name = "mac",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 615    },
 616    [BRW_OPCODE_MACH] = {
 617       .name = "mach",    .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 618    },
 619    [BRW_OPCODE_LZD] = {
 620       .name = "lzd",     .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 621    },
 622    [BRW_OPCODE_FBH] = {
 623       .name = "fbh",     .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
 624    },
 625    [BRW_OPCODE_FBL] = {
 626       .name = "fbl",     .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
 627    },
 628    [BRW_OPCODE_CBIT] = {
 629       .name = "cbit",    .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
 630    },
 631    [BRW_OPCODE_ADDC] = {
 632       .name = "addc",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7),
 633    },
 634    [BRW_OPCODE_SUBB] = {
 635       .name = "subb",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7),
 636    },
 637    [BRW_OPCODE_SAD2] = {
 638       .name = "sad2",    .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 639    },
 640    [BRW_OPCODE_SADA2] = {
 641       .name = "sada2",   .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 642    },
 643    /* Reserved 82-83 */
 644    [BRW_OPCODE_DP4] = {
 645       .name = "dp4",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 646    },
 647    [BRW_OPCODE_DPH] = {
 648       .name = "dph",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 649    },
 650    [BRW_OPCODE_DP3] = {
 651       .name = "dp3",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 652    },
 653    [BRW_OPCODE_DP2] = {
 654       .name = "dp2",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 655    },
 656    /* Reserved 88 */
 657    [BRW_OPCODE_LINE] = {
 658       .name = "line",    .nsrc = 2, .ndst = 1, .gens = GEN_LE(GEN10),
 659    },
 660    [BRW_OPCODE_PLN] = {
 661       .name = "pln",     .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN45) & GEN_LE(GEN10),
 662    },
 663    [BRW_OPCODE_MAD] = {
 664       .name = "mad",     .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN6),
 665    },
 666    [BRW_OPCODE_LRP] = {
 667       .name = "lrp",     .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN6) & GEN_LE(GEN10),
 668    },
 669    [93] = {
 670       .name = "madm",    .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN8),
 671    },
 672    /* Reserved 94-124 */
 673    [BRW_OPCODE_NENOP] = {
 674       .name = "nenop",   .nsrc = 0, .ndst = 0, .gens = GEN45,
 675    },
 676    [BRW_OPCODE_NOP] = {
 677       .name = "nop",     .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 678    },
 679 };
 680
 681 static enum gen
 682 gen_from_devinfo(const struct gen_device_info *devinfo)
 683 {
 684    switch (devinfo->gen) {
 685    case 4: return devinfo->is_g4x ? GEN45 : GEN4;
 686    case 5: return GEN5;
 687    case 6: return GEN6;
 688    case 7: return devinfo->is_haswell ? GEN75 : GEN7;
 689    case 8: return GEN8;
 690    case 9: return GEN9;
 691    case 10: return GEN10;
 692    case 11: return GEN11;
 693    default:
 694       unreachable("not reached");
 695    }
 696 }
 697
 698 /* Return the matching opcode_desc for the specified opcode number and
 699  * hardware generation, or NULL if the opcode is not supported by the device.
 700  */
 701 const struct opcode_desc *
 702 brw_opcode_desc(const struct gen_device_info *devinfo, enum opcode opcode)
 703 {
 704    if (opcode >= ARRAY_SIZE(opcode_descs))
 705       return NULL;
 706
 707    enum gen gen = gen_from_devinfo(devinfo);
 708    if (opcode_descs[opcode].gens != 0) {
 709       if ((opcode_descs[opcode].gens & gen) != 0) {
 710          return &opcode_descs[opcode];
 711       }
 712    } else if (opcode_descs[opcode].table != NULL) {
 713       const struct opcode_desc *table = opcode_descs[opcode].table;
 714       for (unsigned i = 0; i < opcode_descs[opcode].size; i++) {
 715          if ((table[i].gens & gen) != 0) {
 716             return &table[i];
 717          }
 718       }
 719    }
 720    return NULL;
 721 }