src/intel/compiler/brw_eu.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33 #include "brw_eu_defines.h"
  34 #include "brw_eu.h"
  35 #include "brw_shader.h"
  36 #include "common/gen_debug.h"
  37
  38 #include "util/ralloc.h"
  39
  40 /* Returns a conditional modifier that negates the condition. */
  41 enum brw_conditional_mod
  42 brw_negate_cmod(uint32_t cmod)
  43 {
  44    switch (cmod) {
  45    case BRW_CONDITIONAL_Z:
  46       return BRW_CONDITIONAL_NZ;
  47    case BRW_CONDITIONAL_NZ:
  48       return BRW_CONDITIONAL_Z;
  49    case BRW_CONDITIONAL_G:
  50       return BRW_CONDITIONAL_LE;
  51    case BRW_CONDITIONAL_GE:
  52       return BRW_CONDITIONAL_L;
  53    case BRW_CONDITIONAL_L:
  54       return BRW_CONDITIONAL_GE;
  55    case BRW_CONDITIONAL_LE:
  56       return BRW_CONDITIONAL_G;
  57    default:
  58       return ~0;
  59    }
  60 }
  61
  62 /* Returns the corresponding conditional mod for swapping src0 and
  63  * src1 in e.g. CMP.
  64  */
  65 enum brw_conditional_mod
  66 brw_swap_cmod(uint32_t cmod)
  67 {
  68    switch (cmod) {
  69    case BRW_CONDITIONAL_Z:
  70    case BRW_CONDITIONAL_NZ:
  71       return cmod;
  72    case BRW_CONDITIONAL_G:
  73       return BRW_CONDITIONAL_L;
  74    case BRW_CONDITIONAL_GE:
  75       return BRW_CONDITIONAL_LE;
  76    case BRW_CONDITIONAL_L:
  77       return BRW_CONDITIONAL_G;
  78    case BRW_CONDITIONAL_LE:
  79       return BRW_CONDITIONAL_GE;
  80    default:
  81       return BRW_CONDITIONAL_NONE;
  82    }
  83 }
  84
  85 /**
  86  * Get the least significant bit offset of the i+1-th component of immediate
  87  * type \p type.  For \p i equal to the two's complement of j, return the
  88  * offset of the j-th component starting from the end of the vector.  For
  89  * scalar register types return zero.
  90  */
  91 static unsigned
  92 imm_shift(enum brw_reg_type type, unsigned i)
  93 {
  94    assert(type != BRW_REGISTER_TYPE_UV && type != BRW_REGISTER_TYPE_V &&
  95           "Not implemented.");
  96
  97    if (type == BRW_REGISTER_TYPE_VF)
  98       return 8 * (i & 3);
  99    else
 100       return 0;
 101 }
 102
 103 /**
 104  * Swizzle an arbitrary immediate \p x of the given type according to the
 105  * permutation specified as \p swz.
 106  */
 107 uint32_t
 108 brw_swizzle_immediate(enum brw_reg_type type, uint32_t x, unsigned swz)
 109 {
 110    if (imm_shift(type, 1)) {
 111       const unsigned n = 32 / imm_shift(type, 1);
 112       uint32_t y = 0;
 113
 114       for (unsigned i = 0; i < n; i++) {
 115          /* Shift the specified component all the way to the right and left to
 116           * discard any undesired L/MSBs, then shift it right into component i.
 117           */
 118          y |= x >> imm_shift(type, (i & ~3) + BRW_GET_SWZ(swz, i & 3))
 119                 << imm_shift(type, ~0u)
 120                 >> imm_shift(type, ~0u - i);
 121       }
 122
 123       return y;
 124    } else {
 125       return x;
 126    }
 127 }
 128
 129 void
 130 brw_set_default_exec_size(struct brw_codegen *p, unsigned value)
 131 {
 132    brw_inst_set_exec_size(p->devinfo, p->current, value);
 133 }
 134
 135 void brw_set_default_predicate_control( struct brw_codegen *p, unsigned pc )
 136 {
 137    brw_inst_set_pred_control(p->devinfo, p->current, pc);
 138 }
 139
 140 void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse)
 141 {
 142    brw_inst_set_pred_inv(p->devinfo, p->current, predicate_inverse);
 143 }
 144
 145 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg)
 146 {
 147    if (p->devinfo->gen >= 7)
 148       brw_inst_set_flag_reg_nr(p->devinfo, p->current, reg);
 149
 150    brw_inst_set_flag_subreg_nr(p->devinfo, p->current, subreg);
 151 }
 152
 153 void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode )
 154 {
 155    brw_inst_set_access_mode(p->devinfo, p->current, access_mode);
 156 }
 157
 158 void
 159 brw_set_default_compression_control(struct brw_codegen *p,
 160                             enum brw_compression compression_control)
 161 {
 162    if (p->devinfo->gen >= 6) {
 163       /* Since we don't use the SIMD32 support in gen6, we translate
 164        * the pre-gen6 compression control here.
 165        */
 166       switch (compression_control) {
 167       case BRW_COMPRESSION_NONE:
 168          /* This is the "use the first set of bits of dmask/vmask/arf
 169           * according to execsize" option.
 170           */
 171          brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_1Q);
 172          break;
 173       case BRW_COMPRESSION_2NDHALF:
 174          /* For SIMD8, this is "use the second set of 8 bits." */
 175          brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_2Q);
 176          break;
 177       case BRW_COMPRESSION_COMPRESSED:
 178          /* For SIMD16 instruction compression, use the first set of 16 bits
 179           * since we don't do SIMD32 dispatch.
 180           */
 181          brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_1H);
 182          break;
 183       default:
 184          unreachable("not reached");
 185       }
 186    } else {
 187       brw_inst_set_qtr_control(p->devinfo, p->current, compression_control);
 188    }
 189 }
 190
 191 /**
 192  * Enable or disable instruction compression on the given instruction leaving
 193  * the currently selected channel enable group untouched.
 194  */
 195 void
 196 brw_inst_set_compression(const struct gen_device_info *devinfo,
 197                          brw_inst *inst, bool on)
 198 {
 199    if (devinfo->gen >= 6) {
 200       /* No-op, the EU will figure out for us whether the instruction needs to
 201        * be compressed.
 202        */
 203    } else {
 204       /* The channel group and compression controls are non-orthogonal, there
 205        * are two possible representations for uncompressed instructions and we
 206        * may need to preserve the current one to avoid changing the selected
 207        * channel group inadvertently.
 208        */
 209       if (on)
 210          brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_COMPRESSED);
 211       else if (brw_inst_qtr_control(devinfo, inst)
 212                == BRW_COMPRESSION_COMPRESSED)
 213          brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
 214    }
 215 }
 216
 217 void
 218 brw_set_default_compression(struct brw_codegen *p, bool on)
 219 {
 220    brw_inst_set_compression(p->devinfo, p->current, on);
 221 }
 222
 223 /**
 224  * Apply the range of channel enable signals given by
 225  * [group, group + exec_size) to the instruction passed as argument.
 226  */
 227 void
 228 brw_inst_set_group(const struct gen_device_info *devinfo,
 229                    brw_inst *inst, unsigned group)
 230 {
 231    if (devinfo->gen >= 7) {
 232       assert(group % 4 == 0 && group < 32);
 233       brw_inst_set_qtr_control(devinfo, inst, group / 8);
 234       brw_inst_set_nib_control(devinfo, inst, (group / 4) % 2);
 235
 236    } else if (devinfo->gen == 6) {
 237       assert(group % 8 == 0 && group < 32);
 238       brw_inst_set_qtr_control(devinfo, inst, group / 8);
 239
 240    } else {
 241       assert(group % 8 == 0 && group < 16);
 242       /* The channel group and compression controls are non-orthogonal, there
 243        * are two possible representations for group zero and we may need to
 244        * preserve the current one to avoid changing the selected compression
 245        * enable inadvertently.
 246        */
 247       if (group == 8)
 248          brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_2NDHALF);
 249       else if (brw_inst_qtr_control(devinfo, inst) == BRW_COMPRESSION_2NDHALF)
 250          brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
 251    }
 252 }
 253
 254 void
 255 brw_set_default_group(struct brw_codegen *p, unsigned group)
 256 {
 257    brw_inst_set_group(p->devinfo, p->current, group);
 258 }
 259
 260 void brw_set_default_mask_control( struct brw_codegen *p, unsigned value )
 261 {
 262    brw_inst_set_mask_control(p->devinfo, p->current, value);
 263 }
 264
 265 void brw_set_default_saturate( struct brw_codegen *p, bool enable )
 266 {
 267    brw_inst_set_saturate(p->devinfo, p->current, enable);
 268 }
 269
 270 void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value)
 271 {
 272    if (p->devinfo->gen >= 6)
 273       brw_inst_set_acc_wr_control(p->devinfo, p->current, value);
 274 }
 275
 276 void brw_push_insn_state( struct brw_codegen *p )
 277 {
 278    assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
 279    memcpy(p->current + 1, p->current, sizeof(brw_inst));
 280    p->current++;
 281 }
 282
 283 void brw_pop_insn_state( struct brw_codegen *p )
 284 {
 285    assert(p->current != p->stack);
 286    p->current--;
 287 }
 288
 289
 290 /***********************************************************************
 291  */
 292 void
 293 brw_init_codegen(const struct gen_device_info *devinfo,
 294                  struct brw_codegen *p, void *mem_ctx)
 295 {
 296    memset(p, 0, sizeof(*p));
 297
 298    p->devinfo = devinfo;
 299    p->automatic_exec_sizes = true;
 300    /*
 301     * Set the initial instruction store array size to 1024, if found that
 302     * isn't enough, then it will double the store size at brw_next_insn()
 303     * until out of memory.
 304     */
 305    p->store_size = 1024;
 306    p->store = rzalloc_array(mem_ctx, brw_inst, p->store_size);
 307    p->nr_insn = 0;
 308    p->current = p->stack;
 309    memset(p->current, 0, sizeof(p->current[0]));
 310
 311    p->mem_ctx = mem_ctx;
 312
 313    /* Some defaults?
 314     */
 315    brw_set_default_exec_size(p, BRW_EXECUTE_8);
 316    brw_set_default_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
 317    brw_set_default_saturate(p, 0);
 318    brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
 319
 320    /* Set up control flow stack */
 321    p->if_stack_depth = 0;
 322    p->if_stack_array_size = 16;
 323    p->if_stack = rzalloc_array(mem_ctx, int, p->if_stack_array_size);
 324
 325    p->loop_stack_depth = 0;
 326    p->loop_stack_array_size = 16;
 327    p->loop_stack = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 328    p->if_depth_in_loop = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 329 }
 330
 331
 332 const unsigned *brw_get_program( struct brw_codegen *p,
 333                                unsigned *sz )
 334 {
 335    *sz = p->next_insn_offset;
 336    return (const unsigned *)p->store;
 337 }
 338
 339 void
 340 brw_disassemble(const struct gen_device_info *devinfo,
 341                 const void *assembly, int start, int end, FILE *out)
 342 {
 343    bool dump_hex = (INTEL_DEBUG & DEBUG_HEX) != 0;
 344
 345    for (int offset = start; offset < end;) {
 346       const brw_inst *insn = assembly + offset;
 347       brw_inst uncompacted;
 348       bool compacted = brw_inst_cmpt_control(devinfo, insn);
 349       if (0)
 350          fprintf(out, "0x%08x: ", offset);
 351
 352       if (compacted) {
 353          brw_compact_inst *compacted = (void *)insn;
 354          if (dump_hex) {
 355             fprintf(out, "0x%08x 0x%08x                       ",
 356                     ((uint32_t *)insn)[1],
 357                     ((uint32_t *)insn)[0]);
 358          }
 359
 360          brw_uncompact_instruction(devinfo, &uncompacted, compacted);
 361          insn = &uncompacted;
 362          offset += 8;
 363       } else {
 364          if (dump_hex) {
 365             fprintf(out, "0x%08x 0x%08x 0x%08x 0x%08x ",
 366                     ((uint32_t *)insn)[3],
 367                     ((uint32_t *)insn)[2],
 368                     ((uint32_t *)insn)[1],
 369                     ((uint32_t *)insn)[0]);
 370          }
 371          offset += 16;
 372       }
 373
 374       brw_disassemble_inst(out, devinfo, insn, compacted);
 375    }
 376 }
 377
 378 enum gen {
 379    GEN4  = (1 << 0),
 380    GEN45 = (1 << 1),
 381    GEN5  = (1 << 2),
 382    GEN6  = (1 << 3),
 383    GEN7  = (1 << 4),
 384    GEN75 = (1 << 5),
 385    GEN8  = (1 << 6),
 386    GEN9  = (1 << 7),
 387    GEN10  = (1 << 8),
 388    GEN_ALL = ~0
 389 };
 390
 391 #define GEN_LT(gen) ((gen) - 1)
 392 #define GEN_GE(gen) (~GEN_LT(gen))
 393 #define GEN_LE(gen) (GEN_LT(gen) | (gen))
 394
 395 static const struct opcode_desc opcode_10_descs[] = {
 396    { .name = "dim",   .nsrc = 1, .ndst = 1, .gens = GEN75 },
 397    { .name = "smov",  .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN8) },
 398 };
 399
 400 static const struct opcode_desc opcode_35_descs[] = {
 401    { .name = "iff",   .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 402    { .name = "brc",   .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN7) },
 403 };
 404
 405 static const struct opcode_desc opcode_38_descs[] = {
 406    { .name = "do",    .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 407    { .name = "case",  .nsrc = 0, .ndst = 0, .gens = GEN6 },
 408 };
 409
 410 static const struct opcode_desc opcode_44_descs[] = {
 411    { .name = "msave", .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 412    { .name = "call",  .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN6) },
 413 };
 414
 415 static const struct opcode_desc opcode_45_descs[] = {
 416    { .name = "mrest", .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 417    { .name = "ret",   .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN6) },
 418 };
 419
 420 static const struct opcode_desc opcode_46_descs[] = {
 421    { .name = "push",  .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 422    { .name = "fork",  .nsrc = 0, .ndst = 0, .gens = GEN6 },
 423    { .name = "goto",  .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN8) },
 424 };
 425
 426 static const struct opcode_desc opcode_descs[128] = {
 427    [BRW_OPCODE_ILLEGAL] = {
 428       .name = "illegal", .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 429    },
 430    [BRW_OPCODE_MOV] = {
 431       .name = "mov",     .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 432    },
 433    [BRW_OPCODE_SEL] = {
 434       .name = "sel",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 435    },
 436    [BRW_OPCODE_MOVI] = {
 437       .name = "movi",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN45),
 438    },
 439    [BRW_OPCODE_NOT] = {
 440       .name = "not",     .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 441    },
 442    [BRW_OPCODE_AND] = {
 443       .name = "and",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 444    },
 445    [BRW_OPCODE_OR] = {
 446       .name = "or",      .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 447    },
 448    [BRW_OPCODE_XOR] = {
 449       .name = "xor",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 450    },
 451    [BRW_OPCODE_SHR] = {
 452       .name = "shr",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 453    },
 454    [BRW_OPCODE_SHL] = {
 455       .name = "shl",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 456    },
 457    [10] = {
 458       .table = opcode_10_descs, .size = ARRAY_SIZE(opcode_10_descs),
 459    },
 460    /* Reserved - 11 */
 461    [BRW_OPCODE_ASR] = {
 462       .name = "asr",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 463    },
 464    /* Reserved - 13-15 */
 465    [BRW_OPCODE_CMP] = {
 466       .name = "cmp",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 467    },
 468    [BRW_OPCODE_CMPN] = {
 469       .name = "cmpn",    .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 470    },
 471    [BRW_OPCODE_CSEL] = {
 472       .name = "csel",    .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN8),
 473    },
 474    [BRW_OPCODE_F32TO16] = {
 475       .name = "f32to16", .nsrc = 1, .ndst = 1, .gens = GEN7 | GEN75,
 476    },
 477    [BRW_OPCODE_F16TO32] = {
 478       .name = "f16to32", .nsrc = 1, .ndst = 1, .gens = GEN7 | GEN75,
 479    },
 480    /* Reserved - 21-22 */
 481    [BRW_OPCODE_BFREV] = {
 482       .name = "bfrev",   .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
 483    },
 484    [BRW_OPCODE_BFE] = {
 485       .name = "bfe",     .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN7),
 486    },
 487    [BRW_OPCODE_BFI1] = {
 488       .name = "bfi1",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7),
 489    },
 490    [BRW_OPCODE_BFI2] = {
 491       .name = "bfi2",    .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN7),
 492    },
 493    /* Reserved - 27-31 */
 494    [BRW_OPCODE_JMPI] = {
 495       .name = "jmpi",    .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 496    },
 497    [33] = {
 498       .name = "brd",     .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN7),
 499    },
 500    [BRW_OPCODE_IF] = {
 501       .name = "if",      .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 502    },
 503    [35] = {
 504       .table = opcode_35_descs, .size = ARRAY_SIZE(opcode_35_descs),
 505    },
 506    [BRW_OPCODE_ELSE] = {
 507       .name = "else",    .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 508    },
 509    [BRW_OPCODE_ENDIF] = {
 510       .name = "endif",   .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 511    },
 512    [38] = {
 513       .table = opcode_38_descs, .size = ARRAY_SIZE(opcode_38_descs),
 514    },
 515    [BRW_OPCODE_WHILE] = {
 516       .name = "while",   .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 517    },
 518    [BRW_OPCODE_BREAK] = {
 519       .name = "break",   .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 520    },
 521    [BRW_OPCODE_CONTINUE] = {
 522       .name = "cont",    .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 523    },
 524    [BRW_OPCODE_HALT] = {
 525       .name = "halt",    .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 526    },
 527    [43] = {
 528       .name = "calla",   .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN75),
 529    },
 530    [44] = {
 531       .table = opcode_44_descs, .size = ARRAY_SIZE(opcode_44_descs),
 532    },
 533    [45] = {
 534       .table = opcode_45_descs, .size = ARRAY_SIZE(opcode_45_descs),
 535    },
 536    [46] = {
 537       .table = opcode_46_descs, .size = ARRAY_SIZE(opcode_46_descs),
 538    },
 539    [47] = {
 540       .name = "pop",     .nsrc = 2, .ndst = 0, .gens = GEN_LE(GEN5),
 541    },
 542    [BRW_OPCODE_WAIT] = {
 543       .name = "wait",    .nsrc = 1, .ndst = 0, .gens = GEN_ALL,
 544    },
 545    [BRW_OPCODE_SEND] = {
 546       .name = "send",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 547    },
 548    [BRW_OPCODE_SENDC] = {
 549       .name = "sendc",   .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 550    },
 551    [BRW_OPCODE_SENDS] = {
 552       .name = "sends",   .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN9),
 553    },
 554    [BRW_OPCODE_SENDSC] = {
 555       .name = "sendsc",  .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN9),
 556    },
 557    /* Reserved 53-55 */
 558    [BRW_OPCODE_MATH] = {
 559       .name = "math",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN6),
 560    },
 561    /* Reserved 57-63 */
 562    [BRW_OPCODE_ADD] = {
 563       .name = "add",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 564    },
 565    [BRW_OPCODE_MUL] = {
 566       .name = "mul",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 567    },
 568    [BRW_OPCODE_AVG] = {
 569       .name = "avg",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 570    },
 571    [BRW_OPCODE_FRC] = {
 572       .name = "frc",     .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 573    },
 574    [BRW_OPCODE_RNDU] = {
 575       .name = "rndu",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 576    },
 577    [BRW_OPCODE_RNDD] = {
 578       .name = "rndd",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 579    },
 580    [BRW_OPCODE_RNDE] = {
 581       .name = "rnde",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 582    },
 583    [BRW_OPCODE_RNDZ] = {
 584       .name = "rndz",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 585    },
 586    [BRW_OPCODE_MAC] = {
 587       .name = "mac",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 588    },
 589    [BRW_OPCODE_MACH] = {
 590       .name = "mach",    .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 591    },
 592    [BRW_OPCODE_LZD] = {
 593       .name = "lzd",     .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 594    },
 595    [BRW_OPCODE_FBH] = {
 596       .name = "fbh",     .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
 597    },
 598    [BRW_OPCODE_FBL] = {
 599       .name = "fbl",     .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
 600    },
 601    [BRW_OPCODE_CBIT] = {
 602       .name = "cbit",    .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
 603    },
 604    [BRW_OPCODE_ADDC] = {
 605       .name = "addc",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7),
 606    },
 607    [BRW_OPCODE_SUBB] = {
 608       .name = "subb",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7),
 609    },
 610    [BRW_OPCODE_SAD2] = {
 611       .name = "sad2",    .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 612    },
 613    [BRW_OPCODE_SADA2] = {
 614       .name = "sada2",   .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 615    },
 616    /* Reserved 82-83 */
 617    [BRW_OPCODE_DP4] = {
 618       .name = "dp4",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 619    },
 620    [BRW_OPCODE_DPH] = {
 621       .name = "dph",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 622    },
 623    [BRW_OPCODE_DP3] = {
 624       .name = "dp3",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 625    },
 626    [BRW_OPCODE_DP2] = {
 627       .name = "dp2",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 628    },
 629    /* Reserved 88 */
 630    [BRW_OPCODE_LINE] = {
 631       .name = "line",    .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 632    },
 633    [BRW_OPCODE_PLN] = {
 634       .name = "pln",     .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN45),
 635    },
 636    [BRW_OPCODE_MAD] = {
 637       .name = "mad",     .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN6),
 638    },
 639    [BRW_OPCODE_LRP] = {
 640       .name = "lrp",     .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN6),
 641    },
 642    [93] = {
 643       .name = "madm",    .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN8),
 644    },
 645    /* Reserved 94-124 */
 646    [BRW_OPCODE_NENOP] = {
 647       .name = "nenop",   .nsrc = 0, .ndst = 0, .gens = GEN45,
 648    },
 649    [BRW_OPCODE_NOP] = {
 650       .name = "nop",     .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 651    },
 652 };
 653
 654 static enum gen
 655 gen_from_devinfo(const struct gen_device_info *devinfo)
 656 {
 657    switch (devinfo->gen) {
 658    case 4: return devinfo->is_g4x ? GEN45 : GEN4;
 659    case 5: return GEN5;
 660    case 6: return GEN6;
 661    case 7: return devinfo->is_haswell ? GEN75 : GEN7;
 662    case 8: return GEN8;
 663    case 9: return GEN9;
 664    case 10: return GEN10;
 665    default:
 666       unreachable("not reached");
 667    }
 668 }
 669
 670 /* Return the matching opcode_desc for the specified opcode number and
 671  * hardware generation, or NULL if the opcode is not supported by the device.
 672  */
 673 const struct opcode_desc *
 674 brw_opcode_desc(const struct gen_device_info *devinfo, enum opcode opcode)
 675 {
 676    if (opcode >= ARRAY_SIZE(opcode_descs))
 677       return NULL;
 678
 679    enum gen gen = gen_from_devinfo(devinfo);
 680    if (opcode_descs[opcode].gens != 0) {
 681       if ((opcode_descs[opcode].gens & gen) != 0) {
 682          return &opcode_descs[opcode];
 683       }
 684    } else if (opcode_descs[opcode].table != NULL) {
 685       const struct opcode_desc *table = opcode_descs[opcode].table;
 686       for (unsigned i = 0; i < opcode_descs[opcode].size; i++) {
 687          if ((table[i].gens & gen) != 0) {
 688             return &table[i];
 689          }
 690       }
 691    }
 692    return NULL;
 693 }