src/intel/compiler/brw_eu.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32 #include <sys/stat.h>
  33 #include <fcntl.h>
  34
  35 #include "brw_eu_defines.h"
  36 #include "brw_eu.h"
  37 #include "brw_shader.h"
  38 #include "dev/gen_debug.h"
  39
  40 #include "util/ralloc.h"
  41
  42 /* Returns a conditional modifier that negates the condition. */
  43 enum brw_conditional_mod
  44 brw_negate_cmod(uint32_t cmod)
  45 {
  46    switch (cmod) {
  47    case BRW_CONDITIONAL_Z:
  48       return BRW_CONDITIONAL_NZ;
  49    case BRW_CONDITIONAL_NZ:
  50       return BRW_CONDITIONAL_Z;
  51    case BRW_CONDITIONAL_G:
  52       return BRW_CONDITIONAL_LE;
  53    case BRW_CONDITIONAL_GE:
  54       return BRW_CONDITIONAL_L;
  55    case BRW_CONDITIONAL_L:
  56       return BRW_CONDITIONAL_GE;
  57    case BRW_CONDITIONAL_LE:
  58       return BRW_CONDITIONAL_G;
  59    default:
  60       return ~0;
  61    }
  62 }
  63
  64 /* Returns the corresponding conditional mod for swapping src0 and
  65  * src1 in e.g. CMP.
  66  */
  67 enum brw_conditional_mod
  68 brw_swap_cmod(uint32_t cmod)
  69 {
  70    switch (cmod) {
  71    case BRW_CONDITIONAL_Z:
  72    case BRW_CONDITIONAL_NZ:
  73       return cmod;
  74    case BRW_CONDITIONAL_G:
  75       return BRW_CONDITIONAL_L;
  76    case BRW_CONDITIONAL_GE:
  77       return BRW_CONDITIONAL_LE;
  78    case BRW_CONDITIONAL_L:
  79       return BRW_CONDITIONAL_G;
  80    case BRW_CONDITIONAL_LE:
  81       return BRW_CONDITIONAL_GE;
  82    default:
  83       return BRW_CONDITIONAL_NONE;
  84    }
  85 }
  86
  87 /**
  88  * Get the least significant bit offset of the i+1-th component of immediate
  89  * type \p type.  For \p i equal to the two's complement of j, return the
  90  * offset of the j-th component starting from the end of the vector.  For
  91  * scalar register types return zero.
  92  */
  93 static unsigned
  94 imm_shift(enum brw_reg_type type, unsigned i)
  95 {
  96    assert(type != BRW_REGISTER_TYPE_UV && type != BRW_REGISTER_TYPE_V &&
  97           "Not implemented.");
  98
  99    if (type == BRW_REGISTER_TYPE_VF)
 100       return 8 * (i & 3);
 101    else
 102       return 0;
 103 }
 104
 105 /**
 106  * Swizzle an arbitrary immediate \p x of the given type according to the
 107  * permutation specified as \p swz.
 108  */
 109 uint32_t
 110 brw_swizzle_immediate(enum brw_reg_type type, uint32_t x, unsigned swz)
 111 {
 112    if (imm_shift(type, 1)) {
 113       const unsigned n = 32 / imm_shift(type, 1);
 114       uint32_t y = 0;
 115
 116       for (unsigned i = 0; i < n; i++) {
 117          /* Shift the specified component all the way to the right and left to
 118           * discard any undesired L/MSBs, then shift it right into component i.
 119           */
 120          y |= x >> imm_shift(type, (i & ~3) + BRW_GET_SWZ(swz, i & 3))
 121                 << imm_shift(type, ~0u)
 122                 >> imm_shift(type, ~0u - i);
 123       }
 124
 125       return y;
 126    } else {
 127       return x;
 128    }
 129 }
 130
 131 unsigned
 132 brw_get_default_exec_size(struct brw_codegen *p)
 133 {
 134    return p->current->exec_size;
 135 }
 136
 137 unsigned
 138 brw_get_default_group(struct brw_codegen *p)
 139 {
 140    return p->current->group;
 141 }
 142
 143 unsigned
 144 brw_get_default_access_mode(struct brw_codegen *p)
 145 {
 146    return p->current->access_mode;
 147 }
 148
 149 void
 150 brw_set_default_exec_size(struct brw_codegen *p, unsigned value)
 151 {
 152    p->current->exec_size = value;
 153 }
 154
 155 void brw_set_default_predicate_control( struct brw_codegen *p, unsigned pc )
 156 {
 157    p->current->predicate = pc;
 158 }
 159
 160 void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse)
 161 {
 162    p->current->pred_inv = predicate_inverse;
 163 }
 164
 165 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg)
 166 {
 167    assert(subreg < 2);
 168    p->current->flag_subreg = reg * 2 + subreg;
 169 }
 170
 171 void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode )
 172 {
 173    p->current->access_mode = access_mode;
 174 }
 175
 176 void
 177 brw_set_default_compression_control(struct brw_codegen *p,
 178                             enum brw_compression compression_control)
 179 {
 180    switch (compression_control) {
 181    case BRW_COMPRESSION_NONE:
 182       /* This is the "use the first set of bits of dmask/vmask/arf
 183        * according to execsize" option.
 184        */
 185       p->current->group = 0;
 186       break;
 187    case BRW_COMPRESSION_2NDHALF:
 188       /* For SIMD8, this is "use the second set of 8 bits." */
 189       p->current->group = 8;
 190       break;
 191    case BRW_COMPRESSION_COMPRESSED:
 192       /* For SIMD16 instruction compression, use the first set of 16 bits
 193        * since we don't do SIMD32 dispatch.
 194        */
 195       p->current->group = 0;
 196       break;
 197    default:
 198       unreachable("not reached");
 199    }
 200
 201    if (p->devinfo->gen <= 6) {
 202       p->current->compressed =
 203          (compression_control == BRW_COMPRESSION_COMPRESSED);
 204    }
 205 }
 206
 207 /**
 208  * Enable or disable instruction compression on the given instruction leaving
 209  * the currently selected channel enable group untouched.
 210  */
 211 void
 212 brw_inst_set_compression(const struct gen_device_info *devinfo,
 213                          brw_inst *inst, bool on)
 214 {
 215    if (devinfo->gen >= 6) {
 216       /* No-op, the EU will figure out for us whether the instruction needs to
 217        * be compressed.
 218        */
 219    } else {
 220       /* The channel group and compression controls are non-orthogonal, there
 221        * are two possible representations for uncompressed instructions and we
 222        * may need to preserve the current one to avoid changing the selected
 223        * channel group inadvertently.
 224        */
 225       if (on)
 226          brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_COMPRESSED);
 227       else if (brw_inst_qtr_control(devinfo, inst)
 228                == BRW_COMPRESSION_COMPRESSED)
 229          brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
 230    }
 231 }
 232
 233 void
 234 brw_set_default_compression(struct brw_codegen *p, bool on)
 235 {
 236    p->current->compressed = on;
 237 }
 238
 239 /**
 240  * Apply the range of channel enable signals given by
 241  * [group, group + exec_size) to the instruction passed as argument.
 242  */
 243 void
 244 brw_inst_set_group(const struct gen_device_info *devinfo,
 245                    brw_inst *inst, unsigned group)
 246 {
 247    if (devinfo->gen >= 7) {
 248       assert(group % 4 == 0 && group < 32);
 249       brw_inst_set_qtr_control(devinfo, inst, group / 8);
 250       brw_inst_set_nib_control(devinfo, inst, (group / 4) % 2);
 251
 252    } else if (devinfo->gen == 6) {
 253       assert(group % 8 == 0 && group < 32);
 254       brw_inst_set_qtr_control(devinfo, inst, group / 8);
 255
 256    } else {
 257       assert(group % 8 == 0 && group < 16);
 258       /* The channel group and compression controls are non-orthogonal, there
 259        * are two possible representations for group zero and we may need to
 260        * preserve the current one to avoid changing the selected compression
 261        * enable inadvertently.
 262        */
 263       if (group == 8)
 264          brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_2NDHALF);
 265       else if (brw_inst_qtr_control(devinfo, inst) == BRW_COMPRESSION_2NDHALF)
 266          brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
 267    }
 268 }
 269
 270 void
 271 brw_set_default_group(struct brw_codegen *p, unsigned group)
 272 {
 273    p->current->group = group;
 274 }
 275
 276 void brw_set_default_mask_control( struct brw_codegen *p, unsigned value )
 277 {
 278    p->current->mask_control = value;
 279 }
 280
 281 void brw_set_default_saturate( struct brw_codegen *p, bool enable )
 282 {
 283    p->current->saturate = enable;
 284 }
 285
 286 void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value)
 287 {
 288    p->current->acc_wr_control = value;
 289 }
 290
 291 void brw_push_insn_state( struct brw_codegen *p )
 292 {
 293    assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
 294    *(p->current + 1) = *p->current;
 295    p->current++;
 296 }
 297
 298 void brw_pop_insn_state( struct brw_codegen *p )
 299 {
 300    assert(p->current != p->stack);
 301    p->current--;
 302 }
 303
 304
 305 /***********************************************************************
 306  */
 307 void
 308 brw_init_codegen(const struct gen_device_info *devinfo,
 309                  struct brw_codegen *p, void *mem_ctx)
 310 {
 311    memset(p, 0, sizeof(*p));
 312
 313    p->devinfo = devinfo;
 314    p->automatic_exec_sizes = true;
 315    /*
 316     * Set the initial instruction store array size to 1024, if found that
 317     * isn't enough, then it will double the store size at brw_next_insn()
 318     * until out of memory.
 319     */
 320    p->store_size = 1024;
 321    p->store = rzalloc_array(mem_ctx, brw_inst, p->store_size);
 322    p->nr_insn = 0;
 323    p->current = p->stack;
 324    memset(p->current, 0, sizeof(p->current[0]));
 325
 326    p->mem_ctx = mem_ctx;
 327
 328    /* Some defaults?
 329     */
 330    brw_set_default_exec_size(p, BRW_EXECUTE_8);
 331    brw_set_default_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
 332    brw_set_default_saturate(p, 0);
 333    brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
 334
 335    /* Set up control flow stack */
 336    p->if_stack_depth = 0;
 337    p->if_stack_array_size = 16;
 338    p->if_stack = rzalloc_array(mem_ctx, int, p->if_stack_array_size);
 339
 340    p->loop_stack_depth = 0;
 341    p->loop_stack_array_size = 16;
 342    p->loop_stack = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 343    p->if_depth_in_loop = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 344 }
 345
 346
 347 const unsigned *brw_get_program( struct brw_codegen *p,
 348                                unsigned *sz )
 349 {
 350    *sz = p->next_insn_offset;
 351    return (const unsigned *)p->store;
 352 }
 353
 354 bool brw_try_override_assembly(struct brw_codegen *p, int start_offset,
 355                                const char *identifier)
 356 {
 357    const char *read_path = getenv("INTEL_SHADER_ASM_READ_PATH");
 358    if (!read_path) {
 359       return false;
 360    }
 361
 362    char *name = ralloc_asprintf(NULL, "%s/%s.bin", read_path, identifier);
 363
 364    int fd = open(name, O_RDONLY);
 365    ralloc_free(name);
 366
 367    if (fd == -1) {
 368       return false;
 369    }
 370
 371    struct stat sb;
 372    if (fstat(fd, &sb) != 0 || (!S_ISREG(sb.st_mode))) {
 373       close(fd);
 374       return false;
 375    }
 376
 377    p->nr_insn -= (p->next_insn_offset - start_offset) / sizeof(brw_inst);
 378    p->nr_insn += sb.st_size / sizeof(brw_inst);
 379
 380    p->next_insn_offset = start_offset + sb.st_size;
 381    p->store_size = (start_offset + sb.st_size) / sizeof(brw_inst);
 382    p->store = reralloc_size(p->mem_ctx, p->store, p->next_insn_offset);
 383    assert(p->store);
 384
 385    read(fd, p->store + start_offset, sb.st_size);
 386    close(fd);
 387
 388    bool valid = brw_validate_instructions(p->devinfo, p->store,
 389                                           start_offset, p->next_insn_offset,
 390                                           0);
 391    assert(valid);
 392
 393    return true;
 394 }
 395
 396 void
 397 brw_disassemble(const struct gen_device_info *devinfo,
 398                 const void *assembly, int start, int end, FILE *out)
 399 {
 400    bool dump_hex = (INTEL_DEBUG & DEBUG_HEX) != 0;
 401
 402    for (int offset = start; offset < end;) {
 403       const brw_inst *insn = assembly + offset;
 404       brw_inst uncompacted;
 405       bool compacted = brw_inst_cmpt_control(devinfo, insn);
 406       if (0)
 407          fprintf(out, "0x%08x: ", offset);
 408
 409       if (compacted) {
 410          brw_compact_inst *compacted = (void *)insn;
 411          if (dump_hex) {
 412             unsigned char * insn_ptr = ((unsigned char *)&insn[0]);
 413             const unsigned int blank_spaces = 24;
 414             for (int i = 0 ; i < 8; i = i + 4) {
 415                fprintf(out, "%02x %02x %02x %02x ",
 416                        insn_ptr[i],
 417                        insn_ptr[i + 1],
 418                        insn_ptr[i + 2],
 419                        insn_ptr[i + 3]);
 420             }
 421             /* Make compacted instructions hex value output vertically aligned
 422              * with uncompacted instructions hex value
 423              */
 424             fprintf(out, "%*c", blank_spaces, ' ');
 425          }
 426
 427          brw_uncompact_instruction(devinfo, &uncompacted, compacted);
 428          insn = &uncompacted;
 429          offset += 8;
 430       } else {
 431          if (dump_hex) {
 432             unsigned char * insn_ptr = ((unsigned char *)&insn[0]);
 433             for (int i = 0 ; i < 16; i = i + 4) {
 434                fprintf(out, "%02x %02x %02x %02x ",
 435                        insn_ptr[i],
 436                        insn_ptr[i + 1],
 437                        insn_ptr[i + 2],
 438                        insn_ptr[i + 3]);
 439             }
 440          }
 441          offset += 16;
 442       }
 443
 444       brw_disassemble_inst(out, devinfo, insn, compacted);
 445    }
 446 }
 447
 448 enum gen {
 449    GEN4  = (1 << 0),
 450    GEN45 = (1 << 1),
 451    GEN5  = (1 << 2),
 452    GEN6  = (1 << 3),
 453    GEN7  = (1 << 4),
 454    GEN75 = (1 << 5),
 455    GEN8  = (1 << 6),
 456    GEN9  = (1 << 7),
 457    GEN10 = (1 << 8),
 458    GEN11 = (1 << 9),
 459    GEN_ALL = ~0
 460 };
 461
 462 #define GEN_LT(gen) ((gen) - 1)
 463 #define GEN_GE(gen) (~GEN_LT(gen))
 464 #define GEN_LE(gen) (GEN_LT(gen) | (gen))
 465
 466 static const struct opcode_desc opcode_10_descs[] = {
 467    { .name = "dim",   .nsrc = 1, .ndst = 1, .gens = GEN75 },
 468    { .name = "smov",  .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN8) },
 469 };
 470
 471 static const struct opcode_desc opcode_35_descs[] = {
 472    { .name = "iff",   .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 473    { .name = "brc",   .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN7) },
 474 };
 475
 476 static const struct opcode_desc opcode_38_descs[] = {
 477    { .name = "do",    .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 478    { .name = "case",  .nsrc = 0, .ndst = 0, .gens = GEN6 },
 479 };
 480
 481 static const struct opcode_desc opcode_44_descs[] = {
 482    { .name = "msave", .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 483    { .name = "call",  .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN6) },
 484 };
 485
 486 static const struct opcode_desc opcode_45_descs[] = {
 487    { .name = "mrest", .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 488    { .name = "ret",   .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN6) },
 489 };
 490
 491 static const struct opcode_desc opcode_46_descs[] = {
 492    { .name = "push",  .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 493    { .name = "fork",  .nsrc = 0, .ndst = 0, .gens = GEN6 },
 494    { .name = "goto",  .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN8) },
 495 };
 496
 497 static const struct opcode_desc opcode_descs[128] = {
 498    [BRW_OPCODE_ILLEGAL] = {
 499       .name = "illegal", .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 500    },
 501    [BRW_OPCODE_MOV] = {
 502       .name = "mov",     .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 503    },
 504    [BRW_OPCODE_SEL] = {
 505       .name = "sel",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 506    },
 507    [BRW_OPCODE_MOVI] = {
 508       .name = "movi",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN45),
 509    },
 510    [BRW_OPCODE_NOT] = {
 511       .name = "not",     .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 512    },
 513    [BRW_OPCODE_AND] = {
 514       .name = "and",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 515    },
 516    [BRW_OPCODE_OR] = {
 517       .name = "or",      .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 518    },
 519    [BRW_OPCODE_XOR] = {
 520       .name = "xor",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 521    },
 522    [BRW_OPCODE_SHR] = {
 523       .name = "shr",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 524    },
 525    [BRW_OPCODE_SHL] = {
 526       .name = "shl",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 527    },
 528    [10] = {
 529       .table = opcode_10_descs, .size = ARRAY_SIZE(opcode_10_descs),
 530    },
 531    /* Reserved - 11 */
 532    [BRW_OPCODE_ASR] = {
 533       .name = "asr",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 534    },
 535    /* Reserved - 13 */
 536    [BRW_OPCODE_ROR] = {
 537       .name = "ror",     .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN11),
 538    },
 539    [BRW_OPCODE_ROL] = {
 540       .name = "rol",     .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN11),
 541    },
 542    [BRW_OPCODE_CMP] = {
 543       .name = "cmp",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 544    },
 545    [BRW_OPCODE_CMPN] = {
 546       .name = "cmpn",    .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 547    },
 548    [BRW_OPCODE_CSEL] = {
 549       .name = "csel",    .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN8),
 550    },
 551    [BRW_OPCODE_F32TO16] = {
 552       .name = "f32to16", .nsrc = 1, .ndst = 1, .gens = GEN7 | GEN75,
 553    },
 554    [BRW_OPCODE_F16TO32] = {
 555       .name = "f16to32", .nsrc = 1, .ndst = 1, .gens = GEN7 | GEN75,
 556    },
 557    /* Reserved - 21-22 */
 558    [BRW_OPCODE_BFREV] = {
 559       .name = "bfrev",   .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
 560    },
 561    [BRW_OPCODE_BFE] = {
 562       .name = "bfe",     .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN7),
 563    },
 564    [BRW_OPCODE_BFI1] = {
 565       .name = "bfi1",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7),
 566    },
 567    [BRW_OPCODE_BFI2] = {
 568       .name = "bfi2",    .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN7),
 569    },
 570    /* Reserved - 27-31 */
 571    [BRW_OPCODE_JMPI] = {
 572       .name = "jmpi",    .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 573    },
 574    [33] = {
 575       .name = "brd",     .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN7),
 576    },
 577    [BRW_OPCODE_IF] = {
 578       .name = "if",      .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 579    },
 580    [35] = {
 581       .table = opcode_35_descs, .size = ARRAY_SIZE(opcode_35_descs),
 582    },
 583    [BRW_OPCODE_ELSE] = {
 584       .name = "else",    .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 585    },
 586    [BRW_OPCODE_ENDIF] = {
 587       .name = "endif",   .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 588    },
 589    [38] = {
 590       .table = opcode_38_descs, .size = ARRAY_SIZE(opcode_38_descs),
 591    },
 592    [BRW_OPCODE_WHILE] = {
 593       .name = "while",   .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 594    },
 595    [BRW_OPCODE_BREAK] = {
 596       .name = "break",   .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 597    },
 598    [BRW_OPCODE_CONTINUE] = {
 599       .name = "cont",    .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 600    },
 601    [BRW_OPCODE_HALT] = {
 602       .name = "halt",    .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 603    },
 604    [43] = {
 605       .name = "calla",   .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN75),
 606    },
 607    [44] = {
 608       .table = opcode_44_descs, .size = ARRAY_SIZE(opcode_44_descs),
 609    },
 610    [45] = {
 611       .table = opcode_45_descs, .size = ARRAY_SIZE(opcode_45_descs),
 612    },
 613    [46] = {
 614       .table = opcode_46_descs, .size = ARRAY_SIZE(opcode_46_descs),
 615    },
 616    [47] = {
 617       .name = "pop",     .nsrc = 2, .ndst = 0, .gens = GEN_LE(GEN5),
 618    },
 619    [BRW_OPCODE_WAIT] = {
 620       .name = "wait",    .nsrc = 1, .ndst = 0, .gens = GEN_ALL,
 621    },
 622    [BRW_OPCODE_SEND] = {
 623       .name = "send",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 624    },
 625    [BRW_OPCODE_SENDC] = {
 626       .name = "sendc",   .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 627    },
 628    [BRW_OPCODE_SENDS] = {
 629       .name = "sends",   .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN9),
 630    },
 631    [BRW_OPCODE_SENDSC] = {
 632       .name = "sendsc",  .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN9),
 633    },
 634    /* Reserved 53-55 */
 635    [BRW_OPCODE_MATH] = {
 636       .name = "math",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN6),
 637    },
 638    /* Reserved 57-63 */
 639    [BRW_OPCODE_ADD] = {
 640       .name = "add",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 641    },
 642    [BRW_OPCODE_MUL] = {
 643       .name = "mul",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 644    },
 645    [BRW_OPCODE_AVG] = {
 646       .name = "avg",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 647    },
 648    [BRW_OPCODE_FRC] = {
 649       .name = "frc",     .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 650    },
 651    [BRW_OPCODE_RNDU] = {
 652       .name = "rndu",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 653    },
 654    [BRW_OPCODE_RNDD] = {
 655       .name = "rndd",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 656    },
 657    [BRW_OPCODE_RNDE] = {
 658       .name = "rnde",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 659    },
 660    [BRW_OPCODE_RNDZ] = {
 661       .name = "rndz",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 662    },
 663    [BRW_OPCODE_MAC] = {
 664       .name = "mac",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 665    },
 666    [BRW_OPCODE_MACH] = {
 667       .name = "mach",    .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 668    },
 669    [BRW_OPCODE_LZD] = {
 670       .name = "lzd",     .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 671    },
 672    [BRW_OPCODE_FBH] = {
 673       .name = "fbh",     .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
 674    },
 675    [BRW_OPCODE_FBL] = {
 676       .name = "fbl",     .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
 677    },
 678    [BRW_OPCODE_CBIT] = {
 679       .name = "cbit",    .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
 680    },
 681    [BRW_OPCODE_ADDC] = {
 682       .name = "addc",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7),
 683    },
 684    [BRW_OPCODE_SUBB] = {
 685       .name = "subb",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7),
 686    },
 687    [BRW_OPCODE_SAD2] = {
 688       .name = "sad2",    .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 689    },
 690    [BRW_OPCODE_SADA2] = {
 691       .name = "sada2",   .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 692    },
 693    /* Reserved 82-83 */
 694    [BRW_OPCODE_DP4] = {
 695       .name = "dp4",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 696    },
 697    [BRW_OPCODE_DPH] = {
 698       .name = "dph",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 699    },
 700    [BRW_OPCODE_DP3] = {
 701       .name = "dp3",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 702    },
 703    [BRW_OPCODE_DP2] = {
 704       .name = "dp2",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 705    },
 706    /* Reserved 88 */
 707    [BRW_OPCODE_LINE] = {
 708       .name = "line",    .nsrc = 2, .ndst = 1, .gens = GEN_LE(GEN10),
 709    },
 710    [BRW_OPCODE_PLN] = {
 711       .name = "pln",     .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN45) & GEN_LE(GEN10),
 712    },
 713    [BRW_OPCODE_MAD] = {
 714       .name = "mad",     .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN6),
 715    },
 716    [BRW_OPCODE_LRP] = {
 717       .name = "lrp",     .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN6) & GEN_LE(GEN10),
 718    },
 719    [93] = {
 720       .name = "madm",    .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN8),
 721    },
 722    /* Reserved 94-124 */
 723    [BRW_OPCODE_NENOP] = {
 724       .name = "nenop",   .nsrc = 0, .ndst = 0, .gens = GEN45,
 725    },
 726    [BRW_OPCODE_NOP] = {
 727       .name = "nop",     .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 728    },
 729 };
 730
 731 static enum gen
 732 gen_from_devinfo(const struct gen_device_info *devinfo)
 733 {
 734    switch (devinfo->gen) {
 735    case 4: return devinfo->is_g4x ? GEN45 : GEN4;
 736    case 5: return GEN5;
 737    case 6: return GEN6;
 738    case 7: return devinfo->is_haswell ? GEN75 : GEN7;
 739    case 8: return GEN8;
 740    case 9: return GEN9;
 741    case 10: return GEN10;
 742    case 11: return GEN11;
 743    default:
 744       unreachable("not reached");
 745    }
 746 }
 747
 748 /* Return the matching opcode_desc for the specified opcode number and
 749  * hardware generation, or NULL if the opcode is not supported by the device.
 750  */
 751 const struct opcode_desc *
 752 brw_opcode_desc(const struct gen_device_info *devinfo, enum opcode opcode)
 753 {
 754    if (opcode >= ARRAY_SIZE(opcode_descs))
 755       return NULL;
 756
 757    enum gen gen = gen_from_devinfo(devinfo);
 758    if (opcode_descs[opcode].gens != 0) {
 759       if ((opcode_descs[opcode].gens & gen) != 0) {
 760          return &opcode_descs[opcode];
 761       }
 762    } else if (opcode_descs[opcode].table != NULL) {
 763       const struct opcode_desc *table = opcode_descs[opcode].table;
 764       for (unsigned i = 0; i < opcode_descs[opcode].size; i++) {
 765          if ((table[i].gens & gen) != 0) {
 766             return &table[i];
 767          }
 768       }
 769    }
 770    return NULL;
 771 }