src/intel/compiler/brw_eu.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33 #include "brw_eu_defines.h"
  34 #include "brw_eu.h"
  35 #include "brw_shader.h"
  36 #include "common/gen_debug.h"
  37
  38 #include "util/ralloc.h"
  39
  40 /* Returns a conditional modifier that negates the condition. */
  41 enum brw_conditional_mod
  42 brw_negate_cmod(uint32_t cmod)
  43 {
  44    switch (cmod) {
  45    case BRW_CONDITIONAL_Z:
  46       return BRW_CONDITIONAL_NZ;
  47    case BRW_CONDITIONAL_NZ:
  48       return BRW_CONDITIONAL_Z;
  49    case BRW_CONDITIONAL_G:
  50       return BRW_CONDITIONAL_LE;
  51    case BRW_CONDITIONAL_GE:
  52       return BRW_CONDITIONAL_L;
  53    case BRW_CONDITIONAL_L:
  54       return BRW_CONDITIONAL_GE;
  55    case BRW_CONDITIONAL_LE:
  56       return BRW_CONDITIONAL_G;
  57    default:
  58       return ~0;
  59    }
  60 }
  61
  62 /* Returns the corresponding conditional mod for swapping src0 and
  63  * src1 in e.g. CMP.
  64  */
  65 enum brw_conditional_mod
  66 brw_swap_cmod(uint32_t cmod)
  67 {
  68    switch (cmod) {
  69    case BRW_CONDITIONAL_Z:
  70    case BRW_CONDITIONAL_NZ:
  71       return cmod;
  72    case BRW_CONDITIONAL_G:
  73       return BRW_CONDITIONAL_L;
  74    case BRW_CONDITIONAL_GE:
  75       return BRW_CONDITIONAL_LE;
  76    case BRW_CONDITIONAL_L:
  77       return BRW_CONDITIONAL_G;
  78    case BRW_CONDITIONAL_LE:
  79       return BRW_CONDITIONAL_GE;
  80    default:
  81       return BRW_CONDITIONAL_NONE;
  82    }
  83 }
  84
  85 /**
  86  * Get the least significant bit offset of the i+1-th component of immediate
  87  * type \p type.  For \p i equal to the two's complement of j, return the
  88  * offset of the j-th component starting from the end of the vector.  For
  89  * scalar register types return zero.
  90  */
  91 static unsigned
  92 imm_shift(enum brw_reg_type type, unsigned i)
  93 {
  94    assert(type != BRW_REGISTER_TYPE_UV && type != BRW_REGISTER_TYPE_V &&
  95           "Not implemented.");
  96
  97    if (type == BRW_REGISTER_TYPE_VF)
  98       return 8 * (i & 3);
  99    else
 100       return 0;
 101 }
 102
 103 /**
 104  * Swizzle an arbitrary immediate \p x of the given type according to the
 105  * permutation specified as \p swz.
 106  */
 107 uint32_t
 108 brw_swizzle_immediate(enum brw_reg_type type, uint32_t x, unsigned swz)
 109 {
 110    if (imm_shift(type, 1)) {
 111       const unsigned n = 32 / imm_shift(type, 1);
 112       uint32_t y = 0;
 113
 114       for (unsigned i = 0; i < n; i++) {
 115          /* Shift the specified component all the way to the right and left to
 116           * discard any undesired L/MSBs, then shift it right into component i.
 117           */
 118          y |= x >> imm_shift(type, (i & ~3) + BRW_GET_SWZ(swz, i & 3))
 119                 << imm_shift(type, ~0u)
 120                 >> imm_shift(type, ~0u - i);
 121       }
 122
 123       return y;
 124    } else {
 125       return x;
 126    }
 127 }
 128
 129 void
 130 brw_set_default_exec_size(struct brw_codegen *p, unsigned value)
 131 {
 132    brw_inst_set_exec_size(p->devinfo, p->current, value);
 133 }
 134
 135 void brw_set_default_predicate_control( struct brw_codegen *p, unsigned pc )
 136 {
 137    brw_inst_set_pred_control(p->devinfo, p->current, pc);
 138 }
 139
 140 void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse)
 141 {
 142    brw_inst_set_pred_inv(p->devinfo, p->current, predicate_inverse);
 143 }
 144
 145 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg)
 146 {
 147    if (p->devinfo->gen >= 7)
 148       brw_inst_set_flag_reg_nr(p->devinfo, p->current, reg);
 149
 150    brw_inst_set_flag_subreg_nr(p->devinfo, p->current, subreg);
 151 }
 152
 153 void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode )
 154 {
 155    brw_inst_set_access_mode(p->devinfo, p->current, access_mode);
 156 }
 157
 158 void
 159 brw_set_default_compression_control(struct brw_codegen *p,
 160                             enum brw_compression compression_control)
 161 {
 162    if (p->devinfo->gen >= 6) {
 163       /* Since we don't use the SIMD32 support in gen6, we translate
 164        * the pre-gen6 compression control here.
 165        */
 166       switch (compression_control) {
 167       case BRW_COMPRESSION_NONE:
 168          /* This is the "use the first set of bits of dmask/vmask/arf
 169           * according to execsize" option.
 170           */
 171          brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_1Q);
 172          break;
 173       case BRW_COMPRESSION_2NDHALF:
 174          /* For SIMD8, this is "use the second set of 8 bits." */
 175          brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_2Q);
 176          break;
 177       case BRW_COMPRESSION_COMPRESSED:
 178          /* For SIMD16 instruction compression, use the first set of 16 bits
 179           * since we don't do SIMD32 dispatch.
 180           */
 181          brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_1H);
 182          break;
 183       default:
 184          unreachable("not reached");
 185       }
 186    } else {
 187       brw_inst_set_qtr_control(p->devinfo, p->current, compression_control);
 188    }
 189 }
 190
 191 /**
 192  * Enable or disable instruction compression on the given instruction leaving
 193  * the currently selected channel enable group untouched.
 194  */
 195 void
 196 brw_inst_set_compression(const struct gen_device_info *devinfo,
 197                          brw_inst *inst, bool on)
 198 {
 199    if (devinfo->gen >= 6) {
 200       /* No-op, the EU will figure out for us whether the instruction needs to
 201        * be compressed.
 202        */
 203    } else {
 204       /* The channel group and compression controls are non-orthogonal, there
 205        * are two possible representations for uncompressed instructions and we
 206        * may need to preserve the current one to avoid changing the selected
 207        * channel group inadvertently.
 208        */
 209       if (on)
 210          brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_COMPRESSED);
 211       else if (brw_inst_qtr_control(devinfo, inst)
 212                == BRW_COMPRESSION_COMPRESSED)
 213          brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
 214    }
 215 }
 216
 217 void
 218 brw_set_default_compression(struct brw_codegen *p, bool on)
 219 {
 220    brw_inst_set_compression(p->devinfo, p->current, on);
 221 }
 222
 223 /**
 224  * Apply the range of channel enable signals given by
 225  * [group, group + exec_size) to the instruction passed as argument.
 226  */
 227 void
 228 brw_inst_set_group(const struct gen_device_info *devinfo,
 229                    brw_inst *inst, unsigned group)
 230 {
 231    if (devinfo->gen >= 7) {
 232       assert(group % 4 == 0 && group < 32);
 233       brw_inst_set_qtr_control(devinfo, inst, group / 8);
 234       brw_inst_set_nib_control(devinfo, inst, (group / 4) % 2);
 235
 236    } else if (devinfo->gen == 6) {
 237       assert(group % 8 == 0 && group < 32);
 238       brw_inst_set_qtr_control(devinfo, inst, group / 8);
 239
 240    } else {
 241       assert(group % 8 == 0 && group < 16);
 242       /* The channel group and compression controls are non-orthogonal, there
 243        * are two possible representations for group zero and we may need to
 244        * preserve the current one to avoid changing the selected compression
 245        * enable inadvertently.
 246        */
 247       if (group == 8)
 248          brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_2NDHALF);
 249       else if (brw_inst_qtr_control(devinfo, inst) == BRW_COMPRESSION_2NDHALF)
 250          brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
 251    }
 252 }
 253
 254 void
 255 brw_set_default_group(struct brw_codegen *p, unsigned group)
 256 {
 257    brw_inst_set_group(p->devinfo, p->current, group);
 258 }
 259
 260 void brw_set_default_mask_control( struct brw_codegen *p, unsigned value )
 261 {
 262    brw_inst_set_mask_control(p->devinfo, p->current, value);
 263 }
 264
 265 void brw_set_default_saturate( struct brw_codegen *p, bool enable )
 266 {
 267    brw_inst_set_saturate(p->devinfo, p->current, enable);
 268 }
 269
 270 void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value)
 271 {
 272    if (p->devinfo->gen >= 6)
 273       brw_inst_set_acc_wr_control(p->devinfo, p->current, value);
 274 }
 275
 276 void brw_push_insn_state( struct brw_codegen *p )
 277 {
 278    assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
 279    memcpy(p->current + 1, p->current, sizeof(brw_inst));
 280    p->current++;
 281 }
 282
 283 void brw_pop_insn_state( struct brw_codegen *p )
 284 {
 285    assert(p->current != p->stack);
 286    p->current--;
 287 }
 288
 289
 290 /***********************************************************************
 291  */
 292 void
 293 brw_init_codegen(const struct gen_device_info *devinfo,
 294                  struct brw_codegen *p, void *mem_ctx)
 295 {
 296    memset(p, 0, sizeof(*p));
 297
 298    p->devinfo = devinfo;
 299    /*
 300     * Set the initial instruction store array size to 1024, if found that
 301     * isn't enough, then it will double the store size at brw_next_insn()
 302     * until out of memory.
 303     */
 304    p->store_size = 1024;
 305    p->store = rzalloc_array(mem_ctx, brw_inst, p->store_size);
 306    p->nr_insn = 0;
 307    p->current = p->stack;
 308    memset(p->current, 0, sizeof(p->current[0]));
 309
 310    p->mem_ctx = mem_ctx;
 311
 312    /* Some defaults?
 313     */
 314    brw_set_default_exec_size(p, BRW_EXECUTE_8);
 315    brw_set_default_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
 316    brw_set_default_saturate(p, 0);
 317    brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
 318
 319    /* Set up control flow stack */
 320    p->if_stack_depth = 0;
 321    p->if_stack_array_size = 16;
 322    p->if_stack = rzalloc_array(mem_ctx, int, p->if_stack_array_size);
 323
 324    p->loop_stack_depth = 0;
 325    p->loop_stack_array_size = 16;
 326    p->loop_stack = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 327    p->if_depth_in_loop = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 328 }
 329
 330
 331 const unsigned *brw_get_program( struct brw_codegen *p,
 332                                unsigned *sz )
 333 {
 334    *sz = p->next_insn_offset;
 335    return (const unsigned *)p->store;
 336 }
 337
 338 void
 339 brw_disassemble(const struct gen_device_info *devinfo,
 340                 const void *assembly, int start, int end, FILE *out)
 341 {
 342    bool dump_hex = (INTEL_DEBUG & DEBUG_HEX) != 0;
 343
 344    for (int offset = start; offset < end;) {
 345       const brw_inst *insn = assembly + offset;
 346       brw_inst uncompacted;
 347       bool compacted = brw_inst_cmpt_control(devinfo, insn);
 348       if (0)
 349          fprintf(out, "0x%08x: ", offset);
 350
 351       if (compacted) {
 352          brw_compact_inst *compacted = (void *)insn;
 353          if (dump_hex) {
 354             fprintf(out, "0x%08x 0x%08x                       ",
 355                     ((uint32_t *)insn)[1],
 356                     ((uint32_t *)insn)[0]);
 357          }
 358
 359          brw_uncompact_instruction(devinfo, &uncompacted, compacted);
 360          insn = &uncompacted;
 361          offset += 8;
 362       } else {
 363          if (dump_hex) {
 364             fprintf(out, "0x%08x 0x%08x 0x%08x 0x%08x ",
 365                     ((uint32_t *)insn)[3],
 366                     ((uint32_t *)insn)[2],
 367                     ((uint32_t *)insn)[1],
 368                     ((uint32_t *)insn)[0]);
 369          }
 370          offset += 16;
 371       }
 372
 373       brw_disassemble_inst(out, devinfo, insn, compacted);
 374    }
 375 }
 376
 377 enum gen {
 378    GEN4  = (1 << 0),
 379    GEN45 = (1 << 1),
 380    GEN5  = (1 << 2),
 381    GEN6  = (1 << 3),
 382    GEN7  = (1 << 4),
 383    GEN75 = (1 << 5),
 384    GEN8  = (1 << 6),
 385    GEN9  = (1 << 7),
 386    GEN10  = (1 << 8),
 387    GEN_ALL = ~0
 388 };
 389
 390 #define GEN_LT(gen) ((gen) - 1)
 391 #define GEN_GE(gen) (~GEN_LT(gen))
 392 #define GEN_LE(gen) (GEN_LT(gen) | (gen))
 393
 394 static const struct opcode_desc opcode_10_descs[] = {
 395    { .name = "dim",   .nsrc = 1, .ndst = 1, .gens = GEN75 },
 396    { .name = "smov",  .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN8) },
 397 };
 398
 399 static const struct opcode_desc opcode_35_descs[] = {
 400    { .name = "iff",   .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 401    { .name = "brc",   .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN7) },
 402 };
 403
 404 static const struct opcode_desc opcode_38_descs[] = {
 405    { .name = "do",    .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 406    { .name = "case",  .nsrc = 0, .ndst = 0, .gens = GEN6 },
 407 };
 408
 409 static const struct opcode_desc opcode_44_descs[] = {
 410    { .name = "msave", .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 411    { .name = "call",  .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN6) },
 412 };
 413
 414 static const struct opcode_desc opcode_45_descs[] = {
 415    { .name = "mrest", .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 416    { .name = "ret",   .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN6) },
 417 };
 418
 419 static const struct opcode_desc opcode_46_descs[] = {
 420    { .name = "push",  .nsrc = 0, .ndst = 0, .gens = GEN_LE(GEN5) },
 421    { .name = "fork",  .nsrc = 0, .ndst = 0, .gens = GEN6 },
 422    { .name = "goto",  .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN8) },
 423 };
 424
 425 static const struct opcode_desc opcode_descs[128] = {
 426    [BRW_OPCODE_ILLEGAL] = {
 427       .name = "illegal", .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 428    },
 429    [BRW_OPCODE_MOV] = {
 430       .name = "mov",     .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 431    },
 432    [BRW_OPCODE_SEL] = {
 433       .name = "sel",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 434    },
 435    [BRW_OPCODE_MOVI] = {
 436       .name = "movi",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN45),
 437    },
 438    [BRW_OPCODE_NOT] = {
 439       .name = "not",     .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 440    },
 441    [BRW_OPCODE_AND] = {
 442       .name = "and",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 443    },
 444    [BRW_OPCODE_OR] = {
 445       .name = "or",      .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 446    },
 447    [BRW_OPCODE_XOR] = {
 448       .name = "xor",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 449    },
 450    [BRW_OPCODE_SHR] = {
 451       .name = "shr",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 452    },
 453    [BRW_OPCODE_SHL] = {
 454       .name = "shl",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 455    },
 456    [10] = {
 457       .table = opcode_10_descs, .size = ARRAY_SIZE(opcode_10_descs),
 458    },
 459    /* Reserved - 11 */
 460    [BRW_OPCODE_ASR] = {
 461       .name = "asr",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 462    },
 463    /* Reserved - 13-15 */
 464    [BRW_OPCODE_CMP] = {
 465       .name = "cmp",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 466    },
 467    [BRW_OPCODE_CMPN] = {
 468       .name = "cmpn",    .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 469    },
 470    [BRW_OPCODE_CSEL] = {
 471       .name = "csel",    .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN8),
 472    },
 473    [BRW_OPCODE_F32TO16] = {
 474       .name = "f32to16", .nsrc = 1, .ndst = 1, .gens = GEN7 | GEN75,
 475    },
 476    [BRW_OPCODE_F16TO32] = {
 477       .name = "f16to32", .nsrc = 1, .ndst = 1, .gens = GEN7 | GEN75,
 478    },
 479    /* Reserved - 21-22 */
 480    [BRW_OPCODE_BFREV] = {
 481       .name = "bfrev",   .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
 482    },
 483    [BRW_OPCODE_BFE] = {
 484       .name = "bfe",     .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN7),
 485    },
 486    [BRW_OPCODE_BFI1] = {
 487       .name = "bfi1",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7),
 488    },
 489    [BRW_OPCODE_BFI2] = {
 490       .name = "bfi2",    .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN7),
 491    },
 492    /* Reserved - 27-31 */
 493    [BRW_OPCODE_JMPI] = {
 494       .name = "jmpi",    .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 495    },
 496    [33] = {
 497       .name = "brd",     .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN7),
 498    },
 499    [BRW_OPCODE_IF] = {
 500       .name = "if",      .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 501    },
 502    [35] = {
 503       .table = opcode_35_descs, .size = ARRAY_SIZE(opcode_35_descs),
 504    },
 505    [BRW_OPCODE_ELSE] = {
 506       .name = "else",    .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 507    },
 508    [BRW_OPCODE_ENDIF] = {
 509       .name = "endif",   .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 510    },
 511    [38] = {
 512       .table = opcode_38_descs, .size = ARRAY_SIZE(opcode_38_descs),
 513    },
 514    [BRW_OPCODE_WHILE] = {
 515       .name = "while",   .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 516    },
 517    [BRW_OPCODE_BREAK] = {
 518       .name = "break",   .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 519    },
 520    [BRW_OPCODE_CONTINUE] = {
 521       .name = "cont",    .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 522    },
 523    [BRW_OPCODE_HALT] = {
 524       .name = "halt",    .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 525    },
 526    [43] = {
 527       .name = "calla",   .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN75),
 528    },
 529    [44] = {
 530       .table = opcode_44_descs, .size = ARRAY_SIZE(opcode_44_descs),
 531    },
 532    [45] = {
 533       .table = opcode_45_descs, .size = ARRAY_SIZE(opcode_45_descs),
 534    },
 535    [46] = {
 536       .table = opcode_46_descs, .size = ARRAY_SIZE(opcode_46_descs),
 537    },
 538    [47] = {
 539       .name = "pop",     .nsrc = 2, .ndst = 0, .gens = GEN_LE(GEN5),
 540    },
 541    [BRW_OPCODE_WAIT] = {
 542       .name = "wait",    .nsrc = 1, .ndst = 0, .gens = GEN_ALL,
 543    },
 544    [BRW_OPCODE_SEND] = {
 545       .name = "send",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 546    },
 547    [BRW_OPCODE_SENDC] = {
 548       .name = "sendc",   .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 549    },
 550    [BRW_OPCODE_SENDS] = {
 551       .name = "sends",   .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN9),
 552    },
 553    [BRW_OPCODE_SENDSC] = {
 554       .name = "sendsc",  .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN9),
 555    },
 556    /* Reserved 53-55 */
 557    [BRW_OPCODE_MATH] = {
 558       .name = "math",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN6),
 559    },
 560    /* Reserved 57-63 */
 561    [BRW_OPCODE_ADD] = {
 562       .name = "add",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 563    },
 564    [BRW_OPCODE_MUL] = {
 565       .name = "mul",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 566    },
 567    [BRW_OPCODE_AVG] = {
 568       .name = "avg",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 569    },
 570    [BRW_OPCODE_FRC] = {
 571       .name = "frc",     .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 572    },
 573    [BRW_OPCODE_RNDU] = {
 574       .name = "rndu",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 575    },
 576    [BRW_OPCODE_RNDD] = {
 577       .name = "rndd",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 578    },
 579    [BRW_OPCODE_RNDE] = {
 580       .name = "rnde",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 581    },
 582    [BRW_OPCODE_RNDZ] = {
 583       .name = "rndz",    .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 584    },
 585    [BRW_OPCODE_MAC] = {
 586       .name = "mac",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 587    },
 588    [BRW_OPCODE_MACH] = {
 589       .name = "mach",    .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 590    },
 591    [BRW_OPCODE_LZD] = {
 592       .name = "lzd",     .nsrc = 1, .ndst = 1, .gens = GEN_ALL,
 593    },
 594    [BRW_OPCODE_FBH] = {
 595       .name = "fbh",     .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
 596    },
 597    [BRW_OPCODE_FBL] = {
 598       .name = "fbl",     .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
 599    },
 600    [BRW_OPCODE_CBIT] = {
 601       .name = "cbit",    .nsrc = 1, .ndst = 1, .gens = GEN_GE(GEN7),
 602    },
 603    [BRW_OPCODE_ADDC] = {
 604       .name = "addc",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7),
 605    },
 606    [BRW_OPCODE_SUBB] = {
 607       .name = "subb",    .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN7),
 608    },
 609    [BRW_OPCODE_SAD2] = {
 610       .name = "sad2",    .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 611    },
 612    [BRW_OPCODE_SADA2] = {
 613       .name = "sada2",   .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 614    },
 615    /* Reserved 82-83 */
 616    [BRW_OPCODE_DP4] = {
 617       .name = "dp4",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 618    },
 619    [BRW_OPCODE_DPH] = {
 620       .name = "dph",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 621    },
 622    [BRW_OPCODE_DP3] = {
 623       .name = "dp3",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 624    },
 625    [BRW_OPCODE_DP2] = {
 626       .name = "dp2",     .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 627    },
 628    /* Reserved 88 */
 629    [BRW_OPCODE_LINE] = {
 630       .name = "line",    .nsrc = 2, .ndst = 1, .gens = GEN_ALL,
 631    },
 632    [BRW_OPCODE_PLN] = {
 633       .name = "pln",     .nsrc = 2, .ndst = 1, .gens = GEN_GE(GEN45),
 634    },
 635    [BRW_OPCODE_MAD] = {
 636       .name = "mad",     .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN6),
 637    },
 638    [BRW_OPCODE_LRP] = {
 639       .name = "lrp",     .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN6),
 640    },
 641    [93] = {
 642       .name = "madm",    .nsrc = 3, .ndst = 1, .gens = GEN_GE(GEN8),
 643    },
 644    /* Reserved 94-124 */
 645    [BRW_OPCODE_NENOP] = {
 646       .name = "nenop",   .nsrc = 0, .ndst = 0, .gens = GEN45,
 647    },
 648    [BRW_OPCODE_NOP] = {
 649       .name = "nop",     .nsrc = 0, .ndst = 0, .gens = GEN_ALL,
 650    },
 651 };
 652
 653 static enum gen
 654 gen_from_devinfo(const struct gen_device_info *devinfo)
 655 {
 656    switch (devinfo->gen) {
 657    case 4: return devinfo->is_g4x ? GEN45 : GEN4;
 658    case 5: return GEN5;
 659    case 6: return GEN6;
 660    case 7: return devinfo->is_haswell ? GEN75 : GEN7;
 661    case 8: return GEN8;
 662    case 9: return GEN9;
 663    case 10: return GEN10;
 664    default:
 665       unreachable("not reached");
 666    }
 667 }
 668
 669 /* Return the matching opcode_desc for the specified opcode number and
 670  * hardware generation, or NULL if the opcode is not supported by the device.
 671  */
 672 const struct opcode_desc *
 673 brw_opcode_desc(const struct gen_device_info *devinfo, enum opcode opcode)
 674 {
 675    if (opcode >= ARRAY_SIZE(opcode_descs))
 676       return NULL;
 677
 678    enum gen gen = gen_from_devinfo(devinfo);
 679    if (opcode_descs[opcode].gens != 0) {
 680       if ((opcode_descs[opcode].gens & gen) != 0) {
 681          return &opcode_descs[opcode];
 682       }
 683    } else if (opcode_descs[opcode].table != NULL) {
 684       const struct opcode_desc *table = opcode_descs[opcode].table;
 685       for (unsigned i = 0; i < opcode_descs[opcode].size; i++) {
 686          if ((table[i].gens & gen) != 0) {
 687             return &table[i];
 688          }
 689       }
 690    }
 691    return NULL;
 692 }