src/intel/compiler/brw_eu.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33 #ifndef BRW_EU_H
  34 #define BRW_EU_H
  35
  36 #include <stdbool.h>
  37 #include <stdio.h>
  38 #include "brw_inst.h"
  39 #include "brw_eu_defines.h"
  40 #include "brw_reg.h"
  41 #include "brw_disasm_info.h"
  42
  43 #ifdef __cplusplus
  44 extern "C" {
  45 #endif
  46
  47 #define BRW_EU_MAX_INSN_STACK 5
  48
  49 struct brw_insn_state {
  50    /* One of BRW_EXECUTE_* */
  51    unsigned exec_size:3;
  52
  53    /* Group in units of channels */
  54    unsigned group:5;
  55
  56    /* Compression control on gen4-5 */
  57    bool compressed:1;
  58
  59    /* One of BRW_MASK_* */
  60    unsigned mask_control:1;
  61
  62    /* Scheduling info for Gen12+ */
  63    struct tgl_swsb swsb;
  64
  65    bool saturate:1;
  66
  67    /* One of BRW_ALIGN_* */
  68    unsigned access_mode:1;
  69
  70    /* One of BRW_PREDICATE_* */
  71    enum brw_predicate predicate:4;
  72
  73    bool pred_inv:1;
  74
  75    /* Flag subreg.  Bottom bit is subreg, top bit is reg */
  76    unsigned flag_subreg:2;
  77
  78    bool acc_wr_control:1;
  79 };
  80
  81
  82 /* A helper for accessing the last instruction emitted.  This makes it easy
  83  * to set various bits on an instruction without having to create temporary
  84  * variable and assign the emitted instruction to those.
  85  */
  86 #define brw_last_inst (&p->store[p->nr_insn - 1])
  87
  88 struct brw_codegen {
  89    brw_inst *store;
  90    int store_size;
  91    unsigned nr_insn;
  92    unsigned int next_insn_offset;
  93
  94    void *mem_ctx;
  95
  96    /* Allow clients to push/pop instruction state:
  97     */
  98    struct brw_insn_state stack[BRW_EU_MAX_INSN_STACK];
  99    struct brw_insn_state *current;
 100
 101    /** Whether or not the user wants automatic exec sizes
 102     *
 103     * If true, codegen will try to automatically infer the exec size of an
 104     * instruction from the width of the destination register.  If false, it
 105     * will take whatever is set by brw_set_default_exec_size verbatim.
 106     *
 107     * This is set to true by default in brw_init_codegen.
 108     */
 109    bool automatic_exec_sizes;
 110
 111    bool single_program_flow;
 112    const struct gen_device_info *devinfo;
 113
 114    /* Control flow stacks:
 115     * - if_stack contains IF and ELSE instructions which must be patched
 116     *   (and popped) once the matching ENDIF instruction is encountered.
 117     *
 118     *   Just store the instruction pointer(an index).
 119     */
 120    int *if_stack;
 121    int if_stack_depth;
 122    int if_stack_array_size;
 123
 124    /**
 125     * loop_stack contains the instruction pointers of the starts of loops which
 126     * must be patched (and popped) once the matching WHILE instruction is
 127     * encountered.
 128     */
 129    int *loop_stack;
 130    /**
 131     * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
 132     * blocks they were popping out of, to fix up the mask stack.  This tracks
 133     * the IF/ENDIF nesting in each current nested loop level.
 134     */
 135    int *if_depth_in_loop;
 136    int loop_stack_depth;
 137    int loop_stack_array_size;
 138 };
 139
 140 void brw_pop_insn_state( struct brw_codegen *p );
 141 void brw_push_insn_state( struct brw_codegen *p );
 142 unsigned brw_get_default_exec_size(struct brw_codegen *p);
 143 unsigned brw_get_default_group(struct brw_codegen *p);
 144 unsigned brw_get_default_access_mode(struct brw_codegen *p);
 145 struct tgl_swsb brw_get_default_swsb(struct brw_codegen *p);
 146 void brw_set_default_exec_size(struct brw_codegen *p, unsigned value);
 147 void brw_set_default_mask_control( struct brw_codegen *p, unsigned value );
 148 void brw_set_default_saturate( struct brw_codegen *p, bool enable );
 149 void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode );
 150 void brw_inst_set_compression(const struct gen_device_info *devinfo,
 151                               brw_inst *inst, bool on);
 152 void brw_set_default_compression(struct brw_codegen *p, bool on);
 153 void brw_inst_set_group(const struct gen_device_info *devinfo,
 154                         brw_inst *inst, unsigned group);
 155 void brw_set_default_group(struct brw_codegen *p, unsigned group);
 156 void brw_set_default_compression_control(struct brw_codegen *p, enum brw_compression c);
 157 void brw_set_default_predicate_control(struct brw_codegen *p, enum brw_predicate pc);
 158 void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse);
 159 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg);
 160 void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value);
 161 void brw_set_default_swsb(struct brw_codegen *p, struct tgl_swsb value);
 162
 163 void brw_init_codegen(const struct gen_device_info *, struct brw_codegen *p,
 164                       void *mem_ctx);
 165 int brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
 166                          const struct brw_inst *inst, bool is_compacted);
 167 void brw_disassemble(const struct gen_device_info *devinfo,
 168                      const void *assembly, int start, int end, FILE *out);
 169 const unsigned *brw_get_program( struct brw_codegen *p, unsigned *sz );
 170
 171 bool brw_try_override_assembly(struct brw_codegen *p, int start_offset,
 172                                const char *identifier);
 173
 174 brw_inst *brw_next_insn(struct brw_codegen *p, unsigned opcode);
 175 void brw_set_dest(struct brw_codegen *p, brw_inst *insn, struct brw_reg dest);
 176 void brw_set_src0(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg);
 177
 178 void gen6_resolve_implied_move(struct brw_codegen *p,
 179                                struct brw_reg *src,
 180                                unsigned msg_reg_nr);
 181
 182 /* Helpers for regular instructions:
 183  */
 184 #define ALU1(OP)                                \
 185 brw_inst *brw_##OP(struct brw_codegen *p,       \
 186               struct brw_reg dest,              \
 187               struct brw_reg src0);
 188
 189 #define ALU2(OP)                                \
 190 brw_inst *brw_##OP(struct brw_codegen *p,       \
 191               struct brw_reg dest,              \
 192               struct brw_reg src0,              \
 193               struct brw_reg src1);
 194
 195 #define ALU3(OP)                                \
 196 brw_inst *brw_##OP(struct brw_codegen *p,       \
 197               struct brw_reg dest,              \
 198               struct brw_reg src0,              \
 199               struct brw_reg src1,              \
 200               struct brw_reg src2);
 201
 202 ALU1(MOV)
 203 ALU2(SEL)
 204 ALU1(NOT)
 205 ALU2(AND)
 206 ALU2(OR)
 207 ALU2(XOR)
 208 ALU2(SHR)
 209 ALU2(SHL)
 210 ALU1(DIM)
 211 ALU2(ASR)
 212 ALU2(ROL)
 213 ALU2(ROR)
 214 ALU3(CSEL)
 215 ALU1(F32TO16)
 216 ALU1(F16TO32)
 217 ALU2(ADD)
 218 ALU2(AVG)
 219 ALU2(MUL)
 220 ALU1(FRC)
 221 ALU1(RNDD)
 222 ALU1(RNDE)
 223 ALU1(RNDZ)
 224 ALU2(MAC)
 225 ALU2(MACH)
 226 ALU1(LZD)
 227 ALU2(DP4)
 228 ALU2(DPH)
 229 ALU2(DP3)
 230 ALU2(DP2)
 231 ALU2(LINE)
 232 ALU2(PLN)
 233 ALU3(MAD)
 234 ALU3(LRP)
 235 ALU1(BFREV)
 236 ALU3(BFE)
 237 ALU2(BFI1)
 238 ALU3(BFI2)
 239 ALU1(FBH)
 240 ALU1(FBL)
 241 ALU1(CBIT)
 242 ALU2(ADDC)
 243 ALU2(SUBB)
 244 ALU2(MAC)
 245
 246 #undef ALU1
 247 #undef ALU2
 248 #undef ALU3
 249
 250
 251 /* Helpers for SEND instruction:
 252  */
 253
 254 /**
 255  * Construct a message descriptor immediate with the specified common
 256  * descriptor controls.
 257  */
 258 static inline uint32_t
 259 brw_message_desc(const struct gen_device_info *devinfo,
 260                  unsigned msg_length,
 261                  unsigned response_length,
 262                  bool header_present)
 263 {
 264    if (devinfo->gen >= 5) {
 265       return (SET_BITS(msg_length, 28, 25) |
 266               SET_BITS(response_length, 24, 20) |
 267               SET_BITS(header_present, 19, 19));
 268    } else {
 269       return (SET_BITS(msg_length, 23, 20) |
 270               SET_BITS(response_length, 19, 16));
 271    }
 272 }
 273
 274 static inline unsigned
 275 brw_message_desc_mlen(const struct gen_device_info *devinfo, uint32_t desc)
 276 {
 277    if (devinfo->gen >= 5)
 278       return GET_BITS(desc, 28, 25);
 279    else
 280       return GET_BITS(desc, 23, 20);
 281 }
 282
 283 static inline unsigned
 284 brw_message_desc_rlen(const struct gen_device_info *devinfo, uint32_t desc)
 285 {
 286    if (devinfo->gen >= 5)
 287       return GET_BITS(desc, 24, 20);
 288    else
 289       return GET_BITS(desc, 19, 16);
 290 }
 291
 292 static inline bool
 293 brw_message_desc_header_present(ASSERTED const struct gen_device_info *devinfo,
 294                                 uint32_t desc)
 295 {
 296    assert(devinfo->gen >= 5);
 297    return GET_BITS(desc, 19, 19);
 298 }
 299
 300 static inline unsigned
 301 brw_message_ex_desc(UNUSED const struct gen_device_info *devinfo,
 302                     unsigned ex_msg_length)
 303 {
 304    return SET_BITS(ex_msg_length, 9, 6);
 305 }
 306
 307 static inline unsigned
 308 brw_message_ex_desc_ex_mlen(UNUSED const struct gen_device_info *devinfo,
 309                             uint32_t ex_desc)
 310 {
 311    return GET_BITS(ex_desc, 9, 6);
 312 }
 313
 314 static inline uint32_t
 315 brw_urb_desc(const struct gen_device_info *devinfo,
 316              unsigned msg_type,
 317              bool per_slot_offset_present,
 318              bool channel_mask_present,
 319              unsigned global_offset)
 320 {
 321    if (devinfo->gen >= 8) {
 322       return (SET_BITS(per_slot_offset_present, 17, 17) |
 323               SET_BITS(channel_mask_present, 15, 15) |
 324               SET_BITS(global_offset, 14, 4) |
 325               SET_BITS(msg_type, 3, 0));
 326    } else if (devinfo->gen >= 7) {
 327       assert(!channel_mask_present);
 328       return (SET_BITS(per_slot_offset_present, 16, 16) |
 329               SET_BITS(global_offset, 13, 3) |
 330               SET_BITS(msg_type, 3, 0));
 331    } else {
 332       unreachable("unhandled URB write generation");
 333    }
 334 }
 335
 336 /**
 337  * Construct a message descriptor immediate with the specified sampler
 338  * function controls.
 339  */
 340 static inline uint32_t
 341 brw_sampler_desc(const struct gen_device_info *devinfo,
 342                  unsigned binding_table_index,
 343                  unsigned sampler,
 344                  unsigned msg_type,
 345                  unsigned simd_mode,
 346                  unsigned return_format)
 347 {
 348    const unsigned desc = (SET_BITS(binding_table_index, 7, 0) |
 349                           SET_BITS(sampler, 11, 8));
 350    if (devinfo->gen >= 7)
 351       return (desc | SET_BITS(msg_type, 16, 12) |
 352               SET_BITS(simd_mode, 18, 17));
 353    else if (devinfo->gen >= 5)
 354       return (desc | SET_BITS(msg_type, 15, 12) |
 355               SET_BITS(simd_mode, 17, 16));
 356    else if (devinfo->is_g4x)
 357       return desc | SET_BITS(msg_type, 15, 12);
 358    else
 359       return (desc | SET_BITS(return_format, 13, 12) |
 360               SET_BITS(msg_type, 15, 14));
 361 }
 362
 363 static inline unsigned
 364 brw_sampler_desc_binding_table_index(UNUSED const struct gen_device_info *devinfo,
 365                                      uint32_t desc)
 366 {
 367    return GET_BITS(desc, 7, 0);
 368 }
 369
 370 static inline unsigned
 371 brw_sampler_desc_sampler(UNUSED const struct gen_device_info *devinfo, uint32_t desc)
 372 {
 373    return GET_BITS(desc, 11, 8);
 374 }
 375
 376 static inline unsigned
 377 brw_sampler_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
 378 {
 379    if (devinfo->gen >= 7)
 380       return GET_BITS(desc, 16, 12);
 381    else if (devinfo->gen >= 5 || devinfo->is_g4x)
 382       return GET_BITS(desc, 15, 12);
 383    else
 384       return GET_BITS(desc, 15, 14);
 385 }
 386
 387 static inline unsigned
 388 brw_sampler_desc_simd_mode(const struct gen_device_info *devinfo, uint32_t desc)
 389 {
 390    assert(devinfo->gen >= 5);
 391    if (devinfo->gen >= 7)
 392       return GET_BITS(desc, 18, 17);
 393    else
 394       return GET_BITS(desc, 17, 16);
 395 }
 396
 397 static  inline unsigned
 398 brw_sampler_desc_return_format(ASSERTED const struct gen_device_info *devinfo,
 399                                uint32_t desc)
 400 {
 401    assert(devinfo->gen == 4 && !devinfo->is_g4x);
 402    return GET_BITS(desc, 13, 12);
 403 }
 404
 405 /**
 406  * Construct a message descriptor for the dataport
 407  */
 408 static inline uint32_t
 409 brw_dp_desc(const struct gen_device_info *devinfo,
 410             unsigned binding_table_index,
 411             unsigned msg_type,
 412             unsigned msg_control)
 413 {
 414    /* Prior to gen6, things are too inconsistent; use the dp_read/write_desc
 415     * helpers instead.
 416     */
 417    assert(devinfo->gen >= 6);
 418    const unsigned desc = SET_BITS(binding_table_index, 7, 0);
 419    if (devinfo->gen >= 8) {
 420       return (desc | SET_BITS(msg_control, 13, 8) |
 421               SET_BITS(msg_type, 18, 14));
 422    } else if (devinfo->gen >= 7) {
 423       return (desc | SET_BITS(msg_control, 13, 8) |
 424               SET_BITS(msg_type, 17, 14));
 425    } else {
 426       return (desc | SET_BITS(msg_control, 12, 8) |
 427               SET_BITS(msg_type, 16, 13));
 428    }
 429 }
 430
 431 static inline unsigned
 432 brw_dp_desc_binding_table_index(UNUSED const struct gen_device_info *devinfo,
 433                                 uint32_t desc)
 434 {
 435    return GET_BITS(desc, 7, 0);
 436 }
 437
 438 static inline unsigned
 439 brw_dp_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
 440 {
 441    assert(devinfo->gen >= 6);
 442    if (devinfo->gen >= 8)
 443       return GET_BITS(desc, 18, 14);
 444    else if (devinfo->gen >= 7)
 445       return GET_BITS(desc, 17, 14);
 446    else
 447       return GET_BITS(desc, 16, 13);
 448 }
 449
 450 static inline unsigned
 451 brw_dp_desc_msg_control(const struct gen_device_info *devinfo, uint32_t desc)
 452 {
 453    assert(devinfo->gen >= 6);
 454    if (devinfo->gen >= 7)
 455       return GET_BITS(desc, 13, 8);
 456    else
 457       return GET_BITS(desc, 12, 8);
 458 }
 459
 460 /**
 461  * Construct a message descriptor immediate with the specified dataport read
 462  * function controls.
 463  */
 464 static inline uint32_t
 465 brw_dp_read_desc(const struct gen_device_info *devinfo,
 466                  unsigned binding_table_index,
 467                  unsigned msg_control,
 468                  unsigned msg_type,
 469                  unsigned target_cache)
 470 {
 471    if (devinfo->gen >= 6)
 472       return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control);
 473    else if (devinfo->gen >= 5 || devinfo->is_g4x)
 474       return (SET_BITS(binding_table_index, 7, 0) |
 475               SET_BITS(msg_control, 10, 8) |
 476               SET_BITS(msg_type, 13, 11) |
 477               SET_BITS(target_cache, 15, 14));
 478    else
 479       return (SET_BITS(binding_table_index, 7, 0) |
 480               SET_BITS(msg_control, 11, 8) |
 481               SET_BITS(msg_type, 13, 12) |
 482               SET_BITS(target_cache, 15, 14));
 483 }
 484
 485 static inline unsigned
 486 brw_dp_read_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
 487 {
 488    if (devinfo->gen >= 6)
 489       return brw_dp_desc_msg_type(devinfo, desc);
 490    else if (devinfo->gen >= 5 || devinfo->is_g4x)
 491       return GET_BITS(desc, 13, 11);
 492    else
 493       return GET_BITS(desc, 13, 12);
 494 }
 495
 496 static inline unsigned
 497 brw_dp_read_desc_msg_control(const struct gen_device_info *devinfo,
 498                              uint32_t desc)
 499 {
 500    if (devinfo->gen >= 6)
 501       return brw_dp_desc_msg_control(devinfo, desc);
 502    else if (devinfo->gen >= 5 || devinfo->is_g4x)
 503       return GET_BITS(desc, 10, 8);
 504    else
 505       return GET_BITS(desc, 11, 8);
 506 }
 507
 508 /**
 509  * Construct a message descriptor immediate with the specified dataport write
 510  * function controls.
 511  */
 512 static inline uint32_t
 513 brw_dp_write_desc(const struct gen_device_info *devinfo,
 514                   unsigned binding_table_index,
 515                   unsigned msg_control,
 516                   unsigned msg_type,
 517                   unsigned last_render_target,
 518                   unsigned send_commit_msg)
 519 {
 520    assert(devinfo->gen <= 6 || !send_commit_msg);
 521    if (devinfo->gen >= 6)
 522       return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control) |
 523              SET_BITS(last_render_target, 12, 12) |
 524              SET_BITS(send_commit_msg, 17, 17);
 525    else
 526       return (SET_BITS(binding_table_index, 7, 0) |
 527               SET_BITS(msg_control, 11, 8) |
 528               SET_BITS(last_render_target, 11, 11) |
 529               SET_BITS(msg_type, 14, 12) |
 530               SET_BITS(send_commit_msg, 15, 15));
 531 }
 532
 533 static inline unsigned
 534 brw_dp_write_desc_msg_type(const struct gen_device_info *devinfo,
 535                            uint32_t desc)
 536 {
 537    if (devinfo->gen >= 6)
 538       return brw_dp_desc_msg_type(devinfo, desc);
 539    else
 540       return GET_BITS(desc, 14, 12);
 541 }
 542
 543 static inline unsigned
 544 brw_dp_write_desc_msg_control(const struct gen_device_info *devinfo,
 545                               uint32_t desc)
 546 {
 547    if (devinfo->gen >= 6)
 548       return brw_dp_desc_msg_control(devinfo, desc);
 549    else
 550       return GET_BITS(desc, 11, 8);
 551 }
 552
 553 static inline bool
 554 brw_dp_write_desc_last_render_target(const struct gen_device_info *devinfo,
 555                                      uint32_t desc)
 556 {
 557    if (devinfo->gen >= 6)
 558       return GET_BITS(desc, 12, 12);
 559    else
 560       return GET_BITS(desc, 11, 11);
 561 }
 562
 563 static inline bool
 564 brw_dp_write_desc_write_commit(const struct gen_device_info *devinfo,
 565                                uint32_t desc)
 566 {
 567    assert(devinfo->gen <= 6);
 568    if (devinfo->gen >= 6)
 569       return GET_BITS(desc, 17, 17);
 570    else
 571       return GET_BITS(desc, 15, 15);
 572 }
 573
 574 /**
 575  * Construct a message descriptor immediate with the specified dataport
 576  * surface function controls.
 577  */
 578 static inline uint32_t
 579 brw_dp_surface_desc(const struct gen_device_info *devinfo,
 580                     unsigned msg_type,
 581                     unsigned msg_control)
 582 {
 583    assert(devinfo->gen >= 7);
 584    /* We'll OR in the binding table index later */
 585    return brw_dp_desc(devinfo, 0, msg_type, msg_control);
 586 }
 587
 588 static inline uint32_t
 589 brw_dp_untyped_atomic_desc(const struct gen_device_info *devinfo,
 590                            unsigned exec_size, /**< 0 for SIMD4x2 */
 591                            unsigned atomic_op,
 592                            bool response_expected)
 593 {
 594    assert(exec_size <= 8 || exec_size == 16);
 595
 596    unsigned msg_type;
 597    if (devinfo->gen >= 8 || devinfo->is_haswell) {
 598       if (exec_size > 0) {
 599          msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP;
 600       } else {
 601          msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2;
 602       }
 603    } else {
 604       msg_type = GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP;
 605    }
 606
 607    const unsigned msg_control =
 608       SET_BITS(atomic_op, 3, 0) |
 609       SET_BITS(0 < exec_size && exec_size <= 8, 4, 4) |
 610       SET_BITS(response_expected, 5, 5);
 611
 612    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 613 }
 614
 615 static inline uint32_t
 616 brw_dp_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
 617                                  unsigned exec_size,
 618                                  unsigned atomic_op,
 619                                  bool response_expected)
 620 {
 621    assert(exec_size <= 8 || exec_size == 16);
 622    assert(devinfo->gen >= 9);
 623
 624    assert(exec_size > 0);
 625    const unsigned msg_type = GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP;
 626
 627    const unsigned msg_control =
 628       SET_BITS(atomic_op, 1, 0) |
 629       SET_BITS(exec_size <= 8, 4, 4) |
 630       SET_BITS(response_expected, 5, 5);
 631
 632    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 633 }
 634
 635 static inline unsigned
 636 brw_mdc_cmask(unsigned num_channels)
 637 {
 638    /* See also MDC_CMASK in the SKL PRM Vol 2d. */
 639    return 0xf & (0xf << num_channels);
 640 }
 641
 642 static inline uint32_t
 643 brw_dp_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
 644                                unsigned exec_size, /**< 0 for SIMD4x2 */
 645                                unsigned num_channels,
 646                                bool write)
 647 {
 648    assert(exec_size <= 8 || exec_size == 16);
 649
 650    unsigned msg_type;
 651    if (write) {
 652       if (devinfo->gen >= 8 || devinfo->is_haswell) {
 653          msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE;
 654       } else {
 655          msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE;
 656       }
 657    } else {
 658       /* Read */
 659       if (devinfo->gen >= 8 || devinfo->is_haswell) {
 660          msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ;
 661       } else {
 662          msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ;
 663       }
 664    }
 665
 666    /* SIMD4x2 is only valid for read messages on IVB; use SIMD8 instead */
 667    if (write && devinfo->gen == 7 && !devinfo->is_haswell && exec_size == 0)
 668       exec_size = 8;
 669
 670    /* See also MDC_SM3 in the SKL PRM Vol 2d. */
 671    const unsigned simd_mode = exec_size == 0 ? 0 : /* SIMD4x2 */
 672                               exec_size <= 8 ? 2 : 1;
 673
 674    const unsigned msg_control =
 675       SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
 676       SET_BITS(simd_mode, 5, 4);
 677
 678    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 679 }
 680
 681 static inline unsigned
 682 brw_mdc_ds(unsigned bit_size)
 683 {
 684    switch (bit_size) {
 685    case 8:
 686       return GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE;
 687    case 16:
 688       return GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD;
 689    case 32:
 690       return GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD;
 691    default:
 692       unreachable("Unsupported bit_size for byte scattered messages");
 693    }
 694 }
 695
 696 static inline uint32_t
 697 brw_dp_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
 698                               unsigned exec_size,
 699                               unsigned bit_size,
 700                               bool write)
 701 {
 702    assert(exec_size <= 8 || exec_size == 16);
 703
 704    assert(devinfo->gen > 7 || devinfo->is_haswell);
 705    const unsigned msg_type =
 706       write ? HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE :
 707               HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ;
 708
 709    assert(exec_size > 0);
 710    const unsigned msg_control =
 711       SET_BITS(exec_size == 16, 0, 0) |
 712       SET_BITS(brw_mdc_ds(bit_size), 3, 2);
 713
 714    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 715 }
 716
 717 static inline uint32_t
 718 brw_dp_dword_scattered_rw_desc(const struct gen_device_info *devinfo,
 719                                unsigned exec_size,
 720                                bool write)
 721 {
 722    assert(exec_size == 8 || exec_size == 16);
 723
 724    unsigned msg_type;
 725    if (write) {
 726       if (devinfo->gen >= 6) {
 727          msg_type = GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE;
 728       } else {
 729          msg_type = BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE;
 730       }
 731    } else {
 732       if (devinfo->gen >= 7) {
 733          msg_type = GEN7_DATAPORT_DC_DWORD_SCATTERED_READ;
 734       } else if (devinfo->gen > 4 || devinfo->is_g4x) {
 735          msg_type = G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ;
 736       } else {
 737          msg_type = BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ;
 738       }
 739    }
 740
 741    const unsigned msg_control =
 742       SET_BITS(1, 1, 1) | /* Legacy SIMD Mode */
 743       SET_BITS(exec_size == 16, 0, 0);
 744
 745    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 746 }
 747
 748 static inline uint32_t
 749 brw_dp_a64_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
 750                                    unsigned exec_size, /**< 0 for SIMD4x2 */
 751                                    unsigned num_channels,
 752                                    bool write)
 753 {
 754    assert(exec_size <= 8 || exec_size == 16);
 755    assert(devinfo->gen >= 8);
 756
 757    unsigned msg_type =
 758       write ? GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE :
 759               GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ;
 760
 761    /* See also MDC_SM3 in the SKL PRM Vol 2d. */
 762    const unsigned simd_mode = exec_size == 0 ? 0 : /* SIMD4x2 */
 763                               exec_size <= 8 ? 2 : 1;
 764
 765    const unsigned msg_control =
 766       SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
 767       SET_BITS(simd_mode, 5, 4);
 768
 769    return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
 770                       msg_type, msg_control);
 771 }
 772
 773 /**
 774  * Calculate the data size (see MDC_A64_DS in the "Structures" volume of the
 775  * Skylake PRM).
 776  */
 777 static inline uint32_t
 778 brw_mdc_a64_ds(unsigned elems)
 779 {
 780    switch (elems) {
 781    case 1:  return 0;
 782    case 2:  return 1;
 783    case 4:  return 2;
 784    case 8:  return 3;
 785    default:
 786       unreachable("Unsupported elmeent count for A64 scattered message");
 787    }
 788 }
 789
 790 static inline uint32_t
 791 brw_dp_a64_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
 792                                   unsigned exec_size, /**< 0 for SIMD4x2 */
 793                                   unsigned bit_size,
 794                                   bool write)
 795 {
 796    assert(exec_size <= 8 || exec_size == 16);
 797    assert(devinfo->gen >= 8);
 798
 799    unsigned msg_type =
 800       write ? GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE :
 801               GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ;
 802
 803    const unsigned msg_control =
 804       SET_BITS(GEN8_A64_SCATTERED_SUBTYPE_BYTE, 1, 0) |
 805       SET_BITS(brw_mdc_a64_ds(bit_size / 8), 3, 2) |
 806       SET_BITS(exec_size == 16, 4, 4);
 807
 808    return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
 809                       msg_type, msg_control);
 810 }
 811
 812 static inline uint32_t
 813 brw_dp_a64_untyped_atomic_desc(const struct gen_device_info *devinfo,
 814                                ASSERTED unsigned exec_size, /**< 0 for SIMD4x2 */
 815                                unsigned bit_size,
 816                                unsigned atomic_op,
 817                                bool response_expected)
 818 {
 819    assert(exec_size == 8);
 820    assert(devinfo->gen >= 8);
 821    assert(bit_size == 32 || bit_size == 64);
 822
 823    const unsigned msg_type = GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP;
 824
 825    const unsigned msg_control =
 826       SET_BITS(atomic_op, 3, 0) |
 827       SET_BITS(bit_size == 64, 4, 4) |
 828       SET_BITS(response_expected, 5, 5);
 829
 830    return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
 831                       msg_type, msg_control);
 832 }
 833
 834 static inline uint32_t
 835 brw_dp_a64_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
 836                                      ASSERTED unsigned exec_size,
 837                                      unsigned atomic_op,
 838                                      bool response_expected)
 839 {
 840    assert(exec_size == 8);
 841    assert(devinfo->gen >= 9);
 842
 843    assert(exec_size > 0);
 844    const unsigned msg_type = GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP;
 845
 846    const unsigned msg_control =
 847       SET_BITS(atomic_op, 1, 0) |
 848       SET_BITS(response_expected, 5, 5);
 849
 850    return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
 851                       msg_type, msg_control);
 852 }
 853
 854 static inline uint32_t
 855 brw_dp_typed_atomic_desc(const struct gen_device_info *devinfo,
 856                          unsigned exec_size,
 857                          unsigned exec_group,
 858                          unsigned atomic_op,
 859                          bool response_expected)
 860 {
 861    assert(exec_size > 0 || exec_group == 0);
 862    assert(exec_group % 8 == 0);
 863
 864    unsigned msg_type;
 865    if (devinfo->gen >= 8 || devinfo->is_haswell) {
 866       if (exec_size == 0) {
 867          msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2;
 868       } else {
 869          msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP;
 870       }
 871    } else {
 872       /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
 873       assert(exec_size > 0);
 874       msg_type = GEN7_DATAPORT_RC_TYPED_ATOMIC_OP;
 875    }
 876
 877    const bool high_sample_mask = (exec_group / 8) % 2 == 1;
 878
 879    const unsigned msg_control =
 880       SET_BITS(atomic_op, 3, 0) |
 881       SET_BITS(high_sample_mask, 4, 4) |
 882       SET_BITS(response_expected, 5, 5);
 883
 884    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 885 }
 886
 887 static inline uint32_t
 888 brw_dp_typed_surface_rw_desc(const struct gen_device_info *devinfo,
 889                              unsigned exec_size,
 890                              unsigned exec_group,
 891                              unsigned num_channels,
 892                              bool write)
 893 {
 894    assert(exec_size > 0 || exec_group == 0);
 895    assert(exec_group % 8 == 0);
 896
 897    /* Typed surface reads and writes don't support SIMD16 */
 898    assert(exec_size <= 8);
 899
 900    unsigned msg_type;
 901    if (write) {
 902       if (devinfo->gen >= 8 || devinfo->is_haswell) {
 903          msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE;
 904       } else {
 905          msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE;
 906       }
 907    } else {
 908       if (devinfo->gen >= 8 || devinfo->is_haswell) {
 909          msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ;
 910       } else {
 911          msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_READ;
 912       }
 913    }
 914
 915    /* See also MDC_SG3 in the SKL PRM Vol 2d. */
 916    unsigned msg_control;
 917    if (devinfo->gen >= 8 || devinfo->is_haswell) {
 918       /* See also MDC_SG3 in the SKL PRM Vol 2d. */
 919       const unsigned slot_group = exec_size == 0 ? 0 : /* SIMD4x2 */
 920                                   1 + ((exec_group / 8) % 2);
 921
 922       msg_control =
 923          SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
 924          SET_BITS(slot_group, 5, 4);
 925    } else {
 926       /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
 927       assert(exec_size > 0);
 928       const unsigned slot_group = ((exec_group / 8) % 2);
 929
 930       msg_control =
 931          SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
 932          SET_BITS(slot_group, 5, 5);
 933    }
 934
 935    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 936 }
 937
 938 /**
 939  * Construct a message descriptor immediate with the specified pixel
 940  * interpolator function controls.
 941  */
 942 static inline uint32_t
 943 brw_pixel_interp_desc(UNUSED const struct gen_device_info *devinfo,
 944                       unsigned msg_type,
 945                       bool noperspective,
 946                       unsigned simd_mode,
 947                       unsigned slot_group)
 948 {
 949    return (SET_BITS(slot_group, 11, 11) |
 950            SET_BITS(msg_type, 13, 12) |
 951            SET_BITS(!!noperspective, 14, 14) |
 952            SET_BITS(simd_mode, 16, 16));
 953 }
 954
 955 void brw_urb_WRITE(struct brw_codegen *p,
 956                    struct brw_reg dest,
 957                    unsigned msg_reg_nr,
 958                    struct brw_reg src0,
 959                    enum brw_urb_write_flags flags,
 960                    unsigned msg_length,
 961                    unsigned response_length,
 962                    unsigned offset,
 963                    unsigned swizzle);
 964
 965 /**
 966  * Send message to shared unit \p sfid with a possibly indirect descriptor \p
 967  * desc.  If \p desc is not an immediate it will be transparently loaded to an
 968  * address register using an OR instruction.
 969  */
 970 void
 971 brw_send_indirect_message(struct brw_codegen *p,
 972                           unsigned sfid,
 973                           struct brw_reg dst,
 974                           struct brw_reg payload,
 975                           struct brw_reg desc,
 976                           unsigned desc_imm,
 977                           bool eot);
 978
 979 void
 980 brw_send_indirect_split_message(struct brw_codegen *p,
 981                                 unsigned sfid,
 982                                 struct brw_reg dst,
 983                                 struct brw_reg payload0,
 984                                 struct brw_reg payload1,
 985                                 struct brw_reg desc,
 986                                 unsigned desc_imm,
 987                                 struct brw_reg ex_desc,
 988                                 unsigned ex_desc_imm,
 989                                 bool eot);
 990
 991 void brw_ff_sync(struct brw_codegen *p,
 992                    struct brw_reg dest,
 993                    unsigned msg_reg_nr,
 994                    struct brw_reg src0,
 995                    bool allocate,
 996                    unsigned response_length,
 997                    bool eot);
 998
 999 void brw_svb_write(struct brw_codegen *p,
1000                    struct brw_reg dest,
1001                    unsigned msg_reg_nr,
1002                    struct brw_reg src0,
1003                    unsigned binding_table_index,
1004                    bool   send_commit_msg);
1005
1006 brw_inst *brw_fb_WRITE(struct brw_codegen *p,
1007                        struct brw_reg payload,
1008                        struct brw_reg implied_header,
1009                        unsigned msg_control,
1010                        unsigned binding_table_index,
1011                        unsigned msg_length,
1012                        unsigned response_length,
1013                        bool eot,
1014                        bool last_render_target,
1015                        bool header_present);
1016
1017 brw_inst *gen9_fb_READ(struct brw_codegen *p,
1018                        struct brw_reg dst,
1019                        struct brw_reg payload,
1020                        unsigned binding_table_index,
1021                        unsigned msg_length,
1022                        unsigned response_length,
1023                        bool per_sample);
1024
1025 void brw_SAMPLE(struct brw_codegen *p,
1026                 struct brw_reg dest,
1027                 unsigned msg_reg_nr,
1028                 struct brw_reg src0,
1029                 unsigned binding_table_index,
1030                 unsigned sampler,
1031                 unsigned msg_type,
1032                 unsigned response_length,
1033                 unsigned msg_length,
1034                 unsigned header_present,
1035                 unsigned simd_mode,
1036                 unsigned return_format);
1037
1038 void brw_adjust_sampler_state_pointer(struct brw_codegen *p,
1039                                       struct brw_reg header,
1040                                       struct brw_reg sampler_index);
1041
1042 void gen4_math(struct brw_codegen *p,
1043                struct brw_reg dest,
1044                unsigned function,
1045                unsigned msg_reg_nr,
1046                struct brw_reg src,
1047                unsigned precision );
1048
1049 void gen6_math(struct brw_codegen *p,
1050                struct brw_reg dest,
1051                unsigned function,
1052                struct brw_reg src0,
1053                struct brw_reg src1);
1054
1055 void brw_oword_block_read(struct brw_codegen *p,
1056                           struct brw_reg dest,
1057                           struct brw_reg mrf,
1058                           uint32_t offset,
1059                           uint32_t bind_table_index);
1060
1061 unsigned brw_scratch_surface_idx(const struct brw_codegen *p);
1062
1063 void brw_oword_block_read_scratch(struct brw_codegen *p,
1064                                   struct brw_reg dest,
1065                                   struct brw_reg mrf,
1066                                   int num_regs,
1067                                   unsigned offset);
1068
1069 void brw_oword_block_write_scratch(struct brw_codegen *p,
1070                                    struct brw_reg mrf,
1071                                    int num_regs,
1072                                    unsigned offset);
1073
1074 void gen7_block_read_scratch(struct brw_codegen *p,
1075                              struct brw_reg dest,
1076                              int num_regs,
1077                              unsigned offset);
1078
1079 void brw_shader_time_add(struct brw_codegen *p,
1080                          struct brw_reg payload,
1081                          uint32_t surf_index);
1082
1083 /**
1084  * Return the generation-specific jump distance scaling factor.
1085  *
1086  * Given the number of instructions to jump, we need to scale by
1087  * some number to obtain the actual jump distance to program in an
1088  * instruction.
1089  */
1090 static inline unsigned
1091 brw_jump_scale(const struct gen_device_info *devinfo)
1092 {
1093    /* Broadwell measures jump targets in bytes. */
1094    if (devinfo->gen >= 8)
1095       return 16;
1096
1097    /* Ironlake and later measure jump targets in 64-bit data chunks (in order
1098     * (to support compaction), so each 128-bit instruction requires 2 chunks.
1099     */
1100    if (devinfo->gen >= 5)
1101       return 2;
1102
1103    /* Gen4 simply uses the number of 128-bit instructions. */
1104    return 1;
1105 }
1106
1107 void brw_barrier(struct brw_codegen *p, struct brw_reg src);
1108
1109 /* If/else/endif.  Works by manipulating the execution flags on each
1110  * channel.
1111  */
1112 brw_inst *brw_IF(struct brw_codegen *p, unsigned execute_size);
1113 brw_inst *gen6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional,
1114                   struct brw_reg src0, struct brw_reg src1);
1115
1116 void brw_ELSE(struct brw_codegen *p);
1117 void brw_ENDIF(struct brw_codegen *p);
1118
1119 /* DO/WHILE loops:
1120  */
1121 brw_inst *brw_DO(struct brw_codegen *p, unsigned execute_size);
1122
1123 brw_inst *brw_WHILE(struct brw_codegen *p);
1124
1125 brw_inst *brw_BREAK(struct brw_codegen *p);
1126 brw_inst *brw_CONT(struct brw_codegen *p);
1127 brw_inst *brw_HALT(struct brw_codegen *p);
1128
1129 /* Forward jumps:
1130  */
1131 void brw_land_fwd_jump(struct brw_codegen *p, int jmp_insn_idx);
1132
1133 brw_inst *brw_JMPI(struct brw_codegen *p, struct brw_reg index,
1134                    unsigned predicate_control);
1135
1136 void brw_NOP(struct brw_codegen *p);
1137
1138 void brw_WAIT(struct brw_codegen *p);
1139
1140 void brw_SYNC(struct brw_codegen *p, enum tgl_sync_function func);
1141
1142 /* Special case: there is never a destination, execution size will be
1143  * taken from src0:
1144  */
1145 void brw_CMP(struct brw_codegen *p,
1146              struct brw_reg dest,
1147              unsigned conditional,
1148              struct brw_reg src0,
1149              struct brw_reg src1);
1150
1151 void
1152 brw_untyped_atomic(struct brw_codegen *p,
1153                    struct brw_reg dst,
1154                    struct brw_reg payload,
1155                    struct brw_reg surface,
1156                    unsigned atomic_op,
1157                    unsigned msg_length,
1158                    bool response_expected,
1159                    bool header_present);
1160
1161 void
1162 brw_untyped_surface_read(struct brw_codegen *p,
1163                          struct brw_reg dst,
1164                          struct brw_reg payload,
1165                          struct brw_reg surface,
1166                          unsigned msg_length,
1167                          unsigned num_channels);
1168
1169 void
1170 brw_untyped_surface_write(struct brw_codegen *p,
1171                           struct brw_reg payload,
1172                           struct brw_reg surface,
1173                           unsigned msg_length,
1174                           unsigned num_channels,
1175                           bool header_present);
1176
1177 void
1178 brw_memory_fence(struct brw_codegen *p,
1179                  struct brw_reg dst,
1180                  struct brw_reg src,
1181                  enum opcode send_op,
1182                  enum brw_message_target sfid,
1183                  bool commit_enable,
1184                  unsigned bti);
1185
1186 void
1187 brw_pixel_interpolator_query(struct brw_codegen *p,
1188                              struct brw_reg dest,
1189                              struct brw_reg mrf,
1190                              bool noperspective,
1191                              unsigned mode,
1192                              struct brw_reg data,
1193                              unsigned msg_length,
1194                              unsigned response_length);
1195
1196 void
1197 brw_find_live_channel(struct brw_codegen *p,
1198                       struct brw_reg dst,
1199                       struct brw_reg mask);
1200
1201 void
1202 brw_broadcast(struct brw_codegen *p,
1203               struct brw_reg dst,
1204               struct brw_reg src,
1205               struct brw_reg idx);
1206
1207 void
1208 brw_float_controls_mode(struct brw_codegen *p,
1209                         unsigned mode, unsigned mask);
1210
1211 /***********************************************************************
1212  * brw_eu_util.c:
1213  */
1214
1215 void brw_copy_indirect_to_indirect(struct brw_codegen *p,
1216                                    struct brw_indirect dst_ptr,
1217                                    struct brw_indirect src_ptr,
1218                                    unsigned count);
1219
1220 void brw_copy_from_indirect(struct brw_codegen *p,
1221                             struct brw_reg dst,
1222                             struct brw_indirect ptr,
1223                             unsigned count);
1224
1225 void brw_copy4(struct brw_codegen *p,
1226                struct brw_reg dst,
1227                struct brw_reg src,
1228                unsigned count);
1229
1230 void brw_copy8(struct brw_codegen *p,
1231                struct brw_reg dst,
1232                struct brw_reg src,
1233                unsigned count);
1234
1235 void brw_math_invert( struct brw_codegen *p,
1236                       struct brw_reg dst,
1237                       struct brw_reg src);
1238
1239 void brw_set_src1(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg);
1240
1241 void brw_set_desc_ex(struct brw_codegen *p, brw_inst *insn,
1242                      unsigned desc, unsigned ex_desc);
1243
1244 static inline void
1245 brw_set_desc(struct brw_codegen *p, brw_inst *insn, unsigned desc)
1246 {
1247    brw_set_desc_ex(p, insn, desc, 0);
1248 }
1249
1250 void brw_set_uip_jip(struct brw_codegen *p, int start_offset);
1251
1252 enum brw_conditional_mod brw_negate_cmod(enum brw_conditional_mod cmod);
1253 enum brw_conditional_mod brw_swap_cmod(enum brw_conditional_mod cmod);
1254
1255 /* brw_eu_compact.c */
1256 void brw_init_compaction_tables(const struct gen_device_info *devinfo);
1257 void brw_compact_instructions(struct brw_codegen *p, int start_offset,
1258                               struct disasm_info *disasm);
1259 void brw_uncompact_instruction(const struct gen_device_info *devinfo,
1260                                brw_inst *dst, brw_compact_inst *src);
1261 bool brw_try_compact_instruction(const struct gen_device_info *devinfo,
1262                                  brw_compact_inst *dst, const brw_inst *src);
1263
1264 void brw_debug_compact_uncompact(const struct gen_device_info *devinfo,
1265                                  brw_inst *orig, brw_inst *uncompacted);
1266
1267 /* brw_eu_validate.c */
1268 bool brw_validate_instruction(const struct gen_device_info *devinfo,
1269                               const brw_inst *inst, int offset,
1270                               struct disasm_info *disasm);
1271 bool brw_validate_instructions(const struct gen_device_info *devinfo,
1272                                const void *assembly, int start_offset, int end_offset,
1273                                struct disasm_info *disasm);
1274
1275 static inline int
1276 next_offset(const struct gen_device_info *devinfo, void *store, int offset)
1277 {
1278    brw_inst *insn = (brw_inst *)((char *)store + offset);
1279
1280    if (brw_inst_cmpt_control(devinfo, insn))
1281       return offset + 8;
1282    else
1283       return offset + 16;
1284 }
1285
1286 struct opcode_desc {
1287    unsigned ir;
1288    unsigned hw;
1289    const char *name;
1290    int nsrc;
1291    int ndst;
1292    int gens;
1293 };
1294
1295 const struct opcode_desc *
1296 brw_opcode_desc(const struct gen_device_info *devinfo, enum opcode opcode);
1297
1298 const struct opcode_desc *
1299 brw_opcode_desc_from_hw(const struct gen_device_info *devinfo, unsigned hw);
1300
1301 static inline unsigned
1302 brw_opcode_encode(const struct gen_device_info *devinfo, enum opcode opcode)
1303 {
1304    return brw_opcode_desc(devinfo, opcode)->hw;
1305 }
1306
1307 static inline enum opcode
1308 brw_opcode_decode(const struct gen_device_info *devinfo, unsigned hw)
1309 {
1310    const struct opcode_desc *desc = brw_opcode_desc_from_hw(devinfo, hw);
1311    return desc ? (enum opcode)desc->ir : BRW_OPCODE_ILLEGAL;
1312 }
1313
1314 static inline void
1315 brw_inst_set_opcode(const struct gen_device_info *devinfo,
1316                     brw_inst *inst, enum opcode opcode)
1317 {
1318    brw_inst_set_hw_opcode(devinfo, inst, brw_opcode_encode(devinfo, opcode));
1319 }
1320
1321 static inline enum opcode
1322 brw_inst_opcode(const struct gen_device_info *devinfo, const brw_inst *inst)
1323 {
1324    return brw_opcode_decode(devinfo, brw_inst_hw_opcode(devinfo, inst));
1325 }
1326
1327 static inline bool
1328 is_3src(const struct gen_device_info *devinfo, enum opcode opcode)
1329 {
1330    const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
1331    return desc && desc->nsrc == 3;
1332 }
1333
1334 /** Maximum SEND message length */
1335 #define BRW_MAX_MSG_LENGTH 15
1336
1337 /** First MRF register used by pull loads */
1338 #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
1339
1340 /** First MRF register used by spills */
1341 #define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)
1342
1343 #ifdef __cplusplus
1344 }
1345 #endif
1346
1347 #endif