2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
39 #include "brw_eu_defines.h"
41 #include "brw_disasm_info.h"
47 #define BRW_EU_MAX_INSN_STACK 5
49 /* A helper for accessing the last instruction emitted. This makes it easy
50 * to set various bits on an instruction without having to create temporary
51 * variable and assign the emitted instruction to those.
53 #define brw_last_inst (&p->store[p->nr_insn - 1])
59 unsigned int next_insn_offset
;
63 /* Allow clients to push/pop instruction state:
65 brw_inst stack
[BRW_EU_MAX_INSN_STACK
];
68 /** Whether or not the user wants automatic exec sizes
70 * If true, codegen will try to automatically infer the exec size of an
71 * instruction from the width of the destination register. If false, it
72 * will take whatever is set by brw_set_default_exec_size verbatim.
74 * This is set to true by default in brw_init_codegen.
76 bool automatic_exec_sizes
;
78 bool single_program_flow
;
79 const struct gen_device_info
*devinfo
;
81 /* Control flow stacks:
82 * - if_stack contains IF and ELSE instructions which must be patched
83 * (and popped) once the matching ENDIF instruction is encountered.
85 * Just store the instruction pointer(an index).
89 int if_stack_array_size
;
92 * loop_stack contains the instruction pointers of the starts of loops which
93 * must be patched (and popped) once the matching WHILE instruction is
98 * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
99 * blocks they were popping out of, to fix up the mask stack. This tracks
100 * the IF/ENDIF nesting in each current nested loop level.
102 int *if_depth_in_loop
;
103 int loop_stack_depth
;
104 int loop_stack_array_size
;
107 void brw_pop_insn_state( struct brw_codegen
*p
);
108 void brw_push_insn_state( struct brw_codegen
*p
);
109 void brw_set_default_exec_size(struct brw_codegen
*p
, unsigned value
);
110 void brw_set_default_mask_control( struct brw_codegen
*p
, unsigned value
);
111 void brw_set_default_saturate( struct brw_codegen
*p
, bool enable
);
112 void brw_set_default_access_mode( struct brw_codegen
*p
, unsigned access_mode
);
113 void brw_inst_set_compression(const struct gen_device_info
*devinfo
,
114 brw_inst
*inst
, bool on
);
115 void brw_set_default_compression(struct brw_codegen
*p
, bool on
);
116 void brw_inst_set_group(const struct gen_device_info
*devinfo
,
117 brw_inst
*inst
, unsigned group
);
118 void brw_set_default_group(struct brw_codegen
*p
, unsigned group
);
119 void brw_set_default_compression_control(struct brw_codegen
*p
, enum brw_compression c
);
120 void brw_set_default_predicate_control( struct brw_codegen
*p
, unsigned pc
);
121 void brw_set_default_predicate_inverse(struct brw_codegen
*p
, bool predicate_inverse
);
122 void brw_set_default_flag_reg(struct brw_codegen
*p
, int reg
, int subreg
);
123 void brw_set_default_acc_write_control(struct brw_codegen
*p
, unsigned value
);
125 void brw_init_codegen(const struct gen_device_info
*, struct brw_codegen
*p
,
127 int brw_disassemble_inst(FILE *file
, const struct gen_device_info
*devinfo
,
128 const struct brw_inst
*inst
, bool is_compacted
);
129 void brw_disassemble(const struct gen_device_info
*devinfo
,
130 const void *assembly
, int start
, int end
, FILE *out
);
131 const unsigned *brw_get_program( struct brw_codegen
*p
, unsigned *sz
);
133 brw_inst
*brw_next_insn(struct brw_codegen
*p
, unsigned opcode
);
134 void brw_set_dest(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg dest
);
135 void brw_set_src0(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg reg
);
137 void gen6_resolve_implied_move(struct brw_codegen
*p
,
139 unsigned msg_reg_nr
);
141 /* Helpers for regular instructions:
144 brw_inst *brw_##OP(struct brw_codegen *p, \
145 struct brw_reg dest, \
146 struct brw_reg src0);
149 brw_inst *brw_##OP(struct brw_codegen *p, \
150 struct brw_reg dest, \
151 struct brw_reg src0, \
152 struct brw_reg src1);
155 brw_inst *brw_##OP(struct brw_codegen *p, \
156 struct brw_reg dest, \
157 struct brw_reg src0, \
158 struct brw_reg src1, \
159 struct brw_reg src2);
162 void brw_##OP(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0);
213 /* Helpers for SEND instruction:
215 void brw_set_sampler_message(struct brw_codegen
*p
,
217 unsigned binding_table_index
,
220 unsigned response_length
,
222 unsigned header_present
,
224 unsigned return_format
);
226 void brw_set_message_descriptor(struct brw_codegen
*p
,
228 enum brw_message_target sfid
,
230 unsigned response_length
,
234 void brw_set_dp_read_message(struct brw_codegen
*p
,
236 unsigned binding_table_index
,
237 unsigned msg_control
,
239 unsigned target_cache
,
242 unsigned response_length
);
244 void brw_set_dp_write_message(struct brw_codegen
*p
,
246 unsigned binding_table_index
,
247 unsigned msg_control
,
249 unsigned target_cache
,
252 unsigned last_render_target
,
253 unsigned response_length
,
254 unsigned end_of_thread
,
255 unsigned send_commit_msg
);
257 void brw_urb_WRITE(struct brw_codegen
*p
,
261 enum brw_urb_write_flags flags
,
263 unsigned response_length
,
268 * Send message to shared unit \p sfid with a possibly indirect descriptor \p
269 * desc. If \p desc is not an immediate it will be transparently loaded to an
270 * address register using an OR instruction. The returned instruction can be
271 * passed as argument to the usual brw_set_*_message() functions in order to
272 * specify any additional descriptor bits -- If \p desc is an immediate this
273 * will be the SEND instruction itself, otherwise it will be the OR
277 brw_send_indirect_message(struct brw_codegen
*p
,
280 struct brw_reg payload
,
281 struct brw_reg desc
);
283 void brw_ff_sync(struct brw_codegen
*p
,
288 unsigned response_length
,
291 void brw_svb_write(struct brw_codegen
*p
,
295 unsigned binding_table_index
,
296 bool send_commit_msg
);
298 void brw_fb_WRITE(struct brw_codegen
*p
,
299 struct brw_reg payload
,
300 struct brw_reg implied_header
,
301 unsigned msg_control
,
302 unsigned binding_table_index
,
304 unsigned response_length
,
306 bool last_render_target
,
307 bool header_present
);
309 brw_inst
*gen9_fb_READ(struct brw_codegen
*p
,
311 struct brw_reg payload
,
312 unsigned binding_table_index
,
314 unsigned response_length
,
317 void brw_SAMPLE(struct brw_codegen
*p
,
321 unsigned binding_table_index
,
324 unsigned response_length
,
326 unsigned header_present
,
328 unsigned return_format
);
330 void brw_adjust_sampler_state_pointer(struct brw_codegen
*p
,
331 struct brw_reg header
,
332 struct brw_reg sampler_index
);
334 void gen4_math(struct brw_codegen
*p
,
339 unsigned precision
);
341 void gen6_math(struct brw_codegen
*p
,
345 struct brw_reg src1
);
347 void brw_oword_block_read(struct brw_codegen
*p
,
351 uint32_t bind_table_index
);
353 unsigned brw_scratch_surface_idx(const struct brw_codegen
*p
);
355 void brw_oword_block_read_scratch(struct brw_codegen
*p
,
361 void brw_oword_block_write_scratch(struct brw_codegen
*p
,
366 void gen7_block_read_scratch(struct brw_codegen
*p
,
371 void brw_shader_time_add(struct brw_codegen
*p
,
372 struct brw_reg payload
,
373 uint32_t surf_index
);
376 * Return the generation-specific jump distance scaling factor.
378 * Given the number of instructions to jump, we need to scale by
379 * some number to obtain the actual jump distance to program in an
382 static inline unsigned
383 brw_jump_scale(const struct gen_device_info
*devinfo
)
385 /* Broadwell measures jump targets in bytes. */
386 if (devinfo
->gen
>= 8)
389 /* Ironlake and later measure jump targets in 64-bit data chunks (in order
390 * (to support compaction), so each 128-bit instruction requires 2 chunks.
392 if (devinfo
->gen
>= 5)
395 /* Gen4 simply uses the number of 128-bit instructions. */
399 void brw_barrier(struct brw_codegen
*p
, struct brw_reg src
);
401 /* If/else/endif. Works by manipulating the execution flags on each
404 brw_inst
*brw_IF(struct brw_codegen
*p
, unsigned execute_size
);
405 brw_inst
*gen6_IF(struct brw_codegen
*p
, enum brw_conditional_mod conditional
,
406 struct brw_reg src0
, struct brw_reg src1
);
408 void brw_ELSE(struct brw_codegen
*p
);
409 void brw_ENDIF(struct brw_codegen
*p
);
413 brw_inst
*brw_DO(struct brw_codegen
*p
, unsigned execute_size
);
415 brw_inst
*brw_WHILE(struct brw_codegen
*p
);
417 brw_inst
*brw_BREAK(struct brw_codegen
*p
);
418 brw_inst
*brw_CONT(struct brw_codegen
*p
);
419 brw_inst
*gen6_HALT(struct brw_codegen
*p
);
423 void brw_land_fwd_jump(struct brw_codegen
*p
, int jmp_insn_idx
);
425 brw_inst
*brw_JMPI(struct brw_codegen
*p
, struct brw_reg index
,
426 unsigned predicate_control
);
428 void brw_NOP(struct brw_codegen
*p
);
430 void brw_WAIT(struct brw_codegen
*p
);
432 /* Special case: there is never a destination, execution size will be
435 void brw_CMP(struct brw_codegen
*p
,
437 unsigned conditional
,
439 struct brw_reg src1
);
442 brw_untyped_atomic(struct brw_codegen
*p
,
444 struct brw_reg payload
,
445 struct brw_reg surface
,
448 bool response_expected
,
449 bool header_present
);
452 brw_untyped_surface_read(struct brw_codegen
*p
,
454 struct brw_reg payload
,
455 struct brw_reg surface
,
457 unsigned num_channels
);
460 brw_untyped_surface_write(struct brw_codegen
*p
,
461 struct brw_reg payload
,
462 struct brw_reg surface
,
464 unsigned num_channels
,
465 bool header_present
);
468 brw_typed_atomic(struct brw_codegen
*p
,
470 struct brw_reg payload
,
471 struct brw_reg surface
,
474 bool response_expected
,
475 bool header_present
);
478 brw_typed_surface_read(struct brw_codegen
*p
,
480 struct brw_reg payload
,
481 struct brw_reg surface
,
483 unsigned num_channels
,
484 bool header_present
);
487 brw_typed_surface_write(struct brw_codegen
*p
,
488 struct brw_reg payload
,
489 struct brw_reg surface
,
491 unsigned num_channels
,
492 bool header_present
);
495 brw_byte_scattered_read(struct brw_codegen
*p
,
497 struct brw_reg payload
,
498 struct brw_reg surface
,
503 brw_byte_scattered_write(struct brw_codegen
*p
,
504 struct brw_reg payload
,
505 struct brw_reg surface
,
508 bool header_present
);
511 brw_memory_fence(struct brw_codegen
*p
,
515 brw_pixel_interpolator_query(struct brw_codegen
*p
,
522 unsigned response_length
);
525 brw_find_live_channel(struct brw_codegen
*p
,
527 struct brw_reg mask
);
530 brw_broadcast(struct brw_codegen
*p
,
536 brw_rounding_mode(struct brw_codegen
*p
,
537 enum brw_rnd_mode mode
);
539 /***********************************************************************
543 void brw_copy_indirect_to_indirect(struct brw_codegen
*p
,
544 struct brw_indirect dst_ptr
,
545 struct brw_indirect src_ptr
,
548 void brw_copy_from_indirect(struct brw_codegen
*p
,
550 struct brw_indirect ptr
,
553 void brw_copy4(struct brw_codegen
*p
,
558 void brw_copy8(struct brw_codegen
*p
,
563 void brw_math_invert( struct brw_codegen
*p
,
567 void brw_set_src1(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg reg
);
569 void brw_set_uip_jip(struct brw_codegen
*p
, int start_offset
);
571 enum brw_conditional_mod
brw_negate_cmod(uint32_t cmod
);
572 enum brw_conditional_mod
brw_swap_cmod(uint32_t cmod
);
574 /* brw_eu_compact.c */
575 void brw_init_compaction_tables(const struct gen_device_info
*devinfo
);
576 void brw_compact_instructions(struct brw_codegen
*p
, int start_offset
,
577 struct disasm_info
*disasm
);
578 void brw_uncompact_instruction(const struct gen_device_info
*devinfo
,
579 brw_inst
*dst
, brw_compact_inst
*src
);
580 bool brw_try_compact_instruction(const struct gen_device_info
*devinfo
,
581 brw_compact_inst
*dst
, const brw_inst
*src
);
583 void brw_debug_compact_uncompact(const struct gen_device_info
*devinfo
,
584 brw_inst
*orig
, brw_inst
*uncompacted
);
586 /* brw_eu_validate.c */
587 bool brw_validate_instructions(const struct gen_device_info
*devinfo
,
588 const void *assembly
, int start_offset
, int end_offset
,
589 struct disasm_info
*disasm
);
592 next_offset(const struct gen_device_info
*devinfo
, void *store
, int offset
)
594 brw_inst
*insn
= (brw_inst
*)((char *)store
+ offset
);
596 if (brw_inst_cmpt_control(devinfo
, insn
))
603 /* The union is an implementation detail used by brw_opcode_desc() to handle
604 * opcodes that have been reused for different instructions across hardware
607 * The gens field acts as a tag. If it is non-zero, name points to a string
608 * containing the instruction mnemonic. If it is zero, the table field is
609 * valid and either points to a secondary opcode_desc table with 'size'
610 * elements or is NULL and no such instruction exists for the opcode.
618 const struct opcode_desc
*table
;
626 const struct opcode_desc
*
627 brw_opcode_desc(const struct gen_device_info
*devinfo
, enum opcode opcode
);
630 is_3src(const struct gen_device_info
*devinfo
, enum opcode opcode
)
632 const struct opcode_desc
*desc
= brw_opcode_desc(devinfo
, opcode
);
633 return desc
&& desc
->nsrc
== 3;
636 /** Maximum SEND message length */
637 #define BRW_MAX_MSG_LENGTH 15
639 /** First MRF register used by pull loads */
640 #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
642 /** First MRF register used by spills */
643 #define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)