2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
39 #include "brw_eu_defines.h"
41 #include "brw_disasm_info.h"
47 #define BRW_EU_MAX_INSN_STACK 5
49 struct brw_insn_state
{
50 /* One of BRW_EXECUTE_* */
53 /* Group in units of channels */
56 /* Compression control on gen4-5 */
59 /* One of BRW_MASK_* */
60 unsigned mask_control
:1;
64 /* One of BRW_ALIGN_* */
65 unsigned access_mode
:1;
67 /* One of BRW_PREDICATE_* */
68 enum brw_predicate predicate
:4;
72 /* Flag subreg. Bottom bit is subreg, top bit is reg */
73 unsigned flag_subreg
:2;
75 bool acc_wr_control
:1;
79 /* A helper for accessing the last instruction emitted. This makes it easy
80 * to set various bits on an instruction without having to create temporary
81 * variable and assign the emitted instruction to those.
83 #define brw_last_inst (&p->store[p->nr_insn - 1])
89 unsigned int next_insn_offset
;
93 /* Allow clients to push/pop instruction state:
95 struct brw_insn_state stack
[BRW_EU_MAX_INSN_STACK
];
96 struct brw_insn_state
*current
;
98 /** Whether or not the user wants automatic exec sizes
100 * If true, codegen will try to automatically infer the exec size of an
101 * instruction from the width of the destination register. If false, it
102 * will take whatever is set by brw_set_default_exec_size verbatim.
104 * This is set to true by default in brw_init_codegen.
106 bool automatic_exec_sizes
;
108 bool single_program_flow
;
109 const struct gen_device_info
*devinfo
;
111 /* Control flow stacks:
112 * - if_stack contains IF and ELSE instructions which must be patched
113 * (and popped) once the matching ENDIF instruction is encountered.
115 * Just store the instruction pointer(an index).
119 int if_stack_array_size
;
122 * loop_stack contains the instruction pointers of the starts of loops which
123 * must be patched (and popped) once the matching WHILE instruction is
128 * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
129 * blocks they were popping out of, to fix up the mask stack. This tracks
130 * the IF/ENDIF nesting in each current nested loop level.
132 int *if_depth_in_loop
;
133 int loop_stack_depth
;
134 int loop_stack_array_size
;
137 void brw_pop_insn_state( struct brw_codegen
*p
);
138 void brw_push_insn_state( struct brw_codegen
*p
);
139 unsigned brw_get_default_exec_size(struct brw_codegen
*p
);
140 unsigned brw_get_default_group(struct brw_codegen
*p
);
141 unsigned brw_get_default_access_mode(struct brw_codegen
*p
);
142 void brw_set_default_exec_size(struct brw_codegen
*p
, unsigned value
);
143 void brw_set_default_mask_control( struct brw_codegen
*p
, unsigned value
);
144 void brw_set_default_saturate( struct brw_codegen
*p
, bool enable
);
145 void brw_set_default_access_mode( struct brw_codegen
*p
, unsigned access_mode
);
146 void brw_inst_set_compression(const struct gen_device_info
*devinfo
,
147 brw_inst
*inst
, bool on
);
148 void brw_set_default_compression(struct brw_codegen
*p
, bool on
);
149 void brw_inst_set_group(const struct gen_device_info
*devinfo
,
150 brw_inst
*inst
, unsigned group
);
151 void brw_set_default_group(struct brw_codegen
*p
, unsigned group
);
152 void brw_set_default_compression_control(struct brw_codegen
*p
, enum brw_compression c
);
153 void brw_set_default_predicate_control( struct brw_codegen
*p
, unsigned pc
);
154 void brw_set_default_predicate_inverse(struct brw_codegen
*p
, bool predicate_inverse
);
155 void brw_set_default_flag_reg(struct brw_codegen
*p
, int reg
, int subreg
);
156 void brw_set_default_acc_write_control(struct brw_codegen
*p
, unsigned value
);
158 void brw_init_codegen(const struct gen_device_info
*, struct brw_codegen
*p
,
160 int brw_disassemble_inst(FILE *file
, const struct gen_device_info
*devinfo
,
161 const struct brw_inst
*inst
, bool is_compacted
);
162 void brw_disassemble(const struct gen_device_info
*devinfo
,
163 const void *assembly
, int start
, int end
, FILE *out
);
164 const unsigned *brw_get_program( struct brw_codegen
*p
, unsigned *sz
);
166 bool brw_try_override_assembly(struct brw_codegen
*p
, int start_offset
,
167 const char *identifier
);
169 brw_inst
*brw_next_insn(struct brw_codegen
*p
, unsigned opcode
);
170 void brw_set_dest(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg dest
);
171 void brw_set_src0(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg reg
);
173 void gen6_resolve_implied_move(struct brw_codegen
*p
,
175 unsigned msg_reg_nr
);
177 /* Helpers for regular instructions:
180 brw_inst *brw_##OP(struct brw_codegen *p, \
181 struct brw_reg dest, \
182 struct brw_reg src0);
185 brw_inst *brw_##OP(struct brw_codegen *p, \
186 struct brw_reg dest, \
187 struct brw_reg src0, \
188 struct brw_reg src1);
191 brw_inst *brw_##OP(struct brw_codegen *p, \
192 struct brw_reg dest, \
193 struct brw_reg src0, \
194 struct brw_reg src1, \
195 struct brw_reg src2);
198 void brw_##OP(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0);
251 /* Helpers for SEND instruction:
255 * Construct a message descriptor immediate with the specified common
256 * descriptor controls.
258 static inline uint32_t
259 brw_message_desc(const struct gen_device_info
*devinfo
,
261 unsigned response_length
,
264 if (devinfo
->gen
>= 5) {
265 return (SET_BITS(msg_length
, 28, 25) |
266 SET_BITS(response_length
, 24, 20) |
267 SET_BITS(header_present
, 19, 19));
269 return (SET_BITS(msg_length
, 23, 20) |
270 SET_BITS(response_length
, 19, 16));
274 static inline unsigned
275 brw_message_desc_mlen(const struct gen_device_info
*devinfo
, uint32_t desc
)
277 if (devinfo
->gen
>= 5)
278 return GET_BITS(desc
, 28, 25);
280 return GET_BITS(desc
, 23, 20);
283 static inline unsigned
284 brw_message_desc_rlen(const struct gen_device_info
*devinfo
, uint32_t desc
)
286 if (devinfo
->gen
>= 5)
287 return GET_BITS(desc
, 24, 20);
289 return GET_BITS(desc
, 19, 16);
293 brw_message_desc_header_present(ASSERTED
const struct gen_device_info
*devinfo
,
296 assert(devinfo
->gen
>= 5);
297 return GET_BITS(desc
, 19, 19);
300 static inline unsigned
301 brw_message_ex_desc(UNUSED
const struct gen_device_info
*devinfo
,
302 unsigned ex_msg_length
)
304 return SET_BITS(ex_msg_length
, 9, 6);
307 static inline unsigned
308 brw_message_ex_desc_ex_mlen(UNUSED
const struct gen_device_info
*devinfo
,
311 return GET_BITS(ex_desc
, 9, 6);
315 * Construct a message descriptor immediate with the specified sampler
318 static inline uint32_t
319 brw_sampler_desc(const struct gen_device_info
*devinfo
,
320 unsigned binding_table_index
,
324 unsigned return_format
)
326 const unsigned desc
= (SET_BITS(binding_table_index
, 7, 0) |
327 SET_BITS(sampler
, 11, 8));
328 if (devinfo
->gen
>= 7)
329 return (desc
| SET_BITS(msg_type
, 16, 12) |
330 SET_BITS(simd_mode
, 18, 17));
331 else if (devinfo
->gen
>= 5)
332 return (desc
| SET_BITS(msg_type
, 15, 12) |
333 SET_BITS(simd_mode
, 17, 16));
334 else if (devinfo
->is_g4x
)
335 return desc
| SET_BITS(msg_type
, 15, 12);
337 return (desc
| SET_BITS(return_format
, 13, 12) |
338 SET_BITS(msg_type
, 15, 14));
341 static inline unsigned
342 brw_sampler_desc_binding_table_index(UNUSED
const struct gen_device_info
*devinfo
,
345 return GET_BITS(desc
, 7, 0);
348 static inline unsigned
349 brw_sampler_desc_sampler(UNUSED
const struct gen_device_info
*devinfo
, uint32_t desc
)
351 return GET_BITS(desc
, 11, 8);
354 static inline unsigned
355 brw_sampler_desc_msg_type(const struct gen_device_info
*devinfo
, uint32_t desc
)
357 if (devinfo
->gen
>= 7)
358 return GET_BITS(desc
, 16, 12);
359 else if (devinfo
->gen
>= 5 || devinfo
->is_g4x
)
360 return GET_BITS(desc
, 15, 12);
362 return GET_BITS(desc
, 15, 14);
365 static inline unsigned
366 brw_sampler_desc_simd_mode(const struct gen_device_info
*devinfo
, uint32_t desc
)
368 assert(devinfo
->gen
>= 5);
369 if (devinfo
->gen
>= 7)
370 return GET_BITS(desc
, 18, 17);
372 return GET_BITS(desc
, 17, 16);
375 static inline unsigned
376 brw_sampler_desc_return_format(ASSERTED
const struct gen_device_info
*devinfo
,
379 assert(devinfo
->gen
== 4 && !devinfo
->is_g4x
);
380 return GET_BITS(desc
, 13, 12);
384 * Construct a message descriptor for the dataport
386 static inline uint32_t
387 brw_dp_desc(const struct gen_device_info
*devinfo
,
388 unsigned binding_table_index
,
390 unsigned msg_control
)
392 /* Prior to gen6, things are too inconsistent; use the dp_read/write_desc
395 assert(devinfo
->gen
>= 6);
396 const unsigned desc
= SET_BITS(binding_table_index
, 7, 0);
397 if (devinfo
->gen
>= 8) {
398 return (desc
| SET_BITS(msg_control
, 13, 8) |
399 SET_BITS(msg_type
, 18, 14));
400 } else if (devinfo
->gen
>= 7) {
401 return (desc
| SET_BITS(msg_control
, 13, 8) |
402 SET_BITS(msg_type
, 17, 14));
404 return (desc
| SET_BITS(msg_control
, 12, 8) |
405 SET_BITS(msg_type
, 16, 13));
409 static inline unsigned
410 brw_dp_desc_binding_table_index(UNUSED
const struct gen_device_info
*devinfo
,
413 return GET_BITS(desc
, 7, 0);
416 static inline unsigned
417 brw_dp_desc_msg_type(const struct gen_device_info
*devinfo
, uint32_t desc
)
419 assert(devinfo
->gen
>= 6);
420 if (devinfo
->gen
>= 8)
421 return GET_BITS(desc
, 18, 14);
422 else if (devinfo
->gen
>= 7)
423 return GET_BITS(desc
, 17, 14);
425 return GET_BITS(desc
, 16, 13);
428 static inline unsigned
429 brw_dp_desc_msg_control(const struct gen_device_info
*devinfo
, uint32_t desc
)
431 assert(devinfo
->gen
>= 6);
432 if (devinfo
->gen
>= 7)
433 return GET_BITS(desc
, 13, 8);
435 return GET_BITS(desc
, 12, 8);
439 * Construct a message descriptor immediate with the specified dataport read
442 static inline uint32_t
443 brw_dp_read_desc(const struct gen_device_info
*devinfo
,
444 unsigned binding_table_index
,
445 unsigned msg_control
,
447 unsigned target_cache
)
449 if (devinfo
->gen
>= 6)
450 return brw_dp_desc(devinfo
, binding_table_index
, msg_type
, msg_control
);
451 else if (devinfo
->gen
>= 5 || devinfo
->is_g4x
)
452 return (SET_BITS(binding_table_index
, 7, 0) |
453 SET_BITS(msg_control
, 10, 8) |
454 SET_BITS(msg_type
, 13, 11) |
455 SET_BITS(target_cache
, 15, 14));
457 return (SET_BITS(binding_table_index
, 7, 0) |
458 SET_BITS(msg_control
, 11, 8) |
459 SET_BITS(msg_type
, 13, 12) |
460 SET_BITS(target_cache
, 15, 14));
463 static inline unsigned
464 brw_dp_read_desc_msg_type(const struct gen_device_info
*devinfo
, uint32_t desc
)
466 if (devinfo
->gen
>= 6)
467 return brw_dp_desc_msg_type(devinfo
, desc
);
468 else if (devinfo
->gen
>= 5 || devinfo
->is_g4x
)
469 return GET_BITS(desc
, 13, 11);
471 return GET_BITS(desc
, 13, 12);
474 static inline unsigned
475 brw_dp_read_desc_msg_control(const struct gen_device_info
*devinfo
,
478 if (devinfo
->gen
>= 6)
479 return brw_dp_desc_msg_control(devinfo
, desc
);
480 else if (devinfo
->gen
>= 5 || devinfo
->is_g4x
)
481 return GET_BITS(desc
, 10, 8);
483 return GET_BITS(desc
, 11, 8);
487 * Construct a message descriptor immediate with the specified dataport write
490 static inline uint32_t
491 brw_dp_write_desc(const struct gen_device_info
*devinfo
,
492 unsigned binding_table_index
,
493 unsigned msg_control
,
495 unsigned last_render_target
,
496 unsigned send_commit_msg
)
498 assert(devinfo
->gen
<= 6 || !send_commit_msg
);
499 if (devinfo
->gen
>= 6)
500 return brw_dp_desc(devinfo
, binding_table_index
, msg_type
, msg_control
) |
501 SET_BITS(last_render_target
, 12, 12) |
502 SET_BITS(send_commit_msg
, 17, 17);
504 return (SET_BITS(binding_table_index
, 7, 0) |
505 SET_BITS(msg_control
, 11, 8) |
506 SET_BITS(last_render_target
, 11, 11) |
507 SET_BITS(msg_type
, 14, 12) |
508 SET_BITS(send_commit_msg
, 15, 15));
511 static inline unsigned
512 brw_dp_write_desc_msg_type(const struct gen_device_info
*devinfo
,
515 if (devinfo
->gen
>= 6)
516 return brw_dp_desc_msg_type(devinfo
, desc
);
518 return GET_BITS(desc
, 14, 12);
521 static inline unsigned
522 brw_dp_write_desc_msg_control(const struct gen_device_info
*devinfo
,
525 if (devinfo
->gen
>= 6)
526 return brw_dp_desc_msg_control(devinfo
, desc
);
528 return GET_BITS(desc
, 11, 8);
532 brw_dp_write_desc_last_render_target(const struct gen_device_info
*devinfo
,
535 if (devinfo
->gen
>= 6)
536 return GET_BITS(desc
, 12, 12);
538 return GET_BITS(desc
, 11, 11);
542 brw_dp_write_desc_write_commit(const struct gen_device_info
*devinfo
,
545 assert(devinfo
->gen
<= 6);
546 if (devinfo
->gen
>= 6)
547 return GET_BITS(desc
, 17, 17);
549 return GET_BITS(desc
, 15, 15);
553 * Construct a message descriptor immediate with the specified dataport
554 * surface function controls.
556 static inline uint32_t
557 brw_dp_surface_desc(const struct gen_device_info
*devinfo
,
559 unsigned msg_control
)
561 assert(devinfo
->gen
>= 7);
562 /* We'll OR in the binding table index later */
563 return brw_dp_desc(devinfo
, 0, msg_type
, msg_control
);
566 static inline uint32_t
567 brw_dp_untyped_atomic_desc(const struct gen_device_info
*devinfo
,
568 unsigned exec_size
, /**< 0 for SIMD4x2 */
570 bool response_expected
)
572 assert(exec_size
<= 8 || exec_size
== 16);
575 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
577 msg_type
= HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP
;
579 msg_type
= HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2
;
582 msg_type
= GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP
;
585 const unsigned msg_control
=
586 SET_BITS(atomic_op
, 3, 0) |
587 SET_BITS(0 < exec_size
&& exec_size
<= 8, 4, 4) |
588 SET_BITS(response_expected
, 5, 5);
590 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
593 static inline uint32_t
594 brw_dp_untyped_atomic_float_desc(const struct gen_device_info
*devinfo
,
597 bool response_expected
)
599 assert(exec_size
<= 8 || exec_size
== 16);
600 assert(devinfo
->gen
>= 9);
602 assert(exec_size
> 0);
603 const unsigned msg_type
= GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP
;
605 const unsigned msg_control
=
606 SET_BITS(atomic_op
, 1, 0) |
607 SET_BITS(exec_size
<= 8, 4, 4) |
608 SET_BITS(response_expected
, 5, 5);
610 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
613 static inline unsigned
614 brw_mdc_cmask(unsigned num_channels
)
616 /* See also MDC_CMASK in the SKL PRM Vol 2d. */
617 return 0xf & (0xf << num_channels
);
620 static inline uint32_t
621 brw_dp_untyped_surface_rw_desc(const struct gen_device_info
*devinfo
,
622 unsigned exec_size
, /**< 0 for SIMD4x2 */
623 unsigned num_channels
,
626 assert(exec_size
<= 8 || exec_size
== 16);
630 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
631 msg_type
= HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE
;
633 msg_type
= GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE
;
637 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
638 msg_type
= HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ
;
640 msg_type
= GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ
;
644 /* SIMD4x2 is only valid for read messages on IVB; use SIMD8 instead */
645 if (write
&& devinfo
->gen
== 7 && !devinfo
->is_haswell
&& exec_size
== 0)
648 /* See also MDC_SM3 in the SKL PRM Vol 2d. */
649 const unsigned simd_mode
= exec_size
== 0 ? 0 : /* SIMD4x2 */
650 exec_size
<= 8 ? 2 : 1;
652 const unsigned msg_control
=
653 SET_BITS(brw_mdc_cmask(num_channels
), 3, 0) |
654 SET_BITS(simd_mode
, 5, 4);
656 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
659 static inline unsigned
660 brw_mdc_ds(unsigned bit_size
)
664 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE
;
666 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD
;
668 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD
;
670 unreachable("Unsupported bit_size for byte scattered messages");
674 static inline uint32_t
675 brw_dp_byte_scattered_rw_desc(const struct gen_device_info
*devinfo
,
680 assert(exec_size
<= 8 || exec_size
== 16);
682 assert(devinfo
->gen
> 7 || devinfo
->is_haswell
);
683 const unsigned msg_type
=
684 write
? HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE
:
685 HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ
;
687 assert(exec_size
> 0);
688 const unsigned msg_control
=
689 SET_BITS(exec_size
== 16, 0, 0) |
690 SET_BITS(brw_mdc_ds(bit_size
), 3, 2);
692 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
695 static inline uint32_t
696 brw_dp_a64_untyped_surface_rw_desc(const struct gen_device_info
*devinfo
,
697 unsigned exec_size
, /**< 0 for SIMD4x2 */
698 unsigned num_channels
,
701 assert(exec_size
<= 8 || exec_size
== 16);
702 assert(devinfo
->gen
>= 8);
705 write
? GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE
:
706 GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ
;
708 /* See also MDC_SM3 in the SKL PRM Vol 2d. */
709 const unsigned simd_mode
= exec_size
== 0 ? 0 : /* SIMD4x2 */
710 exec_size
<= 8 ? 2 : 1;
712 const unsigned msg_control
=
713 SET_BITS(brw_mdc_cmask(num_channels
), 3, 0) |
714 SET_BITS(simd_mode
, 5, 4);
716 return brw_dp_desc(devinfo
, BRW_BTI_STATELESS
, msg_type
, msg_control
);
720 * Calculate the data size (see MDC_A64_DS in the "Structures" volume of the
723 static inline uint32_t
724 brw_mdc_a64_ds(unsigned elems
)
732 unreachable("Unsupported elmeent count for A64 scattered message");
736 static inline uint32_t
737 brw_dp_a64_byte_scattered_rw_desc(const struct gen_device_info
*devinfo
,
738 unsigned exec_size
, /**< 0 for SIMD4x2 */
742 assert(exec_size
<= 8 || exec_size
== 16);
743 assert(devinfo
->gen
>= 8);
746 write
? GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE
:
747 GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ
;
749 const unsigned msg_control
=
750 SET_BITS(GEN8_A64_SCATTERED_SUBTYPE_BYTE
, 1, 0) |
751 SET_BITS(brw_mdc_a64_ds(bit_size
/ 8), 3, 2) |
752 SET_BITS(exec_size
== 16, 4, 4);
754 return brw_dp_desc(devinfo
, BRW_BTI_STATELESS
, msg_type
, msg_control
);
757 static inline uint32_t
758 brw_dp_a64_untyped_atomic_desc(const struct gen_device_info
*devinfo
,
759 ASSERTED
unsigned exec_size
, /**< 0 for SIMD4x2 */
762 bool response_expected
)
764 assert(exec_size
== 8);
765 assert(devinfo
->gen
>= 8);
766 assert(bit_size
== 32 || bit_size
== 64);
768 const unsigned msg_type
= GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP
;
770 const unsigned msg_control
=
771 SET_BITS(atomic_op
, 3, 0) |
772 SET_BITS(bit_size
== 64, 4, 4) |
773 SET_BITS(response_expected
, 5, 5);
775 return brw_dp_desc(devinfo
, BRW_BTI_STATELESS
, msg_type
, msg_control
);
778 static inline uint32_t
779 brw_dp_a64_untyped_atomic_float_desc(const struct gen_device_info
*devinfo
,
780 ASSERTED
unsigned exec_size
,
782 bool response_expected
)
784 assert(exec_size
== 8);
785 assert(devinfo
->gen
>= 9);
787 assert(exec_size
> 0);
788 const unsigned msg_type
= GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP
;
790 const unsigned msg_control
=
791 SET_BITS(atomic_op
, 1, 0) |
792 SET_BITS(response_expected
, 5, 5);
794 return brw_dp_desc(devinfo
, BRW_BTI_STATELESS
, msg_type
, msg_control
);
797 static inline uint32_t
798 brw_dp_typed_atomic_desc(const struct gen_device_info
*devinfo
,
802 bool response_expected
)
804 assert(exec_size
> 0 || exec_group
== 0);
805 assert(exec_group
% 8 == 0);
808 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
809 if (exec_size
== 0) {
810 msg_type
= HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2
;
812 msg_type
= HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP
;
815 /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
816 assert(exec_size
> 0);
817 msg_type
= GEN7_DATAPORT_RC_TYPED_ATOMIC_OP
;
820 const bool high_sample_mask
= (exec_group
/ 8) % 2 == 1;
822 const unsigned msg_control
=
823 SET_BITS(atomic_op
, 3, 0) |
824 SET_BITS(high_sample_mask
, 4, 4) |
825 SET_BITS(response_expected
, 5, 5);
827 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
830 static inline uint32_t
831 brw_dp_typed_surface_rw_desc(const struct gen_device_info
*devinfo
,
834 unsigned num_channels
,
837 assert(exec_size
> 0 || exec_group
== 0);
838 assert(exec_group
% 8 == 0);
840 /* Typed surface reads and writes don't support SIMD16 */
841 assert(exec_size
<= 8);
845 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
846 msg_type
= HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE
;
848 msg_type
= GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE
;
851 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
852 msg_type
= HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ
;
854 msg_type
= GEN7_DATAPORT_RC_TYPED_SURFACE_READ
;
858 /* See also MDC_SG3 in the SKL PRM Vol 2d. */
859 unsigned msg_control
;
860 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
861 /* See also MDC_SG3 in the SKL PRM Vol 2d. */
862 const unsigned slot_group
= exec_size
== 0 ? 0 : /* SIMD4x2 */
863 1 + ((exec_group
/ 8) % 2);
866 SET_BITS(brw_mdc_cmask(num_channels
), 3, 0) |
867 SET_BITS(slot_group
, 5, 4);
869 /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
870 assert(exec_size
> 0);
871 const unsigned slot_group
= ((exec_group
/ 8) % 2);
874 SET_BITS(brw_mdc_cmask(num_channels
), 3, 0) |
875 SET_BITS(slot_group
, 5, 5);
878 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
882 * Construct a message descriptor immediate with the specified pixel
883 * interpolator function controls.
885 static inline uint32_t
886 brw_pixel_interp_desc(UNUSED
const struct gen_device_info
*devinfo
,
892 return (SET_BITS(slot_group
, 11, 11) |
893 SET_BITS(msg_type
, 13, 12) |
894 SET_BITS(!!noperspective
, 14, 14) |
895 SET_BITS(simd_mode
, 16, 16));
898 void brw_urb_WRITE(struct brw_codegen
*p
,
902 enum brw_urb_write_flags flags
,
904 unsigned response_length
,
909 * Send message to shared unit \p sfid with a possibly indirect descriptor \p
910 * desc. If \p desc is not an immediate it will be transparently loaded to an
911 * address register using an OR instruction.
914 brw_send_indirect_message(struct brw_codegen
*p
,
917 struct brw_reg payload
,
923 brw_send_indirect_split_message(struct brw_codegen
*p
,
926 struct brw_reg payload0
,
927 struct brw_reg payload1
,
930 struct brw_reg ex_desc
,
931 unsigned ex_desc_imm
,
934 void brw_ff_sync(struct brw_codegen
*p
,
939 unsigned response_length
,
942 void brw_svb_write(struct brw_codegen
*p
,
946 unsigned binding_table_index
,
947 bool send_commit_msg
);
949 brw_inst
*brw_fb_WRITE(struct brw_codegen
*p
,
950 struct brw_reg payload
,
951 struct brw_reg implied_header
,
952 unsigned msg_control
,
953 unsigned binding_table_index
,
955 unsigned response_length
,
957 bool last_render_target
,
958 bool header_present
);
960 brw_inst
*gen9_fb_READ(struct brw_codegen
*p
,
962 struct brw_reg payload
,
963 unsigned binding_table_index
,
965 unsigned response_length
,
968 void brw_SAMPLE(struct brw_codegen
*p
,
972 unsigned binding_table_index
,
975 unsigned response_length
,
977 unsigned header_present
,
979 unsigned return_format
);
981 void brw_adjust_sampler_state_pointer(struct brw_codegen
*p
,
982 struct brw_reg header
,
983 struct brw_reg sampler_index
);
985 void gen4_math(struct brw_codegen
*p
,
990 unsigned precision
);
992 void gen6_math(struct brw_codegen
*p
,
996 struct brw_reg src1
);
998 void brw_oword_block_read(struct brw_codegen
*p
,
1002 uint32_t bind_table_index
);
1004 unsigned brw_scratch_surface_idx(const struct brw_codegen
*p
);
1006 void brw_oword_block_read_scratch(struct brw_codegen
*p
,
1007 struct brw_reg dest
,
1012 void brw_oword_block_write_scratch(struct brw_codegen
*p
,
1017 void gen7_block_read_scratch(struct brw_codegen
*p
,
1018 struct brw_reg dest
,
1022 void brw_shader_time_add(struct brw_codegen
*p
,
1023 struct brw_reg payload
,
1024 uint32_t surf_index
);
1027 * Return the generation-specific jump distance scaling factor.
1029 * Given the number of instructions to jump, we need to scale by
1030 * some number to obtain the actual jump distance to program in an
1033 static inline unsigned
1034 brw_jump_scale(const struct gen_device_info
*devinfo
)
1036 /* Broadwell measures jump targets in bytes. */
1037 if (devinfo
->gen
>= 8)
1040 /* Ironlake and later measure jump targets in 64-bit data chunks (in order
1041 * (to support compaction), so each 128-bit instruction requires 2 chunks.
1043 if (devinfo
->gen
>= 5)
1046 /* Gen4 simply uses the number of 128-bit instructions. */
1050 void brw_barrier(struct brw_codegen
*p
, struct brw_reg src
);
1052 /* If/else/endif. Works by manipulating the execution flags on each
1055 brw_inst
*brw_IF(struct brw_codegen
*p
, unsigned execute_size
);
1056 brw_inst
*gen6_IF(struct brw_codegen
*p
, enum brw_conditional_mod conditional
,
1057 struct brw_reg src0
, struct brw_reg src1
);
1059 void brw_ELSE(struct brw_codegen
*p
);
1060 void brw_ENDIF(struct brw_codegen
*p
);
1064 brw_inst
*brw_DO(struct brw_codegen
*p
, unsigned execute_size
);
1066 brw_inst
*brw_WHILE(struct brw_codegen
*p
);
1068 brw_inst
*brw_BREAK(struct brw_codegen
*p
);
1069 brw_inst
*brw_CONT(struct brw_codegen
*p
);
1070 brw_inst
*gen6_HALT(struct brw_codegen
*p
);
1074 void brw_land_fwd_jump(struct brw_codegen
*p
, int jmp_insn_idx
);
1076 brw_inst
*brw_JMPI(struct brw_codegen
*p
, struct brw_reg index
,
1077 unsigned predicate_control
);
1079 void brw_NOP(struct brw_codegen
*p
);
1081 void brw_WAIT(struct brw_codegen
*p
);
1083 /* Special case: there is never a destination, execution size will be
1086 void brw_CMP(struct brw_codegen
*p
,
1087 struct brw_reg dest
,
1088 unsigned conditional
,
1089 struct brw_reg src0
,
1090 struct brw_reg src1
);
1093 brw_untyped_atomic(struct brw_codegen
*p
,
1095 struct brw_reg payload
,
1096 struct brw_reg surface
,
1098 unsigned msg_length
,
1099 bool response_expected
,
1100 bool header_present
);
1103 brw_untyped_surface_read(struct brw_codegen
*p
,
1105 struct brw_reg payload
,
1106 struct brw_reg surface
,
1107 unsigned msg_length
,
1108 unsigned num_channels
);
1111 brw_untyped_surface_write(struct brw_codegen
*p
,
1112 struct brw_reg payload
,
1113 struct brw_reg surface
,
1114 unsigned msg_length
,
1115 unsigned num_channels
,
1116 bool header_present
);
1119 brw_memory_fence(struct brw_codegen
*p
,
1122 enum opcode send_op
,
1127 brw_pixel_interpolator_query(struct brw_codegen
*p
,
1128 struct brw_reg dest
,
1132 struct brw_reg data
,
1133 unsigned msg_length
,
1134 unsigned response_length
);
1137 brw_find_live_channel(struct brw_codegen
*p
,
1139 struct brw_reg mask
);
1142 brw_broadcast(struct brw_codegen
*p
,
1145 struct brw_reg idx
);
1148 brw_float_controls_mode(struct brw_codegen
*p
,
1149 unsigned mode
, unsigned mask
);
1151 /***********************************************************************
1155 void brw_copy_indirect_to_indirect(struct brw_codegen
*p
,
1156 struct brw_indirect dst_ptr
,
1157 struct brw_indirect src_ptr
,
1160 void brw_copy_from_indirect(struct brw_codegen
*p
,
1162 struct brw_indirect ptr
,
1165 void brw_copy4(struct brw_codegen
*p
,
1170 void brw_copy8(struct brw_codegen
*p
,
1175 void brw_math_invert( struct brw_codegen
*p
,
1177 struct brw_reg src
);
1179 void brw_set_src1(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg reg
);
1181 void brw_set_desc_ex(struct brw_codegen
*p
, brw_inst
*insn
,
1182 unsigned desc
, unsigned ex_desc
);
1185 brw_set_desc(struct brw_codegen
*p
, brw_inst
*insn
, unsigned desc
)
1187 brw_set_desc_ex(p
, insn
, desc
, 0);
1190 void brw_set_uip_jip(struct brw_codegen
*p
, int start_offset
);
1192 enum brw_conditional_mod
brw_negate_cmod(uint32_t cmod
);
1193 enum brw_conditional_mod
brw_swap_cmod(uint32_t cmod
);
1195 /* brw_eu_compact.c */
1196 void brw_init_compaction_tables(const struct gen_device_info
*devinfo
);
1197 void brw_compact_instructions(struct brw_codegen
*p
, int start_offset
,
1198 struct disasm_info
*disasm
);
1199 void brw_uncompact_instruction(const struct gen_device_info
*devinfo
,
1200 brw_inst
*dst
, brw_compact_inst
*src
);
1201 bool brw_try_compact_instruction(const struct gen_device_info
*devinfo
,
1202 brw_compact_inst
*dst
, const brw_inst
*src
);
1204 void brw_debug_compact_uncompact(const struct gen_device_info
*devinfo
,
1205 brw_inst
*orig
, brw_inst
*uncompacted
);
1207 /* brw_eu_validate.c */
1208 bool brw_validate_instructions(const struct gen_device_info
*devinfo
,
1209 const void *assembly
, int start_offset
, int end_offset
,
1210 struct disasm_info
*disasm
);
1213 next_offset(const struct gen_device_info
*devinfo
, void *store
, int offset
)
1215 brw_inst
*insn
= (brw_inst
*)((char *)store
+ offset
);
1217 if (brw_inst_cmpt_control(devinfo
, insn
))
1223 struct opcode_desc
{
1224 /* The union is an implementation detail used by brw_opcode_desc() to handle
1225 * opcodes that have been reused for different instructions across hardware
1228 * The gens field acts as a tag. If it is non-zero, name points to a string
1229 * containing the instruction mnemonic. If it is zero, the table field is
1230 * valid and either points to a secondary opcode_desc table with 'size'
1231 * elements or is NULL and no such instruction exists for the opcode.
1239 const struct opcode_desc
*table
;
1247 const struct opcode_desc
*
1248 brw_opcode_desc(const struct gen_device_info
*devinfo
, enum opcode opcode
);
1251 is_3src(const struct gen_device_info
*devinfo
, enum opcode opcode
)
1253 const struct opcode_desc
*desc
= brw_opcode_desc(devinfo
, opcode
);
1254 return desc
&& desc
->nsrc
== 3;
1257 /** Maximum SEND message length */
1258 #define BRW_MAX_MSG_LENGTH 15
1260 /** First MRF register used by pull loads */
1261 #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
1263 /** First MRF register used by spills */
1264 #define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)