2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
39 #include "brw_eu_defines.h"
41 #include "brw_disasm_info.h"
47 #define BRW_EU_MAX_INSN_STACK 5
49 struct brw_insn_state
{
50 /* One of BRW_EXECUTE_* */
53 /* Group in units of channels */
56 /* Compression control on gen4-5 */
59 /* One of BRW_MASK_* */
60 unsigned mask_control
:1;
64 /* One of BRW_ALIGN_* */
65 unsigned access_mode
:1;
67 /* One of BRW_PREDICATE_* */
68 enum brw_predicate predicate
:4;
72 /* Flag subreg. Bottom bit is subreg, top bit is reg */
73 unsigned flag_subreg
:2;
75 bool acc_wr_control
:1;
79 /* A helper for accessing the last instruction emitted. This makes it easy
80 * to set various bits on an instruction without having to create temporary
81 * variable and assign the emitted instruction to those.
83 #define brw_last_inst (&p->store[p->nr_insn - 1])
89 unsigned int next_insn_offset
;
93 /* Allow clients to push/pop instruction state:
95 struct brw_insn_state stack
[BRW_EU_MAX_INSN_STACK
];
96 struct brw_insn_state
*current
;
98 /** Whether or not the user wants automatic exec sizes
100 * If true, codegen will try to automatically infer the exec size of an
101 * instruction from the width of the destination register. If false, it
102 * will take whatever is set by brw_set_default_exec_size verbatim.
104 * This is set to true by default in brw_init_codegen.
106 bool automatic_exec_sizes
;
108 bool single_program_flow
;
109 const struct gen_device_info
*devinfo
;
111 /* Control flow stacks:
112 * - if_stack contains IF and ELSE instructions which must be patched
113 * (and popped) once the matching ENDIF instruction is encountered.
115 * Just store the instruction pointer(an index).
119 int if_stack_array_size
;
122 * loop_stack contains the instruction pointers of the starts of loops which
123 * must be patched (and popped) once the matching WHILE instruction is
128 * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
129 * blocks they were popping out of, to fix up the mask stack. This tracks
130 * the IF/ENDIF nesting in each current nested loop level.
132 int *if_depth_in_loop
;
133 int loop_stack_depth
;
134 int loop_stack_array_size
;
137 void brw_pop_insn_state( struct brw_codegen
*p
);
138 void brw_push_insn_state( struct brw_codegen
*p
);
139 unsigned brw_get_default_exec_size(struct brw_codegen
*p
);
140 unsigned brw_get_default_group(struct brw_codegen
*p
);
141 unsigned brw_get_default_access_mode(struct brw_codegen
*p
);
142 void brw_set_default_exec_size(struct brw_codegen
*p
, unsigned value
);
143 void brw_set_default_mask_control( struct brw_codegen
*p
, unsigned value
);
144 void brw_set_default_saturate( struct brw_codegen
*p
, bool enable
);
145 void brw_set_default_access_mode( struct brw_codegen
*p
, unsigned access_mode
);
146 void brw_inst_set_compression(const struct gen_device_info
*devinfo
,
147 brw_inst
*inst
, bool on
);
148 void brw_set_default_compression(struct brw_codegen
*p
, bool on
);
149 void brw_inst_set_group(const struct gen_device_info
*devinfo
,
150 brw_inst
*inst
, unsigned group
);
151 void brw_set_default_group(struct brw_codegen
*p
, unsigned group
);
152 void brw_set_default_compression_control(struct brw_codegen
*p
, enum brw_compression c
);
153 void brw_set_default_predicate_control( struct brw_codegen
*p
, unsigned pc
);
154 void brw_set_default_predicate_inverse(struct brw_codegen
*p
, bool predicate_inverse
);
155 void brw_set_default_flag_reg(struct brw_codegen
*p
, int reg
, int subreg
);
156 void brw_set_default_acc_write_control(struct brw_codegen
*p
, unsigned value
);
158 void brw_init_codegen(const struct gen_device_info
*, struct brw_codegen
*p
,
160 int brw_disassemble_inst(FILE *file
, const struct gen_device_info
*devinfo
,
161 const struct brw_inst
*inst
, bool is_compacted
);
162 void brw_disassemble(const struct gen_device_info
*devinfo
,
163 const void *assembly
, int start
, int end
, FILE *out
);
164 const unsigned *brw_get_program( struct brw_codegen
*p
, unsigned *sz
);
166 brw_inst
*brw_next_insn(struct brw_codegen
*p
, unsigned opcode
);
167 void brw_set_dest(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg dest
);
168 void brw_set_src0(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg reg
);
170 void gen6_resolve_implied_move(struct brw_codegen
*p
,
172 unsigned msg_reg_nr
);
174 /* Helpers for regular instructions:
177 brw_inst *brw_##OP(struct brw_codegen *p, \
178 struct brw_reg dest, \
179 struct brw_reg src0);
182 brw_inst *brw_##OP(struct brw_codegen *p, \
183 struct brw_reg dest, \
184 struct brw_reg src0, \
185 struct brw_reg src1);
188 brw_inst *brw_##OP(struct brw_codegen *p, \
189 struct brw_reg dest, \
190 struct brw_reg src0, \
191 struct brw_reg src1, \
192 struct brw_reg src2);
195 void brw_##OP(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0);
246 /* Helpers for SEND instruction:
248 void brw_set_sampler_message(struct brw_codegen
*p
,
250 unsigned binding_table_index
,
253 unsigned response_length
,
255 unsigned header_present
,
257 unsigned return_format
);
259 void brw_set_message_descriptor(struct brw_codegen
*p
,
261 enum brw_message_target sfid
,
263 unsigned response_length
,
267 void brw_set_dp_read_message(struct brw_codegen
*p
,
269 unsigned binding_table_index
,
270 unsigned msg_control
,
272 unsigned target_cache
,
275 unsigned response_length
);
277 void brw_set_dp_write_message(struct brw_codegen
*p
,
279 unsigned binding_table_index
,
280 unsigned msg_control
,
282 unsigned target_cache
,
285 unsigned last_render_target
,
286 unsigned response_length
,
287 unsigned end_of_thread
,
288 unsigned send_commit_msg
);
290 void brw_urb_WRITE(struct brw_codegen
*p
,
294 enum brw_urb_write_flags flags
,
296 unsigned response_length
,
301 * Send message to shared unit \p sfid with a possibly indirect descriptor \p
302 * desc. If \p desc is not an immediate it will be transparently loaded to an
303 * address register using an OR instruction. The returned instruction can be
304 * passed as argument to the usual brw_set_*_message() functions in order to
305 * specify any additional descriptor bits -- If \p desc is an immediate this
306 * will be the SEND instruction itself, otherwise it will be the OR
310 brw_send_indirect_message(struct brw_codegen
*p
,
313 struct brw_reg payload
,
314 struct brw_reg desc
);
316 void brw_ff_sync(struct brw_codegen
*p
,
321 unsigned response_length
,
324 void brw_svb_write(struct brw_codegen
*p
,
328 unsigned binding_table_index
,
329 bool send_commit_msg
);
331 brw_inst
*brw_fb_WRITE(struct brw_codegen
*p
,
332 struct brw_reg payload
,
333 struct brw_reg implied_header
,
334 unsigned msg_control
,
335 unsigned binding_table_index
,
337 unsigned response_length
,
339 bool last_render_target
,
340 bool header_present
);
342 brw_inst
*gen9_fb_READ(struct brw_codegen
*p
,
344 struct brw_reg payload
,
345 unsigned binding_table_index
,
347 unsigned response_length
,
350 void brw_SAMPLE(struct brw_codegen
*p
,
354 unsigned binding_table_index
,
357 unsigned response_length
,
359 unsigned header_present
,
361 unsigned return_format
);
363 void brw_adjust_sampler_state_pointer(struct brw_codegen
*p
,
364 struct brw_reg header
,
365 struct brw_reg sampler_index
);
367 void gen4_math(struct brw_codegen
*p
,
372 unsigned precision
);
374 void gen6_math(struct brw_codegen
*p
,
378 struct brw_reg src1
);
380 void brw_oword_block_read(struct brw_codegen
*p
,
384 uint32_t bind_table_index
);
386 unsigned brw_scratch_surface_idx(const struct brw_codegen
*p
);
388 void brw_oword_block_read_scratch(struct brw_codegen
*p
,
394 void brw_oword_block_write_scratch(struct brw_codegen
*p
,
399 void gen7_block_read_scratch(struct brw_codegen
*p
,
404 void brw_shader_time_add(struct brw_codegen
*p
,
405 struct brw_reg payload
,
406 uint32_t surf_index
);
409 * Return the generation-specific jump distance scaling factor.
411 * Given the number of instructions to jump, we need to scale by
412 * some number to obtain the actual jump distance to program in an
415 static inline unsigned
416 brw_jump_scale(const struct gen_device_info
*devinfo
)
418 /* Broadwell measures jump targets in bytes. */
419 if (devinfo
->gen
>= 8)
422 /* Ironlake and later measure jump targets in 64-bit data chunks (in order
423 * (to support compaction), so each 128-bit instruction requires 2 chunks.
425 if (devinfo
->gen
>= 5)
428 /* Gen4 simply uses the number of 128-bit instructions. */
432 void brw_barrier(struct brw_codegen
*p
, struct brw_reg src
);
434 /* If/else/endif. Works by manipulating the execution flags on each
437 brw_inst
*brw_IF(struct brw_codegen
*p
, unsigned execute_size
);
438 brw_inst
*gen6_IF(struct brw_codegen
*p
, enum brw_conditional_mod conditional
,
439 struct brw_reg src0
, struct brw_reg src1
);
441 void brw_ELSE(struct brw_codegen
*p
);
442 void brw_ENDIF(struct brw_codegen
*p
);
446 brw_inst
*brw_DO(struct brw_codegen
*p
, unsigned execute_size
);
448 brw_inst
*brw_WHILE(struct brw_codegen
*p
);
450 brw_inst
*brw_BREAK(struct brw_codegen
*p
);
451 brw_inst
*brw_CONT(struct brw_codegen
*p
);
452 brw_inst
*gen6_HALT(struct brw_codegen
*p
);
456 void brw_land_fwd_jump(struct brw_codegen
*p
, int jmp_insn_idx
);
458 brw_inst
*brw_JMPI(struct brw_codegen
*p
, struct brw_reg index
,
459 unsigned predicate_control
);
461 void brw_NOP(struct brw_codegen
*p
);
463 void brw_WAIT(struct brw_codegen
*p
);
465 /* Special case: there is never a destination, execution size will be
468 void brw_CMP(struct brw_codegen
*p
,
470 unsigned conditional
,
472 struct brw_reg src1
);
475 brw_untyped_atomic(struct brw_codegen
*p
,
477 struct brw_reg payload
,
478 struct brw_reg surface
,
481 bool response_expected
,
482 bool header_present
);
485 brw_untyped_surface_read(struct brw_codegen
*p
,
487 struct brw_reg payload
,
488 struct brw_reg surface
,
490 unsigned num_channels
);
493 brw_untyped_surface_write(struct brw_codegen
*p
,
494 struct brw_reg payload
,
495 struct brw_reg surface
,
497 unsigned num_channels
,
498 bool header_present
);
501 brw_typed_atomic(struct brw_codegen
*p
,
503 struct brw_reg payload
,
504 struct brw_reg surface
,
507 bool response_expected
,
508 bool header_present
);
511 brw_typed_surface_read(struct brw_codegen
*p
,
513 struct brw_reg payload
,
514 struct brw_reg surface
,
516 unsigned num_channels
,
517 bool header_present
);
520 brw_typed_surface_write(struct brw_codegen
*p
,
521 struct brw_reg payload
,
522 struct brw_reg surface
,
524 unsigned num_channels
,
525 bool header_present
);
528 brw_byte_scattered_read(struct brw_codegen
*p
,
530 struct brw_reg payload
,
531 struct brw_reg surface
,
536 brw_byte_scattered_write(struct brw_codegen
*p
,
537 struct brw_reg payload
,
538 struct brw_reg surface
,
541 bool header_present
);
544 brw_memory_fence(struct brw_codegen
*p
,
546 enum opcode send_op
);
549 brw_pixel_interpolator_query(struct brw_codegen
*p
,
556 unsigned response_length
);
559 brw_find_live_channel(struct brw_codegen
*p
,
561 struct brw_reg mask
);
564 brw_broadcast(struct brw_codegen
*p
,
570 brw_rounding_mode(struct brw_codegen
*p
,
571 enum brw_rnd_mode mode
);
573 /***********************************************************************
577 void brw_copy_indirect_to_indirect(struct brw_codegen
*p
,
578 struct brw_indirect dst_ptr
,
579 struct brw_indirect src_ptr
,
582 void brw_copy_from_indirect(struct brw_codegen
*p
,
584 struct brw_indirect ptr
,
587 void brw_copy4(struct brw_codegen
*p
,
592 void brw_copy8(struct brw_codegen
*p
,
597 void brw_math_invert( struct brw_codegen
*p
,
601 void brw_set_src1(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg reg
);
603 void brw_set_desc_ex(struct brw_codegen
*p
, brw_inst
*insn
,
604 unsigned desc
, unsigned ex_desc
);
607 brw_set_desc(struct brw_codegen
*p
, brw_inst
*insn
, unsigned desc
)
609 brw_set_desc_ex(p
, insn
, desc
, 0);
612 void brw_set_uip_jip(struct brw_codegen
*p
, int start_offset
);
614 enum brw_conditional_mod
brw_negate_cmod(uint32_t cmod
);
615 enum brw_conditional_mod
brw_swap_cmod(uint32_t cmod
);
617 /* brw_eu_compact.c */
618 void brw_init_compaction_tables(const struct gen_device_info
*devinfo
);
619 void brw_compact_instructions(struct brw_codegen
*p
, int start_offset
,
620 struct disasm_info
*disasm
);
621 void brw_uncompact_instruction(const struct gen_device_info
*devinfo
,
622 brw_inst
*dst
, brw_compact_inst
*src
);
623 bool brw_try_compact_instruction(const struct gen_device_info
*devinfo
,
624 brw_compact_inst
*dst
, const brw_inst
*src
);
626 void brw_debug_compact_uncompact(const struct gen_device_info
*devinfo
,
627 brw_inst
*orig
, brw_inst
*uncompacted
);
629 /* brw_eu_validate.c */
630 bool brw_validate_instructions(const struct gen_device_info
*devinfo
,
631 const void *assembly
, int start_offset
, int end_offset
,
632 struct disasm_info
*disasm
);
635 next_offset(const struct gen_device_info
*devinfo
, void *store
, int offset
)
637 brw_inst
*insn
= (brw_inst
*)((char *)store
+ offset
);
639 if (brw_inst_cmpt_control(devinfo
, insn
))
646 /* The union is an implementation detail used by brw_opcode_desc() to handle
647 * opcodes that have been reused for different instructions across hardware
650 * The gens field acts as a tag. If it is non-zero, name points to a string
651 * containing the instruction mnemonic. If it is zero, the table field is
652 * valid and either points to a secondary opcode_desc table with 'size'
653 * elements or is NULL and no such instruction exists for the opcode.
661 const struct opcode_desc
*table
;
669 const struct opcode_desc
*
670 brw_opcode_desc(const struct gen_device_info
*devinfo
, enum opcode opcode
);
673 is_3src(const struct gen_device_info
*devinfo
, enum opcode opcode
)
675 const struct opcode_desc
*desc
= brw_opcode_desc(devinfo
, opcode
);
676 return desc
&& desc
->nsrc
== 3;
679 /** Maximum SEND message length */
680 #define BRW_MAX_MSG_LENGTH 15
682 /** First MRF register used by pull loads */
683 #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
685 /** First MRF register used by spills */
686 #define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)