i965/fs: Add infrastructure for generating CSEL instructions.
[mesa.git] / src / intel / compiler / brw_eu.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32
33 #ifndef BRW_EU_H
34 #define BRW_EU_H
35
36 #include <stdbool.h>
37 #include "brw_inst.h"
38 #include "brw_eu_defines.h"
39 #include "brw_reg.h"
40 #include "brw_disasm_info.h"
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 #define BRW_EU_MAX_INSN_STACK 5
47
48 /* A helper for accessing the last instruction emitted. This makes it easy
49 * to set various bits on an instruction without having to create temporary
50 * variable and assign the emitted instruction to those.
51 */
52 #define brw_last_inst (&p->store[p->nr_insn - 1])
53
54 struct brw_codegen {
55 brw_inst *store;
56 int store_size;
57 unsigned nr_insn;
58 unsigned int next_insn_offset;
59
60 void *mem_ctx;
61
62 /* Allow clients to push/pop instruction state:
63 */
64 brw_inst stack[BRW_EU_MAX_INSN_STACK];
65 bool compressed_stack[BRW_EU_MAX_INSN_STACK];
66 brw_inst *current;
67
68 /** Whether or not the user wants automatic exec sizes
69 *
70 * If true, codegen will try to automatically infer the exec size of an
71 * instruction from the width of the destination register. If false, it
72 * will take whatever is set by brw_set_default_exec_size verbatim.
73 *
74 * This is set to true by default in brw_init_codegen.
75 */
76 bool automatic_exec_sizes;
77
78 bool single_program_flow;
79 const struct gen_device_info *devinfo;
80
81 /* Control flow stacks:
82 * - if_stack contains IF and ELSE instructions which must be patched
83 * (and popped) once the matching ENDIF instruction is encountered.
84 *
85 * Just store the instruction pointer(an index).
86 */
87 int *if_stack;
88 int if_stack_depth;
89 int if_stack_array_size;
90
91 /**
92 * loop_stack contains the instruction pointers of the starts of loops which
93 * must be patched (and popped) once the matching WHILE instruction is
94 * encountered.
95 */
96 int *loop_stack;
97 /**
98 * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
99 * blocks they were popping out of, to fix up the mask stack. This tracks
100 * the IF/ENDIF nesting in each current nested loop level.
101 */
102 int *if_depth_in_loop;
103 int loop_stack_depth;
104 int loop_stack_array_size;
105 };
106
107 void brw_pop_insn_state( struct brw_codegen *p );
108 void brw_push_insn_state( struct brw_codegen *p );
109 void brw_set_default_exec_size(struct brw_codegen *p, unsigned value);
110 void brw_set_default_mask_control( struct brw_codegen *p, unsigned value );
111 void brw_set_default_saturate( struct brw_codegen *p, bool enable );
112 void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode );
113 void brw_inst_set_compression(const struct gen_device_info *devinfo,
114 brw_inst *inst, bool on);
115 void brw_set_default_compression(struct brw_codegen *p, bool on);
116 void brw_inst_set_group(const struct gen_device_info *devinfo,
117 brw_inst *inst, unsigned group);
118 void brw_set_default_group(struct brw_codegen *p, unsigned group);
119 void brw_set_default_compression_control(struct brw_codegen *p, enum brw_compression c);
120 void brw_set_default_predicate_control( struct brw_codegen *p, unsigned pc );
121 void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse);
122 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg);
123 void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value);
124
125 void brw_init_codegen(const struct gen_device_info *, struct brw_codegen *p,
126 void *mem_ctx);
127 int brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
128 const struct brw_inst *inst, bool is_compacted);
129 void brw_disassemble(const struct gen_device_info *devinfo,
130 const void *assembly, int start, int end, FILE *out);
131 const unsigned *brw_get_program( struct brw_codegen *p, unsigned *sz );
132
133 brw_inst *brw_next_insn(struct brw_codegen *p, unsigned opcode);
134 void brw_set_dest(struct brw_codegen *p, brw_inst *insn, struct brw_reg dest);
135 void brw_set_src0(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg);
136
137 void gen6_resolve_implied_move(struct brw_codegen *p,
138 struct brw_reg *src,
139 unsigned msg_reg_nr);
140
141 /* Helpers for regular instructions:
142 */
143 #define ALU1(OP) \
144 brw_inst *brw_##OP(struct brw_codegen *p, \
145 struct brw_reg dest, \
146 struct brw_reg src0);
147
148 #define ALU2(OP) \
149 brw_inst *brw_##OP(struct brw_codegen *p, \
150 struct brw_reg dest, \
151 struct brw_reg src0, \
152 struct brw_reg src1);
153
154 #define ALU3(OP) \
155 brw_inst *brw_##OP(struct brw_codegen *p, \
156 struct brw_reg dest, \
157 struct brw_reg src0, \
158 struct brw_reg src1, \
159 struct brw_reg src2);
160
161 #define ROUND(OP) \
162 void brw_##OP(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0);
163
164 ALU1(MOV)
165 ALU2(SEL)
166 ALU1(NOT)
167 ALU2(AND)
168 ALU2(OR)
169 ALU2(XOR)
170 ALU2(SHR)
171 ALU2(SHL)
172 ALU1(DIM)
173 ALU2(ASR)
174 ALU3(CSEL)
175 ALU1(F32TO16)
176 ALU1(F16TO32)
177 ALU2(ADD)
178 ALU2(AVG)
179 ALU2(MUL)
180 ALU1(FRC)
181 ALU1(RNDD)
182 ALU2(MAC)
183 ALU2(MACH)
184 ALU1(LZD)
185 ALU2(DP4)
186 ALU2(DPH)
187 ALU2(DP3)
188 ALU2(DP2)
189 ALU2(LINE)
190 ALU2(PLN)
191 ALU3(MAD)
192 ALU3(LRP)
193 ALU1(BFREV)
194 ALU3(BFE)
195 ALU2(BFI1)
196 ALU3(BFI2)
197 ALU1(FBH)
198 ALU1(FBL)
199 ALU1(CBIT)
200 ALU2(ADDC)
201 ALU2(SUBB)
202 ALU2(MAC)
203
204 ROUND(RNDZ)
205 ROUND(RNDE)
206
207 #undef ALU1
208 #undef ALU2
209 #undef ALU3
210 #undef ROUND
211
212
213 /* Helpers for SEND instruction:
214 */
215 void brw_set_sampler_message(struct brw_codegen *p,
216 brw_inst *insn,
217 unsigned binding_table_index,
218 unsigned sampler,
219 unsigned msg_type,
220 unsigned response_length,
221 unsigned msg_length,
222 unsigned header_present,
223 unsigned simd_mode,
224 unsigned return_format);
225
226 void brw_set_message_descriptor(struct brw_codegen *p,
227 brw_inst *inst,
228 enum brw_message_target sfid,
229 unsigned msg_length,
230 unsigned response_length,
231 bool header_present,
232 bool end_of_thread);
233
234 void brw_set_dp_read_message(struct brw_codegen *p,
235 brw_inst *insn,
236 unsigned binding_table_index,
237 unsigned msg_control,
238 unsigned msg_type,
239 unsigned target_cache,
240 unsigned msg_length,
241 bool header_present,
242 unsigned response_length);
243
244 void brw_set_dp_write_message(struct brw_codegen *p,
245 brw_inst *insn,
246 unsigned binding_table_index,
247 unsigned msg_control,
248 unsigned msg_type,
249 unsigned target_cache,
250 unsigned msg_length,
251 bool header_present,
252 unsigned last_render_target,
253 unsigned response_length,
254 unsigned end_of_thread,
255 unsigned send_commit_msg);
256
257 void brw_urb_WRITE(struct brw_codegen *p,
258 struct brw_reg dest,
259 unsigned msg_reg_nr,
260 struct brw_reg src0,
261 enum brw_urb_write_flags flags,
262 unsigned msg_length,
263 unsigned response_length,
264 unsigned offset,
265 unsigned swizzle);
266
267 /**
268 * Send message to shared unit \p sfid with a possibly indirect descriptor \p
269 * desc. If \p desc is not an immediate it will be transparently loaded to an
270 * address register using an OR instruction. The returned instruction can be
271 * passed as argument to the usual brw_set_*_message() functions in order to
272 * specify any additional descriptor bits -- If \p desc is an immediate this
273 * will be the SEND instruction itself, otherwise it will be the OR
274 * instruction.
275 */
276 struct brw_inst *
277 brw_send_indirect_message(struct brw_codegen *p,
278 unsigned sfid,
279 struct brw_reg dst,
280 struct brw_reg payload,
281 struct brw_reg desc);
282
283 void brw_ff_sync(struct brw_codegen *p,
284 struct brw_reg dest,
285 unsigned msg_reg_nr,
286 struct brw_reg src0,
287 bool allocate,
288 unsigned response_length,
289 bool eot);
290
291 void brw_svb_write(struct brw_codegen *p,
292 struct brw_reg dest,
293 unsigned msg_reg_nr,
294 struct brw_reg src0,
295 unsigned binding_table_index,
296 bool send_commit_msg);
297
298 void brw_fb_WRITE(struct brw_codegen *p,
299 struct brw_reg payload,
300 struct brw_reg implied_header,
301 unsigned msg_control,
302 unsigned binding_table_index,
303 unsigned msg_length,
304 unsigned response_length,
305 bool eot,
306 bool last_render_target,
307 bool header_present);
308
309 brw_inst *gen9_fb_READ(struct brw_codegen *p,
310 struct brw_reg dst,
311 struct brw_reg payload,
312 unsigned binding_table_index,
313 unsigned msg_length,
314 unsigned response_length,
315 bool per_sample);
316
317 void brw_SAMPLE(struct brw_codegen *p,
318 struct brw_reg dest,
319 unsigned msg_reg_nr,
320 struct brw_reg src0,
321 unsigned binding_table_index,
322 unsigned sampler,
323 unsigned msg_type,
324 unsigned response_length,
325 unsigned msg_length,
326 unsigned header_present,
327 unsigned simd_mode,
328 unsigned return_format);
329
330 void brw_adjust_sampler_state_pointer(struct brw_codegen *p,
331 struct brw_reg header,
332 struct brw_reg sampler_index);
333
334 void gen4_math(struct brw_codegen *p,
335 struct brw_reg dest,
336 unsigned function,
337 unsigned msg_reg_nr,
338 struct brw_reg src,
339 unsigned precision );
340
341 void gen6_math(struct brw_codegen *p,
342 struct brw_reg dest,
343 unsigned function,
344 struct brw_reg src0,
345 struct brw_reg src1);
346
347 void brw_oword_block_read(struct brw_codegen *p,
348 struct brw_reg dest,
349 struct brw_reg mrf,
350 uint32_t offset,
351 uint32_t bind_table_index);
352
353 unsigned brw_scratch_surface_idx(const struct brw_codegen *p);
354
355 void brw_oword_block_read_scratch(struct brw_codegen *p,
356 struct brw_reg dest,
357 struct brw_reg mrf,
358 int num_regs,
359 unsigned offset);
360
361 void brw_oword_block_write_scratch(struct brw_codegen *p,
362 struct brw_reg mrf,
363 int num_regs,
364 unsigned offset);
365
366 void gen7_block_read_scratch(struct brw_codegen *p,
367 struct brw_reg dest,
368 int num_regs,
369 unsigned offset);
370
371 void brw_shader_time_add(struct brw_codegen *p,
372 struct brw_reg payload,
373 uint32_t surf_index);
374
375 /**
376 * Return the generation-specific jump distance scaling factor.
377 *
378 * Given the number of instructions to jump, we need to scale by
379 * some number to obtain the actual jump distance to program in an
380 * instruction.
381 */
382 static inline unsigned
383 brw_jump_scale(const struct gen_device_info *devinfo)
384 {
385 /* Broadwell measures jump targets in bytes. */
386 if (devinfo->gen >= 8)
387 return 16;
388
389 /* Ironlake and later measure jump targets in 64-bit data chunks (in order
390 * (to support compaction), so each 128-bit instruction requires 2 chunks.
391 */
392 if (devinfo->gen >= 5)
393 return 2;
394
395 /* Gen4 simply uses the number of 128-bit instructions. */
396 return 1;
397 }
398
399 void brw_barrier(struct brw_codegen *p, struct brw_reg src);
400
401 /* If/else/endif. Works by manipulating the execution flags on each
402 * channel.
403 */
404 brw_inst *brw_IF(struct brw_codegen *p, unsigned execute_size);
405 brw_inst *gen6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional,
406 struct brw_reg src0, struct brw_reg src1);
407
408 void brw_ELSE(struct brw_codegen *p);
409 void brw_ENDIF(struct brw_codegen *p);
410
411 /* DO/WHILE loops:
412 */
413 brw_inst *brw_DO(struct brw_codegen *p, unsigned execute_size);
414
415 brw_inst *brw_WHILE(struct brw_codegen *p);
416
417 brw_inst *brw_BREAK(struct brw_codegen *p);
418 brw_inst *brw_CONT(struct brw_codegen *p);
419 brw_inst *gen6_HALT(struct brw_codegen *p);
420
421 /* Forward jumps:
422 */
423 void brw_land_fwd_jump(struct brw_codegen *p, int jmp_insn_idx);
424
425 brw_inst *brw_JMPI(struct brw_codegen *p, struct brw_reg index,
426 unsigned predicate_control);
427
428 void brw_NOP(struct brw_codegen *p);
429
430 void brw_WAIT(struct brw_codegen *p);
431
432 /* Special case: there is never a destination, execution size will be
433 * taken from src0:
434 */
435 void brw_CMP(struct brw_codegen *p,
436 struct brw_reg dest,
437 unsigned conditional,
438 struct brw_reg src0,
439 struct brw_reg src1);
440
441 void
442 brw_untyped_atomic(struct brw_codegen *p,
443 struct brw_reg dst,
444 struct brw_reg payload,
445 struct brw_reg surface,
446 unsigned atomic_op,
447 unsigned msg_length,
448 bool response_expected,
449 bool header_present);
450
451 void
452 brw_untyped_surface_read(struct brw_codegen *p,
453 struct brw_reg dst,
454 struct brw_reg payload,
455 struct brw_reg surface,
456 unsigned msg_length,
457 unsigned num_channels);
458
459 void
460 brw_untyped_surface_write(struct brw_codegen *p,
461 struct brw_reg payload,
462 struct brw_reg surface,
463 unsigned msg_length,
464 unsigned num_channels,
465 bool header_present);
466
467 void
468 brw_typed_atomic(struct brw_codegen *p,
469 struct brw_reg dst,
470 struct brw_reg payload,
471 struct brw_reg surface,
472 unsigned atomic_op,
473 unsigned msg_length,
474 bool response_expected,
475 bool header_present);
476
477 void
478 brw_typed_surface_read(struct brw_codegen *p,
479 struct brw_reg dst,
480 struct brw_reg payload,
481 struct brw_reg surface,
482 unsigned msg_length,
483 unsigned num_channels,
484 bool header_present);
485
486 void
487 brw_typed_surface_write(struct brw_codegen *p,
488 struct brw_reg payload,
489 struct brw_reg surface,
490 unsigned msg_length,
491 unsigned num_channels,
492 bool header_present);
493
494 void
495 brw_byte_scattered_read(struct brw_codegen *p,
496 struct brw_reg dst,
497 struct brw_reg payload,
498 struct brw_reg surface,
499 unsigned msg_length,
500 unsigned bit_size);
501
502 void
503 brw_byte_scattered_write(struct brw_codegen *p,
504 struct brw_reg payload,
505 struct brw_reg surface,
506 unsigned msg_length,
507 unsigned bit_size,
508 bool header_present);
509
510 void
511 brw_memory_fence(struct brw_codegen *p,
512 struct brw_reg dst);
513
514 void
515 brw_pixel_interpolator_query(struct brw_codegen *p,
516 struct brw_reg dest,
517 struct brw_reg mrf,
518 bool noperspective,
519 unsigned mode,
520 struct brw_reg data,
521 unsigned msg_length,
522 unsigned response_length);
523
524 void
525 brw_find_live_channel(struct brw_codegen *p,
526 struct brw_reg dst,
527 struct brw_reg mask);
528
529 void
530 brw_broadcast(struct brw_codegen *p,
531 struct brw_reg dst,
532 struct brw_reg src,
533 struct brw_reg idx);
534
535 void
536 brw_rounding_mode(struct brw_codegen *p,
537 enum brw_rnd_mode mode);
538
539 /***********************************************************************
540 * brw_eu_util.c:
541 */
542
543 void brw_copy_indirect_to_indirect(struct brw_codegen *p,
544 struct brw_indirect dst_ptr,
545 struct brw_indirect src_ptr,
546 unsigned count);
547
548 void brw_copy_from_indirect(struct brw_codegen *p,
549 struct brw_reg dst,
550 struct brw_indirect ptr,
551 unsigned count);
552
553 void brw_copy4(struct brw_codegen *p,
554 struct brw_reg dst,
555 struct brw_reg src,
556 unsigned count);
557
558 void brw_copy8(struct brw_codegen *p,
559 struct brw_reg dst,
560 struct brw_reg src,
561 unsigned count);
562
563 void brw_math_invert( struct brw_codegen *p,
564 struct brw_reg dst,
565 struct brw_reg src);
566
567 void brw_set_src1(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg);
568
569 void brw_set_uip_jip(struct brw_codegen *p, int start_offset);
570
571 enum brw_conditional_mod brw_negate_cmod(uint32_t cmod);
572 enum brw_conditional_mod brw_swap_cmod(uint32_t cmod);
573
574 /* brw_eu_compact.c */
575 void brw_init_compaction_tables(const struct gen_device_info *devinfo);
576 void brw_compact_instructions(struct brw_codegen *p, int start_offset,
577 struct disasm_info *disasm);
578 void brw_uncompact_instruction(const struct gen_device_info *devinfo,
579 brw_inst *dst, brw_compact_inst *src);
580 bool brw_try_compact_instruction(const struct gen_device_info *devinfo,
581 brw_compact_inst *dst, const brw_inst *src);
582
583 void brw_debug_compact_uncompact(const struct gen_device_info *devinfo,
584 brw_inst *orig, brw_inst *uncompacted);
585
586 /* brw_eu_validate.c */
587 bool brw_validate_instructions(const struct gen_device_info *devinfo,
588 const void *assembly, int start_offset, int end_offset,
589 struct disasm_info *disasm);
590
591 static inline int
592 next_offset(const struct gen_device_info *devinfo, void *store, int offset)
593 {
594 brw_inst *insn = (brw_inst *)((char *)store + offset);
595
596 if (brw_inst_cmpt_control(devinfo, insn))
597 return offset + 8;
598 else
599 return offset + 16;
600 }
601
602 struct opcode_desc {
603 /* The union is an implementation detail used by brw_opcode_desc() to handle
604 * opcodes that have been reused for different instructions across hardware
605 * generations.
606 *
607 * The gens field acts as a tag. If it is non-zero, name points to a string
608 * containing the instruction mnemonic. If it is zero, the table field is
609 * valid and either points to a secondary opcode_desc table with 'size'
610 * elements or is NULL and no such instruction exists for the opcode.
611 */
612 union {
613 struct {
614 char *name;
615 int nsrc;
616 };
617 struct {
618 const struct opcode_desc *table;
619 unsigned size;
620 };
621 };
622 int ndst;
623 int gens;
624 };
625
626 const struct opcode_desc *
627 brw_opcode_desc(const struct gen_device_info *devinfo, enum opcode opcode);
628
629 static inline bool
630 is_3src(const struct gen_device_info *devinfo, enum opcode opcode)
631 {
632 const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
633 return desc && desc->nsrc == 3;
634 }
635
636 /** Maximum SEND message length */
637 #define BRW_MAX_MSG_LENGTH 15
638
639 /** First MRF register used by pull loads */
640 #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
641
642 /** First MRF register used by spills */
643 #define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)
644
645 #ifdef __cplusplus
646 }
647 #endif
648
649 #endif