2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_eu_compact.c
26 * Instruction compaction is a feature of G45 and newer hardware that allows
27 * for a smaller instruction encoding.
29 * The instruction cache is on the order of 32KB, and many programs generate
30 * far more instructions than that. The instruction cache is built to barely
31 * keep up with instruction dispatch ability in cache hit cases -- L1
32 * instruction cache misses that still hit in the next level could limit
33 * throughput by around 50%.
35 * The idea of instruction compaction is that most instructions use a tiny
36 * subset of the GPU functionality, so we can encode what would be a 16 byte
37 * instruction in 8 bytes using some lookup tables for various fields.
40 * Instruction compaction capabilities vary subtly by generation.
42 * G45's support for instruction compaction is very limited. Jump counts on
43 * this generation are in units of 16-byte uncompacted instructions. As such,
44 * all jump targets must be 16-byte aligned. Also, all instructions must be
45 * naturally aligned, i.e. uncompacted instructions must be 16-byte aligned.
46 * A G45-only instruction, NENOP, must be used to provide padding to align
47 * uncompacted instructions.
49 * Gen5 removes these restrictions and changes jump counts to be in units of
50 * 8-byte compacted instructions, allowing jump targets to be only 8-byte
51 * aligned. Uncompacted instructions can also be placed on 8-byte boundaries.
53 * Gen6 adds the ability to compact instructions with a limited range of
54 * immediate values. Compactable immediates have 12 unrestricted bits, and a
55 * 13th bit that's replicated through the high 20 bits, to create the 32-bit
56 * value of DW3 in the uncompacted instruction word.
58 * On Gen7 we can compact some control flow instructions with a small positive
59 * immediate in the low bits of DW3, like ENDIF with the JIP field. Other
60 * control flow instructions with UIP cannot be compacted, because of the
61 * replicated 13th bit. No control flow instructions can be compacted on Gen6
62 * since the jump count field is not in DW3.
68 * else JIP (plus UIP on BDW+)
70 * while JIP (must be negative)
72 * Gen 8 adds support for compacting 3-src instructions.
76 #include "brw_shader.h"
77 #include "brw_disasm_info.h"
78 #include "dev/gen_debug.h"
80 static const uint32_t g45_control_index_table
[32] = {
115 static const uint32_t g45_datatype_table
[32] = {
116 0b001000000000100001,
117 0b001011010110101101,
118 0b001000001000110001,
119 0b001111011110111101,
120 0b001011010110101100,
121 0b001000000110101101,
122 0b001000000000100000,
123 0b010100010110110001,
124 0b001100011000101101,
125 0b001000000000100010,
126 0b001000001000110110,
127 0b010000001000110001,
128 0b001000001000110010,
129 0b011000001000110010,
130 0b001111011110111100,
131 0b001000000100101000,
132 0b010100011000110001,
133 0b001010010100101001,
134 0b001000001000101001,
135 0b010000001000110110,
136 0b101000001000110001,
137 0b001011011000101101,
138 0b001000000100001001,
139 0b001011011000101100,
140 0b110100011000110001,
141 0b001000001110111101,
142 0b110000001000110001,
143 0b011000000100101010,
144 0b101000001000101001,
145 0b001011010110001100,
146 0b001000000110100001,
147 0b001010010100001000,
150 static const uint16_t g45_subreg_table
[32] = {
185 static const uint16_t g45_src_index_table
[32] = {
220 static const uint32_t gen6_control_index_table
[32] = {
255 static const uint32_t gen6_datatype_table
[32] = {
256 0b001001110000000000,
257 0b001000110000100000,
258 0b001001110000000001,
259 0b001000000001100000,
260 0b001010110100101001,
261 0b001000000110101101,
262 0b001100011000101100,
263 0b001011110110101101,
264 0b001000000111101100,
265 0b001000000001100001,
266 0b001000110010100101,
267 0b001000000001000001,
268 0b001000001000110001,
269 0b001000001000101001,
270 0b001000000000100000,
271 0b001000001000110010,
272 0b001010010100101001,
273 0b001011010010100101,
274 0b001000000110100101,
275 0b001100011000101001,
276 0b001011011000101100,
277 0b001011010110100101,
278 0b001011110110100101,
279 0b001111011110111101,
280 0b001111011110111100,
281 0b001111011110111101,
282 0b001111011110011101,
283 0b001111011110111110,
284 0b001000000000100001,
285 0b001000000000100010,
286 0b001001111111011101,
287 0b001000001110111110,
290 static const uint16_t gen6_subreg_table
[32] = {
325 static const uint16_t gen6_src_index_table
[32] = {
360 static const uint32_t gen7_control_index_table
[32] = {
361 0b0000000000000000010,
362 0b0000100000000000000,
363 0b0000100000000000001,
364 0b0000100000000000010,
365 0b0000100000000000011,
366 0b0000100000000000100,
367 0b0000100000000000101,
368 0b0000100000000000111,
369 0b0000100000000001000,
370 0b0000100000000001001,
371 0b0000100000000001101,
372 0b0000110000000000000,
373 0b0000110000000000001,
374 0b0000110000000000010,
375 0b0000110000000000011,
376 0b0000110000000000100,
377 0b0000110000000000101,
378 0b0000110000000000111,
379 0b0000110000000001001,
380 0b0000110000000001101,
381 0b0000110000000010000,
382 0b0000110000100000000,
383 0b0001000000000000000,
384 0b0001000000000000010,
385 0b0001000000000000100,
386 0b0001000000100000000,
387 0b0010110000000000000,
388 0b0010110000000010000,
389 0b0011000000000000000,
390 0b0011000000100000000,
391 0b0101000000000000000,
392 0b0101000000100000000,
395 static const uint32_t gen7_datatype_table
[32] = {
396 0b001000000000000001,
397 0b001000000000100000,
398 0b001000000000100001,
399 0b001000000001100001,
400 0b001000000010111101,
401 0b001000001011111101,
402 0b001000001110100001,
403 0b001000001110100101,
404 0b001000001110111101,
405 0b001000010000100001,
406 0b001000110000100000,
407 0b001000110000100001,
408 0b001001010010100101,
409 0b001001110010100100,
410 0b001001110010100101,
411 0b001111001110111101,
412 0b001111011110011101,
413 0b001111011110111100,
414 0b001111011110111101,
415 0b001111111110111100,
416 0b000000001000001100,
417 0b001000000000111101,
418 0b001000000010100101,
419 0b001000010000100000,
420 0b001001010010100100,
421 0b001001110010000100,
422 0b001010010100001001,
423 0b001101111110111101,
424 0b001111111110111101,
425 0b001011110110101100,
426 0b001010010100101000,
427 0b001010110100101000,
430 static const uint16_t gen7_subreg_table
[32] = {
465 static const uint16_t gen7_src_index_table
[32] = {
500 static const uint32_t gen8_control_index_table
[32] = {
501 0b0000000000000000010,
502 0b0000100000000000000,
503 0b0000100000000000001,
504 0b0000100000000000010,
505 0b0000100000000000011,
506 0b0000100000000000100,
507 0b0000100000000000101,
508 0b0000100000000000111,
509 0b0000100000000001000,
510 0b0000100000000001001,
511 0b0000100000000001101,
512 0b0000110000000000000,
513 0b0000110000000000001,
514 0b0000110000000000010,
515 0b0000110000000000011,
516 0b0000110000000000100,
517 0b0000110000000000101,
518 0b0000110000000000111,
519 0b0000110000000001001,
520 0b0000110000000001101,
521 0b0000110000000010000,
522 0b0000110000100000000,
523 0b0001000000000000000,
524 0b0001000000000000010,
525 0b0001000000000000100,
526 0b0001000000100000000,
527 0b0010110000000000000,
528 0b0010110000000010000,
529 0b0011000000000000000,
530 0b0011000000100000000,
531 0b0101000000000000000,
532 0b0101000000100000000,
535 static const uint32_t gen8_datatype_table
[32] = {
536 0b001000000000000000001,
537 0b001000000000001000000,
538 0b001000000000001000001,
539 0b001000000000011000001,
540 0b001000000000101011101,
541 0b001000000010111011101,
542 0b001000000011101000001,
543 0b001000000011101000101,
544 0b001000000011101011101,
545 0b001000001000001000001,
546 0b001000011000001000000,
547 0b001000011000001000001,
548 0b001000101000101000101,
549 0b001000111000101000100,
550 0b001000111000101000101,
551 0b001011100011101011101,
552 0b001011101011100011101,
553 0b001011101011101011100,
554 0b001011101011101011101,
555 0b001011111011101011100,
556 0b000000000010000001100,
557 0b001000000000001011101,
558 0b001000000000101000101,
559 0b001000001000001000000,
560 0b001000101000101000100,
561 0b001000111000100000100,
562 0b001001001001000001001,
563 0b001010111011101011101,
564 0b001011111011101011101,
565 0b001001111001101001100,
566 0b001001001001001001000,
567 0b001001011001001001000,
570 static const uint16_t gen8_subreg_table
[32] = {
605 static const uint16_t gen8_src_index_table
[32] = {
640 static const uint32_t gen11_datatype_table
[32] = {
641 0b001000000000000000001,
642 0b001000000000001000000,
643 0b001000000000001000001,
644 0b001000000000011000001,
645 0b001000000000101100101,
646 0b001000000101111100101,
647 0b001000000100101000001,
648 0b001000000100101000101,
649 0b001000000100101100101,
650 0b001000001000001000001,
651 0b001000011000001000000,
652 0b001000011000001000001,
653 0b001000101000101000101,
654 0b001000111000101000100,
655 0b001000111000101000101,
656 0b001100100100101100101,
657 0b001100101100100100101,
658 0b001100101100101100100,
659 0b001100101100101100101,
660 0b001100111100101100100,
661 0b000000000010000001100,
662 0b001000000000001100101,
663 0b001000000000101000101,
664 0b001000001000001000000,
665 0b001000101000101000100,
666 0b001000111000100000100,
667 0b001001001001000001001,
668 0b001101111100101100101,
669 0b001100111100101100101,
670 0b001001111001101001100,
671 0b001001001001001001000,
672 0b001001011001001001000,
675 /* This is actually the control index table for Cherryview (26 bits), but the
676 * only difference from Broadwell (24 bits) is that it has two extra 0-bits at
679 * The low 24 bits have the same mappings on both hardware.
681 static const uint32_t gen8_3src_control_index_table
[4] = {
682 0b00100000000110000000000001,
683 0b00000000000110000000000001,
684 0b00000000001000000000000001,
685 0b00000000001000000000100001,
688 /* This is actually the control index table for Cherryview (49 bits), but the
689 * only difference from Broadwell (46 bits) is that it has three extra 0-bits
692 * The low 44 bits have the same mappings on both hardware, and since the high
693 * three bits on Broadwell are zero, we can reuse Cherryview's table.
695 static const uint64_t gen8_3src_source_index_table
[4] = {
696 0b0000001110010011100100111001000001111000000000000,
697 0b0000001110010011100100111001000001111000000000010,
698 0b0000001110010011100100111001000001111000000001000,
699 0b0000001110010011100100111001000001111000000100000,
702 static const uint32_t *control_index_table
;
703 static const uint32_t *datatype_table
;
704 static const uint16_t *subreg_table
;
705 static const uint16_t *src_index_table
;
708 set_control_index(const struct gen_device_info
*devinfo
,
709 brw_compact_inst
*dst
, const brw_inst
*src
)
711 uint32_t uncompacted
= devinfo
->gen
>= 8 /* 17b/G45; 19b/IVB+ */
712 ? (brw_inst_bits(src
, 33, 31) << 16) | /* 3b */
713 (brw_inst_bits(src
, 23, 12) << 4) | /* 12b */
714 (brw_inst_bits(src
, 10, 9) << 2) | /* 2b */
715 (brw_inst_bits(src
, 34, 34) << 1) | /* 1b */
716 (brw_inst_bits(src
, 8, 8)) /* 1b */
717 : (brw_inst_bits(src
, 31, 31) << 16) | /* 1b */
718 (brw_inst_bits(src
, 23, 8)); /* 16b */
720 /* On gen7, the flag register and subregister numbers are integrated into
723 if (devinfo
->gen
== 7)
724 uncompacted
|= brw_inst_bits(src
, 90, 89) << 17; /* 2b */
726 for (int i
= 0; i
< 32; i
++) {
727 if (control_index_table
[i
] == uncompacted
) {
728 brw_compact_inst_set_control_index(devinfo
, dst
, i
);
737 set_datatype_index(const struct gen_device_info
*devinfo
, brw_compact_inst
*dst
,
740 uint32_t uncompacted
= devinfo
->gen
>= 8 /* 18b/G45+; 21b/BDW+ */
741 ? (brw_inst_bits(src
, 63, 61) << 18) | /* 3b */
742 (brw_inst_bits(src
, 94, 89) << 12) | /* 6b */
743 (brw_inst_bits(src
, 46, 35)) /* 12b */
744 : (brw_inst_bits(src
, 63, 61) << 15) | /* 3b */
745 (brw_inst_bits(src
, 46, 32)); /* 15b */
747 for (int i
= 0; i
< 32; i
++) {
748 if (datatype_table
[i
] == uncompacted
) {
749 brw_compact_inst_set_datatype_index(devinfo
, dst
, i
);
758 set_subreg_index(const struct gen_device_info
*devinfo
, brw_compact_inst
*dst
,
759 const brw_inst
*src
, bool is_immediate
)
761 uint16_t uncompacted
= /* 15b */
762 (brw_inst_bits(src
, 52, 48) << 0) | /* 5b */
763 (brw_inst_bits(src
, 68, 64) << 5); /* 5b */
766 uncompacted
|= brw_inst_bits(src
, 100, 96) << 10; /* 5b */
768 for (int i
= 0; i
< 32; i
++) {
769 if (subreg_table
[i
] == uncompacted
) {
770 brw_compact_inst_set_subreg_index(devinfo
, dst
, i
);
779 get_src_index(uint16_t uncompacted
,
782 for (int i
= 0; i
< 32; i
++) {
783 if (src_index_table
[i
] == uncompacted
) {
793 set_src0_index(const struct gen_device_info
*devinfo
,
794 brw_compact_inst
*dst
, const brw_inst
*src
)
797 uint16_t uncompacted
= brw_inst_bits(src
, 88, 77); /* 12b */
799 if (!get_src_index(uncompacted
, &compacted
))
802 brw_compact_inst_set_src0_index(devinfo
, dst
, compacted
);
808 set_src1_index(const struct gen_device_info
*devinfo
, brw_compact_inst
*dst
,
809 const brw_inst
*src
, bool is_immediate
)
814 compacted
= (brw_inst_imm_ud(devinfo
, src
) >> 8) & 0x1f;
816 uint16_t uncompacted
= brw_inst_bits(src
, 120, 109); /* 12b */
818 if (!get_src_index(uncompacted
, &compacted
))
822 brw_compact_inst_set_src1_index(devinfo
, dst
, compacted
);
828 set_3src_control_index(const struct gen_device_info
*devinfo
,
829 brw_compact_inst
*dst
, const brw_inst
*src
)
831 assert(devinfo
->gen
>= 8);
833 uint32_t uncompacted
= /* 24b/BDW; 26b/CHV */
834 (brw_inst_bits(src
, 34, 32) << 21) | /* 3b */
835 (brw_inst_bits(src
, 28, 8)); /* 21b */
837 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
)
838 uncompacted
|= brw_inst_bits(src
, 36, 35) << 24; /* 2b */
840 for (unsigned i
= 0; i
< ARRAY_SIZE(gen8_3src_control_index_table
); i
++) {
841 if (gen8_3src_control_index_table
[i
] == uncompacted
) {
842 brw_compact_inst_set_3src_control_index(devinfo
, dst
, i
);
851 set_3src_source_index(const struct gen_device_info
*devinfo
,
852 brw_compact_inst
*dst
, const brw_inst
*src
)
854 assert(devinfo
->gen
>= 8);
856 uint64_t uncompacted
= /* 46b/BDW; 49b/CHV */
857 (brw_inst_bits(src
, 83, 83) << 43) | /* 1b */
858 (brw_inst_bits(src
, 114, 107) << 35) | /* 8b */
859 (brw_inst_bits(src
, 93, 86) << 27) | /* 8b */
860 (brw_inst_bits(src
, 72, 65) << 19) | /* 8b */
861 (brw_inst_bits(src
, 55, 37)); /* 19b */
863 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
865 (brw_inst_bits(src
, 126, 125) << 47) | /* 2b */
866 (brw_inst_bits(src
, 105, 104) << 45) | /* 2b */
867 (brw_inst_bits(src
, 84, 84) << 44); /* 1b */
870 (brw_inst_bits(src
, 125, 125) << 45) | /* 1b */
871 (brw_inst_bits(src
, 104, 104) << 44); /* 1b */
874 for (unsigned i
= 0; i
< ARRAY_SIZE(gen8_3src_source_index_table
); i
++) {
875 if (gen8_3src_source_index_table
[i
] == uncompacted
) {
876 brw_compact_inst_set_3src_source_index(devinfo
, dst
, i
);
885 has_unmapped_bits(const struct gen_device_info
*devinfo
, const brw_inst
*src
)
887 /* EOT can only be mapped on a send if the src1 is an immediate */
888 if ((brw_inst_opcode(devinfo
, src
) == BRW_OPCODE_SENDC
||
889 brw_inst_opcode(devinfo
, src
) == BRW_OPCODE_SEND
) &&
890 brw_inst_eot(devinfo
, src
))
893 /* Check for instruction bits that don't map to any of the fields of the
894 * compacted instruction. The instruction cannot be compacted if any of
895 * them are set. They overlap with:
896 * - NibCtrl (bit 47 on Gen7, bit 11 on Gen8)
897 * - Dst.AddrImm[9] (bit 47 on Gen8)
898 * - Src0.AddrImm[9] (bit 95 on Gen8)
899 * - Imm64[27:31] (bits 91-95 on Gen7, bit 95 on Gen8)
900 * - UIP[31] (bit 95 on Gen8)
902 if (devinfo
->gen
>= 8) {
903 assert(!brw_inst_bits(src
, 7, 7));
904 return brw_inst_bits(src
, 95, 95) ||
905 brw_inst_bits(src
, 47, 47) ||
906 brw_inst_bits(src
, 11, 11);
908 assert(!brw_inst_bits(src
, 7, 7) &&
909 !(devinfo
->gen
< 7 && brw_inst_bits(src
, 90, 90)));
910 return brw_inst_bits(src
, 95, 91) ||
911 brw_inst_bits(src
, 47, 47);
916 has_3src_unmapped_bits(const struct gen_device_info
*devinfo
,
919 /* Check for three-source instruction bits that don't map to any of the
920 * fields of the compacted instruction. All of them seem to be reserved
923 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
924 assert(!brw_inst_bits(src
, 127, 127) &&
925 !brw_inst_bits(src
, 7, 7));
927 assert(devinfo
->gen
>= 8);
928 assert(!brw_inst_bits(src
, 127, 126) &&
929 !brw_inst_bits(src
, 105, 105) &&
930 !brw_inst_bits(src
, 84, 84) &&
931 !brw_inst_bits(src
, 7, 7));
933 /* Src1Type and Src2Type, used for mixed-precision floating point */
934 if (brw_inst_bits(src
, 36, 35))
942 brw_try_compact_3src_instruction(const struct gen_device_info
*devinfo
,
943 brw_compact_inst
*dst
, const brw_inst
*src
)
945 assert(devinfo
->gen
>= 8);
947 if (has_3src_unmapped_bits(devinfo
, src
))
950 #define compact(field) \
951 brw_compact_inst_set_3src_##field(devinfo, dst, brw_inst_3src_##field(devinfo, src))
952 #define compact_a16(field) \
953 brw_compact_inst_set_3src_##field(devinfo, dst, brw_inst_3src_a16_##field(devinfo, src))
957 if (!set_3src_control_index(devinfo
, dst
, src
))
960 if (!set_3src_source_index(devinfo
, dst
, src
))
964 compact_a16(src0_rep_ctrl
);
965 brw_compact_inst_set_3src_cmpt_control(devinfo
, dst
, true);
966 compact(debug_control
);
968 compact_a16(src1_rep_ctrl
);
969 compact_a16(src2_rep_ctrl
);
970 compact(src0_reg_nr
);
971 compact(src1_reg_nr
);
972 compact(src2_reg_nr
);
973 compact_a16(src0_subreg_nr
);
974 compact_a16(src1_subreg_nr
);
975 compact_a16(src2_subreg_nr
);
983 /* Compacted instructions have 12-bits for immediate sources, and a 13th bit
984 * that's replicated through the high 20 bits.
986 * Effectively this means we get 12-bit integers, 0.0f, and some limited uses
987 * of packed vectors as compactable immediates.
990 is_compactable_immediate(unsigned imm
)
992 /* We get the low 12 bits as-is. */
995 /* We get one bit replicated through the top 20 bits. */
996 return imm
== 0 || imm
== 0xfffff000;
1000 * Applies some small changes to instruction types to increase chances of
1004 precompact(const struct gen_device_info
*devinfo
, brw_inst inst
)
1006 if (brw_inst_src0_reg_file(devinfo
, &inst
) != BRW_IMMEDIATE_VALUE
)
1009 /* The Bspec's section titled "Non-present Operands" claims that if src0
1010 * is an immediate that src1's type must be the same as that of src0.
1012 * The SNB+ DataTypeIndex instruction compaction tables contain mappings
1013 * that do not follow this rule. E.g., from the IVB/HSW table:
1015 * DataTypeIndex 18-Bit Mapping Mapped Meaning
1016 * 3 001000001011111101 r:f | i:vf | a:ud | <1> | dir |
1018 * And from the SNB table:
1020 * DataTypeIndex 18-Bit Mapping Mapped Meaning
1021 * 8 001000000111101100 a:w | i:w | a:ud | <1> | dir |
1023 * Neither of these cause warnings from the simulator when used,
1024 * compacted or otherwise. In fact, all compaction mappings that have an
1025 * immediate in src0 use a:ud for src1.
1027 * The GM45 instruction compaction tables do not contain mapped meanings
1028 * so it's not clear whether it has the restriction. We'll assume it was
1029 * lifted on SNB. (FINISHME: decode the GM45 tables and check.)
1031 * Don't do any of this for 64-bit immediates, since the src1 fields
1032 * overlap with the immediate and setting them would overwrite the
1035 if (devinfo
->gen
>= 6 &&
1036 !(devinfo
->is_haswell
&&
1037 brw_inst_opcode(devinfo
, &inst
) == BRW_OPCODE_DIM
) &&
1038 !(devinfo
->gen
>= 8 &&
1039 (brw_inst_src0_type(devinfo
, &inst
) == BRW_REGISTER_TYPE_DF
||
1040 brw_inst_src0_type(devinfo
, &inst
) == BRW_REGISTER_TYPE_UQ
||
1041 brw_inst_src0_type(devinfo
, &inst
) == BRW_REGISTER_TYPE_Q
))) {
1042 enum brw_reg_file file
= brw_inst_src1_reg_file(devinfo
, &inst
);
1043 brw_inst_set_src1_file_type(devinfo
, &inst
, file
, BRW_REGISTER_TYPE_UD
);
1046 /* Compacted instructions only have 12-bits (plus 1 for the other 20)
1047 * for immediate values. Presumably the hardware engineers realized
1048 * that the only useful floating-point value that could be represented
1049 * in this format is 0.0, which can also be represented as a VF-typed
1050 * immediate, so they gave us the previously mentioned mapping on IVB+.
1052 * Strangely, we do have a mapping for imm:f in src1, so we don't need
1055 * If we see a 0.0:F, change the type to VF so that it can be compacted.
1057 if (brw_inst_imm_ud(devinfo
, &inst
) == 0x0 &&
1058 brw_inst_src0_type(devinfo
, &inst
) == BRW_REGISTER_TYPE_F
&&
1059 brw_inst_dst_type(devinfo
, &inst
) == BRW_REGISTER_TYPE_F
&&
1060 brw_inst_dst_hstride(devinfo
, &inst
) == BRW_HORIZONTAL_STRIDE_1
) {
1061 enum brw_reg_file file
= brw_inst_src0_reg_file(devinfo
, &inst
);
1062 brw_inst_set_src0_file_type(devinfo
, &inst
, file
, BRW_REGISTER_TYPE_VF
);
1065 /* There are no mappings for dst:d | i:d, so if the immediate is suitable
1066 * set the types to :UD so the instruction can be compacted.
1068 if (is_compactable_immediate(brw_inst_imm_ud(devinfo
, &inst
)) &&
1069 brw_inst_cond_modifier(devinfo
, &inst
) == BRW_CONDITIONAL_NONE
&&
1070 brw_inst_src0_type(devinfo
, &inst
) == BRW_REGISTER_TYPE_D
&&
1071 brw_inst_dst_type(devinfo
, &inst
) == BRW_REGISTER_TYPE_D
) {
1072 enum brw_reg_file src_file
= brw_inst_src0_reg_file(devinfo
, &inst
);
1073 enum brw_reg_file dst_file
= brw_inst_dst_reg_file(devinfo
, &inst
);
1075 brw_inst_set_src0_file_type(devinfo
, &inst
, src_file
, BRW_REGISTER_TYPE_UD
);
1076 brw_inst_set_dst_file_type(devinfo
, &inst
, dst_file
, BRW_REGISTER_TYPE_UD
);
1083 * Tries to compact instruction src into dst.
1085 * It doesn't modify dst unless src is compactable, which is relied on by
1086 * brw_compact_instructions().
1089 brw_try_compact_instruction(const struct gen_device_info
*devinfo
,
1090 brw_compact_inst
*dst
, const brw_inst
*src
)
1092 brw_compact_inst temp
;
1094 assert(brw_inst_cmpt_control(devinfo
, src
) == 0);
1096 if (is_3src(devinfo
, brw_inst_opcode(devinfo
, src
))) {
1097 if (devinfo
->gen
>= 8) {
1098 memset(&temp
, 0, sizeof(temp
));
1099 if (brw_try_compact_3src_instruction(devinfo
, &temp
, src
)) {
1111 brw_inst_src0_reg_file(devinfo
, src
) == BRW_IMMEDIATE_VALUE
||
1112 brw_inst_src1_reg_file(devinfo
, src
) == BRW_IMMEDIATE_VALUE
;
1114 (devinfo
->gen
< 6 ||
1115 !is_compactable_immediate(brw_inst_imm_ud(devinfo
, src
)))) {
1119 if (has_unmapped_bits(devinfo
, src
))
1122 memset(&temp
, 0, sizeof(temp
));
1124 #define compact(field) \
1125 brw_compact_inst_set_##field(devinfo, &temp, brw_inst_##field(devinfo, src))
1128 compact(debug_control
);
1130 if (!set_control_index(devinfo
, &temp
, src
))
1132 if (!set_datatype_index(devinfo
, &temp
, src
))
1134 if (!set_subreg_index(devinfo
, &temp
, src
, is_immediate
))
1137 if (devinfo
->gen
>= 6) {
1138 compact(acc_wr_control
);
1140 compact(mask_control_ex
);
1143 compact(cond_modifier
);
1145 if (devinfo
->gen
<= 6)
1146 compact(flag_subreg_nr
);
1148 brw_compact_inst_set_cmpt_control(devinfo
, &temp
, true);
1150 if (!set_src0_index(devinfo
, &temp
, src
))
1152 if (!set_src1_index(devinfo
, &temp
, src
, is_immediate
))
1155 brw_compact_inst_set_dst_reg_nr(devinfo
, &temp
,
1156 brw_inst_dst_da_reg_nr(devinfo
, src
));
1157 brw_compact_inst_set_src0_reg_nr(devinfo
, &temp
,
1158 brw_inst_src0_da_reg_nr(devinfo
, src
));
1161 brw_compact_inst_set_src1_reg_nr(devinfo
, &temp
,
1162 brw_inst_imm_ud(devinfo
, src
) & 0xff);
1164 brw_compact_inst_set_src1_reg_nr(devinfo
, &temp
,
1165 brw_inst_src1_da_reg_nr(devinfo
, src
));
1176 set_uncompacted_control(const struct gen_device_info
*devinfo
, brw_inst
*dst
,
1177 brw_compact_inst
*src
)
1179 uint32_t uncompacted
=
1180 control_index_table
[brw_compact_inst_control_index(devinfo
, src
)];
1182 if (devinfo
->gen
>= 8) {
1183 brw_inst_set_bits(dst
, 33, 31, (uncompacted
>> 16));
1184 brw_inst_set_bits(dst
, 23, 12, (uncompacted
>> 4) & 0xfff);
1185 brw_inst_set_bits(dst
, 10, 9, (uncompacted
>> 2) & 0x3);
1186 brw_inst_set_bits(dst
, 34, 34, (uncompacted
>> 1) & 0x1);
1187 brw_inst_set_bits(dst
, 8, 8, (uncompacted
>> 0) & 0x1);
1189 brw_inst_set_bits(dst
, 31, 31, (uncompacted
>> 16) & 0x1);
1190 brw_inst_set_bits(dst
, 23, 8, (uncompacted
& 0xffff));
1192 if (devinfo
->gen
== 7)
1193 brw_inst_set_bits(dst
, 90, 89, uncompacted
>> 17);
1198 set_uncompacted_datatype(const struct gen_device_info
*devinfo
, brw_inst
*dst
,
1199 brw_compact_inst
*src
)
1201 uint32_t uncompacted
=
1202 datatype_table
[brw_compact_inst_datatype_index(devinfo
, src
)];
1204 if (devinfo
->gen
>= 8) {
1205 brw_inst_set_bits(dst
, 63, 61, (uncompacted
>> 18));
1206 brw_inst_set_bits(dst
, 94, 89, (uncompacted
>> 12) & 0x3f);
1207 brw_inst_set_bits(dst
, 46, 35, (uncompacted
>> 0) & 0xfff);
1209 brw_inst_set_bits(dst
, 63, 61, (uncompacted
>> 15));
1210 brw_inst_set_bits(dst
, 46, 32, (uncompacted
& 0x7fff));
1215 set_uncompacted_subreg(const struct gen_device_info
*devinfo
, brw_inst
*dst
,
1216 brw_compact_inst
*src
)
1218 uint16_t uncompacted
=
1219 subreg_table
[brw_compact_inst_subreg_index(devinfo
, src
)];
1221 brw_inst_set_bits(dst
, 100, 96, (uncompacted
>> 10));
1222 brw_inst_set_bits(dst
, 68, 64, (uncompacted
>> 5) & 0x1f);
1223 brw_inst_set_bits(dst
, 52, 48, (uncompacted
>> 0) & 0x1f);
1227 set_uncompacted_src0(const struct gen_device_info
*devinfo
, brw_inst
*dst
,
1228 brw_compact_inst
*src
)
1230 uint32_t compacted
= brw_compact_inst_src0_index(devinfo
, src
);
1231 uint16_t uncompacted
= src_index_table
[compacted
];
1233 brw_inst_set_bits(dst
, 88, 77, uncompacted
);
1237 set_uncompacted_src1(const struct gen_device_info
*devinfo
, brw_inst
*dst
,
1238 brw_compact_inst
*src
, bool is_immediate
)
1241 signed high5
= brw_compact_inst_src1_index(devinfo
, src
);
1242 /* Replicate top bit of src1_index into high 20 bits of the immediate. */
1243 brw_inst_set_imm_ud(devinfo
, dst
, (high5
<< 27) >> 19);
1245 uint16_t uncompacted
=
1246 src_index_table
[brw_compact_inst_src1_index(devinfo
, src
)];
1248 brw_inst_set_bits(dst
, 120, 109, uncompacted
);
1253 set_uncompacted_3src_control_index(const struct gen_device_info
*devinfo
,
1254 brw_inst
*dst
, brw_compact_inst
*src
)
1256 assert(devinfo
->gen
>= 8);
1258 uint32_t compacted
= brw_compact_inst_3src_control_index(devinfo
, src
);
1259 uint32_t uncompacted
= gen8_3src_control_index_table
[compacted
];
1261 brw_inst_set_bits(dst
, 34, 32, (uncompacted
>> 21) & 0x7);
1262 brw_inst_set_bits(dst
, 28, 8, (uncompacted
>> 0) & 0x1fffff);
1264 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
)
1265 brw_inst_set_bits(dst
, 36, 35, (uncompacted
>> 24) & 0x3);
1269 set_uncompacted_3src_source_index(const struct gen_device_info
*devinfo
,
1270 brw_inst
*dst
, brw_compact_inst
*src
)
1272 assert(devinfo
->gen
>= 8);
1274 uint32_t compacted
= brw_compact_inst_3src_source_index(devinfo
, src
);
1275 uint64_t uncompacted
= gen8_3src_source_index_table
[compacted
];
1277 brw_inst_set_bits(dst
, 83, 83, (uncompacted
>> 43) & 0x1);
1278 brw_inst_set_bits(dst
, 114, 107, (uncompacted
>> 35) & 0xff);
1279 brw_inst_set_bits(dst
, 93, 86, (uncompacted
>> 27) & 0xff);
1280 brw_inst_set_bits(dst
, 72, 65, (uncompacted
>> 19) & 0xff);
1281 brw_inst_set_bits(dst
, 55, 37, (uncompacted
>> 0) & 0x7ffff);
1283 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
1284 brw_inst_set_bits(dst
, 126, 125, (uncompacted
>> 47) & 0x3);
1285 brw_inst_set_bits(dst
, 105, 104, (uncompacted
>> 45) & 0x3);
1286 brw_inst_set_bits(dst
, 84, 84, (uncompacted
>> 44) & 0x1);
1288 brw_inst_set_bits(dst
, 125, 125, (uncompacted
>> 45) & 0x1);
1289 brw_inst_set_bits(dst
, 104, 104, (uncompacted
>> 44) & 0x1);
1294 brw_uncompact_3src_instruction(const struct gen_device_info
*devinfo
,
1295 brw_inst
*dst
, brw_compact_inst
*src
)
1297 assert(devinfo
->gen
>= 8);
1299 #define uncompact(field) \
1300 brw_inst_set_3src_##field(devinfo, dst, brw_compact_inst_3src_##field(devinfo, src))
1301 #define uncompact_a16(field) \
1302 brw_inst_set_3src_a16_##field(devinfo, dst, brw_compact_inst_3src_##field(devinfo, src))
1306 set_uncompacted_3src_control_index(devinfo
, dst
, src
);
1307 set_uncompacted_3src_source_index(devinfo
, dst
, src
);
1309 uncompact(dst_reg_nr
);
1310 uncompact_a16(src0_rep_ctrl
);
1311 brw_inst_set_3src_cmpt_control(devinfo
, dst
, false);
1312 uncompact(debug_control
);
1313 uncompact(saturate
);
1314 uncompact_a16(src1_rep_ctrl
);
1315 uncompact_a16(src2_rep_ctrl
);
1316 uncompact(src0_reg_nr
);
1317 uncompact(src1_reg_nr
);
1318 uncompact(src2_reg_nr
);
1319 uncompact_a16(src0_subreg_nr
);
1320 uncompact_a16(src1_subreg_nr
);
1321 uncompact_a16(src2_subreg_nr
);
1324 #undef uncompact_a16
1328 brw_uncompact_instruction(const struct gen_device_info
*devinfo
, brw_inst
*dst
,
1329 brw_compact_inst
*src
)
1331 memset(dst
, 0, sizeof(*dst
));
1333 if (devinfo
->gen
>= 8 &&
1334 is_3src(devinfo
, brw_compact_inst_3src_opcode(devinfo
, src
))) {
1335 brw_uncompact_3src_instruction(devinfo
, dst
, src
);
1339 #define uncompact(field) \
1340 brw_inst_set_##field(devinfo, dst, brw_compact_inst_##field(devinfo, src))
1343 uncompact(debug_control
);
1345 set_uncompacted_control(devinfo
, dst
, src
);
1346 set_uncompacted_datatype(devinfo
, dst
, src
);
1348 /* src0/1 register file fields are in the datatype table. */
1349 bool is_immediate
= brw_inst_src0_reg_file(devinfo
, dst
) == BRW_IMMEDIATE_VALUE
||
1350 brw_inst_src1_reg_file(devinfo
, dst
) == BRW_IMMEDIATE_VALUE
;
1352 set_uncompacted_subreg(devinfo
, dst
, src
);
1354 if (devinfo
->gen
>= 6) {
1355 uncompact(acc_wr_control
);
1357 uncompact(mask_control_ex
);
1360 uncompact(cond_modifier
);
1362 if (devinfo
->gen
<= 6)
1363 uncompact(flag_subreg_nr
);
1365 set_uncompacted_src0(devinfo
, dst
, src
);
1366 set_uncompacted_src1(devinfo
, dst
, src
, is_immediate
);
1368 brw_inst_set_dst_da_reg_nr(devinfo
, dst
,
1369 brw_compact_inst_dst_reg_nr(devinfo
, src
));
1370 brw_inst_set_src0_da_reg_nr(devinfo
, dst
,
1371 brw_compact_inst_src0_reg_nr(devinfo
, src
));
1374 brw_inst_set_imm_ud(devinfo
, dst
,
1375 brw_inst_imm_ud(devinfo
, dst
) |
1376 brw_compact_inst_src1_reg_nr(devinfo
, src
));
1378 brw_inst_set_src1_da_reg_nr(devinfo
, dst
,
1379 brw_compact_inst_src1_reg_nr(devinfo
, src
));
1385 void brw_debug_compact_uncompact(const struct gen_device_info
*devinfo
,
1387 brw_inst
*uncompacted
)
1389 fprintf(stderr
, "Instruction compact/uncompact changed (gen%d):\n",
1392 fprintf(stderr
, " before: ");
1393 brw_disassemble_inst(stderr
, devinfo
, orig
, true);
1395 fprintf(stderr
, " after: ");
1396 brw_disassemble_inst(stderr
, devinfo
, uncompacted
, false);
1398 uint32_t *before_bits
= (uint32_t *)orig
;
1399 uint32_t *after_bits
= (uint32_t *)uncompacted
;
1400 fprintf(stderr
, " changed bits:\n");
1401 for (int i
= 0; i
< 128; i
++) {
1402 uint32_t before
= before_bits
[i
/ 32] & (1 << (i
& 31));
1403 uint32_t after
= after_bits
[i
/ 32] & (1 << (i
& 31));
1405 if (before
!= after
) {
1406 fprintf(stderr
, " bit %d, %s to %s\n", i
,
1407 before
? "set" : "unset",
1408 after
? "set" : "unset");
1414 compacted_between(int old_ip
, int old_target_ip
, int *compacted_counts
)
1416 int this_compacted_count
= compacted_counts
[old_ip
];
1417 int target_compacted_count
= compacted_counts
[old_target_ip
];
1418 return target_compacted_count
- this_compacted_count
;
1422 update_uip_jip(const struct gen_device_info
*devinfo
, brw_inst
*insn
,
1423 int this_old_ip
, int *compacted_counts
)
1425 /* JIP and UIP are in units of:
1426 * - bytes on Gen8+; and
1427 * - compacted instructions on Gen6+.
1429 int shift
= devinfo
->gen
>= 8 ? 3 : 0;
1431 int32_t jip_compacted
= brw_inst_jip(devinfo
, insn
) >> shift
;
1432 jip_compacted
-= compacted_between(this_old_ip
,
1433 this_old_ip
+ (jip_compacted
/ 2),
1435 brw_inst_set_jip(devinfo
, insn
, jip_compacted
<< shift
);
1437 if (brw_inst_opcode(devinfo
, insn
) == BRW_OPCODE_ENDIF
||
1438 brw_inst_opcode(devinfo
, insn
) == BRW_OPCODE_WHILE
||
1439 (brw_inst_opcode(devinfo
, insn
) == BRW_OPCODE_ELSE
&& devinfo
->gen
<= 7))
1442 int32_t uip_compacted
= brw_inst_uip(devinfo
, insn
) >> shift
;
1443 uip_compacted
-= compacted_between(this_old_ip
,
1444 this_old_ip
+ (uip_compacted
/ 2),
1446 brw_inst_set_uip(devinfo
, insn
, uip_compacted
<< shift
);
1450 update_gen4_jump_count(const struct gen_device_info
*devinfo
, brw_inst
*insn
,
1451 int this_old_ip
, int *compacted_counts
)
1453 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
);
1455 /* Jump Count is in units of:
1456 * - uncompacted instructions on G45; and
1457 * - compacted instructions on Gen5.
1459 int shift
= devinfo
->is_g4x
? 1 : 0;
1461 int jump_count_compacted
= brw_inst_gen4_jump_count(devinfo
, insn
) << shift
;
1463 int target_old_ip
= this_old_ip
+ (jump_count_compacted
/ 2);
1465 int this_compacted_count
= compacted_counts
[this_old_ip
];
1466 int target_compacted_count
= compacted_counts
[target_old_ip
];
1468 jump_count_compacted
-= (target_compacted_count
- this_compacted_count
);
1469 brw_inst_set_gen4_jump_count(devinfo
, insn
, jump_count_compacted
>> shift
);
1473 brw_init_compaction_tables(const struct gen_device_info
*devinfo
)
1475 assert(g45_control_index_table
[ARRAY_SIZE(g45_control_index_table
) - 1] != 0);
1476 assert(g45_datatype_table
[ARRAY_SIZE(g45_datatype_table
) - 1] != 0);
1477 assert(g45_subreg_table
[ARRAY_SIZE(g45_subreg_table
) - 1] != 0);
1478 assert(g45_src_index_table
[ARRAY_SIZE(g45_src_index_table
) - 1] != 0);
1479 assert(gen6_control_index_table
[ARRAY_SIZE(gen6_control_index_table
) - 1] != 0);
1480 assert(gen6_datatype_table
[ARRAY_SIZE(gen6_datatype_table
) - 1] != 0);
1481 assert(gen6_subreg_table
[ARRAY_SIZE(gen6_subreg_table
) - 1] != 0);
1482 assert(gen6_src_index_table
[ARRAY_SIZE(gen6_src_index_table
) - 1] != 0);
1483 assert(gen7_control_index_table
[ARRAY_SIZE(gen7_control_index_table
) - 1] != 0);
1484 assert(gen7_datatype_table
[ARRAY_SIZE(gen7_datatype_table
) - 1] != 0);
1485 assert(gen7_subreg_table
[ARRAY_SIZE(gen7_subreg_table
) - 1] != 0);
1486 assert(gen7_src_index_table
[ARRAY_SIZE(gen7_src_index_table
) - 1] != 0);
1487 assert(gen8_control_index_table
[ARRAY_SIZE(gen8_control_index_table
) - 1] != 0);
1488 assert(gen8_datatype_table
[ARRAY_SIZE(gen8_datatype_table
) - 1] != 0);
1489 assert(gen8_subreg_table
[ARRAY_SIZE(gen8_subreg_table
) - 1] != 0);
1490 assert(gen8_src_index_table
[ARRAY_SIZE(gen8_src_index_table
) - 1] != 0);
1491 assert(gen11_datatype_table
[ARRAY_SIZE(gen11_datatype_table
) - 1] != 0);
1493 switch (devinfo
->gen
) {
1495 control_index_table
= NULL
;
1496 datatype_table
= NULL
;
1497 subreg_table
= NULL
;
1498 src_index_table
= NULL
;
1501 control_index_table
= gen8_control_index_table
;
1502 datatype_table
= gen11_datatype_table
;
1503 subreg_table
= gen8_subreg_table
;
1504 src_index_table
= gen8_src_index_table
;
1509 control_index_table
= gen8_control_index_table
;
1510 datatype_table
= gen8_datatype_table
;
1511 subreg_table
= gen8_subreg_table
;
1512 src_index_table
= gen8_src_index_table
;
1515 control_index_table
= gen7_control_index_table
;
1516 datatype_table
= gen7_datatype_table
;
1517 subreg_table
= gen7_subreg_table
;
1518 src_index_table
= gen7_src_index_table
;
1521 control_index_table
= gen6_control_index_table
;
1522 datatype_table
= gen6_datatype_table
;
1523 subreg_table
= gen6_subreg_table
;
1524 src_index_table
= gen6_src_index_table
;
1528 control_index_table
= g45_control_index_table
;
1529 datatype_table
= g45_datatype_table
;
1530 subreg_table
= g45_subreg_table
;
1531 src_index_table
= g45_src_index_table
;
1534 unreachable("unknown generation");
1539 brw_compact_instructions(struct brw_codegen
*p
, int start_offset
,
1540 struct disasm_info
*disasm
)
1542 if (unlikely(INTEL_DEBUG
& DEBUG_NO_COMPACTION
) || p
->devinfo
->gen
> 11)
1545 const struct gen_device_info
*devinfo
= p
->devinfo
;
1546 void *store
= p
->store
+ start_offset
/ 16;
1547 /* For an instruction at byte offset 16*i before compaction, this is the
1548 * number of compacted instructions minus the number of padding NOP/NENOPs
1551 int compacted_counts
[(p
->next_insn_offset
- start_offset
) / sizeof(brw_inst
)];
1552 /* For an instruction at byte offset 8*i after compaction, this was its IP
1553 * (in 16-byte units) before compaction.
1555 int old_ip
[(p
->next_insn_offset
- start_offset
) / sizeof(brw_compact_inst
) + 1];
1557 if (devinfo
->gen
== 4 && !devinfo
->is_g4x
)
1561 int compacted_count
= 0;
1562 for (int src_offset
= 0; src_offset
< p
->next_insn_offset
- start_offset
;
1563 src_offset
+= sizeof(brw_inst
)) {
1564 brw_inst
*src
= store
+ src_offset
;
1565 void *dst
= store
+ offset
;
1567 old_ip
[offset
/ sizeof(brw_compact_inst
)] = src_offset
/ sizeof(brw_inst
);
1568 compacted_counts
[src_offset
/ sizeof(brw_inst
)] = compacted_count
;
1570 brw_inst inst
= precompact(devinfo
, *src
);
1571 brw_inst saved
= inst
;
1573 if (brw_try_compact_instruction(devinfo
, dst
, &inst
)) {
1577 brw_inst uncompacted
;
1578 brw_uncompact_instruction(devinfo
, &uncompacted
, dst
);
1579 if (memcmp(&saved
, &uncompacted
, sizeof(uncompacted
))) {
1580 brw_debug_compact_uncompact(devinfo
, &saved
, &uncompacted
);
1584 offset
+= sizeof(brw_compact_inst
);
1586 /* All uncompacted instructions need to be aligned on G45. */
1587 if ((offset
& sizeof(brw_compact_inst
)) != 0 && devinfo
->is_g4x
){
1588 brw_compact_inst
*align
= store
+ offset
;
1589 memset(align
, 0, sizeof(*align
));
1590 brw_compact_inst_set_opcode(devinfo
, align
, BRW_OPCODE_NENOP
);
1591 brw_compact_inst_set_cmpt_control(devinfo
, align
, true);
1592 offset
+= sizeof(brw_compact_inst
);
1594 compacted_counts
[src_offset
/ sizeof(brw_inst
)] = compacted_count
;
1595 old_ip
[offset
/ sizeof(brw_compact_inst
)] = src_offset
/ sizeof(brw_inst
);
1597 dst
= store
+ offset
;
1600 /* If we didn't compact this intruction, we need to move it down into
1603 if (offset
!= src_offset
) {
1604 memmove(dst
, src
, sizeof(brw_inst
));
1606 offset
+= sizeof(brw_inst
);
1610 /* Add an entry for the ending offset of the program. This greatly
1611 * simplifies the linked list walk at the end of the function.
1613 old_ip
[offset
/ sizeof(brw_compact_inst
)] =
1614 (p
->next_insn_offset
- start_offset
) / sizeof(brw_inst
);
1616 /* Fix up control flow offsets. */
1617 p
->next_insn_offset
= start_offset
+ offset
;
1618 for (offset
= 0; offset
< p
->next_insn_offset
- start_offset
;
1619 offset
= next_offset(devinfo
, store
, offset
)) {
1620 brw_inst
*insn
= store
+ offset
;
1621 int this_old_ip
= old_ip
[offset
/ sizeof(brw_compact_inst
)];
1622 int this_compacted_count
= compacted_counts
[this_old_ip
];
1624 switch (brw_inst_opcode(devinfo
, insn
)) {
1625 case BRW_OPCODE_BREAK
:
1626 case BRW_OPCODE_CONTINUE
:
1627 case BRW_OPCODE_HALT
:
1628 if (devinfo
->gen
>= 6) {
1629 update_uip_jip(devinfo
, insn
, this_old_ip
, compacted_counts
);
1631 update_gen4_jump_count(devinfo
, insn
, this_old_ip
,
1637 case BRW_OPCODE_IFF
:
1638 case BRW_OPCODE_ELSE
:
1639 case BRW_OPCODE_ENDIF
:
1640 case BRW_OPCODE_WHILE
:
1641 if (devinfo
->gen
>= 7) {
1642 if (brw_inst_cmpt_control(devinfo
, insn
)) {
1643 brw_inst uncompacted
;
1644 brw_uncompact_instruction(devinfo
, &uncompacted
,
1645 (brw_compact_inst
*)insn
);
1647 update_uip_jip(devinfo
, &uncompacted
, this_old_ip
,
1650 bool ret
= brw_try_compact_instruction(devinfo
,
1651 (brw_compact_inst
*)insn
,
1653 assert(ret
); (void)ret
;
1655 update_uip_jip(devinfo
, insn
, this_old_ip
, compacted_counts
);
1657 } else if (devinfo
->gen
== 6) {
1658 assert(!brw_inst_cmpt_control(devinfo
, insn
));
1660 /* Jump Count is in units of compacted instructions on Gen6. */
1661 int jump_count_compacted
= brw_inst_gen6_jump_count(devinfo
, insn
);
1663 int target_old_ip
= this_old_ip
+ (jump_count_compacted
/ 2);
1664 int target_compacted_count
= compacted_counts
[target_old_ip
];
1665 jump_count_compacted
-= (target_compacted_count
- this_compacted_count
);
1666 brw_inst_set_gen6_jump_count(devinfo
, insn
, jump_count_compacted
);
1668 update_gen4_jump_count(devinfo
, insn
, this_old_ip
,
1673 case BRW_OPCODE_ADD
:
1674 /* Add instructions modifying the IP register use an immediate src1,
1675 * and Gens that use this cannot compact instructions with immediate
1678 if (brw_inst_cmpt_control(devinfo
, insn
))
1681 if (brw_inst_dst_reg_file(devinfo
, insn
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
1682 brw_inst_dst_da_reg_nr(devinfo
, insn
) == BRW_ARF_IP
) {
1683 assert(brw_inst_src1_reg_file(devinfo
, insn
) == BRW_IMMEDIATE_VALUE
);
1686 int jump_compacted
= brw_inst_imm_d(devinfo
, insn
) >> shift
;
1688 int target_old_ip
= this_old_ip
+ (jump_compacted
/ 2);
1689 int target_compacted_count
= compacted_counts
[target_old_ip
];
1690 jump_compacted
-= (target_compacted_count
- this_compacted_count
);
1691 brw_inst_set_imm_ud(devinfo
, insn
, jump_compacted
<< shift
);
1697 /* p->nr_insn is counting the number of uncompacted instructions still, so
1698 * divide. We do want to be sure there's a valid instruction in any
1699 * alignment padding, so that the next compression pass (for the FS 8/16
1700 * compile passes) parses correctly.
1702 if (p
->next_insn_offset
& sizeof(brw_compact_inst
)) {
1703 brw_compact_inst
*align
= store
+ offset
;
1704 memset(align
, 0, sizeof(*align
));
1705 brw_compact_inst_set_opcode(devinfo
, align
, BRW_OPCODE_NOP
);
1706 brw_compact_inst_set_cmpt_control(devinfo
, align
, true);
1707 p
->next_insn_offset
+= sizeof(brw_compact_inst
);
1709 p
->nr_insn
= p
->next_insn_offset
/ sizeof(brw_inst
);
1711 /* Update the instruction offsets for each group. */
1715 foreach_list_typed(struct inst_group
, group
, link
, &disasm
->group_list
) {
1716 while (start_offset
+ old_ip
[offset
/ sizeof(brw_compact_inst
)] *
1717 sizeof(brw_inst
) != group
->offset
) {
1718 assert(start_offset
+ old_ip
[offset
/ sizeof(brw_compact_inst
)] *
1719 sizeof(brw_inst
) < group
->offset
);
1720 offset
= next_offset(devinfo
, store
, offset
);
1723 group
->offset
= start_offset
+ offset
;
1725 offset
= next_offset(devinfo
, store
, offset
);