projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
intel/compiler: Add a INVALID_{,HW_}REG_TYPE macros
[mesa.git] / src / intel / compiler / brw_eu_compact.c
1 /*
2 * Copyright © 2012-2018 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_eu_compact.c
25 *
26 * Instruction compaction is a feature of G45 and newer hardware that allows
27 * for a smaller instruction encoding.
28 *
29 * The instruction cache is on the order of 32KB, and many programs generate
30 * far more instructions than that. The instruction cache is built to barely
31 * keep up with instruction dispatch ability in cache hit cases -- L1
32 * instruction cache misses that still hit in the next level could limit
33 * throughput by around 50%.
34 *
35 * The idea of instruction compaction is that most instructions use a tiny
36 * subset of the GPU functionality, so we can encode what would be a 16 byte
37 * instruction in 8 bytes using some lookup tables for various fields.
38 *
39 *
40 * Instruction compaction capabilities vary subtly by generation.
41 *
42 * G45's support for instruction compaction is very limited. Jump counts on
43 * this generation are in units of 16-byte uncompacted instructions. As such,
44 * all jump targets must be 16-byte aligned. Also, all instructions must be
45 * naturally aligned, i.e. uncompacted instructions must be 16-byte aligned.
46 * A G45-only instruction, NENOP, must be used to provide padding to align
47 * uncompacted instructions.
48 *
49 * Gen5 removes these restrictions and changes jump counts to be in units of
50 * 8-byte compacted instructions, allowing jump targets to be only 8-byte
51 * aligned. Uncompacted instructions can also be placed on 8-byte boundaries.
52 *
53 * Gen6 adds the ability to compact instructions with a limited range of
54 * immediate values. Compactable immediates have 12 unrestricted bits, and a
55 * 13th bit that's replicated through the high 20 bits, to create the 32-bit
56 * value of DW3 in the uncompacted instruction word.
57 *
58 * On Gen7 we can compact some control flow instructions with a small positive
59 * immediate in the low bits of DW3, like ENDIF with the JIP field. Other
60 * control flow instructions with UIP cannot be compacted, because of the
61 * replicated 13th bit. No control flow instructions can be compacted on Gen6
62 * since the jump count field is not in DW3.
63 *
64 * break JIP/UIP
65 * cont JIP/UIP
66 * halt JIP/UIP
67 * if JIP/UIP
68 * else JIP (plus UIP on BDW+)
69 * endif JIP
70 * while JIP (must be negative)
71 *
72 * Gen 8 adds support for compacting 3-src instructions.
73 *
74 * Gen12 reduces the number of bits that available to compacted immediates from
75 * 13 to 12, but improves the compaction of floating-point immediates by
76 * allowing the high bits to be encoded (the sign, 8-bit exponent, and the
77 * three most significant bits of the mantissa), rather than the lowest bits of
78 * the mantissa.
79 */
80
81 #include "brw_eu.h"
82 #include "brw_shader.h"
83 #include "brw_disasm_info.h"
84 #include "dev/gen_debug.h"
85
86 static const uint32_t g45_control_index_table[32] = {
87 0b00000000000000000,
88 0b01000000000000000,
89 0b00110000000000000,
90 0b00000000000000010,
91 0b00100000000000000,
92 0b00010000000000000,
93 0b01000000000100000,
94 0b01000000100000000,
95 0b01010000000100000,
96 0b00000000100000010,
97 0b11000000000000000,
98 0b00001000100000010,
99 0b01001000100000000,
100 0b00000000100000000,
101 0b11000000000100000,
102 0b00001000100000000,
103 0b10110000000000000,
104 0b11010000000100000,
105 0b00110000100000000,
106 0b00100000100000000,
107 0b01000000000001000,
108 0b01000000000000100,
109 0b00111100000000000,
110 0b00101011000000000,
111 0b00110000000010000,
112 0b00010000100000000,
113 0b01000000000100100,
114 0b01000000000101000,
115 0b00110000000000110,
116 0b00000000000001010,
117 0b01010000000101000,
118 0b01010000000100100,
119 };
120
121 static const uint32_t g45_datatype_table[32] = {
122 0b001000000000100001,
123 0b001011010110101101,
124 0b001000001000110001,
125 0b001111011110111101,
126 0b001011010110101100,
127 0b001000000110101101,
128 0b001000000000100000,
129 0b010100010110110001,
130 0b001100011000101101,
131 0b001000000000100010,
132 0b001000001000110110,
133 0b010000001000110001,
134 0b001000001000110010,
135 0b011000001000110010,
136 0b001111011110111100,
137 0b001000000100101000,
138 0b010100011000110001,
139 0b001010010100101001,
140 0b001000001000101001,
141 0b010000001000110110,
142 0b101000001000110001,
143 0b001011011000101101,
144 0b001000000100001001,
145 0b001011011000101100,
146 0b110100011000110001,
147 0b001000001110111101,
148 0b110000001000110001,
149 0b011000000100101010,
150 0b101000001000101001,
151 0b001011010110001100,
152 0b001000000110100001,
153 0b001010010100001000,
154 };
155
156 static const uint16_t g45_subreg_table[32] = {
157 0b000000000000000,
158 0b000000010000000,
159 0b000001000000000,
160 0b000100000000000,
161 0b000000000100000,
162 0b100000000000000,
163 0b000000000010000,
164 0b001100000000000,
165 0b001010000000000,
166 0b000000100000000,
167 0b001000000000000,
168 0b000000000001000,
169 0b000000001000000,
170 0b000000000000001,
171 0b000010000000000,
172 0b000000010100000,
173 0b000000000000111,
174 0b000001000100000,
175 0b011000000000000,
176 0b000000110000000,
177 0b000000000000010,
178 0b000000000000100,
179 0b000000001100000,
180 0b000100000000010,
181 0b001110011000110,
182 0b001110100001000,
183 0b000110011000110,
184 0b000001000011000,
185 0b000110010000100,
186 0b001100000000110,
187 0b000000010000110,
188 0b000001000110000,
189 };
190
191 static const uint16_t g45_src_index_table[32] = {
192 0b000000000000,
193 0b010001101000,
194 0b010110001000,
195 0b011010010000,
196 0b001101001000,
197 0b010110001010,
198 0b010101110000,
199 0b011001111000,
200 0b001000101000,
201 0b000000101000,
202 0b010001010000,
203 0b111101101100,
204 0b010110001100,
205 0b010001101100,
206 0b011010010100,
207 0b010001001100,
208 0b001100101000,
209 0b000000000010,
210 0b111101001100,
211 0b011001101000,
212 0b010101001000,
213 0b000000000100,
214 0b000000101100,
215 0b010001101010,
216 0b000000111000,
217 0b010101011000,
218 0b000100100000,
219 0b010110000000,
220 0b010000000100,
221 0b010000111000,
222 0b000101100000,
223 0b111101110100,
224 };
225
226 static const uint32_t gen6_control_index_table[32] = {
227 0b00000000000000000,
228 0b01000000000000000,
229 0b00110000000000000,
230 0b00000000100000000,
231 0b00010000000000000,
232 0b00001000100000000,
233 0b00000000100000010,
234 0b00000000000000010,
235 0b01000000100000000,
236 0b01010000000000000,
237 0b10110000000000000,
238 0b00100000000000000,
239 0b11010000000000000,
240 0b11000000000000000,
241 0b01001000100000000,
242 0b01000000000001000,
243 0b01000000000000100,
244 0b00000000000001000,
245 0b00000000000000100,
246 0b00111000100000000,
247 0b00001000100000010,
248 0b00110000100000000,
249 0b00110000000000001,
250 0b00100000000000001,
251 0b00110000000000010,
252 0b00110000000000101,
253 0b00110000000001001,
254 0b00110000000010000,
255 0b00110000000000011,
256 0b00110000000000100,
257 0b00110000100001000,
258 0b00100000000001001,
259 };
260
261 static const uint32_t gen6_datatype_table[32] = {
262 0b001001110000000000,
263 0b001000110000100000,
264 0b001001110000000001,
265 0b001000000001100000,
266 0b001010110100101001,
267 0b001000000110101101,
268 0b001100011000101100,
269 0b001011110110101101,
270 0b001000000111101100,
271 0b001000000001100001,
272 0b001000110010100101,
273 0b001000000001000001,
274 0b001000001000110001,
275 0b001000001000101001,
276 0b001000000000100000,
277 0b001000001000110010,
278 0b001010010100101001,
279 0b001011010010100101,
280 0b001000000110100101,
281 0b001100011000101001,
282 0b001011011000101100,
283 0b001011010110100101,
284 0b001011110110100101,
285 0b001111011110111101,
286 0b001111011110111100,
287 0b001111011110111101,
288 0b001111011110011101,
289 0b001111011110111110,
290 0b001000000000100001,
291 0b001000000000100010,
292 0b001001111111011101,
293 0b001000001110111110,
294 };
295
296 static const uint16_t gen6_subreg_table[32] = {
297 0b000000000000000,
298 0b000000000000100,
299 0b000000110000000,
300 0b111000000000000,
301 0b011110000001000,
302 0b000010000000000,
303 0b000000000010000,
304 0b000110000001100,
305 0b001000000000000,
306 0b000001000000000,
307 0b000001010010100,
308 0b000000001010110,
309 0b010000000000000,
310 0b110000000000000,
311 0b000100000000000,
312 0b000000010000000,
313 0b000000000001000,
314 0b100000000000000,
315 0b000001010000000,
316 0b001010000000000,
317 0b001100000000000,
318 0b000000001010100,
319 0b101101010010100,
320 0b010100000000000,
321 0b000000010001111,
322 0b011000000000000,
323 0b111110000000000,
324 0b101000000000000,
325 0b000000000001111,
326 0b000100010001111,
327 0b001000010001111,
328 0b000110000000000,
329 };
330
331 static const uint16_t gen6_src_index_table[32] = {
332 0b000000000000,
333 0b010110001000,
334 0b010001101000,
335 0b001000101000,
336 0b011010010000,
337 0b000100100000,
338 0b010001101100,
339 0b010101110000,
340 0b011001111000,
341 0b001100101000,
342 0b010110001100,
343 0b001000100000,
344 0b010110001010,
345 0b000000000010,
346 0b010101010000,
347 0b010101101000,
348 0b111101001100,
349 0b111100101100,
350 0b011001110000,
351 0b010110001001,
352 0b010101011000,
353 0b001101001000,
354 0b010000101100,
355 0b010000000000,
356 0b001101110000,
357 0b001100010000,
358 0b001100000000,
359 0b010001101010,
360 0b001101111000,
361 0b000001110000,
362 0b001100100000,
363 0b001101010000,
364 };
365
366 static const uint32_t gen7_control_index_table[32] = {
367 0b0000000000000000010,
368 0b0000100000000000000,
369 0b0000100000000000001,
370 0b0000100000000000010,
371 0b0000100000000000011,
372 0b0000100000000000100,
373 0b0000100000000000101,
374 0b0000100000000000111,
375 0b0000100000000001000,
376 0b0000100000000001001,
377 0b0000100000000001101,
378 0b0000110000000000000,
379 0b0000110000000000001,
380 0b0000110000000000010,
381 0b0000110000000000011,
382 0b0000110000000000100,
383 0b0000110000000000101,
384 0b0000110000000000111,
385 0b0000110000000001001,
386 0b0000110000000001101,
387 0b0000110000000010000,
388 0b0000110000100000000,
389 0b0001000000000000000,
390 0b0001000000000000010,
391 0b0001000000000000100,
392 0b0001000000100000000,
393 0b0010110000000000000,
394 0b0010110000000010000,
395 0b0011000000000000000,
396 0b0011000000100000000,
397 0b0101000000000000000,
398 0b0101000000100000000,
399 };
400
401 static const uint32_t gen7_datatype_table[32] = {
402 0b001000000000000001,
403 0b001000000000100000,
404 0b001000000000100001,
405 0b001000000001100001,
406 0b001000000010111101,
407 0b001000001011111101,
408 0b001000001110100001,
409 0b001000001110100101,
410 0b001000001110111101,
411 0b001000010000100001,
412 0b001000110000100000,
413 0b001000110000100001,
414 0b001001010010100101,
415 0b001001110010100100,
416 0b001001110010100101,
417 0b001111001110111101,
418 0b001111011110011101,
419 0b001111011110111100,
420 0b001111011110111101,
421 0b001111111110111100,
422 0b000000001000001100,
423 0b001000000000111101,
424 0b001000000010100101,
425 0b001000010000100000,
426 0b001001010010100100,
427 0b001001110010000100,
428 0b001010010100001001,
429 0b001101111110111101,
430 0b001111111110111101,
431 0b001011110110101100,
432 0b001010010100101000,
433 0b001010110100101000,
434 };
435
436 static const uint16_t gen7_subreg_table[32] = {
437 0b000000000000000,
438 0b000000000000001,
439 0b000000000001000,
440 0b000000000001111,
441 0b000000000010000,
442 0b000000010000000,
443 0b000000100000000,
444 0b000000110000000,
445 0b000001000000000,
446 0b000001000010000,
447 0b000010100000000,
448 0b001000000000000,
449 0b001000000000001,
450 0b001000010000001,
451 0b001000010000010,
452 0b001000010000011,
453 0b001000010000100,
454 0b001000010000111,
455 0b001000010001000,
456 0b001000010001110,
457 0b001000010001111,
458 0b001000110000000,
459 0b001000111101000,
460 0b010000000000000,
461 0b010000110000000,
462 0b011000000000000,
463 0b011110010000111,
464 0b100000000000000,
465 0b101000000000000,
466 0b110000000000000,
467 0b111000000000000,
468 0b111000000011100,
469 };
470
471 static const uint16_t gen7_src_index_table[32] = {
472 0b000000000000,
473 0b000000000010,
474 0b000000010000,
475 0b000000010010,
476 0b000000011000,
477 0b000000100000,
478 0b000000101000,
479 0b000001001000,
480 0b000001010000,
481 0b000001110000,
482 0b000001111000,
483 0b001100000000,
484 0b001100000010,
485 0b001100001000,
486 0b001100010000,
487 0b001100010010,
488 0b001100100000,
489 0b001100101000,
490 0b001100111000,
491 0b001101000000,
492 0b001101000010,
493 0b001101001000,
494 0b001101010000,
495 0b001101100000,
496 0b001101101000,
497 0b001101110000,
498 0b001101110001,
499 0b001101111000,
500 0b010001101000,
501 0b010001101001,
502 0b010001101010,
503 0b010110001000,
504 };
505
506 static const uint32_t gen8_control_index_table[32] = {
507 0b0000000000000000010,
508 0b0000100000000000000,
509 0b0000100000000000001,
510 0b0000100000000000010,
511 0b0000100000000000011,
512 0b0000100000000000100,
513 0b0000100000000000101,
514 0b0000100000000000111,
515 0b0000100000000001000,
516 0b0000100000000001001,
517 0b0000100000000001101,
518 0b0000110000000000000,
519 0b0000110000000000001,
520 0b0000110000000000010,
521 0b0000110000000000011,
522 0b0000110000000000100,
523 0b0000110000000000101,
524 0b0000110000000000111,
525 0b0000110000000001001,
526 0b0000110000000001101,
527 0b0000110000000010000,
528 0b0000110000100000000,
529 0b0001000000000000000,
530 0b0001000000000000010,
531 0b0001000000000000100,
532 0b0001000000100000000,
533 0b0010110000000000000,
534 0b0010110000000010000,
535 0b0011000000000000000,
536 0b0011000000100000000,
537 0b0101000000000000000,
538 0b0101000000100000000,
539 };
540
541 static const uint32_t gen8_datatype_table[32] = {
542 0b001000000000000000001,
543 0b001000000000001000000,
544 0b001000000000001000001,
545 0b001000000000011000001,
546 0b001000000000101011101,
547 0b001000000010111011101,
548 0b001000000011101000001,
549 0b001000000011101000101,
550 0b001000000011101011101,
551 0b001000001000001000001,
552 0b001000011000001000000,
553 0b001000011000001000001,
554 0b001000101000101000101,
555 0b001000111000101000100,
556 0b001000111000101000101,
557 0b001011100011101011101,
558 0b001011101011100011101,
559 0b001011101011101011100,
560 0b001011101011101011101,
561 0b001011111011101011100,
562 0b000000000010000001100,
563 0b001000000000001011101,
564 0b001000000000101000101,
565 0b001000001000001000000,
566 0b001000101000101000100,
567 0b001000111000100000100,
568 0b001001001001000001001,
569 0b001010111011101011101,
570 0b001011111011101011101,
571 0b001001111001101001100,
572 0b001001001001001001000,
573 0b001001011001001001000,
574 };
575
576 static const uint16_t gen8_subreg_table[32] = {
577 0b000000000000000,
578 0b000000000000001,
579 0b000000000001000,
580 0b000000000001111,
581 0b000000000010000,
582 0b000000010000000,
583 0b000000100000000,
584 0b000000110000000,
585 0b000001000000000,
586 0b000001000010000,
587 0b000001010000000,
588 0b001000000000000,
589 0b001000000000001,
590 0b001000010000001,
591 0b001000010000010,
592 0b001000010000011,
593 0b001000010000100,
594 0b001000010000111,
595 0b001000010001000,
596 0b001000010001110,
597 0b001000010001111,
598 0b001000110000000,
599 0b001000111101000,
600 0b010000000000000,
601 0b010000110000000,
602 0b011000000000000,
603 0b011110010000111,
604 0b100000000000000,
605 0b101000000000000,
606 0b110000000000000,
607 0b111000000000000,
608 0b111000000011100,
609 };
610
611 static const uint16_t gen8_src_index_table[32] = {
612 0b000000000000,
613 0b000000000010,
614 0b000000010000,
615 0b000000010010,
616 0b000000011000,
617 0b000000100000,
618 0b000000101000,
619 0b000001001000,
620 0b000001010000,
621 0b000001110000,
622 0b000001111000,
623 0b001100000000,
624 0b001100000010,
625 0b001100001000,
626 0b001100010000,
627 0b001100010010,
628 0b001100100000,
629 0b001100101000,
630 0b001100111000,
631 0b001101000000,
632 0b001101000010,
633 0b001101001000,
634 0b001101010000,
635 0b001101100000,
636 0b001101101000,
637 0b001101110000,
638 0b001101110001,
639 0b001101111000,
640 0b010001101000,
641 0b010001101001,
642 0b010001101010,
643 0b010110001000,
644 };
645
646 static const uint32_t gen11_datatype_table[32] = {
647 0b001000000000000000001,
648 0b001000000000001000000,
649 0b001000000000001000001,
650 0b001000000000011000001,
651 0b001000000000101100101,
652 0b001000000101111100101,
653 0b001000000100101000001,
654 0b001000000100101000101,
655 0b001000000100101100101,
656 0b001000001000001000001,
657 0b001000011000001000000,
658 0b001000011000001000001,
659 0b001000101000101000101,
660 0b001000111000101000100,
661 0b001000111000101000101,
662 0b001100100100101100101,
663 0b001100101100100100101,
664 0b001100101100101100100,
665 0b001100101100101100101,
666 0b001100111100101100100,
667 0b000000000010000001100,
668 0b001000000000001100101,
669 0b001000000000101000101,
670 0b001000001000001000000,
671 0b001000101000101000100,
672 0b001000111000100000100,
673 0b001001001001000001001,
674 0b001101111100101100101,
675 0b001100111100101100101,
676 0b001001111001101001100,
677 0b001001001001001001000,
678 0b001001011001001001000,
679 };
680
681 static const uint32_t gen12_control_index_table[32] = {
682 0b000000000000000000100, /* (16|M0) */
683 0b000000000000000000011, /* (8|M0) */
684 0b000000010000000000000, /* (W) (1|M0) */
685 0b000000010000000000100, /* (W) (16|M0) */
686 0b000000010000000000011, /* (W) (8|M0) */
687 0b010000000000000000100, /* (16|M0) (ge)f0.0 */
688 0b000000000000000100100, /* (16|M16) */
689 0b010100000000000000100, /* (16|M0) (lt)f0.0 */
690 0b000000000000000000000, /* (1|M0) */
691 0b000010000000000000100, /* (16|M0) (sat) */
692 0b000000000000000010011, /* (8|M8) */
693 0b001100000000000000100, /* (16|M0) (gt)f0.0 */
694 0b000100000000000000100, /* (16|M0) (eq)f0.0 */
695 0b000100010000000000100, /* (W) (16|M0) (eq)f0.0 */
696 0b001000000000000000100, /* (16|M0) (ne)f0.0 */
697 0b000000000000100000100, /* (f0.0) (16|M0) */
698 0b010100000000000000011, /* (8|M0) (lt)f0.0 */
699 0b000000000000110000100, /* (f1.0) (16|M0) */
700 0b000000010000000000001, /* (W) (2|M0) */
701 0b000000000000101000100, /* (f0.1) (16|M0) */
702 0b000000000000111000100, /* (f1.1) (16|M0) */
703 0b010000010000000000100, /* (W) (16|M0) (ge)f0.0 */
704 0b000000000000000100011, /* (8|M16) */
705 0b000000000000000110011, /* (8|M24) */
706 0b010100010000000000100, /* (W) (16|M0) (lt)f0.0 */
707 0b010000000000000000011, /* (8|M0) (ge)f0.0 */
708 0b000100010000000000000, /* (W) (1|M0) (eq)f0.0 */
709 0b000010000000000000011, /* (8|M0) (sat) */
710 0b010100000000010000100, /* (16|M0) (lt)f1.0 */
711 0b000100000000000000011, /* (8|M0) (eq)f0.0 */
712 0b000001000000000000011, /* (8|M0) {AccWrEn} */
713 0b000000010000000100100, /* (W) (16|M16) */
714 };
715
716 static const uint32_t gen12_datatype_table[32] = {
717 0b11010110100101010100, /* grf<1>:f grf:f grf:f */
718 0b00000110100101010100, /* grf<1>:f grf:f arf:ub */
719 0b00000010101101010100, /* grf<1>:f imm:f arf:ub */
720 0b01010110110101010100, /* grf<1>:f grf:f imm:f */
721 0b11010100100101010100, /* arf<1>:f grf:f grf:f */
722 0b11010010100101010100, /* grf<1>:f arf:f grf:f */
723 0b01010100110101010100, /* arf<1>:f grf:f imm:f */
724 0b00000000100000000000, /* arf<1>:ub arf:ub arf:ub */
725 0b11010000100101010100, /* arf<1>:f arf:f grf:f */
726 0b00101110110011001100, /* grf<1>:d grf:d imm:w */
727 0b10110110100011001100, /* grf<1>:d grf:d grf:d */
728 0b01010010110101010100, /* grf<1>:f arf:f imm:f */
729 0b10010110100001000100, /* grf<1>:ud grf:ud grf:ud */
730 0b01010000110101010100, /* arf<1>:f arf:f imm:f */
731 0b00110110110011001100, /* grf<1>:d grf:d imm:d */
732 0b00010110110001000100, /* grf<1>:ud grf:ud imm:ud */
733 0b00000111000101010100, /* grf<2>:f grf:f arf:ub */
734 0b00101100110011001100, /* arf<1>:d grf:d imm:w */
735 0b00000000100000100010, /* arf<1>:uw arf:uw arf:ub */
736 0b00000010100001000100, /* grf<1>:ud arf:ud arf:ub */
737 0b00100110110000101010, /* grf<1>:w grf:uw imm:uv */
738 0b00001110110000100010, /* grf<1>:uw grf:uw imm:uw */
739 0b10010111000001000100, /* grf<2>:ud grf:ud grf:ud */
740 0b00000110100101001100, /* grf<1>:d grf:f arf:ub */
741 0b10001100100011001100, /* arf<1>:d grf:d grf:uw */
742 0b00000110100001010100, /* grf<1>:f grf:ud arf:ub */
743 0b00101110110001001100, /* grf<1>:d grf:ud imm:w */
744 0b00000010100000100010, /* grf<1>:uw arf:uw arf:ub */
745 0b00000110100000110100, /* grf<1>:f grf:uw arf:ub */
746 0b00000110100000010100, /* grf<1>:f grf:ub arf:ub */
747 0b00000110100011010100, /* grf<1>:f grf:d arf:ub */
748 0b00000010100101010100, /* grf<1>:f arf:f arf:ub */
749 };
750
751 static const uint16_t gen12_subreg_table[32] = {
752 0b000000000000000, /* .0 .0 .0 */
753 0b100000000000000, /* .0 .0 .16 */
754 0b001000000000000, /* .0 .0 .4 */
755 0b011000000000000, /* .0 .0 .12 */
756 0b000000010000000, /* .0 .4 .0 */
757 0b010000000000000, /* .0 .0 .8 */
758 0b101000000000000, /* .0 .0 .20 */
759 0b000000000001000, /* .8 .0 .0 */
760 0b000000100000000, /* .0 .8 .0 */
761 0b110000000000000, /* .0 .0 .24 */
762 0b111000000000000, /* .0 .0 .28 */
763 0b000001000000000, /* .0 .16 .0 */
764 0b000000000000100, /* .4 .0 .0 */
765 0b000001100000000, /* .0 .24 .0 */
766 0b000001010000000, /* .0 .20 .0 */
767 0b000000110000000, /* .0 .12 .0 */
768 0b000001110000000, /* .0 .28 .0 */
769 0b000000000011100, /* .28 .0 .0 */
770 0b000000000010000, /* .16 .0 .0 */
771 0b000000000001100, /* .12 .0 .0 */
772 0b000000000011000, /* .24 .0 .0 */
773 0b000000000010100, /* .20 .0 .0 */
774 0b000000000000010, /* .2 .0 .0 */
775 0b000000101000000, /* .0 .10 .0 */
776 0b000000001000000, /* .0 .2 .0 */
777 0b000000010000100, /* .4 .4 .0 */
778 0b000000001011100, /* .28 .2 .0 */
779 0b000000001000010, /* .2 .2 .0 */
780 0b000000110001100, /* .12 .12 .0 */
781 0b000000000100000, /* .0 .1 .0 */
782 0b000000001100000, /* .0 .3 .0 */
783 0b110001100000000, /* .0 .24 .24 */
784 };
785
786 static const uint16_t gen12_src0_index_table[16] = {
787 0b010001100100, /* r<8;8,1> */
788 0b000000000000, /* r<0;1,0> */
789 0b010001100110, /* -r<8;8,1> */
790 0b010001100101, /* (abs)r<8;8,1> */
791 0b000000000010, /* -r<0;1,0> */
792 0b001000000000, /* r<2;1,0> */
793 0b001001000000, /* r<2;4,0> */
794 0b001101000000, /* r<4;4,0> */
795 0b001000100100, /* r<2;2,1> */
796 0b001100000000, /* r<4;1,0> */
797 0b001000100110, /* -r<2;2,1> */
798 0b001101000100, /* r<4;4,1> */
799 0b010001100111, /* -(abs)r<8;8,1> */
800 0b000100000000, /* r<1;1,0> */
801 0b000000000001, /* (abs)r<0;1,0> */
802 0b111100010000, /* r[a]<1,0> */
803 };
804
805 static const uint16_t gen12_src1_index_table[16] = {
806 0b000100011001, /* r<8;8,1> */
807 0b000000000000, /* r<0;1,0> */
808 0b100100011001, /* -r<8;8,1> */
809 0b100000000000, /* -r<0;1,0> */
810 0b010100011001, /* (abs)r<8;8,1> */
811 0b100011010000, /* -r<4;4,0> */
812 0b000010000000, /* r<2;1,0> */
813 0b000010001001, /* r<2;2,1> */
814 0b100010001001, /* -r<2;2,1> */
815 0b000011010000, /* r<4;4,0> */
816 0b000011010001, /* r<4;4,1> */
817 0b000011000000, /* r<4;1,0> */
818 0b110100011001, /* -(abs)r<8;8,1> */
819 0b010000000000, /* (abs)r<0;1,0> */
820 0b110000000000, /* -(abs)r<0;1,0> */
821 0b100011010001, /* -r<4;4,1> */
822 };
823
824 /* This is actually the control index table for Cherryview (26 bits), but the
825 * only difference from Broadwell (24 bits) is that it has two extra 0-bits at
826 * the start.
827 *
828 * The low 24 bits have the same mappings on both hardware.
829 */
830 static const uint32_t gen8_3src_control_index_table[4] = {
831 0b00100000000110000000000001,
832 0b00000000000110000000000001,
833 0b00000000001000000000000001,
834 0b00000000001000000000100001,
835 };
836
837 /* This is actually the control index table for Cherryview (49 bits), but the
838 * only difference from Broadwell (46 bits) is that it has three extra 0-bits
839 * at the start.
840 *
841 * The low 44 bits have the same mappings on both hardware, and since the high
842 * three bits on Broadwell are zero, we can reuse Cherryview's table.
843 */
844 static const uint64_t gen8_3src_source_index_table[4] = {
845 0b0000001110010011100100111001000001111000000000000,
846 0b0000001110010011100100111001000001111000000000010,
847 0b0000001110010011100100111001000001111000000001000,
848 0b0000001110010011100100111001000001111000000100000,
849 };
850
851 static const uint64_t gen12_3src_control_index_table[32] = {
852 0b000001001010010101000000000000000100, /* (16|M0) grf<1>:f :f :f :f */
853 0b000001001010010101000000000000000011, /* (8|M0) grf<1>:f :f :f :f */
854 0b000001001000010101000000000000000011, /* (8|M0) arf<1>:f :f :f :f */
855 0b000001001010010101000010000000000011, /* (W) (8|M0) grf<1>:f :f :f :f */
856 0b000001001000010101000010000000000011, /* (W) (8|M0) arf<1>:f :f :f :f */
857 0b000001001000010101000000000000010011, /* (8|M8) arf<1>:f :f :f :f */
858 0b000001001010010101000000000000010011, /* (8|M8) grf<1>:f :f :f :f */
859 0b000001001000010101000010000000010011, /* (W) (8|M8) arf<1>:f :f :f :f */
860 0b000001001010010101000010000000010011, /* (W) (8|M8) grf<1>:f :f :f :f */
861 0b000001001010010101000010000000000100, /* (W) (16|M0) grf<1>:f :f :f :f */
862 0b000001001000010101000000000000000100, /* (16|M0) arf<1>:f :f :f :f */
863 0b000001001010010101010000000000000100, /* (16|M0) (sat)grf<1>:f :f :f :f */
864 0b000001001010010101000000000000100100, /* (16|M16) grf<1>:f :f :f :f */
865 0b000001001000010101000010000000000100, /* (W) (16|M0) arf<1>:f :f :f :f */
866 0b000001001010010101000010000000000000, /* (W) (1|M0) grf<1>:f :f :f :f */
867 0b000001001010010101010000000000000011, /* (8|M0) (sat)grf<1>:f :f :f :f */
868 0b000001001000010101000010000000110011, /* (W) (8|M24) arf<1>:f :f :f :f */
869 0b000001001000010101000010000000100011, /* (W) (8|M16) arf<1>:f :f :f :f */
870 0b000001001010010101000010000000110011, /* (W) (8|M24) grf<1>:f :f :f :f */
871 0b000001001010010101000010000000100011, /* (W) (8|M16) grf<1>:f :f :f :f */
872 0b000001001000010101000000000000100011, /* (8|M16) arf<1>:f :f :f :f */
873 0b000001001000010101000000000000110011, /* (8|M24) arf<1>:f :f :f :f */
874 0b000001001010010101000000000000100011, /* (8|M16) grf<1>:f :f :f :f */
875 0b000001001010010101000000000000110011, /* (8|M24) grf<1>:f :f :f :f */
876 0b000001001000010101010000000000000100, /* (16|M0) (sat)arf<1>:f :f :f :f */
877 0b000001001010010101010010000000000100, /* (W) (16|M0) (sat)grf<1>:f :f :f :f */
878 0b000001001010010101000010000000100100, /* (W) (16|M16) grf<1>:f :f :f :f */
879 0b000001001010010001000010000000000000, /* (W) (1|M0) grf<1>:ud :ud :ud :ud */
880 0b000001001000010101000000000000100100, /* (16|M16) arf<1>:f :f :f :f */
881 0b000001001010010101010000000000100100, /* (16|M16) (sat)grf<1>:f :f :f :f */
882 0b000001001010010101000010000000000010, /* (W) (4|M0) grf<1>:f :f :f :f */
883 0b000001001000010101010000000000000011, /* (8|M0) (sat)arf<1>:f :f :f :f */
884 };
885
886 static const uint32_t gen12_3src_source_index_table[32] = {
887 0b100101100001100000000, /* grf<0;0> grf<8;1> grf<0> */
888 0b100101100001001000010, /* arf<4;1> grf<8;1> grf<0> */
889 0b101101100001101000011, /* grf<8;1> grf<8;1> grf<1> */
890 0b100101100001101000011, /* grf<8;1> grf<8;1> grf<0> */
891 0b101100000000101000011, /* grf<8;1> grf<0;0> grf<1> */
892 0b101101100001101001011, /* -grf<8;1> grf<8;1> grf<1> */
893 0b101001100001101000011, /* grf<8;1> arf<8;1> grf<1> */
894 0b100001100001100000000, /* grf<0;0> arf<8;1> grf<0> */
895 0b101101100001100000000, /* grf<0;0> grf<8;1> grf<1> */
896 0b101101100101101000011, /* grf<8;1> grf<8;1> -grf<1> */
897 0b101101110001101000011, /* grf<8;1> -grf<8;1> grf<1> */
898 0b101100000000100000000, /* grf<0;0> grf<0;0> grf<1> */
899 0b100001100001101000011, /* grf<8;1> arf<8;1> grf<0> */
900 0b100101110001100000000, /* grf<0;0> -grf<8;1> grf<0> */
901 0b100101110001101000011, /* grf<8;1> -grf<8;1> grf<0> */
902 0b100101100001101001011, /* -grf<8;1> grf<8;1> grf<0> */
903 0b100100000000101000011, /* grf<8;1> grf<0;0> grf<0> */
904 0b100101100001100001000, /* -grf<0;0> grf<8;1> grf<0> */
905 0b100100000000100000000, /* grf<0;0> grf<0;0> grf<0> */
906 0b101101110001100000000, /* grf<0;0> -grf<8;1> grf<1> */
907 0b100101100101100000000, /* grf<0;0> grf<8;1> -grf<0> */
908 0b101001100001100000000, /* grf<0;0> arf<8;1> grf<1> */
909 0b100101100101101000011, /* grf<8;1> grf<8;1> -grf<0> */
910 0b101101100101101001011, /* -grf<8;1> grf<8;1> -grf<1> */
911 0b101001100001101001011, /* -grf<8;1> arf<8;1> grf<1> */
912 0b101101110001101001011, /* -grf<8;1> -grf<8;1> grf<1> */
913 0b101100010000101000011, /* grf<8;1> -grf<0;0> grf<1> */
914 0b101100000100101000011, /* grf<8;1> grf<0;0> -grf<1> */
915 0b101101100001100001000, /* -grf<0;0> grf<8;1> grf<1> */
916 0b101101100101100000000, /* grf<0;0> grf<8;1> -grf<1> */
917 0b100100000100101000011, /* grf<8;1> grf<0;0> -grf<0> */
918 0b101001100101101000011, /* grf<8;1> arf<8;1> -grf<1> */
919 };
920
921 static const uint32_t gen12_3src_subreg_table[32] = {
922 0b00000000000000000000, /* .0 .0 .0 .0 */
923 0b00100000000000000000, /* .0 .0 .0 .4 */
924 0b00000000000110000000, /* .0 .12 .0 .0 */
925 0b10100000000000000000, /* .0 .0 .0 .20 */
926 0b10000000001110000000, /* .0 .28 .0 .16 */
927 0b01100000000000000000, /* .0 .0 .0 .12 */
928 0b01000000000000000000, /* .0 .0 .0 .8 */
929 0b00000010000000000000, /* .0 .0 .8 .0 */
930 0b00000001000000000000, /* .0 .0 .4 .0 */
931 0b11000000000000000000, /* .0 .0 .0 .24 */
932 0b10000000000000000000, /* .0 .0 .0 .16 */
933 0b11100000000000000000, /* .0 .0 .0 .28 */
934 0b00000110000000000000, /* .0 .0 .24 .0 */
935 0b00000000000010000000, /* .0 .4 .0 .0 */
936 0b00000100000000000000, /* .0 .0 .16 .0 */
937 0b00000011000000000000, /* .0 .0 .12 .0 */
938 0b00000101000000000000, /* .0 .0 .20 .0 */
939 0b00000111000000000000, /* .0 .0 .28 .0 */
940 0b00000000000100000000, /* .0 .8 .0 .0 */
941 0b00000000001000000000, /* .0 .16 .0 .0 */
942 0b00000000001100000000, /* .0 .24 .0 .0 */
943 0b00000000001010000000, /* .0 .20 .0 .0 */
944 0b00000000001110000000, /* .0 .28 .0 .0 */
945 0b11000000001110000000, /* .0 .28 .0 .24 */
946 0b00100000000100000000, /* .0 .8 .0 .4 */
947 0b00100000000110000000, /* .0 .12 .0 .4 */
948 0b01000000000110000000, /* .0 .12 .0 .8 */
949 0b10000000001100000000, /* .0 .24 .0 .16 */
950 0b10000000001010000000, /* .0 .20 .0 .16 */
951 0b01100000000010000000, /* .0 .4 .0 .12 */
952 0b10100000001110000000, /* .0 .28 .0 .20 */
953 0b01000000000010000000, /* .0 .4 .0 .8 */
954 };
955
956 static const uint32_t *control_index_table;
957 static const uint32_t *datatype_table;
958 static const uint16_t *subreg_table;
959 static const uint16_t *src0_index_table;
960 static const uint16_t *src1_index_table;
961
962 static bool
963 set_control_index(const struct gen_device_info *devinfo,
964 brw_compact_inst *dst, const brw_inst *src)
965 {
966 uint32_t uncompacted; /* 17b/G45; 19b/IVB+; 21b/TGL+ */
967
968 if (devinfo->gen >= 12) {
969 uncompacted = (brw_inst_bits(src, 95, 92) << 17) | /* 4b */
970 (brw_inst_bits(src, 34, 34) << 16) | /* 1b */
971 (brw_inst_bits(src, 33, 33) << 15) | /* 1b */
972 (brw_inst_bits(src, 32, 32) << 14) | /* 1b */
973 (brw_inst_bits(src, 31, 31) << 13) | /* 1b */
974 (brw_inst_bits(src, 28, 28) << 12) | /* 1b */
975 (brw_inst_bits(src, 27, 24) << 8) | /* 4b */
976 (brw_inst_bits(src, 23, 22) << 6) | /* 2b */
977 (brw_inst_bits(src, 21, 19) << 3) | /* 3b */
978 (brw_inst_bits(src, 18, 16)); /* 3b */
979 } else if (devinfo->gen >= 8) {
980 uncompacted = (brw_inst_bits(src, 33, 31) << 16) | /* 3b */
981 (brw_inst_bits(src, 23, 12) << 4) | /* 12b */
982 (brw_inst_bits(src, 10, 9) << 2) | /* 2b */
983 (brw_inst_bits(src, 34, 34) << 1) | /* 1b */
984 (brw_inst_bits(src, 8, 8)); /* 1b */
985 } else {
986 uncompacted = (brw_inst_bits(src, 31, 31) << 16) | /* 1b */
987 (brw_inst_bits(src, 23, 8)); /* 16b */
988
989 /* On gen7, the flag register and subregister numbers are integrated into
990 * the control index.
991 */
992 if (devinfo->gen == 7)
993 uncompacted |= brw_inst_bits(src, 90, 89) << 17; /* 2b */
994 }
995
996 for (int i = 0; i < 32; i++) {
997 if (control_index_table[i] == uncompacted) {
998 brw_compact_inst_set_control_index(devinfo, dst, i);
999 return true;
1000 }
1001 }
1002
1003 return false;
1004 }
1005
1006 static bool
1007 set_datatype_index(const struct gen_device_info *devinfo, brw_compact_inst *dst,
1008 const brw_inst *src, bool is_immediate)
1009 {
1010 uint32_t uncompacted; /* 18b/G45+; 21b/BDW+; 20b/TGL+ */
1011
1012 if (devinfo->gen >= 12) {
1013 uncompacted = (brw_inst_bits(src, 91, 88) << 15) | /* 4b */
1014 (brw_inst_bits(src, 66, 66) << 14) | /* 1b */
1015 (brw_inst_bits(src, 50, 50) << 13) | /* 1b */
1016 (brw_inst_bits(src, 49, 48) << 11) | /* 2b */
1017 (brw_inst_bits(src, 47, 47) << 10) | /* 1b */
1018 (brw_inst_bits(src, 46, 46) << 9) | /* 1b */
1019 (brw_inst_bits(src, 43, 40) << 5) | /* 4b */
1020 (brw_inst_bits(src, 39, 36) << 1) | /* 4b */
1021 (brw_inst_bits(src, 35, 35)); /* 1b */
1022
1023 /* Src1.RegFile overlaps with the immediate, so ignore it if an immediate
1024 * is present
1025 */
1026 if (!is_immediate) {
1027 uncompacted |= brw_inst_bits(src, 98, 98) << 19; /* 1b */
1028 }
1029 } else if (devinfo->gen >= 8) {
1030 uncompacted = (brw_inst_bits(src, 63, 61) << 18) | /* 3b */
1031 (brw_inst_bits(src, 94, 89) << 12) | /* 6b */
1032 (brw_inst_bits(src, 46, 35)); /* 12b */
1033 } else {
1034 uncompacted = (brw_inst_bits(src, 63, 61) << 15) | /* 3b */
1035 (brw_inst_bits(src, 46, 32)); /* 15b */
1036 }
1037
1038 for (int i = 0; i < 32; i++) {
1039 if (datatype_table[i] == uncompacted) {
1040 brw_compact_inst_set_datatype_index(devinfo, dst, i);
1041 return true;
1042 }
1043 }
1044
1045 return false;
1046 }
1047
1048 static bool
1049 set_subreg_index(const struct gen_device_info *devinfo, brw_compact_inst *dst,
1050 const brw_inst *src, bool is_immediate)
1051 {
1052 uint16_t uncompacted; /* 15b */
1053
1054 if (devinfo->gen >= 12) {
1055 uncompacted = (brw_inst_bits(src, 55, 51) << 0) | /* 5b */
1056 (brw_inst_bits(src, 71, 67) << 5); /* 5b */
1057
1058 if (!is_immediate)
1059 uncompacted |= brw_inst_bits(src, 103, 99) << 10; /* 5b */
1060 } else {
1061 uncompacted = (brw_inst_bits(src, 52, 48) << 0) | /* 5b */
1062 (brw_inst_bits(src, 68, 64) << 5); /* 5b */
1063
1064 if (!is_immediate)
1065 uncompacted |= brw_inst_bits(src, 100, 96) << 10; /* 5b */
1066 }
1067
1068 for (int i = 0; i < 32; i++) {
1069 if (subreg_table[i] == uncompacted) {
1070 brw_compact_inst_set_subreg_index(devinfo, dst, i);
1071 return true;
1072 }
1073 }
1074
1075 return false;
1076 }
1077
1078 static bool
1079 set_src0_index(const struct gen_device_info *devinfo,
1080 brw_compact_inst *dst, const brw_inst *src)
1081 {
1082 uint16_t uncompacted; /* 12b */
1083 int table_len;
1084
1085 if (devinfo->gen >= 12) {
1086 table_len = ARRAY_SIZE(gen12_src0_index_table);
1087 uncompacted = (brw_inst_bits(src, 87, 84) << 8) | /* 4b */
1088 (brw_inst_bits(src, 83, 81) << 5) | /* 3b */
1089 (brw_inst_bits(src, 80, 80) << 4) | /* 1b */
1090 (brw_inst_bits(src, 65, 64) << 2) | /* 2b */
1091 (brw_inst_bits(src, 45, 44)); /* 2b */
1092 } else {
1093 table_len = ARRAY_SIZE(gen8_src_index_table);
1094 uncompacted = brw_inst_bits(src, 88, 77); /* 12b */
1095 }
1096
1097 for (int i = 0; i < table_len; i++) {
1098 if (src0_index_table[i] == uncompacted) {
1099 brw_compact_inst_set_src0_index(devinfo, dst, i);
1100 return true;
1101 }
1102 }
1103
1104 return false;
1105 }
1106
1107 static bool
1108 set_src1_index(const struct gen_device_info *devinfo, brw_compact_inst *dst,
1109 const brw_inst *src, bool is_immediate, unsigned imm)
1110 {
1111 if (is_immediate) {
1112 if (devinfo->gen >= 12) {
1113 /* src1 index takes the low 4 bits of the 12-bit compacted value */
1114 brw_compact_inst_set_src1_index(devinfo, dst, imm & 0xf);
1115 } else {
1116 /* src1 index takes the high 5 bits of the 13-bit compacted value */
1117 brw_compact_inst_set_src1_index(devinfo, dst, imm >> 8);
1118 }
1119 return true;
1120 } else {
1121 uint16_t uncompacted; /* 12b */
1122 int table_len;
1123
1124 if (devinfo->gen >= 12) {
1125 table_len = ARRAY_SIZE(gen12_src0_index_table);
1126 uncompacted = (brw_inst_bits(src, 121, 120) << 10) | /* 2b */
1127 (brw_inst_bits(src, 119, 116) << 6) | /* 4b */
1128 (brw_inst_bits(src, 115, 113) << 3) | /* 3b */
1129 (brw_inst_bits(src, 112, 112) << 2) | /* 1b */
1130 (brw_inst_bits(src, 97, 96)); /* 2b */
1131 } else {
1132 table_len = ARRAY_SIZE(gen8_src_index_table);
1133 uncompacted = brw_inst_bits(src, 120, 109); /* 12b */
1134 }
1135
1136 for (int i = 0; i < table_len; i++) {
1137 if (src1_index_table[i] == uncompacted) {
1138 brw_compact_inst_set_src1_index(devinfo, dst, i);
1139 return true;
1140 }
1141 }
1142 }
1143
1144 return false;
1145 }
1146
1147 static bool
1148 set_3src_control_index(const struct gen_device_info *devinfo,
1149 brw_compact_inst *dst, const brw_inst *src)
1150 {
1151 assert(devinfo->gen >= 8);
1152
1153 if (devinfo->gen >= 12) {
1154 uint64_t uncompacted = /* 36b/TGL+ */
1155 (brw_inst_bits(src, 95, 92) << 32) | /* 4b */
1156 (brw_inst_bits(src, 90, 88) << 29) | /* 3b */
1157 (brw_inst_bits(src, 82, 80) << 26) | /* 3b */
1158 (brw_inst_bits(src, 50, 50) << 25) | /* 1b */
1159 (brw_inst_bits(src, 48, 48) << 24) | /* 1b */
1160 (brw_inst_bits(src, 42, 40) << 21) | /* 3b */
1161 (brw_inst_bits(src, 39, 39) << 20) | /* 1b */
1162 (brw_inst_bits(src, 38, 36) << 17) | /* 3b */
1163 (brw_inst_bits(src, 34, 34) << 16) | /* 1b */
1164 (brw_inst_bits(src, 33, 33) << 15) | /* 1b */
1165 (brw_inst_bits(src, 32, 32) << 14) | /* 1b */
1166 (brw_inst_bits(src, 31, 31) << 13) | /* 1b */
1167 (brw_inst_bits(src, 28, 28) << 12) | /* 1b */
1168 (brw_inst_bits(src, 27, 24) << 8) | /* 4b */
1169 (brw_inst_bits(src, 23, 23) << 7) | /* 1b */
1170 (brw_inst_bits(src, 22, 22) << 6) | /* 1b */
1171 (brw_inst_bits(src, 21, 19) << 3) | /* 3b */
1172 (brw_inst_bits(src, 18, 16)); /* 3b */
1173
1174 for (unsigned i = 0; i < ARRAY_SIZE(gen12_3src_control_index_table); i++) {
1175 if (gen12_3src_control_index_table[i] == uncompacted) {
1176 brw_compact_inst_set_3src_control_index(devinfo, dst, i);
1177 return true;
1178 }
1179 }
1180 } else {
1181 uint32_t uncompacted = /* 24b/BDW; 26b/CHV/SKL+ */
1182 (brw_inst_bits(src, 34, 32) << 21) | /* 3b */
1183 (brw_inst_bits(src, 28, 8)); /* 21b */
1184
1185 if (devinfo->gen >= 9 || devinfo->is_cherryview) {
1186 uncompacted |=
1187 brw_inst_bits(src, 36, 35) << 24; /* 2b */
1188 }
1189
1190 for (unsigned i = 0; i < ARRAY_SIZE(gen8_3src_control_index_table); i++) {
1191 if (gen8_3src_control_index_table[i] == uncompacted) {
1192 brw_compact_inst_set_3src_control_index(devinfo, dst, i);
1193 return true;
1194 }
1195 }
1196 }
1197
1198 return false;
1199 }
1200
1201 static bool
1202 set_3src_source_index(const struct gen_device_info *devinfo,
1203 brw_compact_inst *dst, const brw_inst *src)
1204 {
1205 assert(devinfo->gen >= 8);
1206
1207 if (devinfo->gen >= 12) {
1208 uint32_t uncompacted = /* 21b/TGL+ */
1209 (brw_inst_bits(src, 114, 114) << 20) | /* 1b */
1210 (brw_inst_bits(src, 113, 112) << 18) | /* 2b */
1211 (brw_inst_bits(src, 98, 98) << 17) | /* 1b */
1212 (brw_inst_bits(src, 97, 96) << 15) | /* 2b */
1213 (brw_inst_bits(src, 91, 91) << 14) | /* 1b */
1214 (brw_inst_bits(src, 87, 86) << 12) | /* 2b */
1215 (brw_inst_bits(src, 85, 84) << 10) | /* 2b */
1216 (brw_inst_bits(src, 83, 83) << 9) | /* 1b */
1217 (brw_inst_bits(src, 66, 66) << 8) | /* 1b */
1218 (brw_inst_bits(src, 65, 64) << 6) | /* 2b */
1219 (brw_inst_bits(src, 47, 47) << 5) | /* 1b */
1220 (brw_inst_bits(src, 46, 46) << 4) | /* 1b */
1221 (brw_inst_bits(src, 45, 44) << 2) | /* 2b */
1222 (brw_inst_bits(src, 43, 43) << 1) | /* 1b */
1223 (brw_inst_bits(src, 35, 35)); /* 1b */
1224
1225 for (unsigned i = 0; i < ARRAY_SIZE(gen12_3src_source_index_table); i++) {
1226 if (gen12_3src_source_index_table[i] == uncompacted) {
1227 brw_compact_inst_set_3src_source_index(devinfo, dst, i);
1228 return true;
1229 }
1230 }
1231 } else {
1232 uint64_t uncompacted = /* 46b/BDW; 49b/CHV/SKL+ */
1233 (brw_inst_bits(src, 83, 83) << 43) | /* 1b */
1234 (brw_inst_bits(src, 114, 107) << 35) | /* 8b */
1235 (brw_inst_bits(src, 93, 86) << 27) | /* 8b */
1236 (brw_inst_bits(src, 72, 65) << 19) | /* 8b */
1237 (brw_inst_bits(src, 55, 37)); /* 19b */
1238
1239 if (devinfo->gen >= 9 || devinfo->is_cherryview) {
1240 uncompacted |=
1241 (brw_inst_bits(src, 126, 125) << 47) | /* 2b */
1242 (brw_inst_bits(src, 105, 104) << 45) | /* 2b */
1243 (brw_inst_bits(src, 84, 84) << 44); /* 1b */
1244 } else {
1245 uncompacted |=
1246 (brw_inst_bits(src, 125, 125) << 45) | /* 1b */
1247 (brw_inst_bits(src, 104, 104) << 44); /* 1b */
1248 }
1249
1250 for (unsigned i = 0; i < ARRAY_SIZE(gen8_3src_source_index_table); i++) {
1251 if (gen8_3src_source_index_table[i] == uncompacted) {
1252 brw_compact_inst_set_3src_source_index(devinfo, dst, i);
1253 return true;
1254 }
1255 }
1256 }
1257
1258 return false;
1259 }
1260
1261 static bool
1262 set_3src_subreg_index(const struct gen_device_info *devinfo,
1263 brw_compact_inst *dst, const brw_inst *src)
1264 {
1265 assert(devinfo->gen >= 12);
1266
1267 uint32_t uncompacted = /* 20b/TGL+ */
1268 (brw_inst_bits(src, 119, 115) << 15) | /* 5b */
1269 (brw_inst_bits(src, 103, 99) << 10) | /* 5b */
1270 (brw_inst_bits(src, 71, 67) << 5) | /* 5b */
1271 (brw_inst_bits(src, 55, 51)); /* 5b */
1272
1273 for (unsigned i = 0; i < ARRAY_SIZE(gen12_3src_subreg_table); i++) {
1274 if (gen12_3src_subreg_table[i] == uncompacted) {
1275 brw_compact_inst_set_3src_subreg_index(devinfo, dst, i);
1276 return true;
1277 }
1278 }
1279
1280 return false;
1281 }
1282
1283 static bool
1284 has_unmapped_bits(const struct gen_device_info *devinfo, const brw_inst *src)
1285 {
1286 /* EOT can only be mapped on a send if the src1 is an immediate */
1287 if ((brw_inst_opcode(devinfo, src) == BRW_OPCODE_SENDC ||
1288 brw_inst_opcode(devinfo, src) == BRW_OPCODE_SEND) &&
1289 brw_inst_eot(devinfo, src))
1290 return true;
1291
1292 /* Check for instruction bits that don't map to any of the fields of the
1293 * compacted instruction. The instruction cannot be compacted if any of
1294 * them are set. They overlap with:
1295 * - NibCtrl (bit 47 on Gen7, bit 11 on Gen8)
1296 * - Dst.AddrImm[9] (bit 47 on Gen8)
1297 * - Src0.AddrImm[9] (bit 95 on Gen8)
1298 * - Imm64[27:31] (bits 91-95 on Gen7, bit 95 on Gen8)
1299 * - UIP[31] (bit 95 on Gen8)
1300 */
1301 if (devinfo->gen >= 12) {
1302 assert(!brw_inst_bits(src, 7, 7));
1303 return false;
1304 } else if (devinfo->gen >= 8) {
1305 assert(!brw_inst_bits(src, 7, 7));
1306 return brw_inst_bits(src, 95, 95) ||
1307 brw_inst_bits(src, 47, 47) ||
1308 brw_inst_bits(src, 11, 11);
1309 } else {
1310 assert(!brw_inst_bits(src, 7, 7) &&
1311 !(devinfo->gen < 7 && brw_inst_bits(src, 90, 90)));
1312 return brw_inst_bits(src, 95, 91) ||
1313 brw_inst_bits(src, 47, 47);
1314 }
1315 }
1316
1317 static bool
1318 has_3src_unmapped_bits(const struct gen_device_info *devinfo,
1319 const brw_inst *src)
1320 {
1321 /* Check for three-source instruction bits that don't map to any of the
1322 * fields of the compacted instruction. All of them seem to be reserved
1323 * bits currently.
1324 */
1325 if (devinfo->gen >= 12) {
1326 assert(!brw_inst_bits(src, 7, 7));
1327 } else if (devinfo->gen >= 9 || devinfo->is_cherryview) {
1328 assert(!brw_inst_bits(src, 127, 127) &&
1329 !brw_inst_bits(src, 7, 7));
1330 } else {
1331 assert(devinfo->gen >= 8);
1332 assert(!brw_inst_bits(src, 127, 126) &&
1333 !brw_inst_bits(src, 105, 105) &&
1334 !brw_inst_bits(src, 84, 84) &&
1335 !brw_inst_bits(src, 7, 7));
1336
1337 /* Src1Type and Src2Type, used for mixed-precision floating point */
1338 if (brw_inst_bits(src, 36, 35))
1339 return true;
1340 }
1341
1342 return false;
1343 }
1344
1345 static bool
1346 brw_try_compact_3src_instruction(const struct gen_device_info *devinfo,
1347 brw_compact_inst *dst, const brw_inst *src)
1348 {
1349 assert(devinfo->gen >= 8);
1350
1351 if (has_3src_unmapped_bits(devinfo, src))
1352 return false;
1353
1354 #define compact(field) \
1355 brw_compact_inst_set_3src_##field(devinfo, dst, brw_inst_3src_##field(devinfo, src))
1356 #define compact_a16(field) \
1357 brw_compact_inst_set_3src_##field(devinfo, dst, brw_inst_3src_a16_##field(devinfo, src))
1358
1359 compact(hw_opcode);
1360
1361 if (!set_3src_control_index(devinfo, dst, src))
1362 return false;
1363
1364 if (!set_3src_source_index(devinfo, dst, src))
1365 return false;
1366
1367 if (devinfo->gen >= 12) {
1368 if (!set_3src_subreg_index(devinfo, dst, src))
1369 return false;
1370
1371 compact(swsb);
1372 compact(debug_control);
1373 compact(dst_reg_nr);
1374 compact(src0_reg_nr);
1375 compact(src1_reg_nr);
1376 compact(src2_reg_nr);
1377 } else {
1378 compact(dst_reg_nr);
1379 compact_a16(src0_rep_ctrl);
1380 compact(debug_control);
1381 compact(saturate);
1382 compact_a16(src1_rep_ctrl);
1383 compact_a16(src2_rep_ctrl);
1384 compact(src0_reg_nr);
1385 compact(src1_reg_nr);
1386 compact(src2_reg_nr);
1387 compact_a16(src0_subreg_nr);
1388 compact_a16(src1_subreg_nr);
1389 compact_a16(src2_subreg_nr);
1390 }
1391 brw_compact_inst_set_3src_cmpt_control(devinfo, dst, true);
1392
1393 #undef compact
1394 #undef compact_a16
1395
1396 return true;
1397 }
1398
1399 /* On SNB through ICL, compacted instructions have 12-bits for immediate
1400 * sources, and a 13th bit that's replicated through the high 20 bits.
1401 *
1402 * Effectively this means we get 12-bit integers, 0.0f, and some limited uses
1403 * of packed vectors as compactable immediates.
1404 *
1405 * On TGL+, the high 12-bits of floating-point values (:f and :hf) are encoded
1406 * rather than the low 12-bits. For signed integer the 12th bit is replicated,
1407 * while for unsigned integers it is not.
1408 *
1409 * Returns the compacted immediate, or -1 if immediate cannot be compacted
1410 */
1411 static int
1412 compact_immediate(const struct gen_device_info *devinfo,
1413 enum brw_reg_type type, unsigned imm)
1414 {
1415 if (devinfo->gen >= 12) {
1416 switch (type) {
1417 case BRW_REGISTER_TYPE_F:
1418 /* We get the high 12-bits as-is; rest must be zero */
1419 if ((imm & 0xfffff) == 0)
1420 return (imm >> 20) & 0xfff;
1421 break;
1422 case BRW_REGISTER_TYPE_HF:
1423 /* We get the high 12-bits as-is; rest must be zero */
1424 if ((imm & 0xf) == 0)
1425 return (imm >> 4) & 0xfff;
1426 break;
1427 case BRW_REGISTER_TYPE_UD:
1428 case BRW_REGISTER_TYPE_VF:
1429 case BRW_REGISTER_TYPE_UV:
1430 case BRW_REGISTER_TYPE_V:
1431 /* We get the low 12-bits as-is; rest must be zero */
1432 if ((imm & 0xfffff000) == 0)
1433 return imm & 0xfff;
1434 break;
1435 case BRW_REGISTER_TYPE_UW:
1436 /* We get the low 12-bits as-is; rest must be zero */
1437 if ((imm & 0xf000) == 0)
1438 return imm & 0xfff;
1439 break;
1440 case BRW_REGISTER_TYPE_D:
1441 /* We get the low 11-bits as-is; 12th is replicated */
1442 if (((int)imm >> 11) == 0 || ((int)imm >> 11) == -1)
1443 return imm & 0xfff;
1444 break;
1445 case BRW_REGISTER_TYPE_W:
1446 /* We get the low 11-bits as-is; 12th is replicated */
1447 if (((short)imm >> 11) == 0 || ((short)imm >> 11) == -1)
1448 return imm & 0xfff;
1449 break;
1450 case BRW_REGISTER_TYPE_NF:
1451 case BRW_REGISTER_TYPE_DF:
1452 case BRW_REGISTER_TYPE_Q:
1453 case BRW_REGISTER_TYPE_UQ:
1454 case BRW_REGISTER_TYPE_B:
1455 case BRW_REGISTER_TYPE_UB:
1456 unreachable("not reached");
1457 }
1458 } else {
1459 /* We get the low 12 bits as-is; 13th is replicated */
1460 if (((int)imm >> 12) == 0 || ((int)imm >> 12 == -1)) {
1461 return imm & 0x1fff;
1462 }
1463 }
1464
1465 return -1;
1466 }
1467
1468 static int
1469 uncompact_immediate(const struct gen_device_info *devinfo,
1470 enum brw_reg_type type, unsigned compact_imm)
1471 {
1472 if (devinfo->gen >= 12) {
1473 switch (type) {
1474 case BRW_REGISTER_TYPE_F:
1475 return compact_imm << 20;
1476 case BRW_REGISTER_TYPE_HF:
1477 return (compact_imm << 20) | (compact_imm << 4);
1478 case BRW_REGISTER_TYPE_UD:
1479 case BRW_REGISTER_TYPE_VF:
1480 case BRW_REGISTER_TYPE_UV:
1481 case BRW_REGISTER_TYPE_V:
1482 return compact_imm;
1483 case BRW_REGISTER_TYPE_UW:
1484 /* Replicate */
1485 return compact_imm << 16 | compact_imm;
1486 case BRW_REGISTER_TYPE_D:
1487 /* Extend the 12th bit into the high 20 bits */
1488 return (int)(compact_imm << 20) >> 20;
1489 case BRW_REGISTER_TYPE_W:
1490 /* Extend the 12th bit into the high 4 bits and replicate */
1491 return ( (int)(compact_imm << 20) >> 4) |
1492 ((short)(compact_imm << 4) >> 4);
1493 case BRW_REGISTER_TYPE_NF:
1494 case BRW_REGISTER_TYPE_DF:
1495 case BRW_REGISTER_TYPE_Q:
1496 case BRW_REGISTER_TYPE_UQ:
1497 case BRW_REGISTER_TYPE_B:
1498 case BRW_REGISTER_TYPE_UB:
1499 unreachable("not reached");
1500 }
1501 } else {
1502 /* Replicate the 13th bit into the high 19 bits */
1503 return (int)(compact_imm << 19) >> 19;
1504 }
1505
1506 unreachable("not reached");
1507 }
1508
1509 static bool
1510 has_immediate(const struct gen_device_info *devinfo, const brw_inst *inst,
1511 enum brw_reg_type *type)
1512 {
1513 if (brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
1514 *type = brw_inst_src0_type(devinfo, inst);
1515 return *type != INVALID_REG_TYPE;
1516 } else if (brw_inst_src1_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
1517 *type = brw_inst_src1_type(devinfo, inst);
1518 return *type != INVALID_REG_TYPE;
1519 }
1520
1521 return false;
1522 }
1523
1524 /**
1525 * Applies some small changes to instruction types to increase chances of
1526 * compaction.
1527 */
1528 static brw_inst
1529 precompact(const struct gen_device_info *devinfo, brw_inst inst)
1530 {
1531 if (brw_inst_src0_reg_file(devinfo, &inst) != BRW_IMMEDIATE_VALUE)
1532 return inst;
1533
1534 /* The Bspec's section titled "Non-present Operands" claims that if src0
1535 * is an immediate that src1's type must be the same as that of src0.
1536 *
1537 * The SNB+ DataTypeIndex instruction compaction tables contain mappings
1538 * that do not follow this rule. E.g., from the IVB/HSW table:
1539 *
1540 * DataTypeIndex 18-Bit Mapping Mapped Meaning
1541 * 3 001000001011111101 r:f | i:vf | a:ud | <1> | dir |
1542 *
1543 * And from the SNB table:
1544 *
1545 * DataTypeIndex 18-Bit Mapping Mapped Meaning
1546 * 8 001000000111101100 a:w | i:w | a:ud | <1> | dir |
1547 *
1548 * Neither of these cause warnings from the simulator when used,
1549 * compacted or otherwise. In fact, all compaction mappings that have an
1550 * immediate in src0 use a:ud for src1.
1551 *
1552 * The GM45 instruction compaction tables do not contain mapped meanings
1553 * so it's not clear whether it has the restriction. We'll assume it was
1554 * lifted on SNB. (FINISHME: decode the GM45 tables and check.)
1555 *
1556 * Don't do any of this for 64-bit immediates, since the src1 fields
1557 * overlap with the immediate and setting them would overwrite the
1558 * immediate we set.
1559 */
1560 if (devinfo->gen >= 6 &&
1561 !(devinfo->is_haswell &&
1562 brw_inst_opcode(devinfo, &inst) == BRW_OPCODE_DIM) &&
1563 !(devinfo->gen >= 8 &&
1564 (brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_DF ||
1565 brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_UQ ||
1566 brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_Q))) {
1567 brw_inst_set_src1_reg_hw_type(devinfo, &inst, 0);
1568 }
1569
1570 /* Compacted instructions only have 12-bits (plus 1 for the other 20)
1571 * for immediate values. Presumably the hardware engineers realized
1572 * that the only useful floating-point value that could be represented
1573 * in this format is 0.0, which can also be represented as a VF-typed
1574 * immediate, so they gave us the previously mentioned mapping on IVB+.
1575 *
1576 * Strangely, we do have a mapping for imm:f in src1, so we don't need
1577 * to do this there.
1578 *
1579 * If we see a 0.0:F, change the type to VF so that it can be compacted.
1580 *
1581 * Compaction of floating-point immediates is improved on Gen12, thus
1582 * removing the need for this.
1583 */
1584 if (devinfo->gen < 12 &&
1585 brw_inst_imm_ud(devinfo, &inst) == 0x0 &&
1586 brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_F &&
1587 brw_inst_dst_type(devinfo, &inst) == BRW_REGISTER_TYPE_F &&
1588 brw_inst_dst_hstride(devinfo, &inst) == BRW_HORIZONTAL_STRIDE_1) {
1589 enum brw_reg_file file = brw_inst_src0_reg_file(devinfo, &inst);
1590 brw_inst_set_src0_file_type(devinfo, &inst, file, BRW_REGISTER_TYPE_VF);
1591 }
1592
1593 /* There are no mappings for dst:d | i:d, so if the immediate is suitable
1594 * set the types to :UD so the instruction can be compacted.
1595 *
1596 * FINISHME: Use dst:f | imm:f on Gen12
1597 */
1598 if (devinfo->gen < 12 &&
1599 compact_immediate(devinfo, BRW_REGISTER_TYPE_D,
1600 brw_inst_imm_ud(devinfo, &inst)) != -1 &&
1601 brw_inst_cond_modifier(devinfo, &inst) == BRW_CONDITIONAL_NONE &&
1602 brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_D &&
1603 brw_inst_dst_type(devinfo, &inst) == BRW_REGISTER_TYPE_D) {
1604 enum brw_reg_file src_file = brw_inst_src0_reg_file(devinfo, &inst);
1605 enum brw_reg_file dst_file = brw_inst_dst_reg_file(devinfo, &inst);
1606
1607 brw_inst_set_src0_file_type(devinfo, &inst, src_file, BRW_REGISTER_TYPE_UD);
1608 brw_inst_set_dst_file_type(devinfo, &inst, dst_file, BRW_REGISTER_TYPE_UD);
1609 }
1610
1611 return inst;
1612 }
1613
1614 /**
1615 * Tries to compact instruction src into dst.
1616 *
1617 * It doesn't modify dst unless src is compactable, which is relied on by
1618 * brw_compact_instructions().
1619 */
1620 bool
1621 brw_try_compact_instruction(const struct gen_device_info *devinfo,
1622 brw_compact_inst *dst, const brw_inst *src)
1623 {
1624 brw_compact_inst temp;
1625
1626 assert(brw_inst_cmpt_control(devinfo, src) == 0);
1627
1628 if (is_3src(devinfo, brw_inst_opcode(devinfo, src))) {
1629 if (devinfo->gen >= 8) {
1630 memset(&temp, 0, sizeof(temp));
1631 if (brw_try_compact_3src_instruction(devinfo, &temp, src)) {
1632 *dst = temp;
1633 return true;
1634 } else {
1635 return false;
1636 }
1637 } else {
1638 return false;
1639 }
1640 }
1641
1642 enum brw_reg_type type;
1643 bool is_immediate = has_immediate(devinfo, src, &type);
1644
1645 unsigned compacted_imm = 0;
1646
1647 if (is_immediate) {
1648 /* Instructions with immediates cannot be compacted on Gen < 6 */
1649 if (devinfo->gen < 6)
1650 return false;
1651
1652 compacted_imm = compact_immediate(devinfo, type,
1653 brw_inst_imm_ud(devinfo, src));
1654 if (compacted_imm == -1)
1655 return false;
1656 }
1657
1658 if (has_unmapped_bits(devinfo, src))
1659 return false;
1660
1661 memset(&temp, 0, sizeof(temp));
1662
1663 #define compact(field) \
1664 brw_compact_inst_set_##field(devinfo, &temp, brw_inst_##field(devinfo, src))
1665 #define compact_reg(field) \
1666 brw_compact_inst_set_##field##_reg_nr(devinfo, &temp, \
1667 brw_inst_##field##_da_reg_nr(devinfo, src))
1668
1669 compact(hw_opcode);
1670 compact(debug_control);
1671
1672 if (!set_control_index(devinfo, &temp, src))
1673 return false;
1674 if (!set_datatype_index(devinfo, &temp, src, is_immediate))
1675 return false;
1676 if (!set_subreg_index(devinfo, &temp, src, is_immediate))
1677 return false;
1678 if (!set_src0_index(devinfo, &temp, src))
1679 return false;
1680 if (!set_src1_index(devinfo, &temp, src, is_immediate, compacted_imm))
1681 return false;
1682
1683 if (devinfo->gen >= 12) {
1684 compact(swsb);
1685 compact_reg(dst);
1686 compact_reg(src0);
1687
1688 if (is_immediate) {
1689 /* src1 reg takes the high 8 bits (of the 12-bit compacted value) */
1690 brw_compact_inst_set_src1_reg_nr(devinfo, &temp, compacted_imm >> 4);
1691 } else {
1692 compact_reg(src1);
1693 }
1694 } else {
1695 if (devinfo->gen >= 6) {
1696 compact(acc_wr_control);
1697 } else {
1698 compact(mask_control_ex);
1699 }
1700
1701 if (devinfo->gen <= 6)
1702 compact(flag_subreg_nr);
1703
1704 compact(cond_modifier);
1705
1706 compact_reg(dst);
1707 compact_reg(src0);
1708
1709 if (is_immediate) {
1710 /* src1 reg takes the low 8 bits (of the 13-bit compacted value) */
1711 brw_compact_inst_set_src1_reg_nr(devinfo, &temp, compacted_imm & 0xff);
1712 } else {
1713 compact_reg(src1);
1714 }
1715 }
1716 brw_compact_inst_set_cmpt_control(devinfo, &temp, true);
1717
1718 #undef compact
1719 #undef compact_reg
1720
1721 *dst = temp;
1722
1723 return true;
1724 }
1725
1726 static void
1727 set_uncompacted_control(const struct gen_device_info *devinfo, brw_inst *dst,
1728 brw_compact_inst *src)
1729 {
1730 uint32_t uncompacted =
1731 control_index_table[brw_compact_inst_control_index(devinfo, src)];
1732
1733 if (devinfo->gen >= 12) {
1734 brw_inst_set_bits(dst, 95, 92, (uncompacted >> 17));
1735 brw_inst_set_bits(dst, 34, 34, (uncompacted >> 16) & 0x1);
1736 brw_inst_set_bits(dst, 33, 33, (uncompacted >> 15) & 0x1);
1737 brw_inst_set_bits(dst, 32, 32, (uncompacted >> 14) & 0x1);
1738 brw_inst_set_bits(dst, 31, 31, (uncompacted >> 13) & 0x1);
1739 brw_inst_set_bits(dst, 28, 28, (uncompacted >> 12) & 0x1);
1740 brw_inst_set_bits(dst, 27, 24, (uncompacted >> 8) & 0xf);
1741 brw_inst_set_bits(dst, 23, 22, (uncompacted >> 6) & 0x3);
1742 brw_inst_set_bits(dst, 21, 19, (uncompacted >> 3) & 0x7);
1743 brw_inst_set_bits(dst, 18, 16, (uncompacted >> 0) & 0x7);
1744 } else if (devinfo->gen >= 8) {
1745 brw_inst_set_bits(dst, 33, 31, (uncompacted >> 16));
1746 brw_inst_set_bits(dst, 23, 12, (uncompacted >> 4) & 0xfff);
1747 brw_inst_set_bits(dst, 10, 9, (uncompacted >> 2) & 0x3);
1748 brw_inst_set_bits(dst, 34, 34, (uncompacted >> 1) & 0x1);
1749 brw_inst_set_bits(dst, 8, 8, (uncompacted >> 0) & 0x1);
1750 } else {
1751 brw_inst_set_bits(dst, 31, 31, (uncompacted >> 16) & 0x1);
1752 brw_inst_set_bits(dst, 23, 8, (uncompacted & 0xffff));
1753
1754 if (devinfo->gen == 7)
1755 brw_inst_set_bits(dst, 90, 89, uncompacted >> 17);
1756 }
1757 }
1758
1759 static void
1760 set_uncompacted_datatype(const struct gen_device_info *devinfo, brw_inst *dst,
1761 brw_compact_inst *src)
1762 {
1763 uint32_t uncompacted =
1764 datatype_table[brw_compact_inst_datatype_index(devinfo, src)];
1765
1766 if (devinfo->gen >= 12) {
1767 brw_inst_set_bits(dst, 98, 98, (uncompacted >> 19));
1768 brw_inst_set_bits(dst, 91, 88, (uncompacted >> 15) & 0xf);
1769 brw_inst_set_bits(dst, 66, 66, (uncompacted >> 14) & 0x1);
1770 brw_inst_set_bits(dst, 50, 50, (uncompacted >> 13) & 0x1);
1771 brw_inst_set_bits(dst, 49, 48, (uncompacted >> 11) & 0x3);
1772 brw_inst_set_bits(dst, 47, 47, (uncompacted >> 10) & 0x1);
1773 brw_inst_set_bits(dst, 46, 46, (uncompacted >> 9) & 0x1);
1774 brw_inst_set_bits(dst, 43, 40, (uncompacted >> 5) & 0xf);
1775 brw_inst_set_bits(dst, 39, 36, (uncompacted >> 1) & 0xf);
1776 brw_inst_set_bits(dst, 35, 35, (uncompacted >> 0) & 0x1);
1777 } else if (devinfo->gen >= 8) {
1778 brw_inst_set_bits(dst, 63, 61, (uncompacted >> 18));
1779 brw_inst_set_bits(dst, 94, 89, (uncompacted >> 12) & 0x3f);
1780 brw_inst_set_bits(dst, 46, 35, (uncompacted >> 0) & 0xfff);
1781 } else {
1782 brw_inst_set_bits(dst, 63, 61, (uncompacted >> 15));
1783 brw_inst_set_bits(dst, 46, 32, (uncompacted & 0x7fff));
1784 }
1785 }
1786
1787 static void
1788 set_uncompacted_subreg(const struct gen_device_info *devinfo, brw_inst *dst,
1789 brw_compact_inst *src)
1790 {
1791 uint16_t uncompacted =
1792 subreg_table[brw_compact_inst_subreg_index(devinfo, src)];
1793
1794 if (devinfo->gen >= 12) {
1795 brw_inst_set_bits(dst, 103, 99, (uncompacted >> 10));
1796 brw_inst_set_bits(dst, 71, 67, (uncompacted >> 5) & 0x1f);
1797 brw_inst_set_bits(dst, 55, 51, (uncompacted >> 0) & 0x1f);
1798 } else {
1799 brw_inst_set_bits(dst, 100, 96, (uncompacted >> 10));
1800 brw_inst_set_bits(dst, 68, 64, (uncompacted >> 5) & 0x1f);
1801 brw_inst_set_bits(dst, 52, 48, (uncompacted >> 0) & 0x1f);
1802 }
1803 }
1804
1805 static void
1806 set_uncompacted_src0(const struct gen_device_info *devinfo, brw_inst *dst,
1807 brw_compact_inst *src)
1808 {
1809 uint32_t compacted = brw_compact_inst_src0_index(devinfo, src);
1810 uint16_t uncompacted = src0_index_table[compacted];
1811
1812 if (devinfo->gen >= 12) {
1813 brw_inst_set_bits(dst, 87, 84, (uncompacted >> 8));
1814 brw_inst_set_bits(dst, 83, 81, (uncompacted >> 5) & 0x7);
1815 brw_inst_set_bits(dst, 80, 80, (uncompacted >> 4) & 0x1);
1816 brw_inst_set_bits(dst, 65, 64, (uncompacted >> 2) & 0x3);
1817 brw_inst_set_bits(dst, 45, 44, (uncompacted >> 0) & 0x3);
1818 } else {
1819 brw_inst_set_bits(dst, 88, 77, uncompacted);
1820 }
1821 }
1822
1823 static void
1824 set_uncompacted_src1(const struct gen_device_info *devinfo, brw_inst *dst,
1825 brw_compact_inst *src)
1826 {
1827 uint16_t uncompacted =
1828 src1_index_table[brw_compact_inst_src1_index(devinfo, src)];
1829
1830 if (devinfo->gen >= 12) {
1831 brw_inst_set_bits(dst, 121, 120, (uncompacted >> 10));
1832 brw_inst_set_bits(dst, 119, 116, (uncompacted >> 6) & 0xf);
1833 brw_inst_set_bits(dst, 115, 113, (uncompacted >> 3) & 0x7);
1834 brw_inst_set_bits(dst, 112, 112, (uncompacted >> 2) & 0x1);
1835 brw_inst_set_bits(dst, 97, 96, (uncompacted >> 0) & 0x3);
1836 } else {
1837 brw_inst_set_bits(dst, 120, 109, uncompacted);
1838 }
1839 }
1840
1841 static void
1842 set_uncompacted_3src_control_index(const struct gen_device_info *devinfo,
1843 brw_inst *dst, brw_compact_inst *src)
1844 {
1845 assert(devinfo->gen >= 8);
1846
1847 if (devinfo->gen >= 12) {
1848 uint64_t compacted = brw_compact_inst_3src_control_index(devinfo, src);
1849 uint64_t uncompacted = gen12_3src_control_index_table[compacted];
1850
1851 brw_inst_set_bits(dst, 95, 92, (uncompacted >> 32));
1852 brw_inst_set_bits(dst, 90, 88, (uncompacted >> 29) & 0x7);
1853 brw_inst_set_bits(dst, 82, 80, (uncompacted >> 26) & 0x7);
1854 brw_inst_set_bits(dst, 50, 50, (uncompacted >> 25) & 0x1);
1855 brw_inst_set_bits(dst, 48, 48, (uncompacted >> 24) & 0x1);
1856 brw_inst_set_bits(dst, 42, 40, (uncompacted >> 21) & 0x7);
1857 brw_inst_set_bits(dst, 39, 39, (uncompacted >> 20) & 0x1);
1858 brw_inst_set_bits(dst, 38, 36, (uncompacted >> 17) & 0x7);
1859 brw_inst_set_bits(dst, 34, 34, (uncompacted >> 16) & 0x1);
1860 brw_inst_set_bits(dst, 33, 33, (uncompacted >> 15) & 0x1);
1861 brw_inst_set_bits(dst, 32, 32, (uncompacted >> 14) & 0x1);
1862 brw_inst_set_bits(dst, 31, 31, (uncompacted >> 13) & 0x1);
1863 brw_inst_set_bits(dst, 28, 28, (uncompacted >> 12) & 0x1);
1864 brw_inst_set_bits(dst, 27, 24, (uncompacted >> 8) & 0xf);
1865 brw_inst_set_bits(dst, 23, 23, (uncompacted >> 7) & 0x1);
1866 brw_inst_set_bits(dst, 22, 22, (uncompacted >> 6) & 0x1);
1867 brw_inst_set_bits(dst, 21, 19, (uncompacted >> 3) & 0x7);
1868 brw_inst_set_bits(dst, 18, 16, (uncompacted >> 0) & 0x7);
1869 } else {
1870 uint32_t compacted = brw_compact_inst_3src_control_index(devinfo, src);
1871 uint32_t uncompacted = gen8_3src_control_index_table[compacted];
1872
1873 brw_inst_set_bits(dst, 34, 32, (uncompacted >> 21) & 0x7);
1874 brw_inst_set_bits(dst, 28, 8, (uncompacted >> 0) & 0x1fffff);
1875
1876 if (devinfo->gen >= 9 || devinfo->is_cherryview)
1877 brw_inst_set_bits(dst, 36, 35, (uncompacted >> 24) & 0x3);
1878 }
1879 }
1880
1881 static void
1882 set_uncompacted_3src_source_index(const struct gen_device_info *devinfo,
1883 brw_inst *dst, brw_compact_inst *src)
1884 {
1885 assert(devinfo->gen >= 8);
1886
1887 uint32_t compacted = brw_compact_inst_3src_source_index(devinfo, src);
1888
1889 if (devinfo->gen >= 12) {
1890 uint32_t uncompacted = gen12_3src_source_index_table[compacted];
1891
1892 brw_inst_set_bits(dst, 114, 114, (uncompacted >> 20));
1893 brw_inst_set_bits(dst, 113, 112, (uncompacted >> 18) & 0x3);
1894 brw_inst_set_bits(dst, 98, 98, (uncompacted >> 17) & 0x1);
1895 brw_inst_set_bits(dst, 97, 96, (uncompacted >> 15) & 0x3);
1896 brw_inst_set_bits(dst, 91, 91, (uncompacted >> 14) & 0x1);
1897 brw_inst_set_bits(dst, 87, 86, (uncompacted >> 12) & 0x3);
1898 brw_inst_set_bits(dst, 85, 84, (uncompacted >> 10) & 0x3);
1899 brw_inst_set_bits(dst, 83, 83, (uncompacted >> 9) & 0x1);
1900 brw_inst_set_bits(dst, 66, 66, (uncompacted >> 8) & 0x1);
1901 brw_inst_set_bits(dst, 65, 64, (uncompacted >> 6) & 0x3);
1902 brw_inst_set_bits(dst, 47, 47, (uncompacted >> 5) & 0x1);
1903 brw_inst_set_bits(dst, 46, 46, (uncompacted >> 4) & 0x1);
1904 brw_inst_set_bits(dst, 45, 44, (uncompacted >> 2) & 0x3);
1905 brw_inst_set_bits(dst, 43, 43, (uncompacted >> 1) & 0x1);
1906 brw_inst_set_bits(dst, 35, 35, (uncompacted >> 0) & 0x1);
1907 } else {
1908 uint64_t uncompacted = gen8_3src_source_index_table[compacted];
1909
1910 brw_inst_set_bits(dst, 83, 83, (uncompacted >> 43) & 0x1);
1911 brw_inst_set_bits(dst, 114, 107, (uncompacted >> 35) & 0xff);
1912 brw_inst_set_bits(dst, 93, 86, (uncompacted >> 27) & 0xff);
1913 brw_inst_set_bits(dst, 72, 65, (uncompacted >> 19) & 0xff);
1914 brw_inst_set_bits(dst, 55, 37, (uncompacted >> 0) & 0x7ffff);
1915
1916 if (devinfo->gen >= 9 || devinfo->is_cherryview) {
1917 brw_inst_set_bits(dst, 126, 125, (uncompacted >> 47) & 0x3);
1918 brw_inst_set_bits(dst, 105, 104, (uncompacted >> 45) & 0x3);
1919 brw_inst_set_bits(dst, 84, 84, (uncompacted >> 44) & 0x1);
1920 } else {
1921 brw_inst_set_bits(dst, 125, 125, (uncompacted >> 45) & 0x1);
1922 brw_inst_set_bits(dst, 104, 104, (uncompacted >> 44) & 0x1);
1923 }
1924 }
1925 }
1926
1927 static void
1928 set_uncompacted_3src_subreg_index(const struct gen_device_info *devinfo,
1929 brw_inst *dst, brw_compact_inst *src)
1930 {
1931 assert(devinfo->gen >= 12);
1932
1933 uint32_t compacted = brw_compact_inst_3src_subreg_index(devinfo, src);
1934 uint32_t uncompacted = gen12_3src_subreg_table[compacted];
1935
1936 brw_inst_set_bits(dst, 119, 115, (uncompacted >> 15));
1937 brw_inst_set_bits(dst, 103, 99, (uncompacted >> 10) & 0x1f);
1938 brw_inst_set_bits(dst, 71, 67, (uncompacted >> 5) & 0x1f);
1939 brw_inst_set_bits(dst, 55, 51, (uncompacted >> 0) & 0x1f);
1940 }
1941
1942 static void
1943 brw_uncompact_3src_instruction(const struct gen_device_info *devinfo,
1944 brw_inst *dst, brw_compact_inst *src)
1945 {
1946 assert(devinfo->gen >= 8);
1947
1948 #define uncompact(field) \
1949 brw_inst_set_3src_##field(devinfo, dst, brw_compact_inst_3src_##field(devinfo, src))
1950 #define uncompact_a16(field) \
1951 brw_inst_set_3src_a16_##field(devinfo, dst, brw_compact_inst_3src_##field(devinfo, src))
1952
1953 uncompact(hw_opcode);
1954
1955 if (devinfo->gen >= 12) {
1956 set_uncompacted_3src_control_index(devinfo, dst, src);
1957 set_uncompacted_3src_source_index(devinfo, dst, src);
1958 set_uncompacted_3src_subreg_index(devinfo, dst, src);
1959
1960 uncompact(debug_control);
1961 uncompact(swsb);
1962 uncompact(dst_reg_nr);
1963 uncompact(src0_reg_nr);
1964 uncompact(src1_reg_nr);
1965 uncompact(src2_reg_nr);
1966 } else {
1967 set_uncompacted_3src_control_index(devinfo, dst, src);
1968 set_uncompacted_3src_source_index(devinfo, dst, src);
1969
1970 uncompact(dst_reg_nr);
1971 uncompact_a16(src0_rep_ctrl);
1972 uncompact(debug_control);
1973 uncompact(saturate);
1974 uncompact_a16(src1_rep_ctrl);
1975 uncompact_a16(src2_rep_ctrl);
1976 uncompact(src0_reg_nr);
1977 uncompact(src1_reg_nr);
1978 uncompact(src2_reg_nr);
1979 uncompact_a16(src0_subreg_nr);
1980 uncompact_a16(src1_subreg_nr);
1981 uncompact_a16(src2_subreg_nr);
1982 }
1983 brw_inst_set_3src_cmpt_control(devinfo, dst, false);
1984
1985 #undef uncompact
1986 #undef uncompact_a16
1987 }
1988
1989 void
1990 brw_uncompact_instruction(const struct gen_device_info *devinfo, brw_inst *dst,
1991 brw_compact_inst *src)
1992 {
1993 memset(dst, 0, sizeof(*dst));
1994
1995 if (devinfo->gen >= 8 &&
1996 is_3src(devinfo, brw_opcode_decode(
1997 devinfo, brw_compact_inst_3src_hw_opcode(devinfo, src)))) {
1998 brw_uncompact_3src_instruction(devinfo, dst, src);
1999 return;
2000 }
2001
2002 #define uncompact(field) \
2003 brw_inst_set_##field(devinfo, dst, brw_compact_inst_##field(devinfo, src))
2004 #define uncompact_reg(field) \
2005 brw_inst_set_##field##_da_reg_nr(devinfo, dst, \
2006 brw_compact_inst_##field##_reg_nr(devinfo, src))
2007
2008 uncompact(hw_opcode);
2009 uncompact(debug_control);
2010
2011 set_uncompacted_control(devinfo, dst, src);
2012 set_uncompacted_datatype(devinfo, dst, src);
2013 set_uncompacted_subreg(devinfo, dst, src);
2014 set_uncompacted_src0(devinfo, dst, src);
2015
2016 enum brw_reg_type type;
2017 if (has_immediate(devinfo, dst, &type)) {
2018 unsigned imm = uncompact_immediate(devinfo, type,
2019 brw_compact_inst_imm(devinfo, src));
2020 brw_inst_set_imm_ud(devinfo, dst, imm);
2021 } else {
2022 set_uncompacted_src1(devinfo, dst, src);
2023 uncompact_reg(src1);
2024 }
2025
2026 if (devinfo->gen >= 12) {
2027 uncompact(swsb);
2028 uncompact_reg(dst);
2029 uncompact_reg(src0);
2030 } else {
2031 if (devinfo->gen >= 6) {
2032 uncompact(acc_wr_control);
2033 } else {
2034 uncompact(mask_control_ex);
2035 }
2036
2037 uncompact(cond_modifier);
2038
2039 if (devinfo->gen <= 6)
2040 uncompact(flag_subreg_nr);
2041
2042 uncompact_reg(dst);
2043 uncompact_reg(src0);
2044 }
2045 brw_inst_set_cmpt_control(devinfo, dst, false);
2046
2047 #undef uncompact
2048 #undef uncompact_reg
2049 }
2050
2051 void brw_debug_compact_uncompact(const struct gen_device_info *devinfo,
2052 brw_inst *orig,
2053 brw_inst *uncompacted)
2054 {
2055 fprintf(stderr, "Instruction compact/uncompact changed (gen%d):\n",
2056 devinfo->gen);
2057
2058 fprintf(stderr, " before: ");
2059 brw_disassemble_inst(stderr, devinfo, orig, true);
2060
2061 fprintf(stderr, " after: ");
2062 brw_disassemble_inst(stderr, devinfo, uncompacted, false);
2063
2064 uint32_t *before_bits = (uint32_t *)orig;
2065 uint32_t *after_bits = (uint32_t *)uncompacted;
2066 fprintf(stderr, " changed bits:\n");
2067 for (int i = 0; i < 128; i++) {
2068 uint32_t before = before_bits[i / 32] & (1 << (i & 31));
2069 uint32_t after = after_bits[i / 32] & (1 << (i & 31));
2070
2071 if (before != after) {
2072 fprintf(stderr, " bit %d, %s to %s\n", i,
2073 before ? "set" : "unset",
2074 after ? "set" : "unset");
2075 }
2076 }
2077 }
2078
2079 static int
2080 compacted_between(int old_ip, int old_target_ip, int *compacted_counts)
2081 {
2082 int this_compacted_count = compacted_counts[old_ip];
2083 int target_compacted_count = compacted_counts[old_target_ip];
2084 return target_compacted_count - this_compacted_count;
2085 }
2086
2087 static void
2088 update_uip_jip(const struct gen_device_info *devinfo, brw_inst *insn,
2089 int this_old_ip, int *compacted_counts)
2090 {
2091 /* JIP and UIP are in units of:
2092 * - bytes on Gen8+; and
2093 * - compacted instructions on Gen6+.
2094 */
2095 int shift = devinfo->gen >= 8 ? 3 : 0;
2096
2097 int32_t jip_compacted = brw_inst_jip(devinfo, insn) >> shift;
2098 jip_compacted -= compacted_between(this_old_ip,
2099 this_old_ip + (jip_compacted / 2),
2100 compacted_counts);
2101 brw_inst_set_jip(devinfo, insn, jip_compacted << shift);
2102
2103 if (brw_inst_opcode(devinfo, insn) == BRW_OPCODE_ENDIF ||
2104 brw_inst_opcode(devinfo, insn) == BRW_OPCODE_WHILE ||
2105 (brw_inst_opcode(devinfo, insn) == BRW_OPCODE_ELSE && devinfo->gen <= 7))
2106 return;
2107
2108 int32_t uip_compacted = brw_inst_uip(devinfo, insn) >> shift;
2109 uip_compacted -= compacted_between(this_old_ip,
2110 this_old_ip + (uip_compacted / 2),
2111 compacted_counts);
2112 brw_inst_set_uip(devinfo, insn, uip_compacted << shift);
2113 }
2114
2115 static void
2116 update_gen4_jump_count(const struct gen_device_info *devinfo, brw_inst *insn,
2117 int this_old_ip, int *compacted_counts)
2118 {
2119 assert(devinfo->gen == 5 || devinfo->is_g4x);
2120
2121 /* Jump Count is in units of:
2122 * - uncompacted instructions on G45; and
2123 * - compacted instructions on Gen5.
2124 */
2125 int shift = devinfo->is_g4x ? 1 : 0;
2126
2127 int jump_count_compacted = brw_inst_gen4_jump_count(devinfo, insn) << shift;
2128
2129 int target_old_ip = this_old_ip + (jump_count_compacted / 2);
2130
2131 int this_compacted_count = compacted_counts[this_old_ip];
2132 int target_compacted_count = compacted_counts[target_old_ip];
2133
2134 jump_count_compacted -= (target_compacted_count - this_compacted_count);
2135 brw_inst_set_gen4_jump_count(devinfo, insn, jump_count_compacted >> shift);
2136 }
2137
2138 void
2139 brw_init_compaction_tables(const struct gen_device_info *devinfo)
2140 {
2141 assert(g45_control_index_table[ARRAY_SIZE(g45_control_index_table) - 1] != 0);
2142 assert(g45_datatype_table[ARRAY_SIZE(g45_datatype_table) - 1] != 0);
2143 assert(g45_subreg_table[ARRAY_SIZE(g45_subreg_table) - 1] != 0);
2144 assert(g45_src_index_table[ARRAY_SIZE(g45_src_index_table) - 1] != 0);
2145 assert(gen6_control_index_table[ARRAY_SIZE(gen6_control_index_table) - 1] != 0);
2146 assert(gen6_datatype_table[ARRAY_SIZE(gen6_datatype_table) - 1] != 0);
2147 assert(gen6_subreg_table[ARRAY_SIZE(gen6_subreg_table) - 1] != 0);
2148 assert(gen6_src_index_table[ARRAY_SIZE(gen6_src_index_table) - 1] != 0);
2149 assert(gen7_control_index_table[ARRAY_SIZE(gen7_control_index_table) - 1] != 0);
2150 assert(gen7_datatype_table[ARRAY_SIZE(gen7_datatype_table) - 1] != 0);
2151 assert(gen7_subreg_table[ARRAY_SIZE(gen7_subreg_table) - 1] != 0);
2152 assert(gen7_src_index_table[ARRAY_SIZE(gen7_src_index_table) - 1] != 0);
2153 assert(gen8_control_index_table[ARRAY_SIZE(gen8_control_index_table) - 1] != 0);
2154 assert(gen8_datatype_table[ARRAY_SIZE(gen8_datatype_table) - 1] != 0);
2155 assert(gen8_subreg_table[ARRAY_SIZE(gen8_subreg_table) - 1] != 0);
2156 assert(gen8_src_index_table[ARRAY_SIZE(gen8_src_index_table) - 1] != 0);
2157 assert(gen11_datatype_table[ARRAY_SIZE(gen11_datatype_table) - 1] != 0);
2158 assert(gen12_control_index_table[ARRAY_SIZE(gen12_control_index_table) - 1] != 0);
2159 assert(gen12_datatype_table[ARRAY_SIZE(gen12_datatype_table) - 1] != 0);
2160 assert(gen12_subreg_table[ARRAY_SIZE(gen12_subreg_table) - 1] != 0);
2161 assert(gen12_src0_index_table[ARRAY_SIZE(gen12_src0_index_table) - 1] != 0);
2162 assert(gen12_src1_index_table[ARRAY_SIZE(gen12_src1_index_table) - 1] != 0);
2163
2164 switch (devinfo->gen) {
2165 case 12:
2166 control_index_table = gen12_control_index_table;;
2167 datatype_table = gen12_datatype_table;
2168 subreg_table = gen12_subreg_table;
2169 src0_index_table = gen12_src0_index_table;
2170 src1_index_table = gen12_src1_index_table;
2171 break;
2172 case 11:
2173 control_index_table = gen8_control_index_table;
2174 datatype_table = gen11_datatype_table;
2175 subreg_table = gen8_subreg_table;
2176 src0_index_table = gen8_src_index_table;
2177 src1_index_table = gen8_src_index_table;
2178 break;
2179 case 10:
2180 case 9:
2181 case 8:
2182 control_index_table = gen8_control_index_table;
2183 datatype_table = gen8_datatype_table;
2184 subreg_table = gen8_subreg_table;
2185 src0_index_table = gen8_src_index_table;
2186 src1_index_table = gen8_src_index_table;
2187 break;
2188 case 7:
2189 control_index_table = gen7_control_index_table;
2190 datatype_table = gen7_datatype_table;
2191 subreg_table = gen7_subreg_table;
2192 src0_index_table = gen7_src_index_table;
2193 src1_index_table = gen7_src_index_table;
2194 break;
2195 case 6:
2196 control_index_table = gen6_control_index_table;
2197 datatype_table = gen6_datatype_table;
2198 subreg_table = gen6_subreg_table;
2199 src0_index_table = gen6_src_index_table;
2200 src1_index_table = gen6_src_index_table;
2201 break;
2202 case 5:
2203 case 4:
2204 control_index_table = g45_control_index_table;
2205 datatype_table = g45_datatype_table;
2206 subreg_table = g45_subreg_table;
2207 src0_index_table = g45_src_index_table;
2208 src1_index_table = g45_src_index_table;
2209 break;
2210 default:
2211 unreachable("unknown generation");
2212 }
2213 }
2214
2215 void
2216 brw_compact_instructions(struct brw_codegen *p, int start_offset,
2217 struct disasm_info *disasm)
2218 {
2219 if (unlikely(INTEL_DEBUG & DEBUG_NO_COMPACTION))
2220 return;
2221
2222 const struct gen_device_info *devinfo = p->devinfo;
2223 void *store = p->store + start_offset / 16;
2224 /* For an instruction at byte offset 16*i before compaction, this is the
2225 * number of compacted instructions minus the number of padding NOP/NENOPs
2226 * that preceded it.
2227 */
2228 int compacted_counts[(p->next_insn_offset - start_offset) / sizeof(brw_inst)];
2229 /* For an instruction at byte offset 8*i after compaction, this was its IP
2230 * (in 16-byte units) before compaction.
2231 */
2232 int old_ip[(p->next_insn_offset - start_offset) / sizeof(brw_compact_inst) + 1];
2233
2234 if (devinfo->gen == 4 && !devinfo->is_g4x)
2235 return;
2236
2237 int offset = 0;
2238 int compacted_count = 0;
2239 for (int src_offset = 0; src_offset < p->next_insn_offset - start_offset;
2240 src_offset += sizeof(brw_inst)) {
2241 brw_inst *src = store + src_offset;
2242 void *dst = store + offset;
2243
2244 old_ip[offset / sizeof(brw_compact_inst)] = src_offset / sizeof(brw_inst);
2245 compacted_counts[src_offset / sizeof(brw_inst)] = compacted_count;
2246
2247 brw_inst inst = precompact(devinfo, *src);
2248 brw_inst saved = inst;
2249
2250 if (brw_try_compact_instruction(devinfo, dst, &inst)) {
2251 compacted_count++;
2252
2253 if (INTEL_DEBUG) {
2254 brw_inst uncompacted;
2255 brw_uncompact_instruction(devinfo, &uncompacted, dst);
2256 if (memcmp(&saved, &uncompacted, sizeof(uncompacted))) {
2257 brw_debug_compact_uncompact(devinfo, &saved, &uncompacted);
2258 }
2259 }
2260
2261 offset += sizeof(brw_compact_inst);
2262 } else {
2263 /* All uncompacted instructions need to be aligned on G45. */
2264 if ((offset & sizeof(brw_compact_inst)) != 0 && devinfo->is_g4x){
2265 brw_compact_inst *align = store + offset;
2266 memset(align, 0, sizeof(*align));
2267 brw_compact_inst_set_hw_opcode(
2268 devinfo, align, brw_opcode_encode(devinfo, BRW_OPCODE_NENOP));
2269 brw_compact_inst_set_cmpt_control(devinfo, align, true);
2270 offset += sizeof(brw_compact_inst);
2271 compacted_count--;
2272 compacted_counts[src_offset / sizeof(brw_inst)] = compacted_count;
2273 old_ip[offset / sizeof(brw_compact_inst)] = src_offset / sizeof(brw_inst);
2274
2275 dst = store + offset;
2276 }
2277
2278 /* If we didn't compact this intruction, we need to move it down into
2279 * place.
2280 */
2281 if (offset != src_offset) {
2282 memmove(dst, src, sizeof(brw_inst));
2283 }
2284 offset += sizeof(brw_inst);
2285 }
2286 }
2287
2288 /* Add an entry for the ending offset of the program. This greatly
2289 * simplifies the linked list walk at the end of the function.
2290 */
2291 old_ip[offset / sizeof(brw_compact_inst)] =
2292 (p->next_insn_offset - start_offset) / sizeof(brw_inst);
2293
2294 /* Fix up control flow offsets. */
2295 p->next_insn_offset = start_offset + offset;
2296 for (offset = 0; offset < p->next_insn_offset - start_offset;
2297 offset = next_offset(devinfo, store, offset)) {
2298 brw_inst *insn = store + offset;
2299 int this_old_ip = old_ip[offset / sizeof(brw_compact_inst)];
2300 int this_compacted_count = compacted_counts[this_old_ip];
2301
2302 switch (brw_inst_opcode(devinfo, insn)) {
2303 case BRW_OPCODE_BREAK:
2304 case BRW_OPCODE_CONTINUE:
2305 case BRW_OPCODE_HALT:
2306 if (devinfo->gen >= 6) {
2307 update_uip_jip(devinfo, insn, this_old_ip, compacted_counts);
2308 } else {
2309 update_gen4_jump_count(devinfo, insn, this_old_ip,
2310 compacted_counts);
2311 }
2312 break;
2313
2314 case BRW_OPCODE_IF:
2315 case BRW_OPCODE_IFF:
2316 case BRW_OPCODE_ELSE:
2317 case BRW_OPCODE_ENDIF:
2318 case BRW_OPCODE_WHILE:
2319 if (devinfo->gen >= 7) {
2320 if (brw_inst_cmpt_control(devinfo, insn)) {
2321 brw_inst uncompacted;
2322 brw_uncompact_instruction(devinfo, &uncompacted,
2323 (brw_compact_inst *)insn);
2324
2325 update_uip_jip(devinfo, &uncompacted, this_old_ip,
2326 compacted_counts);
2327
2328 bool ret = brw_try_compact_instruction(devinfo,
2329 (brw_compact_inst *)insn,
2330 &uncompacted);
2331 assert(ret); (void)ret;
2332 } else {
2333 update_uip_jip(devinfo, insn, this_old_ip, compacted_counts);
2334 }
2335 } else if (devinfo->gen == 6) {
2336 assert(!brw_inst_cmpt_control(devinfo, insn));
2337
2338 /* Jump Count is in units of compacted instructions on Gen6. */
2339 int jump_count_compacted = brw_inst_gen6_jump_count(devinfo, insn);
2340
2341 int target_old_ip = this_old_ip + (jump_count_compacted / 2);
2342 int target_compacted_count = compacted_counts[target_old_ip];
2343 jump_count_compacted -= (target_compacted_count - this_compacted_count);
2344 brw_inst_set_gen6_jump_count(devinfo, insn, jump_count_compacted);
2345 } else {
2346 update_gen4_jump_count(devinfo, insn, this_old_ip,
2347 compacted_counts);
2348 }
2349 break;
2350
2351 case BRW_OPCODE_ADD:
2352 /* Add instructions modifying the IP register use an immediate src1,
2353 * and Gens that use this cannot compact instructions with immediate
2354 * operands.
2355 */
2356 if (brw_inst_cmpt_control(devinfo, insn))
2357 break;
2358
2359 if (brw_inst_dst_reg_file(devinfo, insn) == BRW_ARCHITECTURE_REGISTER_FILE &&
2360 brw_inst_dst_da_reg_nr(devinfo, insn) == BRW_ARF_IP) {
2361 assert(brw_inst_src1_reg_file(devinfo, insn) == BRW_IMMEDIATE_VALUE);
2362
2363 int shift = 3;
2364 int jump_compacted = brw_inst_imm_d(devinfo, insn) >> shift;
2365
2366 int target_old_ip = this_old_ip + (jump_compacted / 2);
2367 int target_compacted_count = compacted_counts[target_old_ip];
2368 jump_compacted -= (target_compacted_count - this_compacted_count);
2369 brw_inst_set_imm_ud(devinfo, insn, jump_compacted << shift);
2370 }
2371 break;
2372
2373 default:
2374 break;
2375 }
2376 }
2377
2378 /* p->nr_insn is counting the number of uncompacted instructions still, so
2379 * divide. We do want to be sure there's a valid instruction in any
2380 * alignment padding, so that the next compression pass (for the FS 8/16
2381 * compile passes) parses correctly.
2382 */
2383 if (p->next_insn_offset & sizeof(brw_compact_inst)) {
2384 brw_compact_inst *align = store + offset;
2385 memset(align, 0, sizeof(*align));
2386 brw_compact_inst_set_hw_opcode(
2387 devinfo, align, brw_opcode_encode(devinfo, BRW_OPCODE_NOP));
2388 brw_compact_inst_set_cmpt_control(devinfo, align, true);
2389 p->next_insn_offset += sizeof(brw_compact_inst);
2390 }
2391 p->nr_insn = p->next_insn_offset / sizeof(brw_inst);
2392
2393 /* Update the instruction offsets for each group. */
2394 if (disasm) {
2395 int offset = 0;
2396
2397 foreach_list_typed(struct inst_group, group, link, &disasm->group_list) {
2398 while (start_offset + old_ip[offset / sizeof(brw_compact_inst)] *
2399 sizeof(brw_inst) != group->offset) {
2400 assert(start_offset + old_ip[offset / sizeof(brw_compact_inst)] *
2401 sizeof(brw_inst) < group->offset);
2402 offset = next_offset(devinfo, store, offset);
2403 }
2404
2405 group->offset = start_offset + offset;
2406
2407 offset = next_offset(devinfo, store, offset);
2408 }
2409 }
2410 }