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intel/fs: Remove FS_OPCODE_UNPACK_HALF_2x16_SPLIT opcodes.
[mesa.git] / src / intel / compiler / brw_eu_defines.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32 #ifndef BRW_EU_DEFINES_H
33 #define BRW_EU_DEFINES_H
34
35 #include "util/macros.h"
36
37 /* The following hunk, up-to "Execution Unit" is used by both the
38 * intel/compiler and i965 codebase. */
39
40 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
41 /* Using the GNU statement expression extension */
42 #define SET_FIELD(value, field) \
43 ({ \
44 uint32_t fieldval = (value) << field ## _SHIFT; \
45 assert((fieldval & ~ field ## _MASK) == 0); \
46 fieldval & field ## _MASK; \
47 })
48
49 #define SET_BITS(value, high, low) \
50 ({ \
51 const uint32_t fieldval = (value) << (low); \
52 assert((fieldval & ~INTEL_MASK(high, low)) == 0); \
53 fieldval & INTEL_MASK(high, low); \
54 })
55
56 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
57 #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)
58
59 #define _3DPRIM_POINTLIST 0x01
60 #define _3DPRIM_LINELIST 0x02
61 #define _3DPRIM_LINESTRIP 0x03
62 #define _3DPRIM_TRILIST 0x04
63 #define _3DPRIM_TRISTRIP 0x05
64 #define _3DPRIM_TRIFAN 0x06
65 #define _3DPRIM_QUADLIST 0x07
66 #define _3DPRIM_QUADSTRIP 0x08
67 #define _3DPRIM_LINELIST_ADJ 0x09 /* G45+ */
68 #define _3DPRIM_LINESTRIP_ADJ 0x0A /* G45+ */
69 #define _3DPRIM_TRILIST_ADJ 0x0B /* G45+ */
70 #define _3DPRIM_TRISTRIP_ADJ 0x0C /* G45+ */
71 #define _3DPRIM_TRISTRIP_REVERSE 0x0D
72 #define _3DPRIM_POLYGON 0x0E
73 #define _3DPRIM_RECTLIST 0x0F
74 #define _3DPRIM_LINELOOP 0x10
75 #define _3DPRIM_POINTLIST_BF 0x11
76 #define _3DPRIM_LINESTRIP_CONT 0x12
77 #define _3DPRIM_LINESTRIP_BF 0x13
78 #define _3DPRIM_LINESTRIP_CONT_BF 0x14
79 #define _3DPRIM_TRIFAN_NOSTIPPLE 0x16
80 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); })
81
82 /* Bitfields for the URB_WRITE message, DW2 of message header: */
83 #define URB_WRITE_PRIM_END 0x1
84 #define URB_WRITE_PRIM_START 0x2
85 #define URB_WRITE_PRIM_TYPE_SHIFT 2
86
87 #define BRW_SPRITE_POINT_ENABLE 16
88
89 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT 0
90 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID 1
91
92 /* Execution Unit (EU) defines
93 */
94
95 #define BRW_ALIGN_1 0
96 #define BRW_ALIGN_16 1
97
98 #define BRW_ADDRESS_DIRECT 0
99 #define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1
100
101 #define BRW_CHANNEL_X 0
102 #define BRW_CHANNEL_Y 1
103 #define BRW_CHANNEL_Z 2
104 #define BRW_CHANNEL_W 3
105
106 enum brw_compression {
107 BRW_COMPRESSION_NONE = 0,
108 BRW_COMPRESSION_2NDHALF = 1,
109 BRW_COMPRESSION_COMPRESSED = 2,
110 };
111
112 #define GEN6_COMPRESSION_1Q 0
113 #define GEN6_COMPRESSION_2Q 1
114 #define GEN6_COMPRESSION_3Q 2
115 #define GEN6_COMPRESSION_4Q 3
116 #define GEN6_COMPRESSION_1H 0
117 #define GEN6_COMPRESSION_2H 2
118
119 enum PACKED brw_conditional_mod {
120 BRW_CONDITIONAL_NONE = 0,
121 BRW_CONDITIONAL_Z = 1,
122 BRW_CONDITIONAL_NZ = 2,
123 BRW_CONDITIONAL_EQ = 1, /* Z */
124 BRW_CONDITIONAL_NEQ = 2, /* NZ */
125 BRW_CONDITIONAL_G = 3,
126 BRW_CONDITIONAL_GE = 4,
127 BRW_CONDITIONAL_L = 5,
128 BRW_CONDITIONAL_LE = 6,
129 BRW_CONDITIONAL_R = 7, /* Gen <= 5 */
130 BRW_CONDITIONAL_O = 8,
131 BRW_CONDITIONAL_U = 9,
132 };
133
134 #define BRW_DEBUG_NONE 0
135 #define BRW_DEBUG_BREAKPOINT 1
136
137 #define BRW_DEPENDENCY_NORMAL 0
138 #define BRW_DEPENDENCY_NOTCLEARED 1
139 #define BRW_DEPENDENCY_NOTCHECKED 2
140 #define BRW_DEPENDENCY_DISABLE 3
141
142 enum PACKED brw_execution_size {
143 BRW_EXECUTE_1 = 0,
144 BRW_EXECUTE_2 = 1,
145 BRW_EXECUTE_4 = 2,
146 BRW_EXECUTE_8 = 3,
147 BRW_EXECUTE_16 = 4,
148 BRW_EXECUTE_32 = 5,
149 };
150
151 enum PACKED brw_horizontal_stride {
152 BRW_HORIZONTAL_STRIDE_0 = 0,
153 BRW_HORIZONTAL_STRIDE_1 = 1,
154 BRW_HORIZONTAL_STRIDE_2 = 2,
155 BRW_HORIZONTAL_STRIDE_4 = 3,
156 };
157
158 enum PACKED gen10_align1_3src_src_horizontal_stride {
159 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 = 0,
160 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1 = 1,
161 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2 = 2,
162 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4 = 3,
163 };
164
165 enum PACKED gen10_align1_3src_dst_horizontal_stride {
166 BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1 = 0,
167 BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_2 = 1,
168 };
169
170 #define BRW_INSTRUCTION_NORMAL 0
171 #define BRW_INSTRUCTION_SATURATE 1
172
173 #define BRW_MASK_ENABLE 0
174 #define BRW_MASK_DISABLE 1
175
176 /** @{
177 *
178 * Gen6 has replaced "mask enable/disable" with WECtrl, which is
179 * effectively the same but much simpler to think about. Now, there
180 * are two contributors ANDed together to whether channels are
181 * executed: The predication on the instruction, and the channel write
182 * enable.
183 */
184 /**
185 * This is the default value. It means that a channel's write enable is set
186 * if the per-channel IP is pointing at this instruction.
187 */
188 #define BRW_WE_NORMAL 0
189 /**
190 * This is used like BRW_MASK_DISABLE, and causes all channels to have
191 * their write enable set. Note that predication still contributes to
192 * whether the channel actually gets written.
193 */
194 #define BRW_WE_ALL 1
195 /** @} */
196
197 enum opcode {
198 /* These are the actual hardware opcodes. */
199 BRW_OPCODE_ILLEGAL = 0,
200 BRW_OPCODE_MOV = 1,
201 BRW_OPCODE_SEL = 2,
202 BRW_OPCODE_MOVI = 3, /**< G45+ */
203 BRW_OPCODE_NOT = 4,
204 BRW_OPCODE_AND = 5,
205 BRW_OPCODE_OR = 6,
206 BRW_OPCODE_XOR = 7,
207 BRW_OPCODE_SHR = 8,
208 BRW_OPCODE_SHL = 9,
209 BRW_OPCODE_DIM = 10, /**< Gen7.5 only */ /* Reused */
210 BRW_OPCODE_SMOV = 10, /**< Gen8+ */ /* Reused */
211 /* Reserved - 11 */
212 BRW_OPCODE_ASR = 12,
213 /* Reserved - 13-15 */
214 BRW_OPCODE_CMP = 16,
215 BRW_OPCODE_CMPN = 17,
216 BRW_OPCODE_CSEL = 18, /**< Gen8+ */
217 BRW_OPCODE_F32TO16 = 19, /**< Gen7 only */
218 BRW_OPCODE_F16TO32 = 20, /**< Gen7 only */
219 /* Reserved - 21-22 */
220 BRW_OPCODE_BFREV = 23, /**< Gen7+ */
221 BRW_OPCODE_BFE = 24, /**< Gen7+ */
222 BRW_OPCODE_BFI1 = 25, /**< Gen7+ */
223 BRW_OPCODE_BFI2 = 26, /**< Gen7+ */
224 /* Reserved - 27-31 */
225 BRW_OPCODE_JMPI = 32,
226 BRW_OPCODE_BRD = 33, /**< Gen7+ */
227 BRW_OPCODE_IF = 34,
228 BRW_OPCODE_IFF = 35, /**< Pre-Gen6 */ /* Reused */
229 BRW_OPCODE_BRC = 35, /**< Gen7+ */ /* Reused */
230 BRW_OPCODE_ELSE = 36,
231 BRW_OPCODE_ENDIF = 37,
232 BRW_OPCODE_DO = 38, /**< Pre-Gen6 */ /* Reused */
233 BRW_OPCODE_CASE = 38, /**< Gen6 only */ /* Reused */
234 BRW_OPCODE_WHILE = 39,
235 BRW_OPCODE_BREAK = 40,
236 BRW_OPCODE_CONTINUE = 41,
237 BRW_OPCODE_HALT = 42,
238 BRW_OPCODE_CALLA = 43, /**< Gen7.5+ */
239 BRW_OPCODE_MSAVE = 44, /**< Pre-Gen6 */ /* Reused */
240 BRW_OPCODE_CALL = 44, /**< Gen6+ */ /* Reused */
241 BRW_OPCODE_MREST = 45, /**< Pre-Gen6 */ /* Reused */
242 BRW_OPCODE_RET = 45, /**< Gen6+ */ /* Reused */
243 BRW_OPCODE_PUSH = 46, /**< Pre-Gen6 */ /* Reused */
244 BRW_OPCODE_FORK = 46, /**< Gen6 only */ /* Reused */
245 BRW_OPCODE_GOTO = 46, /**< Gen8+ */ /* Reused */
246 BRW_OPCODE_POP = 47, /**< Pre-Gen6 */
247 BRW_OPCODE_WAIT = 48,
248 BRW_OPCODE_SEND = 49,
249 BRW_OPCODE_SENDC = 50,
250 BRW_OPCODE_SENDS = 51, /**< Gen9+ */
251 BRW_OPCODE_SENDSC = 52, /**< Gen9+ */
252 /* Reserved 53-55 */
253 BRW_OPCODE_MATH = 56, /**< Gen6+ */
254 /* Reserved 57-63 */
255 BRW_OPCODE_ADD = 64,
256 BRW_OPCODE_MUL = 65,
257 BRW_OPCODE_AVG = 66,
258 BRW_OPCODE_FRC = 67,
259 BRW_OPCODE_RNDU = 68,
260 BRW_OPCODE_RNDD = 69,
261 BRW_OPCODE_RNDE = 70,
262 BRW_OPCODE_RNDZ = 71,
263 BRW_OPCODE_MAC = 72,
264 BRW_OPCODE_MACH = 73,
265 BRW_OPCODE_LZD = 74,
266 BRW_OPCODE_FBH = 75, /**< Gen7+ */
267 BRW_OPCODE_FBL = 76, /**< Gen7+ */
268 BRW_OPCODE_CBIT = 77, /**< Gen7+ */
269 BRW_OPCODE_ADDC = 78, /**< Gen7+ */
270 BRW_OPCODE_SUBB = 79, /**< Gen7+ */
271 BRW_OPCODE_SAD2 = 80,
272 BRW_OPCODE_SADA2 = 81,
273 /* Reserved 82-83 */
274 BRW_OPCODE_DP4 = 84,
275 BRW_OPCODE_DPH = 85,
276 BRW_OPCODE_DP3 = 86,
277 BRW_OPCODE_DP2 = 87,
278 /* Reserved 88 */
279 BRW_OPCODE_LINE = 89,
280 BRW_OPCODE_PLN = 90, /**< G45+ */
281 BRW_OPCODE_MAD = 91, /**< Gen6+ */
282 BRW_OPCODE_LRP = 92, /**< Gen6+ */
283 BRW_OPCODE_MADM = 93, /**< Gen8+ */
284 /* Reserved 94-124 */
285 BRW_OPCODE_NENOP = 125, /**< G45 only */
286 BRW_OPCODE_NOP = 126,
287 /* Reserved 127 */
288
289 /* These are compiler backend opcodes that get translated into other
290 * instructions.
291 */
292 FS_OPCODE_FB_WRITE = 128,
293
294 /**
295 * Same as FS_OPCODE_FB_WRITE but expects its arguments separately as
296 * individual sources instead of as a single payload blob. The
297 * position/ordering of the arguments are defined by the enum
298 * fb_write_logical_srcs.
299 */
300 FS_OPCODE_FB_WRITE_LOGICAL,
301
302 FS_OPCODE_REP_FB_WRITE,
303
304 FS_OPCODE_FB_READ,
305 FS_OPCODE_FB_READ_LOGICAL,
306
307 SHADER_OPCODE_RCP,
308 SHADER_OPCODE_RSQ,
309 SHADER_OPCODE_SQRT,
310 SHADER_OPCODE_EXP2,
311 SHADER_OPCODE_LOG2,
312 SHADER_OPCODE_POW,
313 SHADER_OPCODE_INT_QUOTIENT,
314 SHADER_OPCODE_INT_REMAINDER,
315 SHADER_OPCODE_SIN,
316 SHADER_OPCODE_COS,
317
318 /**
319 * Texture sampling opcodes.
320 *
321 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
322 * opcode but instead of taking a single payload blob they expect their
323 * arguments separately as individual sources. The position/ordering of the
324 * arguments are defined by the enum tex_logical_srcs.
325 */
326 SHADER_OPCODE_TEX,
327 SHADER_OPCODE_TEX_LOGICAL,
328 SHADER_OPCODE_TXD,
329 SHADER_OPCODE_TXD_LOGICAL,
330 SHADER_OPCODE_TXF,
331 SHADER_OPCODE_TXF_LOGICAL,
332 SHADER_OPCODE_TXF_LZ,
333 SHADER_OPCODE_TXL,
334 SHADER_OPCODE_TXL_LOGICAL,
335 SHADER_OPCODE_TXL_LZ,
336 SHADER_OPCODE_TXS,
337 SHADER_OPCODE_TXS_LOGICAL,
338 FS_OPCODE_TXB,
339 FS_OPCODE_TXB_LOGICAL,
340 SHADER_OPCODE_TXF_CMS,
341 SHADER_OPCODE_TXF_CMS_LOGICAL,
342 SHADER_OPCODE_TXF_CMS_W,
343 SHADER_OPCODE_TXF_CMS_W_LOGICAL,
344 SHADER_OPCODE_TXF_UMS,
345 SHADER_OPCODE_TXF_UMS_LOGICAL,
346 SHADER_OPCODE_TXF_MCS,
347 SHADER_OPCODE_TXF_MCS_LOGICAL,
348 SHADER_OPCODE_LOD,
349 SHADER_OPCODE_LOD_LOGICAL,
350 SHADER_OPCODE_TG4,
351 SHADER_OPCODE_TG4_LOGICAL,
352 SHADER_OPCODE_TG4_OFFSET,
353 SHADER_OPCODE_TG4_OFFSET_LOGICAL,
354 SHADER_OPCODE_SAMPLEINFO,
355 SHADER_OPCODE_SAMPLEINFO_LOGICAL,
356
357 SHADER_OPCODE_IMAGE_SIZE,
358
359 /**
360 * Combines multiple sources of size 1 into a larger virtual GRF.
361 * For example, parameters for a send-from-GRF message. Or, updating
362 * channels of a size 4 VGRF used to store vec4s such as texturing results.
363 *
364 * This will be lowered into MOVs from each source to consecutive offsets
365 * of the destination VGRF.
366 *
367 * src[0] may be BAD_FILE. If so, the lowering pass skips emitting the MOV,
368 * but still reserves the first channel of the destination VGRF. This can be
369 * used to reserve space for, say, a message header set up by the generators.
370 */
371 SHADER_OPCODE_LOAD_PAYLOAD,
372
373 /**
374 * Packs a number of sources into a single value. Unlike LOAD_PAYLOAD, this
375 * acts intra-channel, obtaining the final value for each channel by
376 * combining the sources values for the same channel, the first source
377 * occupying the lowest bits and the last source occupying the highest
378 * bits.
379 */
380 FS_OPCODE_PACK,
381
382 SHADER_OPCODE_SHADER_TIME_ADD,
383
384 /**
385 * Typed and untyped surface access opcodes.
386 *
387 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
388 * opcode but instead of taking a single payload blob they expect their
389 * arguments separately as individual sources:
390 *
391 * Source 0: [required] Surface coordinates.
392 * Source 1: [optional] Operation source.
393 * Source 2: [required] Surface index.
394 * Source 3: [required] Number of coordinate components (as UD immediate).
395 * Source 4: [required] Opcode-specific control immediate, same as source 2
396 * of the matching non-LOGICAL opcode.
397 */
398 SHADER_OPCODE_UNTYPED_ATOMIC,
399 SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
400 SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT,
401 SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL,
402 SHADER_OPCODE_UNTYPED_SURFACE_READ,
403 SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
404 SHADER_OPCODE_UNTYPED_SURFACE_WRITE,
405 SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
406
407 SHADER_OPCODE_TYPED_ATOMIC,
408 SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
409 SHADER_OPCODE_TYPED_SURFACE_READ,
410 SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
411 SHADER_OPCODE_TYPED_SURFACE_WRITE,
412 SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
413
414 SHADER_OPCODE_RND_MODE,
415
416 /**
417 * Byte scattered write/read opcodes.
418 *
419 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
420 * opcode, but instead of taking a single payload blog they expect their
421 * arguments separately as individual sources, like untyped write/read.
422 */
423 SHADER_OPCODE_BYTE_SCATTERED_READ,
424 SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
425 SHADER_OPCODE_BYTE_SCATTERED_WRITE,
426 SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
427
428 SHADER_OPCODE_MEMORY_FENCE,
429
430 SHADER_OPCODE_GEN4_SCRATCH_READ,
431 SHADER_OPCODE_GEN4_SCRATCH_WRITE,
432 SHADER_OPCODE_GEN7_SCRATCH_READ,
433
434 /**
435 * Gen8+ SIMD8 URB Read messages.
436 */
437 SHADER_OPCODE_URB_READ_SIMD8,
438 SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT,
439
440 SHADER_OPCODE_URB_WRITE_SIMD8,
441 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT,
442 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,
443 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT,
444
445 /**
446 * Return the index of an arbitrary live channel (i.e. one of the channels
447 * enabled in the current execution mask) and assign it to the first
448 * component of the destination. Expected to be used as input for the
449 * BROADCAST pseudo-opcode.
450 */
451 SHADER_OPCODE_FIND_LIVE_CHANNEL,
452
453 /**
454 * Pick the channel from its first source register given by the index
455 * specified as second source. Useful for variable indexing of surfaces.
456 *
457 * Note that because the result of this instruction is by definition
458 * uniform and it can always be splatted to multiple channels using a
459 * scalar regioning mode, only the first channel of the destination region
460 * is guaranteed to be updated, which implies that BROADCAST instructions
461 * should usually be marked force_writemask_all.
462 */
463 SHADER_OPCODE_BROADCAST,
464
465 /* Pick the channel from its first source register given by the index
466 * specified as second source.
467 *
468 * This is similar to the BROADCAST instruction except that it takes a
469 * dynamic index and potentially puts a different value in each output
470 * channel.
471 */
472 SHADER_OPCODE_SHUFFLE,
473
474 /* Select between src0 and src1 based on channel enables.
475 *
476 * This instruction copies src0 into the enabled channels of the
477 * destination and copies src1 into the disabled channels.
478 */
479 SHADER_OPCODE_SEL_EXEC,
480
481 /* This turns into an align16 mov from src0 to dst with a swizzle
482 * provided as an immediate in src1.
483 */
484 SHADER_OPCODE_QUAD_SWIZZLE,
485
486 /* Take every Nth element in src0 and broadcast it to the group of N
487 * channels in which it lives in the destination. The offset within the
488 * cluster is given by src1 and the cluster size is given by src2.
489 */
490 SHADER_OPCODE_CLUSTER_BROADCAST,
491
492 SHADER_OPCODE_GET_BUFFER_SIZE,
493
494 SHADER_OPCODE_INTERLOCK,
495
496 VEC4_OPCODE_MOV_BYTES,
497 VEC4_OPCODE_PACK_BYTES,
498 VEC4_OPCODE_UNPACK_UNIFORM,
499 VEC4_OPCODE_DOUBLE_TO_F32,
500 VEC4_OPCODE_DOUBLE_TO_D32,
501 VEC4_OPCODE_DOUBLE_TO_U32,
502 VEC4_OPCODE_TO_DOUBLE,
503 VEC4_OPCODE_PICK_LOW_32BIT,
504 VEC4_OPCODE_PICK_HIGH_32BIT,
505 VEC4_OPCODE_SET_LOW_32BIT,
506 VEC4_OPCODE_SET_HIGH_32BIT,
507
508 FS_OPCODE_DDX_COARSE,
509 FS_OPCODE_DDX_FINE,
510 /**
511 * Compute dFdy(), dFdyCoarse(), or dFdyFine().
512 */
513 FS_OPCODE_DDY_COARSE,
514 FS_OPCODE_DDY_FINE,
515 FS_OPCODE_LINTERP,
516 FS_OPCODE_PIXEL_X,
517 FS_OPCODE_PIXEL_Y,
518 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
519 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7,
520 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4,
521 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7,
522 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
523 FS_OPCODE_DISCARD_JUMP,
524 FS_OPCODE_SET_SAMPLE_ID,
525 FS_OPCODE_PACK_HALF_2x16_SPLIT,
526 FS_OPCODE_PLACEHOLDER_HALT,
527 FS_OPCODE_INTERPOLATE_AT_SAMPLE,
528 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
529 FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET,
530
531 VS_OPCODE_URB_WRITE,
532 VS_OPCODE_PULL_CONSTANT_LOAD,
533 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
534 VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
535
536 VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
537
538 /**
539 * Write geometry shader output data to the URB.
540 *
541 * Unlike VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
542 * R0 to the first MRF. This allows the geometry shader to override the
543 * "Slot {0,1} Offset" fields in the message header.
544 */
545 GS_OPCODE_URB_WRITE,
546
547 /**
548 * Write geometry shader output data to the URB and request a new URB
549 * handle (gen6).
550 *
551 * This opcode doesn't do an implied move from R0 to the first MRF.
552 */
553 GS_OPCODE_URB_WRITE_ALLOCATE,
554
555 /**
556 * Terminate the geometry shader thread by doing an empty URB write.
557 *
558 * This opcode doesn't do an implied move from R0 to the first MRF. This
559 * allows the geometry shader to override the "GS Number of Output Vertices
560 * for Slot {0,1}" fields in the message header.
561 */
562 GS_OPCODE_THREAD_END,
563
564 /**
565 * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header.
566 *
567 * - dst is the MRF containing the message header.
568 *
569 * - src0.x indicates which portion of the URB should be written to (e.g. a
570 * vertex number)
571 *
572 * - src1 is an immediate multiplier which will be applied to src0
573 * (e.g. the size of a single vertex in the URB).
574 *
575 * Note: the hardware will apply this offset *in addition to* the offset in
576 * vec4_instruction::offset.
577 */
578 GS_OPCODE_SET_WRITE_OFFSET,
579
580 /**
581 * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a
582 * URB_WRITE message header.
583 *
584 * - dst is the MRF containing the message header.
585 *
586 * - src0.x is the vertex count. The upper 16 bits will be ignored.
587 */
588 GS_OPCODE_SET_VERTEX_COUNT,
589
590 /**
591 * Set DWORD 2 of dst to the value in src.
592 */
593 GS_OPCODE_SET_DWORD_2,
594
595 /**
596 * Prepare the dst register for storage in the "Channel Mask" fields of a
597 * URB_WRITE message header.
598 *
599 * DWORD 4 of dst is shifted left by 4 bits, so that later,
600 * GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the
601 * final channel mask.
602 *
603 * Note: since GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to
604 * form the final channel mask, DWORDs 0 and 4 of the dst register must not
605 * have any extraneous bits set prior to execution of this opcode (that is,
606 * they should be in the range 0x0 to 0xf).
607 */
608 GS_OPCODE_PREPARE_CHANNEL_MASKS,
609
610 /**
611 * Set the "Channel Mask" fields of a URB_WRITE message header.
612 *
613 * - dst is the MRF containing the message header.
614 *
615 * - src.x is the channel mask, as prepared by
616 * GS_OPCODE_PREPARE_CHANNEL_MASKS. DWORDs 0 and 4 are OR'ed together to
617 * form the final channel mask.
618 */
619 GS_OPCODE_SET_CHANNEL_MASKS,
620
621 /**
622 * Get the "Instance ID" fields from the payload.
623 *
624 * - dst is the GRF for gl_InvocationID.
625 */
626 GS_OPCODE_GET_INSTANCE_ID,
627
628 /**
629 * Send a FF_SYNC message to allocate initial URB handles (gen6).
630 *
631 * - dst will be used as the writeback register for the FF_SYNC operation.
632 *
633 * - src0 is the number of primitives written.
634 *
635 * - src1 is the value to hold in M0.0: number of SO vertices to write
636 * and number of SO primitives needed. Its value will be overwritten
637 * with the SVBI values if transform feedback is enabled.
638 *
639 * Note: This opcode uses an implicit MRF register for the ff_sync message
640 * header, so the caller is expected to set inst->base_mrf and initialize
641 * that MRF register to r0. This opcode will also write to this MRF register
642 * to include the allocated URB handle so it can then be reused directly as
643 * the header in the URB write operation we are allocating the handle for.
644 */
645 GS_OPCODE_FF_SYNC,
646
647 /**
648 * Move r0.1 (which holds PrimitiveID information in gen6) to a separate
649 * register.
650 *
651 * - dst is the GRF where PrimitiveID information will be moved.
652 */
653 GS_OPCODE_SET_PRIMITIVE_ID,
654
655 /**
656 * Write transform feedback data to the SVB by sending a SVB WRITE message.
657 * Used in gen6.
658 *
659 * - dst is the MRF register containing the message header.
660 *
661 * - src0 is the register where the vertex data is going to be copied from.
662 *
663 * - src1 is the destination register when write commit occurs.
664 */
665 GS_OPCODE_SVB_WRITE,
666
667 /**
668 * Set destination index in the SVB write message payload (M0.5). Used
669 * in gen6 for transform feedback.
670 *
671 * - dst is the header to save the destination indices for SVB WRITE.
672 * - src is the register that holds the destination indices value.
673 */
674 GS_OPCODE_SVB_SET_DST_INDEX,
675
676 /**
677 * Prepare Mx.0 subregister for being used in the FF_SYNC message header.
678 * Used in gen6 for transform feedback.
679 *
680 * - dst will hold the register with the final Mx.0 value.
681 *
682 * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite)
683 *
684 * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded)
685 *
686 * - src2 is the value to hold in M0: number of SO vertices to write
687 * and number of SO primitives needed.
688 */
689 GS_OPCODE_FF_SYNC_SET_PRIMITIVES,
690
691 /**
692 * Terminate the compute shader.
693 */
694 CS_OPCODE_CS_TERMINATE,
695
696 /**
697 * GLSL barrier()
698 */
699 SHADER_OPCODE_BARRIER,
700
701 /**
702 * Calculate the high 32-bits of a 32x32 multiply.
703 */
704 SHADER_OPCODE_MULH,
705
706 /**
707 * A MOV that uses VxH indirect addressing.
708 *
709 * Source 0: A register to start from (HW_REG).
710 * Source 1: An indirect offset (in bytes, UD GRF).
711 * Source 2: The length of the region that could be accessed (in bytes,
712 * UD immediate).
713 */
714 SHADER_OPCODE_MOV_INDIRECT,
715
716 VEC4_OPCODE_URB_READ,
717 TCS_OPCODE_GET_INSTANCE_ID,
718 TCS_OPCODE_URB_WRITE,
719 TCS_OPCODE_SET_INPUT_URB_OFFSETS,
720 TCS_OPCODE_SET_OUTPUT_URB_OFFSETS,
721 TCS_OPCODE_GET_PRIMITIVE_ID,
722 TCS_OPCODE_CREATE_BARRIER_HEADER,
723 TCS_OPCODE_SRC0_010_IS_ZERO,
724 TCS_OPCODE_RELEASE_INPUT,
725 TCS_OPCODE_THREAD_END,
726
727 TES_OPCODE_GET_PRIMITIVE_ID,
728 TES_OPCODE_CREATE_INPUT_READ_HEADER,
729 TES_OPCODE_ADD_INDIRECT_URB_OFFSET,
730 };
731
732 enum brw_urb_write_flags {
733 BRW_URB_WRITE_NO_FLAGS = 0,
734
735 /**
736 * Causes a new URB entry to be allocated, and its address stored in the
737 * destination register (gen < 7).
738 */
739 BRW_URB_WRITE_ALLOCATE = 0x1,
740
741 /**
742 * Causes the current URB entry to be deallocated (gen < 7).
743 */
744 BRW_URB_WRITE_UNUSED = 0x2,
745
746 /**
747 * Causes the thread to terminate.
748 */
749 BRW_URB_WRITE_EOT = 0x4,
750
751 /**
752 * Indicates that the given URB entry is complete, and may be sent further
753 * down the 3D pipeline (gen < 7).
754 */
755 BRW_URB_WRITE_COMPLETE = 0x8,
756
757 /**
758 * Indicates that an additional offset (which may be different for the two
759 * vec4 slots) is stored in the message header (gen == 7).
760 */
761 BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10,
762
763 /**
764 * Indicates that the channel masks in the URB_WRITE message header should
765 * not be overridden to 0xff (gen == 7).
766 */
767 BRW_URB_WRITE_USE_CHANNEL_MASKS = 0x20,
768
769 /**
770 * Indicates that the data should be sent to the URB using the
771 * URB_WRITE_OWORD message rather than URB_WRITE_HWORD (gen == 7). This
772 * causes offsets to be interpreted as multiples of an OWORD instead of an
773 * HWORD, and only allows one OWORD to be written.
774 */
775 BRW_URB_WRITE_OWORD = 0x40,
776
777 /**
778 * Convenient combination of flags: end the thread while simultaneously
779 * marking the given URB entry as complete.
780 */
781 BRW_URB_WRITE_EOT_COMPLETE = BRW_URB_WRITE_EOT | BRW_URB_WRITE_COMPLETE,
782
783 /**
784 * Convenient combination of flags: mark the given URB entry as complete
785 * and simultaneously allocate a new one.
786 */
787 BRW_URB_WRITE_ALLOCATE_COMPLETE =
788 BRW_URB_WRITE_ALLOCATE | BRW_URB_WRITE_COMPLETE,
789 };
790
791 enum fb_write_logical_srcs {
792 FB_WRITE_LOGICAL_SRC_COLOR0, /* REQUIRED */
793 FB_WRITE_LOGICAL_SRC_COLOR1, /* for dual source blend messages */
794 FB_WRITE_LOGICAL_SRC_SRC0_ALPHA,
795 FB_WRITE_LOGICAL_SRC_SRC_DEPTH, /* gl_FragDepth */
796 FB_WRITE_LOGICAL_SRC_DST_DEPTH, /* GEN4-5: passthrough from thread */
797 FB_WRITE_LOGICAL_SRC_SRC_STENCIL, /* gl_FragStencilRefARB */
798 FB_WRITE_LOGICAL_SRC_OMASK, /* Sample Mask (gl_SampleMask) */
799 FB_WRITE_LOGICAL_SRC_COMPONENTS, /* REQUIRED */
800 FB_WRITE_LOGICAL_NUM_SRCS
801 };
802
803 enum tex_logical_srcs {
804 /** Texture coordinates */
805 TEX_LOGICAL_SRC_COORDINATE,
806 /** Shadow comparator */
807 TEX_LOGICAL_SRC_SHADOW_C,
808 /** dPdx if the operation takes explicit derivatives, otherwise LOD value */
809 TEX_LOGICAL_SRC_LOD,
810 /** dPdy if the operation takes explicit derivatives */
811 TEX_LOGICAL_SRC_LOD2,
812 /** Min LOD */
813 TEX_LOGICAL_SRC_MIN_LOD,
814 /** Sample index */
815 TEX_LOGICAL_SRC_SAMPLE_INDEX,
816 /** MCS data */
817 TEX_LOGICAL_SRC_MCS,
818 /** REQUIRED: Texture surface index */
819 TEX_LOGICAL_SRC_SURFACE,
820 /** Texture sampler index */
821 TEX_LOGICAL_SRC_SAMPLER,
822 /** Texel offset for gathers */
823 TEX_LOGICAL_SRC_TG4_OFFSET,
824 /** REQUIRED: Number of coordinate components (as UD immediate) */
825 TEX_LOGICAL_SRC_COORD_COMPONENTS,
826 /** REQUIRED: Number of derivative components (as UD immediate) */
827 TEX_LOGICAL_SRC_GRAD_COMPONENTS,
828
829 TEX_LOGICAL_NUM_SRCS,
830 };
831
832 #ifdef __cplusplus
833 /**
834 * Allow brw_urb_write_flags enums to be ORed together.
835 */
836 inline brw_urb_write_flags
837 operator|(brw_urb_write_flags x, brw_urb_write_flags y)
838 {
839 return static_cast<brw_urb_write_flags>(static_cast<int>(x) |
840 static_cast<int>(y));
841 }
842 #endif
843
844 enum PACKED brw_predicate {
845 BRW_PREDICATE_NONE = 0,
846 BRW_PREDICATE_NORMAL = 1,
847 BRW_PREDICATE_ALIGN1_ANYV = 2,
848 BRW_PREDICATE_ALIGN1_ALLV = 3,
849 BRW_PREDICATE_ALIGN1_ANY2H = 4,
850 BRW_PREDICATE_ALIGN1_ALL2H = 5,
851 BRW_PREDICATE_ALIGN1_ANY4H = 6,
852 BRW_PREDICATE_ALIGN1_ALL4H = 7,
853 BRW_PREDICATE_ALIGN1_ANY8H = 8,
854 BRW_PREDICATE_ALIGN1_ALL8H = 9,
855 BRW_PREDICATE_ALIGN1_ANY16H = 10,
856 BRW_PREDICATE_ALIGN1_ALL16H = 11,
857 BRW_PREDICATE_ALIGN1_ANY32H = 12,
858 BRW_PREDICATE_ALIGN1_ALL32H = 13,
859 BRW_PREDICATE_ALIGN16_REPLICATE_X = 2,
860 BRW_PREDICATE_ALIGN16_REPLICATE_Y = 3,
861 BRW_PREDICATE_ALIGN16_REPLICATE_Z = 4,
862 BRW_PREDICATE_ALIGN16_REPLICATE_W = 5,
863 BRW_PREDICATE_ALIGN16_ANY4H = 6,
864 BRW_PREDICATE_ALIGN16_ALL4H = 7,
865 };
866
867 enum PACKED brw_reg_file {
868 BRW_ARCHITECTURE_REGISTER_FILE = 0,
869 BRW_GENERAL_REGISTER_FILE = 1,
870 BRW_MESSAGE_REGISTER_FILE = 2,
871 BRW_IMMEDIATE_VALUE = 3,
872
873 ARF = BRW_ARCHITECTURE_REGISTER_FILE,
874 FIXED_GRF = BRW_GENERAL_REGISTER_FILE,
875 MRF = BRW_MESSAGE_REGISTER_FILE,
876 IMM = BRW_IMMEDIATE_VALUE,
877
878 /* These are not hardware values */
879 VGRF,
880 ATTR,
881 UNIFORM, /* prog_data->params[reg] */
882 BAD_FILE,
883 };
884
885 enum PACKED gen10_align1_3src_reg_file {
886 BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE = 0,
887 BRW_ALIGN1_3SRC_IMMEDIATE_VALUE = 1, /* src0, src2 */
888 BRW_ALIGN1_3SRC_ACCUMULATOR = 1, /* dest, src1 */
889 };
890
891 /* CNL adds Align1 support for 3-src instructions. Bit 35 of the instruction
892 * word is "Execution Datatype" which controls whether the instruction operates
893 * on float or integer types. The register arguments have fields that offer
894 * more fine control their respective types.
895 */
896 enum PACKED gen10_align1_3src_exec_type {
897 BRW_ALIGN1_3SRC_EXEC_TYPE_INT = 0,
898 BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT = 1,
899 };
900
901 #define BRW_ARF_NULL 0x00
902 #define BRW_ARF_ADDRESS 0x10
903 #define BRW_ARF_ACCUMULATOR 0x20
904 #define BRW_ARF_FLAG 0x30
905 #define BRW_ARF_MASK 0x40
906 #define BRW_ARF_MASK_STACK 0x50
907 #define BRW_ARF_MASK_STACK_DEPTH 0x60
908 #define BRW_ARF_STATE 0x70
909 #define BRW_ARF_CONTROL 0x80
910 #define BRW_ARF_NOTIFICATION_COUNT 0x90
911 #define BRW_ARF_IP 0xA0
912 #define BRW_ARF_TDR 0xB0
913 #define BRW_ARF_TIMESTAMP 0xC0
914
915 #define BRW_MRF_COMPR4 (1 << 7)
916
917 #define BRW_AMASK 0
918 #define BRW_IMASK 1
919 #define BRW_LMASK 2
920 #define BRW_CMASK 3
921
922
923
924 #define BRW_THREAD_NORMAL 0
925 #define BRW_THREAD_ATOMIC 1
926 #define BRW_THREAD_SWITCH 2
927
928 enum PACKED brw_vertical_stride {
929 BRW_VERTICAL_STRIDE_0 = 0,
930 BRW_VERTICAL_STRIDE_1 = 1,
931 BRW_VERTICAL_STRIDE_2 = 2,
932 BRW_VERTICAL_STRIDE_4 = 3,
933 BRW_VERTICAL_STRIDE_8 = 4,
934 BRW_VERTICAL_STRIDE_16 = 5,
935 BRW_VERTICAL_STRIDE_32 = 6,
936 BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF,
937 };
938
939 enum PACKED gen10_align1_3src_vertical_stride {
940 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0,
941 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1,
942 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4 = 2,
943 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8 = 3,
944 };
945
946 enum PACKED brw_width {
947 BRW_WIDTH_1 = 0,
948 BRW_WIDTH_2 = 1,
949 BRW_WIDTH_4 = 2,
950 BRW_WIDTH_8 = 3,
951 BRW_WIDTH_16 = 4,
952 };
953
954 /**
955 * Message target: Shared Function ID for where to SEND a message.
956 *
957 * These are enumerated in the ISA reference under "send - Send Message".
958 * In particular, see the following tables:
959 * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition"
960 * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor"
961 * - Ivybridge PRM, Volume 1 Part 1, section 3.2.7 "GPE Function IDs"
962 */
963 enum brw_message_target {
964 BRW_SFID_NULL = 0,
965 BRW_SFID_MATH = 1, /* Only valid on Gen4-5 */
966 BRW_SFID_SAMPLER = 2,
967 BRW_SFID_MESSAGE_GATEWAY = 3,
968 BRW_SFID_DATAPORT_READ = 4,
969 BRW_SFID_DATAPORT_WRITE = 5,
970 BRW_SFID_URB = 6,
971 BRW_SFID_THREAD_SPAWNER = 7,
972 BRW_SFID_VME = 8,
973
974 GEN6_SFID_DATAPORT_SAMPLER_CACHE = 4,
975 GEN6_SFID_DATAPORT_RENDER_CACHE = 5,
976 GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9,
977
978 GEN7_SFID_DATAPORT_DATA_CACHE = 10,
979 GEN7_SFID_PIXEL_INTERPOLATOR = 11,
980 HSW_SFID_DATAPORT_DATA_CACHE_1 = 12,
981 HSW_SFID_CRE = 13,
982 };
983
984 #define GEN7_MESSAGE_TARGET_DP_DATA_CACHE 10
985
986 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0
987 #define BRW_SAMPLER_RETURN_FORMAT_UINT32 2
988 #define BRW_SAMPLER_RETURN_FORMAT_SINT32 3
989
990 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0
991 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0
992 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0
993 #define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1
994 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1
995 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1
996 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2
997 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2
998 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0
999 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2
1000 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0
1001 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1
1002 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE 1
1003 #define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2
1004 #define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2
1005 #define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3
1006 #define BRW_SAMPLER_MESSAGE_SIMD8_LD 3
1007 #define BRW_SAMPLER_MESSAGE_SIMD16_LD 3
1008
1009 #define GEN5_SAMPLER_MESSAGE_SAMPLE 0
1010 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS 1
1011 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD 2
1012 #define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE 3
1013 #define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS 4
1014 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
1015 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6
1016 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LD 7
1017 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4 8
1018 #define GEN5_SAMPLER_MESSAGE_LOD 9
1019 #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10
1020 #define GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO 11
1021 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C 16
1022 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO 17
1023 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
1024 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
1025 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LZ 24
1026 #define GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ 25
1027 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ 26
1028 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W 28
1029 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29
1030 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS 30
1031 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS 31
1032
1033 /* for GEN5 only */
1034 #define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0
1035 #define BRW_SAMPLER_SIMD_MODE_SIMD8 1
1036 #define BRW_SAMPLER_SIMD_MODE_SIMD16 2
1037 #define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3
1038
1039 /* GEN9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2
1040 * behavior by setting bit 22 of dword 2 in the message header. */
1041 #define GEN9_SAMPLER_SIMD_MODE_SIMD8D 0
1042 #define GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2 (1 << 22)
1043
1044 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0
1045 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1
1046 #define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2
1047 #define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3
1048 #define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4
1049 #define BRW_DATAPORT_OWORD_BLOCK_DWORDS(n) \
1050 ((n) == 4 ? BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \
1051 (n) == 8 ? BRW_DATAPORT_OWORD_BLOCK_2_OWORDS : \
1052 (n) == 16 ? BRW_DATAPORT_OWORD_BLOCK_4_OWORDS : \
1053 (n) == 32 ? BRW_DATAPORT_OWORD_BLOCK_8_OWORDS : \
1054 (abort(), ~0))
1055
1056 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0
1057 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2
1058
1059 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2
1060 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3
1061
1062 /* This one stays the same across generations. */
1063 #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0
1064 /* GEN4 */
1065 #define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1
1066 #define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2
1067 #define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3
1068 /* G45, GEN5 */
1069 #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1070 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1071 #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ 3
1072 #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1073 #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1074 /* GEN6 */
1075 #define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1076 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1077 #define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1078 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5
1079 #define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1080
1081 #define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0
1082 #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1
1083 #define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2
1084
1085 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0
1086 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1
1087 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2
1088 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3
1089 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4
1090
1091 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0
1092 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1
1093 #define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2
1094 #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3
1095 #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4
1096 #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5
1097 #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7
1098
1099 /* GEN6 */
1100 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7
1101 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8
1102 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 9
1103 #define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 10
1104 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 11
1105 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 12
1106 #define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13
1107 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14
1108
1109 /* GEN7 */
1110 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_READ 4
1111 #define GEN7_DATAPORT_RC_TYPED_SURFACE_READ 5
1112 #define GEN7_DATAPORT_RC_TYPED_ATOMIC_OP 6
1113 #define GEN7_DATAPORT_RC_MEMORY_FENCE 7
1114 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_WRITE 10
1115 #define GEN7_DATAPORT_RC_RENDER_TARGET_WRITE 12
1116 #define GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE 13
1117 #define GEN7_DATAPORT_DC_OWORD_BLOCK_READ 0
1118 #define GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ 1
1119 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ 2
1120 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_READ 3
1121 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_READ 4
1122 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ 5
1123 #define GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP 6
1124 #define GEN7_DATAPORT_DC_MEMORY_FENCE 7
1125 #define GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE 8
1126 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE 10
1127 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE 11
1128 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE 12
1129 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE 13
1130
1131 #define GEN7_DATAPORT_SCRATCH_READ ((1 << 18) | \
1132 (0 << 17))
1133 #define GEN7_DATAPORT_SCRATCH_WRITE ((1 << 18) | \
1134 (1 << 17))
1135 #define GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT 12
1136
1137 #define GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET 0
1138 #define GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE 1
1139 #define GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID 2
1140 #define GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET 3
1141
1142 /* HSW */
1143 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ 0
1144 #define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ 1
1145 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_READ 2
1146 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_READ 3
1147 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ 4
1148 #define HSW_DATAPORT_DC_PORT0_MEMORY_FENCE 7
1149 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_WRITE 8
1150 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_WRITE 10
1151 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_WRITE 11
1152 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE 12
1153
1154 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ 1
1155 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP 2
1156 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2 3
1157 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ 4
1158 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ 5
1159 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP 6
1160 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2 7
1161 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE 9
1162 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE 10
1163 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP 11
1164 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2 12
1165 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE 13
1166 #define GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP 0x1b
1167
1168 /* GEN9 */
1169 #define GEN9_DATAPORT_RC_RENDER_TARGET_WRITE 12
1170 #define GEN9_DATAPORT_RC_RENDER_TARGET_READ 13
1171
1172 /* Dataport special binding table indices: */
1173 #define BRW_BTI_STATELESS 255
1174 #define GEN7_BTI_SLM 254
1175 /* Note that on Gen8+ BTI 255 was redefined to be IA-coherent according to the
1176 * hardware spec, however because the DRM sets bit 4 of HDC_CHICKEN0 on BDW,
1177 * CHV and at least some pre-production steppings of SKL due to
1178 * WaForceEnableNonCoherent, HDC memory access may have been overridden by the
1179 * kernel to be non-coherent (matching the behavior of the same BTI on
1180 * pre-Gen8 hardware) and BTI 255 may actually be an alias for BTI 253.
1181 */
1182 #define GEN8_BTI_STATELESS_IA_COHERENT 255
1183 #define GEN8_BTI_STATELESS_NON_COHERENT 253
1184
1185 /* Dataport atomic operations for Untyped Atomic Integer Operation message
1186 * (and others).
1187 */
1188 #define BRW_AOP_AND 1
1189 #define BRW_AOP_OR 2
1190 #define BRW_AOP_XOR 3
1191 #define BRW_AOP_MOV 4
1192 #define BRW_AOP_INC 5
1193 #define BRW_AOP_DEC 6
1194 #define BRW_AOP_ADD 7
1195 #define BRW_AOP_SUB 8
1196 #define BRW_AOP_REVSUB 9
1197 #define BRW_AOP_IMAX 10
1198 #define BRW_AOP_IMIN 11
1199 #define BRW_AOP_UMAX 12
1200 #define BRW_AOP_UMIN 13
1201 #define BRW_AOP_CMPWR 14
1202 #define BRW_AOP_PREDEC 15
1203
1204 /* Dataport atomic operations for Untyped Atomic Float Operation message. */
1205 #define BRW_AOP_FMAX 1
1206 #define BRW_AOP_FMIN 2
1207 #define BRW_AOP_FCMPWR 3
1208
1209 #define BRW_MATH_FUNCTION_INV 1
1210 #define BRW_MATH_FUNCTION_LOG 2
1211 #define BRW_MATH_FUNCTION_EXP 3
1212 #define BRW_MATH_FUNCTION_SQRT 4
1213 #define BRW_MATH_FUNCTION_RSQ 5
1214 #define BRW_MATH_FUNCTION_SIN 6
1215 #define BRW_MATH_FUNCTION_COS 7
1216 #define BRW_MATH_FUNCTION_SINCOS 8 /* gen4, gen5 */
1217 #define BRW_MATH_FUNCTION_FDIV 9 /* gen6+ */
1218 #define BRW_MATH_FUNCTION_POW 10
1219 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
1220 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12
1221 #define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13
1222 #define GEN8_MATH_FUNCTION_INVM 14
1223 #define GEN8_MATH_FUNCTION_RSQRTM 15
1224
1225 #define BRW_MATH_INTEGER_UNSIGNED 0
1226 #define BRW_MATH_INTEGER_SIGNED 1
1227
1228 #define BRW_MATH_PRECISION_FULL 0
1229 #define BRW_MATH_PRECISION_PARTIAL 1
1230
1231 #define BRW_MATH_SATURATE_NONE 0
1232 #define BRW_MATH_SATURATE_SATURATE 1
1233
1234 #define BRW_MATH_DATA_VECTOR 0
1235 #define BRW_MATH_DATA_SCALAR 1
1236
1237 #define BRW_URB_OPCODE_WRITE_HWORD 0
1238 #define BRW_URB_OPCODE_WRITE_OWORD 1
1239 #define BRW_URB_OPCODE_READ_HWORD 2
1240 #define BRW_URB_OPCODE_READ_OWORD 3
1241 #define GEN7_URB_OPCODE_ATOMIC_MOV 4
1242 #define GEN7_URB_OPCODE_ATOMIC_INC 5
1243 #define GEN8_URB_OPCODE_ATOMIC_ADD 6
1244 #define GEN8_URB_OPCODE_SIMD8_WRITE 7
1245 #define GEN8_URB_OPCODE_SIMD8_READ 8
1246
1247 #define BRW_URB_SWIZZLE_NONE 0
1248 #define BRW_URB_SWIZZLE_INTERLEAVE 1
1249 #define BRW_URB_SWIZZLE_TRANSPOSE 2
1250
1251 #define BRW_SCRATCH_SPACE_SIZE_1K 0
1252 #define BRW_SCRATCH_SPACE_SIZE_2K 1
1253 #define BRW_SCRATCH_SPACE_SIZE_4K 2
1254 #define BRW_SCRATCH_SPACE_SIZE_8K 3
1255 #define BRW_SCRATCH_SPACE_SIZE_16K 4
1256 #define BRW_SCRATCH_SPACE_SIZE_32K 5
1257 #define BRW_SCRATCH_SPACE_SIZE_64K 6
1258 #define BRW_SCRATCH_SPACE_SIZE_128K 7
1259 #define BRW_SCRATCH_SPACE_SIZE_256K 8
1260 #define BRW_SCRATCH_SPACE_SIZE_512K 9
1261 #define BRW_SCRATCH_SPACE_SIZE_1M 10
1262 #define BRW_SCRATCH_SPACE_SIZE_2M 11
1263
1264 #define BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY 0
1265 #define BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY 1
1266 #define BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG 2
1267 #define BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP 3
1268 #define BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG 4
1269 #define BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE 5
1270 #define BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE 6
1271
1272
1273 /* Gen7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size
1274 * is 2^9, or 512. It's counted in multiples of 64 bytes.
1275 *
1276 * Identical for VS, DS, and HS.
1277 */
1278 #define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES (512*64)
1279 #define GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES (512*64)
1280 #define GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES (512*64)
1281 #define GEN7_MAX_VS_URB_ENTRY_SIZE_BYTES (512*64)
1282
1283 /* Gen6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit
1284 * (128 bytes) URB rows and the maximum allowed value is 5 rows.
1285 */
1286 #define GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES (5*128)
1287
1288 /* GS Thread Payload
1289 */
1290
1291 /* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62. It's
1292 * counted in multiples of 16 bytes.
1293 */
1294 #define GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES (62*16)
1295
1296
1297 /* R0 */
1298 # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27
1299
1300 /* CR0.0[5:4] Floating-Point Rounding Modes
1301 * Skylake PRM, Volume 7 Part 1, "Control Register", page 756
1302 */
1303
1304 #define BRW_CR0_RND_MODE_MASK 0x30
1305 #define BRW_CR0_RND_MODE_SHIFT 4
1306
1307 enum PACKED brw_rnd_mode {
1308 BRW_RND_MODE_RTNE = 0, /* Round to Nearest or Even */
1309 BRW_RND_MODE_RU = 1, /* Round Up, toward +inf */
1310 BRW_RND_MODE_RD = 2, /* Round Down, toward -inf */
1311 BRW_RND_MODE_RTZ = 3, /* Round Toward Zero */
1312 BRW_RND_MODE_UNSPECIFIED, /* Unspecified rounding mode */
1313 };
1314
1315 /* MDC_DS - Data Size Message Descriptor Control Field
1316 * Skylake PRM, Volume 2d, page 129
1317 *
1318 * Specifies the number of Bytes to be read or written per Dword used at
1319 * byte_scattered read/write and byte_scaled read/write messages.
1320 */
1321 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE 0
1322 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD 1
1323 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD 2
1324
1325 #endif /* BRW_EU_DEFINES_H */