src/intel/compiler/brw_eu_defines.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32 #ifndef BRW_EU_DEFINES_H
  33 #define BRW_EU_DEFINES_H
  34
  35 #include "util/macros.h"
  36
  37 /* The following hunk, up-to "Execution Unit" is used by both the
  38  * intel/compiler and i965 codebase. */
  39
  40 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
  41 /* Using the GNU statement expression extension */
  42 #define SET_FIELD(value, field)                                         \
  43    ({                                                                   \
  44       uint32_t fieldval = (uint32_t)(value) << field ## _SHIFT;         \
  45       assert((fieldval & ~ field ## _MASK) == 0);                       \
  46       fieldval & field ## _MASK;                                        \
  47    })
  48
  49 #define SET_BITS(value, high, low)                                      \
  50    ({                                                                   \
  51       const uint32_t fieldval = (uint32_t)(value) << (low);             \
  52       assert((fieldval & ~INTEL_MASK(high, low)) == 0);                 \
  53       fieldval & INTEL_MASK(high, low);                                 \
  54    })
  55
  56 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
  57 #define GET_FIELD(word, field) (((word)  & field ## _MASK) >> field ## _SHIFT)
  58
  59 #define _3DPRIM_POINTLIST         0x01
  60 #define _3DPRIM_LINELIST          0x02
  61 #define _3DPRIM_LINESTRIP         0x03
  62 #define _3DPRIM_TRILIST           0x04
  63 #define _3DPRIM_TRISTRIP          0x05
  64 #define _3DPRIM_TRIFAN            0x06
  65 #define _3DPRIM_QUADLIST          0x07
  66 #define _3DPRIM_QUADSTRIP         0x08
  67 #define _3DPRIM_LINELIST_ADJ      0x09 /* G45+ */
  68 #define _3DPRIM_LINESTRIP_ADJ     0x0A /* G45+ */
  69 #define _3DPRIM_TRILIST_ADJ       0x0B /* G45+ */
  70 #define _3DPRIM_TRISTRIP_ADJ      0x0C /* G45+ */
  71 #define _3DPRIM_TRISTRIP_REVERSE  0x0D
  72 #define _3DPRIM_POLYGON           0x0E
  73 #define _3DPRIM_RECTLIST          0x0F
  74 #define _3DPRIM_LINELOOP          0x10
  75 #define _3DPRIM_POINTLIST_BF      0x11
  76 #define _3DPRIM_LINESTRIP_CONT    0x12
  77 #define _3DPRIM_LINESTRIP_BF      0x13
  78 #define _3DPRIM_LINESTRIP_CONT_BF 0x14
  79 #define _3DPRIM_TRIFAN_NOSTIPPLE  0x16
  80 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); })
  81
  82 /* Bitfields for the URB_WRITE message, DW2 of message header: */
  83 #define URB_WRITE_PRIM_END              0x1
  84 #define URB_WRITE_PRIM_START            0x2
  85 #define URB_WRITE_PRIM_TYPE_SHIFT       2
  86
  87 #define BRW_SPRITE_POINT_ENABLE  16
  88
  89 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT          0
  90 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID          1
  91
  92 /* Execution Unit (EU) defines
  93  */
  94
  95 #define BRW_ALIGN_1   0
  96 #define BRW_ALIGN_16  1
  97
  98 #define BRW_ADDRESS_DIRECT                        0
  99 #define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER    1
 100
 101 #define BRW_CHANNEL_X     0
 102 #define BRW_CHANNEL_Y     1
 103 #define BRW_CHANNEL_Z     2
 104 #define BRW_CHANNEL_W     3
 105
 106 enum brw_compression {
 107    BRW_COMPRESSION_NONE       = 0,
 108    BRW_COMPRESSION_2NDHALF    = 1,
 109    BRW_COMPRESSION_COMPRESSED = 2,
 110 };
 111
 112 #define GEN6_COMPRESSION_1Q             0
 113 #define GEN6_COMPRESSION_2Q             1
 114 #define GEN6_COMPRESSION_3Q             2
 115 #define GEN6_COMPRESSION_4Q             3
 116 #define GEN6_COMPRESSION_1H             0
 117 #define GEN6_COMPRESSION_2H             2
 118
 119 enum PACKED brw_conditional_mod {
 120    BRW_CONDITIONAL_NONE = 0,
 121    BRW_CONDITIONAL_Z    = 1,
 122    BRW_CONDITIONAL_NZ   = 2,
 123    BRW_CONDITIONAL_EQ   = 1,    /* Z */
 124    BRW_CONDITIONAL_NEQ  = 2,    /* NZ */
 125    BRW_CONDITIONAL_G    = 3,
 126    BRW_CONDITIONAL_GE   = 4,
 127    BRW_CONDITIONAL_L    = 5,
 128    BRW_CONDITIONAL_LE   = 6,
 129    BRW_CONDITIONAL_R    = 7,    /* Gen <= 5 */
 130    BRW_CONDITIONAL_O    = 8,
 131    BRW_CONDITIONAL_U    = 9,
 132 };
 133
 134 #define BRW_DEBUG_NONE        0
 135 #define BRW_DEBUG_BREAKPOINT  1
 136
 137 #define BRW_DEPENDENCY_NORMAL         0
 138 #define BRW_DEPENDENCY_NOTCLEARED     1
 139 #define BRW_DEPENDENCY_NOTCHECKED     2
 140 #define BRW_DEPENDENCY_DISABLE        3
 141
 142 enum PACKED brw_execution_size {
 143    BRW_EXECUTE_1  = 0,
 144    BRW_EXECUTE_2  = 1,
 145    BRW_EXECUTE_4  = 2,
 146    BRW_EXECUTE_8  = 3,
 147    BRW_EXECUTE_16 = 4,
 148    BRW_EXECUTE_32 = 5,
 149 };
 150
 151 enum PACKED brw_horizontal_stride {
 152    BRW_HORIZONTAL_STRIDE_0 = 0,
 153    BRW_HORIZONTAL_STRIDE_1 = 1,
 154    BRW_HORIZONTAL_STRIDE_2 = 2,
 155    BRW_HORIZONTAL_STRIDE_4 = 3,
 156 };
 157
 158 enum PACKED gen10_align1_3src_src_horizontal_stride {
 159    BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 = 0,
 160    BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1 = 1,
 161    BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2 = 2,
 162    BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4 = 3,
 163 };
 164
 165 enum PACKED gen10_align1_3src_dst_horizontal_stride {
 166    BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1 = 0,
 167    BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_2 = 1,
 168 };
 169
 170 #define BRW_INSTRUCTION_NORMAL    0
 171 #define BRW_INSTRUCTION_SATURATE  1
 172
 173 #define BRW_MASK_ENABLE   0
 174 #define BRW_MASK_DISABLE  1
 175
 176 /** @{
 177  *
 178  * Gen6 has replaced "mask enable/disable" with WECtrl, which is
 179  * effectively the same but much simpler to think about.  Now, there
 180  * are two contributors ANDed together to whether channels are
 181  * executed: The predication on the instruction, and the channel write
 182  * enable.
 183  */
 184 /**
 185  * This is the default value.  It means that a channel's write enable is set
 186  * if the per-channel IP is pointing at this instruction.
 187  */
 188 #define BRW_WE_NORMAL           0
 189 /**
 190  * This is used like BRW_MASK_DISABLE, and causes all channels to have
 191  * their write enable set.  Note that predication still contributes to
 192  * whether the channel actually gets written.
 193  */
 194 #define BRW_WE_ALL              1
 195 /** @} */
 196
 197 enum opcode {
 198    /* These are the actual hardware instructions. */
 199    BRW_OPCODE_ILLEGAL,
 200    BRW_OPCODE_SYNC,
 201    BRW_OPCODE_MOV,
 202    BRW_OPCODE_SEL,
 203    BRW_OPCODE_MOVI, /**< G45+ */
 204    BRW_OPCODE_NOT,
 205    BRW_OPCODE_AND,
 206    BRW_OPCODE_OR,
 207    BRW_OPCODE_XOR,
 208    BRW_OPCODE_SHR,
 209    BRW_OPCODE_SHL,
 210    BRW_OPCODE_DIM, /**< Gen7.5 only */
 211    BRW_OPCODE_SMOV, /**< Gen8+ */
 212    BRW_OPCODE_ASR,
 213    BRW_OPCODE_ROR,  /**< Gen11+ */
 214    BRW_OPCODE_ROL,  /**< Gen11+ */
 215    BRW_OPCODE_CMP,
 216    BRW_OPCODE_CMPN,
 217    BRW_OPCODE_CSEL, /**< Gen8+ */
 218    BRW_OPCODE_F32TO16, /**< Gen7 only */
 219    BRW_OPCODE_F16TO32, /**< Gen7 only */
 220    BRW_OPCODE_BFREV, /**< Gen7+ */
 221    BRW_OPCODE_BFE, /**< Gen7+ */
 222    BRW_OPCODE_BFI1, /**< Gen7+ */
 223    BRW_OPCODE_BFI2, /**< Gen7+ */
 224    BRW_OPCODE_JMPI,
 225    BRW_OPCODE_BRD, /**< Gen7+ */
 226    BRW_OPCODE_IF,
 227    BRW_OPCODE_IFF, /**< Pre-Gen6 */
 228    BRW_OPCODE_BRC, /**< Gen7+ */
 229    BRW_OPCODE_ELSE,
 230    BRW_OPCODE_ENDIF,
 231    BRW_OPCODE_DO, /**< Pre-Gen6 */
 232    BRW_OPCODE_CASE, /**< Gen6 only */
 233    BRW_OPCODE_WHILE,
 234    BRW_OPCODE_BREAK,
 235    BRW_OPCODE_CONTINUE,
 236    BRW_OPCODE_HALT,
 237    BRW_OPCODE_CALLA, /**< Gen7.5+ */
 238    BRW_OPCODE_MSAVE, /**< Pre-Gen6 */
 239    BRW_OPCODE_CALL, /**< Gen6+ */
 240    BRW_OPCODE_MREST, /**< Pre-Gen6 */
 241    BRW_OPCODE_RET, /**< Gen6+ */
 242    BRW_OPCODE_PUSH, /**< Pre-Gen6 */
 243    BRW_OPCODE_FORK, /**< Gen6 only */
 244    BRW_OPCODE_GOTO, /**< Gen8+ */
 245    BRW_OPCODE_POP, /**< Pre-Gen6 */
 246    BRW_OPCODE_WAIT,
 247    BRW_OPCODE_SEND,
 248    BRW_OPCODE_SENDC,
 249    BRW_OPCODE_SENDS, /**< Gen9+ */
 250    BRW_OPCODE_SENDSC, /**< Gen9+ */
 251    BRW_OPCODE_MATH, /**< Gen6+ */
 252    BRW_OPCODE_ADD,
 253    BRW_OPCODE_MUL,
 254    BRW_OPCODE_AVG,
 255    BRW_OPCODE_FRC,
 256    BRW_OPCODE_RNDU,
 257    BRW_OPCODE_RNDD,
 258    BRW_OPCODE_RNDE,
 259    BRW_OPCODE_RNDZ,
 260    BRW_OPCODE_MAC,
 261    BRW_OPCODE_MACH,
 262    BRW_OPCODE_LZD,
 263    BRW_OPCODE_FBH, /**< Gen7+ */
 264    BRW_OPCODE_FBL, /**< Gen7+ */
 265    BRW_OPCODE_CBIT, /**< Gen7+ */
 266    BRW_OPCODE_ADDC, /**< Gen7+ */
 267    BRW_OPCODE_SUBB, /**< Gen7+ */
 268    BRW_OPCODE_SAD2,
 269    BRW_OPCODE_SADA2,
 270    BRW_OPCODE_DP4,
 271    BRW_OPCODE_DPH,
 272    BRW_OPCODE_DP3,
 273    BRW_OPCODE_DP2,
 274    BRW_OPCODE_LINE,
 275    BRW_OPCODE_PLN, /**< G45+ */
 276    BRW_OPCODE_MAD, /**< Gen6+ */
 277    BRW_OPCODE_LRP, /**< Gen6+ */
 278    BRW_OPCODE_MADM, /**< Gen8+ */
 279    BRW_OPCODE_NENOP, /**< G45 only */
 280    BRW_OPCODE_NOP,
 281
 282    NUM_BRW_OPCODES,
 283
 284    /* These are compiler backend opcodes that get translated into other
 285     * instructions.
 286     */
 287    FS_OPCODE_FB_WRITE = NUM_BRW_OPCODES,
 288
 289    /**
 290     * Same as FS_OPCODE_FB_WRITE but expects its arguments separately as
 291     * individual sources instead of as a single payload blob. The
 292     * position/ordering of the arguments are defined by the enum
 293     * fb_write_logical_srcs.
 294     */
 295    FS_OPCODE_FB_WRITE_LOGICAL,
 296
 297    FS_OPCODE_REP_FB_WRITE,
 298
 299    FS_OPCODE_FB_READ,
 300    FS_OPCODE_FB_READ_LOGICAL,
 301
 302    SHADER_OPCODE_RCP,
 303    SHADER_OPCODE_RSQ,
 304    SHADER_OPCODE_SQRT,
 305    SHADER_OPCODE_EXP2,
 306    SHADER_OPCODE_LOG2,
 307    SHADER_OPCODE_POW,
 308    SHADER_OPCODE_INT_QUOTIENT,
 309    SHADER_OPCODE_INT_REMAINDER,
 310    SHADER_OPCODE_SIN,
 311    SHADER_OPCODE_COS,
 312
 313    /**
 314     * A generic "send" opcode.  The first two sources are the message
 315     * descriptor and extended message descriptor respectively.  The third
 316     * and optional fourth sources are the message payload
 317     */
 318    SHADER_OPCODE_SEND,
 319
 320    /**
 321     * An "undefined" write which does nothing but indicates to liveness that
 322     * we don't care about any values in the register which predate this
 323     * instruction.  Used to prevent partial writes from causing issues with
 324     * live ranges.
 325     */
 326    SHADER_OPCODE_UNDEF,
 327
 328    /**
 329     * Texture sampling opcodes.
 330     *
 331     * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
 332     * opcode but instead of taking a single payload blob they expect their
 333     * arguments separately as individual sources. The position/ordering of the
 334     * arguments are defined by the enum tex_logical_srcs.
 335     */
 336    SHADER_OPCODE_TEX,
 337    SHADER_OPCODE_TEX_LOGICAL,
 338    SHADER_OPCODE_TXD,
 339    SHADER_OPCODE_TXD_LOGICAL,
 340    SHADER_OPCODE_TXF,
 341    SHADER_OPCODE_TXF_LOGICAL,
 342    SHADER_OPCODE_TXF_LZ,
 343    SHADER_OPCODE_TXL,
 344    SHADER_OPCODE_TXL_LOGICAL,
 345    SHADER_OPCODE_TXL_LZ,
 346    SHADER_OPCODE_TXS,
 347    SHADER_OPCODE_TXS_LOGICAL,
 348    FS_OPCODE_TXB,
 349    FS_OPCODE_TXB_LOGICAL,
 350    SHADER_OPCODE_TXF_CMS,
 351    SHADER_OPCODE_TXF_CMS_LOGICAL,
 352    SHADER_OPCODE_TXF_CMS_W,
 353    SHADER_OPCODE_TXF_CMS_W_LOGICAL,
 354    SHADER_OPCODE_TXF_UMS,
 355    SHADER_OPCODE_TXF_UMS_LOGICAL,
 356    SHADER_OPCODE_TXF_MCS,
 357    SHADER_OPCODE_TXF_MCS_LOGICAL,
 358    SHADER_OPCODE_LOD,
 359    SHADER_OPCODE_LOD_LOGICAL,
 360    SHADER_OPCODE_TG4,
 361    SHADER_OPCODE_TG4_LOGICAL,
 362    SHADER_OPCODE_TG4_OFFSET,
 363    SHADER_OPCODE_TG4_OFFSET_LOGICAL,
 364    SHADER_OPCODE_SAMPLEINFO,
 365    SHADER_OPCODE_SAMPLEINFO_LOGICAL,
 366
 367    SHADER_OPCODE_IMAGE_SIZE_LOGICAL,
 368
 369    /**
 370     * Combines multiple sources of size 1 into a larger virtual GRF.
 371     * For example, parameters for a send-from-GRF message.  Or, updating
 372     * channels of a size 4 VGRF used to store vec4s such as texturing results.
 373     *
 374     * This will be lowered into MOVs from each source to consecutive offsets
 375     * of the destination VGRF.
 376     *
 377     * src[0] may be BAD_FILE.  If so, the lowering pass skips emitting the MOV,
 378     * but still reserves the first channel of the destination VGRF.  This can be
 379     * used to reserve space for, say, a message header set up by the generators.
 380     */
 381    SHADER_OPCODE_LOAD_PAYLOAD,
 382
 383    /**
 384     * Packs a number of sources into a single value. Unlike LOAD_PAYLOAD, this
 385     * acts intra-channel, obtaining the final value for each channel by
 386     * combining the sources values for the same channel, the first source
 387     * occupying the lowest bits and the last source occupying the highest
 388     * bits.
 389     */
 390    FS_OPCODE_PACK,
 391
 392    SHADER_OPCODE_SHADER_TIME_ADD,
 393
 394    /**
 395     * Typed and untyped surface access opcodes.
 396     *
 397     * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
 398     * opcode but instead of taking a single payload blob they expect their
 399     * arguments separately as individual sources:
 400     *
 401     * Source 0: [required] Surface coordinates.
 402     * Source 1: [optional] Operation source.
 403     * Source 2: [required] Surface index.
 404     * Source 3: [required] Number of coordinate components (as UD immediate).
 405     * Source 4: [required] Opcode-specific control immediate, same as source 2
 406     *                      of the matching non-LOGICAL opcode.
 407     */
 408    VEC4_OPCODE_UNTYPED_ATOMIC,
 409    SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
 410    SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL,
 411    VEC4_OPCODE_UNTYPED_SURFACE_READ,
 412    SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
 413    VEC4_OPCODE_UNTYPED_SURFACE_WRITE,
 414    SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
 415
 416    /**
 417     * Untyped A64 surface access opcodes.
 418     *
 419     * Source 0: 64-bit address
 420     * Source 1: Operational source
 421     * Source 2: [required] Opcode-specific control immediate, same as source 2
 422     *                      of the matching non-LOGICAL opcode.
 423     */
 424    SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL,
 425    SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL,
 426    SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL,
 427    SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL,
 428    SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL,
 429    SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL,
 430    SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL,
 431
 432    SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
 433    SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
 434    SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
 435
 436    SHADER_OPCODE_RND_MODE,
 437    SHADER_OPCODE_FLOAT_CONTROL_MODE,
 438
 439    /**
 440     * Byte scattered write/read opcodes.
 441     *
 442     * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
 443     * opcode, but instead of taking a single payload blog they expect their
 444     * arguments separately as individual sources, like untyped write/read.
 445     */
 446    SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
 447    SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
 448
 449    /**
 450     * Memory fence messages.
 451     *
 452     * Source 0: Must be register g0, used as header.
 453     * Source 1: Immediate bool to indicate whether or not we need to stall
 454     *           until memory transactions prior to the fence are completed.
 455     * Source 2: Immediate byte indicating which memory to fence.  Zero means
 456     *           global memory; GEN7_BTI_SLM means SLM (for Gen11+ only).
 457     *
 458     * Vec4 backend only uses Source 0.
 459     */
 460    SHADER_OPCODE_MEMORY_FENCE,
 461
 462    SHADER_OPCODE_GEN4_SCRATCH_READ,
 463    SHADER_OPCODE_GEN4_SCRATCH_WRITE,
 464    SHADER_OPCODE_GEN7_SCRATCH_READ,
 465
 466    /**
 467     * Gen8+ SIMD8 URB Read messages.
 468     */
 469    SHADER_OPCODE_URB_READ_SIMD8,
 470    SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT,
 471
 472    SHADER_OPCODE_URB_WRITE_SIMD8,
 473    SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT,
 474    SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,
 475    SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT,
 476
 477    /**
 478     * Return the index of an arbitrary live channel (i.e. one of the channels
 479     * enabled in the current execution mask) and assign it to the first
 480     * component of the destination.  Expected to be used as input for the
 481     * BROADCAST pseudo-opcode.
 482     */
 483    SHADER_OPCODE_FIND_LIVE_CHANNEL,
 484
 485    /**
 486     * Pick the channel from its first source register given by the index
 487     * specified as second source.  Useful for variable indexing of surfaces.
 488     *
 489     * Note that because the result of this instruction is by definition
 490     * uniform and it can always be splatted to multiple channels using a
 491     * scalar regioning mode, only the first channel of the destination region
 492     * is guaranteed to be updated, which implies that BROADCAST instructions
 493     * should usually be marked force_writemask_all.
 494     */
 495    SHADER_OPCODE_BROADCAST,
 496
 497    /* Pick the channel from its first source register given by the index
 498     * specified as second source.
 499     *
 500     * This is similar to the BROADCAST instruction except that it takes a
 501     * dynamic index and potentially puts a different value in each output
 502     * channel.
 503     */
 504    SHADER_OPCODE_SHUFFLE,
 505
 506    /* Select between src0 and src1 based on channel enables.
 507     *
 508     * This instruction copies src0 into the enabled channels of the
 509     * destination and copies src1 into the disabled channels.
 510     */
 511    SHADER_OPCODE_SEL_EXEC,
 512
 513    /* This turns into an align16 mov from src0 to dst with a swizzle
 514     * provided as an immediate in src1.
 515     */
 516    SHADER_OPCODE_QUAD_SWIZZLE,
 517
 518    /* Take every Nth element in src0 and broadcast it to the group of N
 519     * channels in which it lives in the destination.  The offset within the
 520     * cluster is given by src1 and the cluster size is given by src2.
 521     */
 522    SHADER_OPCODE_CLUSTER_BROADCAST,
 523
 524    SHADER_OPCODE_GET_BUFFER_SIZE,
 525
 526    SHADER_OPCODE_INTERLOCK,
 527
 528    VEC4_OPCODE_MOV_BYTES,
 529    VEC4_OPCODE_PACK_BYTES,
 530    VEC4_OPCODE_UNPACK_UNIFORM,
 531    VEC4_OPCODE_DOUBLE_TO_F32,
 532    VEC4_OPCODE_DOUBLE_TO_D32,
 533    VEC4_OPCODE_DOUBLE_TO_U32,
 534    VEC4_OPCODE_TO_DOUBLE,
 535    VEC4_OPCODE_PICK_LOW_32BIT,
 536    VEC4_OPCODE_PICK_HIGH_32BIT,
 537    VEC4_OPCODE_SET_LOW_32BIT,
 538    VEC4_OPCODE_SET_HIGH_32BIT,
 539
 540    FS_OPCODE_DDX_COARSE,
 541    FS_OPCODE_DDX_FINE,
 542    /**
 543     * Compute dFdy(), dFdyCoarse(), or dFdyFine().
 544     */
 545    FS_OPCODE_DDY_COARSE,
 546    FS_OPCODE_DDY_FINE,
 547    FS_OPCODE_LINTERP,
 548    FS_OPCODE_PIXEL_X,
 549    FS_OPCODE_PIXEL_Y,
 550    FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
 551    FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7,
 552    FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4,
 553    FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
 554    FS_OPCODE_DISCARD_JUMP,
 555    FS_OPCODE_SET_SAMPLE_ID,
 556    FS_OPCODE_PACK_HALF_2x16_SPLIT,
 557    FS_OPCODE_PLACEHOLDER_HALT,
 558    FS_OPCODE_INTERPOLATE_AT_SAMPLE,
 559    FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
 560    FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET,
 561
 562    VS_OPCODE_URB_WRITE,
 563    VS_OPCODE_PULL_CONSTANT_LOAD,
 564    VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
 565    VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
 566
 567    VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
 568
 569    /**
 570     * Write geometry shader output data to the URB.
 571     *
 572     * Unlike VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
 573     * R0 to the first MRF.  This allows the geometry shader to override the
 574     * "Slot {0,1} Offset" fields in the message header.
 575     */
 576    GS_OPCODE_URB_WRITE,
 577
 578    /**
 579     * Write geometry shader output data to the URB and request a new URB
 580     * handle (gen6).
 581     *
 582     * This opcode doesn't do an implied move from R0 to the first MRF.
 583     */
 584    GS_OPCODE_URB_WRITE_ALLOCATE,
 585
 586    /**
 587     * Terminate the geometry shader thread by doing an empty URB write.
 588     *
 589     * This opcode doesn't do an implied move from R0 to the first MRF.  This
 590     * allows the geometry shader to override the "GS Number of Output Vertices
 591     * for Slot {0,1}" fields in the message header.
 592     */
 593    GS_OPCODE_THREAD_END,
 594
 595    /**
 596     * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header.
 597     *
 598     * - dst is the MRF containing the message header.
 599     *
 600     * - src0.x indicates which portion of the URB should be written to (e.g. a
 601     *   vertex number)
 602     *
 603     * - src1 is an immediate multiplier which will be applied to src0
 604     *   (e.g. the size of a single vertex in the URB).
 605     *
 606     * Note: the hardware will apply this offset *in addition to* the offset in
 607     * vec4_instruction::offset.
 608     */
 609    GS_OPCODE_SET_WRITE_OFFSET,
 610
 611    /**
 612     * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a
 613     * URB_WRITE message header.
 614     *
 615     * - dst is the MRF containing the message header.
 616     *
 617     * - src0.x is the vertex count.  The upper 16 bits will be ignored.
 618     */
 619    GS_OPCODE_SET_VERTEX_COUNT,
 620
 621    /**
 622     * Set DWORD 2 of dst to the value in src.
 623     */
 624    GS_OPCODE_SET_DWORD_2,
 625
 626    /**
 627     * Prepare the dst register for storage in the "Channel Mask" fields of a
 628     * URB_WRITE message header.
 629     *
 630     * DWORD 4 of dst is shifted left by 4 bits, so that later,
 631     * GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the
 632     * final channel mask.
 633     *
 634     * Note: since GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to
 635     * form the final channel mask, DWORDs 0 and 4 of the dst register must not
 636     * have any extraneous bits set prior to execution of this opcode (that is,
 637     * they should be in the range 0x0 to 0xf).
 638     */
 639    GS_OPCODE_PREPARE_CHANNEL_MASKS,
 640
 641    /**
 642     * Set the "Channel Mask" fields of a URB_WRITE message header.
 643     *
 644     * - dst is the MRF containing the message header.
 645     *
 646     * - src.x is the channel mask, as prepared by
 647     *   GS_OPCODE_PREPARE_CHANNEL_MASKS.  DWORDs 0 and 4 are OR'ed together to
 648     *   form the final channel mask.
 649     */
 650    GS_OPCODE_SET_CHANNEL_MASKS,
 651
 652    /**
 653     * Get the "Instance ID" fields from the payload.
 654     *
 655     * - dst is the GRF for gl_InvocationID.
 656     */
 657    GS_OPCODE_GET_INSTANCE_ID,
 658
 659    /**
 660     * Send a FF_SYNC message to allocate initial URB handles (gen6).
 661     *
 662     * - dst will be used as the writeback register for the FF_SYNC operation.
 663     *
 664     * - src0 is the number of primitives written.
 665     *
 666     * - src1 is the value to hold in M0.0: number of SO vertices to write
 667     *   and number of SO primitives needed. Its value will be overwritten
 668     *   with the SVBI values if transform feedback is enabled.
 669     *
 670     * Note: This opcode uses an implicit MRF register for the ff_sync message
 671     * header, so the caller is expected to set inst->base_mrf and initialize
 672     * that MRF register to r0. This opcode will also write to this MRF register
 673     * to include the allocated URB handle so it can then be reused directly as
 674     * the header in the URB write operation we are allocating the handle for.
 675     */
 676    GS_OPCODE_FF_SYNC,
 677
 678    /**
 679     * Move r0.1 (which holds PrimitiveID information in gen6) to a separate
 680     * register.
 681     *
 682     * - dst is the GRF where PrimitiveID information will be moved.
 683     */
 684    GS_OPCODE_SET_PRIMITIVE_ID,
 685
 686    /**
 687     * Write transform feedback data to the SVB by sending a SVB WRITE message.
 688     * Used in gen6.
 689     *
 690     * - dst is the MRF register containing the message header.
 691     *
 692     * - src0 is the register where the vertex data is going to be copied from.
 693     *
 694     * - src1 is the destination register when write commit occurs.
 695     */
 696    GS_OPCODE_SVB_WRITE,
 697
 698    /**
 699     * Set destination index in the SVB write message payload (M0.5). Used
 700     * in gen6 for transform feedback.
 701     *
 702     * - dst is the header to save the destination indices for SVB WRITE.
 703     * - src is the register that holds the destination indices value.
 704     */
 705    GS_OPCODE_SVB_SET_DST_INDEX,
 706
 707    /**
 708     * Prepare Mx.0 subregister for being used in the FF_SYNC message header.
 709     * Used in gen6 for transform feedback.
 710     *
 711     * - dst will hold the register with the final Mx.0 value.
 712     *
 713     * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite)
 714     *
 715     * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded)
 716     *
 717     * - src2 is the value to hold in M0: number of SO vertices to write
 718     *   and number of SO primitives needed.
 719     */
 720    GS_OPCODE_FF_SYNC_SET_PRIMITIVES,
 721
 722    /**
 723     * Terminate the compute shader.
 724     */
 725    CS_OPCODE_CS_TERMINATE,
 726
 727    /**
 728     * GLSL barrier()
 729     */
 730    SHADER_OPCODE_BARRIER,
 731
 732    /**
 733     * Calculate the high 32-bits of a 32x32 multiply.
 734     */
 735    SHADER_OPCODE_MULH,
 736
 737    /**
 738     * A MOV that uses VxH indirect addressing.
 739     *
 740     * Source 0: A register to start from (HW_REG).
 741     * Source 1: An indirect offset (in bytes, UD GRF).
 742     * Source 2: The length of the region that could be accessed (in bytes,
 743     *           UD immediate).
 744     */
 745    SHADER_OPCODE_MOV_INDIRECT,
 746
 747    VEC4_OPCODE_URB_READ,
 748    TCS_OPCODE_GET_INSTANCE_ID,
 749    TCS_OPCODE_URB_WRITE,
 750    TCS_OPCODE_SET_INPUT_URB_OFFSETS,
 751    TCS_OPCODE_SET_OUTPUT_URB_OFFSETS,
 752    TCS_OPCODE_GET_PRIMITIVE_ID,
 753    TCS_OPCODE_CREATE_BARRIER_HEADER,
 754    TCS_OPCODE_SRC0_010_IS_ZERO,
 755    TCS_OPCODE_RELEASE_INPUT,
 756    TCS_OPCODE_THREAD_END,
 757
 758    TES_OPCODE_GET_PRIMITIVE_ID,
 759    TES_OPCODE_CREATE_INPUT_READ_HEADER,
 760    TES_OPCODE_ADD_INDIRECT_URB_OFFSET,
 761 };
 762
 763 enum brw_urb_write_flags {
 764    BRW_URB_WRITE_NO_FLAGS = 0,
 765
 766    /**
 767     * Causes a new URB entry to be allocated, and its address stored in the
 768     * destination register (gen < 7).
 769     */
 770    BRW_URB_WRITE_ALLOCATE = 0x1,
 771
 772    /**
 773     * Causes the current URB entry to be deallocated (gen < 7).
 774     */
 775    BRW_URB_WRITE_UNUSED = 0x2,
 776
 777    /**
 778     * Causes the thread to terminate.
 779     */
 780    BRW_URB_WRITE_EOT = 0x4,
 781
 782    /**
 783     * Indicates that the given URB entry is complete, and may be sent further
 784     * down the 3D pipeline (gen < 7).
 785     */
 786    BRW_URB_WRITE_COMPLETE = 0x8,
 787
 788    /**
 789     * Indicates that an additional offset (which may be different for the two
 790     * vec4 slots) is stored in the message header (gen == 7).
 791     */
 792    BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10,
 793
 794    /**
 795     * Indicates that the channel masks in the URB_WRITE message header should
 796     * not be overridden to 0xff (gen == 7).
 797     */
 798    BRW_URB_WRITE_USE_CHANNEL_MASKS = 0x20,
 799
 800    /**
 801     * Indicates that the data should be sent to the URB using the
 802     * URB_WRITE_OWORD message rather than URB_WRITE_HWORD (gen == 7).  This
 803     * causes offsets to be interpreted as multiples of an OWORD instead of an
 804     * HWORD, and only allows one OWORD to be written.
 805     */
 806    BRW_URB_WRITE_OWORD = 0x40,
 807
 808    /**
 809     * Convenient combination of flags: end the thread while simultaneously
 810     * marking the given URB entry as complete.
 811     */
 812    BRW_URB_WRITE_EOT_COMPLETE = BRW_URB_WRITE_EOT | BRW_URB_WRITE_COMPLETE,
 813
 814    /**
 815     * Convenient combination of flags: mark the given URB entry as complete
 816     * and simultaneously allocate a new one.
 817     */
 818    BRW_URB_WRITE_ALLOCATE_COMPLETE =
 819       BRW_URB_WRITE_ALLOCATE | BRW_URB_WRITE_COMPLETE,
 820 };
 821
 822 enum fb_write_logical_srcs {
 823    FB_WRITE_LOGICAL_SRC_COLOR0,      /* REQUIRED */
 824    FB_WRITE_LOGICAL_SRC_COLOR1,      /* for dual source blend messages */
 825    FB_WRITE_LOGICAL_SRC_SRC0_ALPHA,
 826    FB_WRITE_LOGICAL_SRC_SRC_DEPTH,   /* gl_FragDepth */
 827    FB_WRITE_LOGICAL_SRC_DST_DEPTH,   /* GEN4-5: passthrough from thread */
 828    FB_WRITE_LOGICAL_SRC_SRC_STENCIL, /* gl_FragStencilRefARB */
 829    FB_WRITE_LOGICAL_SRC_OMASK,       /* Sample Mask (gl_SampleMask) */
 830    FB_WRITE_LOGICAL_SRC_COMPONENTS,  /* REQUIRED */
 831    FB_WRITE_LOGICAL_NUM_SRCS
 832 };
 833
 834 enum tex_logical_srcs {
 835    /** Texture coordinates */
 836    TEX_LOGICAL_SRC_COORDINATE,
 837    /** Shadow comparator */
 838    TEX_LOGICAL_SRC_SHADOW_C,
 839    /** dPdx if the operation takes explicit derivatives, otherwise LOD value */
 840    TEX_LOGICAL_SRC_LOD,
 841    /** dPdy if the operation takes explicit derivatives */
 842    TEX_LOGICAL_SRC_LOD2,
 843    /** Min LOD */
 844    TEX_LOGICAL_SRC_MIN_LOD,
 845    /** Sample index */
 846    TEX_LOGICAL_SRC_SAMPLE_INDEX,
 847    /** MCS data */
 848    TEX_LOGICAL_SRC_MCS,
 849    /** REQUIRED: Texture surface index */
 850    TEX_LOGICAL_SRC_SURFACE,
 851    /** Texture sampler index */
 852    TEX_LOGICAL_SRC_SAMPLER,
 853    /** Texture surface bindless handle */
 854    TEX_LOGICAL_SRC_SURFACE_HANDLE,
 855    /** Texture sampler bindless handle */
 856    TEX_LOGICAL_SRC_SAMPLER_HANDLE,
 857    /** Texel offset for gathers */
 858    TEX_LOGICAL_SRC_TG4_OFFSET,
 859    /** REQUIRED: Number of coordinate components (as UD immediate) */
 860    TEX_LOGICAL_SRC_COORD_COMPONENTS,
 861    /** REQUIRED: Number of derivative components (as UD immediate) */
 862    TEX_LOGICAL_SRC_GRAD_COMPONENTS,
 863
 864    TEX_LOGICAL_NUM_SRCS,
 865 };
 866
 867 enum surface_logical_srcs {
 868    /** Surface binding table index */
 869    SURFACE_LOGICAL_SRC_SURFACE,
 870    /** Surface bindless handle */
 871    SURFACE_LOGICAL_SRC_SURFACE_HANDLE,
 872    /** Surface address; could be multi-dimensional for typed opcodes */
 873    SURFACE_LOGICAL_SRC_ADDRESS,
 874    /** Data to be written or used in an atomic op */
 875    SURFACE_LOGICAL_SRC_DATA,
 876    /** Surface number of dimensions.  Affects the size of ADDRESS */
 877    SURFACE_LOGICAL_SRC_IMM_DIMS,
 878    /** Per-opcode immediate argument.  For atomics, this is the atomic opcode */
 879    SURFACE_LOGICAL_SRC_IMM_ARG,
 880
 881    SURFACE_LOGICAL_NUM_SRCS
 882 };
 883
 884 #ifdef __cplusplus
 885 /**
 886  * Allow brw_urb_write_flags enums to be ORed together.
 887  */
 888 inline brw_urb_write_flags
 889 operator|(brw_urb_write_flags x, brw_urb_write_flags y)
 890 {
 891    return static_cast<brw_urb_write_flags>(static_cast<int>(x) |
 892                                            static_cast<int>(y));
 893 }
 894 #endif
 895
 896 enum PACKED brw_predicate {
 897    BRW_PREDICATE_NONE                =  0,
 898    BRW_PREDICATE_NORMAL              =  1,
 899    BRW_PREDICATE_ALIGN1_ANYV         =  2,
 900    BRW_PREDICATE_ALIGN1_ALLV         =  3,
 901    BRW_PREDICATE_ALIGN1_ANY2H        =  4,
 902    BRW_PREDICATE_ALIGN1_ALL2H        =  5,
 903    BRW_PREDICATE_ALIGN1_ANY4H        =  6,
 904    BRW_PREDICATE_ALIGN1_ALL4H        =  7,
 905    BRW_PREDICATE_ALIGN1_ANY8H        =  8,
 906    BRW_PREDICATE_ALIGN1_ALL8H        =  9,
 907    BRW_PREDICATE_ALIGN1_ANY16H       = 10,
 908    BRW_PREDICATE_ALIGN1_ALL16H       = 11,
 909    BRW_PREDICATE_ALIGN1_ANY32H       = 12,
 910    BRW_PREDICATE_ALIGN1_ALL32H       = 13,
 911    BRW_PREDICATE_ALIGN16_REPLICATE_X =  2,
 912    BRW_PREDICATE_ALIGN16_REPLICATE_Y =  3,
 913    BRW_PREDICATE_ALIGN16_REPLICATE_Z =  4,
 914    BRW_PREDICATE_ALIGN16_REPLICATE_W =  5,
 915    BRW_PREDICATE_ALIGN16_ANY4H       =  6,
 916    BRW_PREDICATE_ALIGN16_ALL4H       =  7,
 917 };
 918
 919 enum PACKED brw_reg_file {
 920    BRW_ARCHITECTURE_REGISTER_FILE = 0,
 921    BRW_GENERAL_REGISTER_FILE      = 1,
 922    BRW_MESSAGE_REGISTER_FILE      = 2,
 923    BRW_IMMEDIATE_VALUE            = 3,
 924
 925    ARF = BRW_ARCHITECTURE_REGISTER_FILE,
 926    FIXED_GRF = BRW_GENERAL_REGISTER_FILE,
 927    MRF = BRW_MESSAGE_REGISTER_FILE,
 928    IMM = BRW_IMMEDIATE_VALUE,
 929
 930    /* These are not hardware values */
 931    VGRF,
 932    ATTR,
 933    UNIFORM, /* prog_data->params[reg] */
 934    BAD_FILE,
 935 };
 936
 937 enum PACKED gen10_align1_3src_reg_file {
 938    BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE = 0,
 939    BRW_ALIGN1_3SRC_IMMEDIATE_VALUE       = 1, /* src0, src2 */
 940    BRW_ALIGN1_3SRC_ACCUMULATOR           = 1, /* dest, src1 */
 941 };
 942
 943 /* CNL adds Align1 support for 3-src instructions. Bit 35 of the instruction
 944  * word is "Execution Datatype" which controls whether the instruction operates
 945  * on float or integer types. The register arguments have fields that offer
 946  * more fine control their respective types.
 947  */
 948 enum PACKED gen10_align1_3src_exec_type {
 949    BRW_ALIGN1_3SRC_EXEC_TYPE_INT   = 0,
 950    BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT = 1,
 951 };
 952
 953 #define BRW_ARF_NULL                  0x00
 954 #define BRW_ARF_ADDRESS               0x10
 955 #define BRW_ARF_ACCUMULATOR           0x20
 956 #define BRW_ARF_FLAG                  0x30
 957 #define BRW_ARF_MASK                  0x40
 958 #define BRW_ARF_MASK_STACK            0x50
 959 #define BRW_ARF_MASK_STACK_DEPTH      0x60
 960 #define BRW_ARF_STATE                 0x70
 961 #define BRW_ARF_CONTROL               0x80
 962 #define BRW_ARF_NOTIFICATION_COUNT    0x90
 963 #define BRW_ARF_IP                    0xA0
 964 #define BRW_ARF_TDR                   0xB0
 965 #define BRW_ARF_TIMESTAMP             0xC0
 966
 967 #define BRW_MRF_COMPR4                  (1 << 7)
 968
 969 #define BRW_AMASK   0
 970 #define BRW_IMASK   1
 971 #define BRW_LMASK   2
 972 #define BRW_CMASK   3
 973
 974
 975
 976 #define BRW_THREAD_NORMAL     0
 977 #define BRW_THREAD_ATOMIC     1
 978 #define BRW_THREAD_SWITCH     2
 979
 980 enum PACKED brw_vertical_stride {
 981    BRW_VERTICAL_STRIDE_0               = 0,
 982    BRW_VERTICAL_STRIDE_1               = 1,
 983    BRW_VERTICAL_STRIDE_2               = 2,
 984    BRW_VERTICAL_STRIDE_4               = 3,
 985    BRW_VERTICAL_STRIDE_8               = 4,
 986    BRW_VERTICAL_STRIDE_16              = 5,
 987    BRW_VERTICAL_STRIDE_32              = 6,
 988    BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF,
 989 };
 990
 991 enum PACKED gen10_align1_3src_vertical_stride {
 992    BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0,
 993    BRW_ALIGN1_3SRC_VERTICAL_STRIDE_1 = 1,
 994    BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1,
 995    BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4 = 2,
 996    BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8 = 3,
 997 };
 998
 999 enum PACKED brw_width {
1000    BRW_WIDTH_1  = 0,
1001    BRW_WIDTH_2  = 1,
1002    BRW_WIDTH_4  = 2,
1003    BRW_WIDTH_8  = 3,
1004    BRW_WIDTH_16 = 4,
1005 };
1006
1007 /**
1008  * Message target: Shared Function ID for where to SEND a message.
1009  *
1010  * These are enumerated in the ISA reference under "send - Send Message".
1011  * In particular, see the following tables:
1012  * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition"
1013  * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor"
1014  * - Ivybridge PRM, Volume 1 Part 1, section 3.2.7 "GPE Function IDs"
1015  */
1016 enum brw_message_target {
1017    BRW_SFID_NULL                     = 0,
1018    BRW_SFID_MATH                     = 1, /* Only valid on Gen4-5 */
1019    BRW_SFID_SAMPLER                  = 2,
1020    BRW_SFID_MESSAGE_GATEWAY          = 3,
1021    BRW_SFID_DATAPORT_READ            = 4,
1022    BRW_SFID_DATAPORT_WRITE           = 5,
1023    BRW_SFID_URB                      = 6,
1024    BRW_SFID_THREAD_SPAWNER           = 7,
1025    BRW_SFID_VME                      = 8,
1026
1027    GEN6_SFID_DATAPORT_SAMPLER_CACHE  = 4,
1028    GEN6_SFID_DATAPORT_RENDER_CACHE   = 5,
1029    GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9,
1030
1031    GEN7_SFID_DATAPORT_DATA_CACHE     = 10,
1032    GEN7_SFID_PIXEL_INTERPOLATOR      = 11,
1033    HSW_SFID_DATAPORT_DATA_CACHE_1    = 12,
1034    HSW_SFID_CRE                      = 13,
1035 };
1036
1037 #define GEN7_MESSAGE_TARGET_DP_DATA_CACHE     10
1038
1039 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32     0
1040 #define BRW_SAMPLER_RETURN_FORMAT_UINT32      2
1041 #define BRW_SAMPLER_RETURN_FORMAT_SINT32      3
1042
1043 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE              0
1044 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE             0
1045 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS        0
1046 #define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX             1
1047 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD        1
1048 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD         1
1049 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS  2
1050 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS    2
1051 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE    0
1052 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE     2
1053 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0
1054 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1
1055 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE  1
1056 #define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO           2
1057 #define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO            2
1058 #define BRW_SAMPLER_MESSAGE_SIMD4X2_LD                3
1059 #define BRW_SAMPLER_MESSAGE_SIMD8_LD                  3
1060 #define BRW_SAMPLER_MESSAGE_SIMD16_LD                 3
1061
1062 #define GEN5_SAMPLER_MESSAGE_SAMPLE              0
1063 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS         1
1064 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD          2
1065 #define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE      3
1066 #define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS       4
1067 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
1068 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE  6
1069 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LD           7
1070 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4      8
1071 #define GEN5_SAMPLER_MESSAGE_LOD                 9
1072 #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO      10
1073 #define GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO   11
1074 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C    16
1075 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO   17
1076 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
1077 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
1078 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LZ           24
1079 #define GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ         25
1080 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ        26
1081 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W     28
1082 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS       29
1083 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS       30
1084 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS       31
1085
1086 /* for GEN5 only */
1087 #define BRW_SAMPLER_SIMD_MODE_SIMD4X2                   0
1088 #define BRW_SAMPLER_SIMD_MODE_SIMD8                     1
1089 #define BRW_SAMPLER_SIMD_MODE_SIMD16                    2
1090 #define BRW_SAMPLER_SIMD_MODE_SIMD32_64                 3
1091
1092 /* GEN9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2
1093  * behavior by setting bit 22 of dword 2 in the message header. */
1094 #define GEN9_SAMPLER_SIMD_MODE_SIMD8D                   0
1095 #define GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2        (1 << 22)
1096
1097 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW   0
1098 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH  1
1099 #define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS     2
1100 #define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS     3
1101 #define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS     4
1102 #define BRW_DATAPORT_OWORD_BLOCK_DWORDS(n)              \
1103    ((n) == 4 ? BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW :    \
1104     (n) == 8 ? BRW_DATAPORT_OWORD_BLOCK_2_OWORDS :      \
1105     (n) == 16 ? BRW_DATAPORT_OWORD_BLOCK_4_OWORDS :     \
1106     (n) == 32 ? BRW_DATAPORT_OWORD_BLOCK_8_OWORDS :     \
1107     (abort(), ~0))
1108
1109 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD     0
1110 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS    2
1111
1112 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS   2
1113 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS  3
1114
1115 /* This one stays the same across generations. */
1116 #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ          0
1117 /* GEN4 */
1118 #define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ     1
1119 #define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ          2
1120 #define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ      3
1121 /* G45, GEN5 */
1122 #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ         1
1123 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ     2
1124 #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ      3
1125 #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ          4
1126 #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ      6
1127 /* GEN6 */
1128 #define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ        1
1129 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ     2
1130 #define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ          4
1131 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ  5
1132 #define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ      6
1133
1134 #define BRW_DATAPORT_READ_TARGET_DATA_CACHE      0
1135 #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE    1
1136 #define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE   2
1137
1138 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE                0
1139 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED     1
1140 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01         2
1141 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23         3
1142 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01       4
1143
1144 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE                0
1145 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE           1
1146 #define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE                2
1147 #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE            3
1148 #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE              4
1149 #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE     5
1150 #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE               7
1151
1152 /* GEN6 */
1153 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE              7
1154 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE               8
1155 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE          9
1156 #define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE               10
1157 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE           11
1158 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE             12
1159 #define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE               13
1160 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE       14
1161
1162 /* GEN7 */
1163 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_READ                           4
1164 #define GEN7_DATAPORT_RC_TYPED_SURFACE_READ                         5
1165 #define GEN7_DATAPORT_RC_TYPED_ATOMIC_OP                            6
1166 #define GEN7_DATAPORT_RC_MEMORY_FENCE                               7
1167 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_WRITE                          10
1168 #define GEN7_DATAPORT_RC_RENDER_TARGET_WRITE                        12
1169 #define GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE                        13
1170 #define GEN7_DATAPORT_DC_OWORD_BLOCK_READ                           0
1171 #define GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ                 1
1172 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ                      2
1173 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_READ                       3
1174 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_READ                        4
1175 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ                       5
1176 #define GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP                          6
1177 #define GEN7_DATAPORT_DC_MEMORY_FENCE                               7
1178 #define GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE                          8
1179 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE                     10
1180 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE                      11
1181 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE                       12
1182 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE                      13
1183
1184 #define GEN7_DATAPORT_SCRATCH_READ                            ((1 << 18) | \
1185                                                                (0 << 17))
1186 #define GEN7_DATAPORT_SCRATCH_WRITE                           ((1 << 18) | \
1187                                                                (1 << 17))
1188 #define GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT                        12
1189
1190 #define GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET     0
1191 #define GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE            1
1192 #define GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID          2
1193 #define GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET   3
1194
1195 /* HSW */
1196 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ                      0
1197 #define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ            1
1198 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_READ                 2
1199 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_READ                  3
1200 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ                   4
1201 #define HSW_DATAPORT_DC_PORT0_MEMORY_FENCE                          7
1202 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_WRITE                     8
1203 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_WRITE                10
1204 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_WRITE                 11
1205 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE                  12
1206
1207 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ                  1
1208 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP                     2
1209 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2             3
1210 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ                      4
1211 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ                    5
1212 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP                       6
1213 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2               7
1214 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE                 9
1215 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE                     10
1216 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP                     11
1217 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2             12
1218 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE                   13
1219 #define GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ                   0x10
1220 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ             0x11
1221 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP                0x12
1222 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE            0x19
1223 #define GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE                  0x1a
1224 #define GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP              0x1b
1225 #define GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP          0x1d
1226
1227 /* GEN9 */
1228 #define GEN9_DATAPORT_RC_RENDER_TARGET_WRITE                        12
1229 #define GEN9_DATAPORT_RC_RENDER_TARGET_READ                         13
1230
1231 /* A64 scattered message subtype */
1232 #define GEN8_A64_SCATTERED_SUBTYPE_BYTE                             0
1233 #define GEN8_A64_SCATTERED_SUBTYPE_DWORD                            1
1234 #define GEN8_A64_SCATTERED_SUBTYPE_QWORD                            2
1235 #define GEN8_A64_SCATTERED_SUBTYPE_HWORD                            3
1236
1237 /* Dataport special binding table indices: */
1238 #define BRW_BTI_STATELESS                255
1239 #define GEN7_BTI_SLM                     254
1240 /* Note that on Gen8+ BTI 255 was redefined to be IA-coherent according to the
1241  * hardware spec, however because the DRM sets bit 4 of HDC_CHICKEN0 on BDW,
1242  * CHV and at least some pre-production steppings of SKL due to
1243  * WaForceEnableNonCoherent, HDC memory access may have been overridden by the
1244  * kernel to be non-coherent (matching the behavior of the same BTI on
1245  * pre-Gen8 hardware) and BTI 255 may actually be an alias for BTI 253.
1246  */
1247 #define GEN8_BTI_STATELESS_IA_COHERENT   255
1248 #define GEN8_BTI_STATELESS_NON_COHERENT  253
1249 #define GEN9_BTI_BINDLESS                252
1250
1251 /* Dataport atomic operations for Untyped Atomic Integer Operation message
1252  * (and others).
1253  */
1254 #define BRW_AOP_AND                   1
1255 #define BRW_AOP_OR                    2
1256 #define BRW_AOP_XOR                   3
1257 #define BRW_AOP_MOV                   4
1258 #define BRW_AOP_INC                   5
1259 #define BRW_AOP_DEC                   6
1260 #define BRW_AOP_ADD                   7
1261 #define BRW_AOP_SUB                   8
1262 #define BRW_AOP_REVSUB                9
1263 #define BRW_AOP_IMAX                  10
1264 #define BRW_AOP_IMIN                  11
1265 #define BRW_AOP_UMAX                  12
1266 #define BRW_AOP_UMIN                  13
1267 #define BRW_AOP_CMPWR                 14
1268 #define BRW_AOP_PREDEC                15
1269
1270 /* Dataport atomic operations for Untyped Atomic Float Operation message. */
1271 #define BRW_AOP_FMAX                  1
1272 #define BRW_AOP_FMIN                  2
1273 #define BRW_AOP_FCMPWR                3
1274
1275 #define BRW_MATH_FUNCTION_INV                              1
1276 #define BRW_MATH_FUNCTION_LOG                              2
1277 #define BRW_MATH_FUNCTION_EXP                              3
1278 #define BRW_MATH_FUNCTION_SQRT                             4
1279 #define BRW_MATH_FUNCTION_RSQ                              5
1280 #define BRW_MATH_FUNCTION_SIN                              6
1281 #define BRW_MATH_FUNCTION_COS                              7
1282 #define BRW_MATH_FUNCTION_SINCOS                           8 /* gen4, gen5 */
1283 #define BRW_MATH_FUNCTION_FDIV                             9 /* gen6+ */
1284 #define BRW_MATH_FUNCTION_POW                              10
1285 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER   11
1286 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT                 12
1287 #define BRW_MATH_FUNCTION_INT_DIV_REMAINDER                13
1288 #define GEN8_MATH_FUNCTION_INVM                            14
1289 #define GEN8_MATH_FUNCTION_RSQRTM                          15
1290
1291 #define BRW_MATH_INTEGER_UNSIGNED     0
1292 #define BRW_MATH_INTEGER_SIGNED       1
1293
1294 #define BRW_MATH_PRECISION_FULL        0
1295 #define BRW_MATH_PRECISION_PARTIAL     1
1296
1297 #define BRW_MATH_SATURATE_NONE         0
1298 #define BRW_MATH_SATURATE_SATURATE     1
1299
1300 #define BRW_MATH_DATA_VECTOR  0
1301 #define BRW_MATH_DATA_SCALAR  1
1302
1303 #define BRW_URB_OPCODE_WRITE_HWORD  0
1304 #define BRW_URB_OPCODE_WRITE_OWORD  1
1305 #define BRW_URB_OPCODE_READ_HWORD   2
1306 #define BRW_URB_OPCODE_READ_OWORD   3
1307 #define GEN7_URB_OPCODE_ATOMIC_MOV  4
1308 #define GEN7_URB_OPCODE_ATOMIC_INC  5
1309 #define GEN8_URB_OPCODE_ATOMIC_ADD  6
1310 #define GEN8_URB_OPCODE_SIMD8_WRITE 7
1311 #define GEN8_URB_OPCODE_SIMD8_READ  8
1312
1313 #define BRW_URB_SWIZZLE_NONE          0
1314 #define BRW_URB_SWIZZLE_INTERLEAVE    1
1315 #define BRW_URB_SWIZZLE_TRANSPOSE     2
1316
1317 #define BRW_SCRATCH_SPACE_SIZE_1K     0
1318 #define BRW_SCRATCH_SPACE_SIZE_2K     1
1319 #define BRW_SCRATCH_SPACE_SIZE_4K     2
1320 #define BRW_SCRATCH_SPACE_SIZE_8K     3
1321 #define BRW_SCRATCH_SPACE_SIZE_16K    4
1322 #define BRW_SCRATCH_SPACE_SIZE_32K    5
1323 #define BRW_SCRATCH_SPACE_SIZE_64K    6
1324 #define BRW_SCRATCH_SPACE_SIZE_128K   7
1325 #define BRW_SCRATCH_SPACE_SIZE_256K   8
1326 #define BRW_SCRATCH_SPACE_SIZE_512K   9
1327 #define BRW_SCRATCH_SPACE_SIZE_1M     10
1328 #define BRW_SCRATCH_SPACE_SIZE_2M     11
1329
1330 #define BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY         0
1331 #define BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY        1
1332 #define BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG          2
1333 #define BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP        3
1334 #define BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG          4
1335 #define BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE 5
1336 #define BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE      6
1337
1338
1339 /* Gen7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size
1340  * is 2^9, or 512.  It's counted in multiples of 64 bytes.
1341  *
1342  * Identical for VS, DS, and HS.
1343  */
1344 #define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES                (512*64)
1345 #define GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES                (512*64)
1346 #define GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES                (512*64)
1347 #define GEN7_MAX_VS_URB_ENTRY_SIZE_BYTES                (512*64)
1348
1349 /* Gen6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit
1350  * (128 bytes) URB rows and the maximum allowed value is 5 rows.
1351  */
1352 #define GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES                (5*128)
1353
1354 /* GS Thread Payload
1355  */
1356
1357 /* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62. It's
1358  * counted in multiples of 16 bytes.
1359  */
1360 #define GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES            (62*16)
1361
1362
1363 /* R0 */
1364 # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT              27
1365
1366 /* CR0.0[5:4] Floating-Point Rounding Modes
1367  *  Skylake PRM, Volume 7 Part 1, "Control Register", page 756
1368  */
1369
1370 #define BRW_CR0_RND_MODE_MASK     0x30
1371 #define BRW_CR0_RND_MODE_SHIFT    4
1372
1373 enum PACKED brw_rnd_mode {
1374    BRW_RND_MODE_RTNE = 0,  /* Round to Nearest or Even */
1375    BRW_RND_MODE_RU = 1,    /* Round Up, toward +inf */
1376    BRW_RND_MODE_RD = 2,    /* Round Down, toward -inf */
1377    BRW_RND_MODE_RTZ = 3,   /* Round Toward Zero */
1378    BRW_RND_MODE_UNSPECIFIED,  /* Unspecified rounding mode */
1379 };
1380
1381 #define BRW_CR0_FP64_DENORM_PRESERVE (1 << 6)
1382 #define BRW_CR0_FP32_DENORM_PRESERVE (1 << 7)
1383 #define BRW_CR0_FP16_DENORM_PRESERVE (1 << 10)
1384
1385 #define BRW_CR0_FP_MODE_MASK (BRW_CR0_FP64_DENORM_PRESERVE | \
1386                               BRW_CR0_FP32_DENORM_PRESERVE | \
1387                               BRW_CR0_FP16_DENORM_PRESERVE | \
1388                               BRW_CR0_RND_MODE_MASK)
1389
1390 /* MDC_DS - Data Size Message Descriptor Control Field
1391  * Skylake PRM, Volume 2d, page 129
1392  *
1393  * Specifies the number of Bytes to be read or written per Dword used at
1394  * byte_scattered read/write and byte_scaled read/write messages.
1395  */
1396 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE     0
1397 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD     1
1398 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD    2
1399
1400 #endif /* BRW_EU_DEFINES_H */