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i965: Move enums to brw_compiler.h.
[mesa.git] / src / intel / compiler / brw_eu_defines.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32 #ifndef BRW_EU_DEFINES_H
33 #define BRW_EU_DEFINES_H
34
35 #include "util/macros.h"
36
37 /* The following hunk, up-to "Execution Unit" is used by both the
38 * intel/compiler and i965 codebase. */
39
40 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
41 /* Using the GNU statement expression extension */
42 #define SET_FIELD(value, field) \
43 ({ \
44 uint32_t fieldval = (value) << field ## _SHIFT; \
45 assert((fieldval & ~ field ## _MASK) == 0); \
46 fieldval & field ## _MASK; \
47 })
48
49 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
50 #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)
51
52 #define _3DPRIM_POINTLIST 0x01
53 #define _3DPRIM_LINELIST 0x02
54 #define _3DPRIM_LINESTRIP 0x03
55 #define _3DPRIM_TRILIST 0x04
56 #define _3DPRIM_TRISTRIP 0x05
57 #define _3DPRIM_TRIFAN 0x06
58 #define _3DPRIM_QUADLIST 0x07
59 #define _3DPRIM_QUADSTRIP 0x08
60 #define _3DPRIM_LINELIST_ADJ 0x09 /* G45+ */
61 #define _3DPRIM_LINESTRIP_ADJ 0x0A /* G45+ */
62 #define _3DPRIM_TRILIST_ADJ 0x0B /* G45+ */
63 #define _3DPRIM_TRISTRIP_ADJ 0x0C /* G45+ */
64 #define _3DPRIM_TRISTRIP_REVERSE 0x0D
65 #define _3DPRIM_POLYGON 0x0E
66 #define _3DPRIM_RECTLIST 0x0F
67 #define _3DPRIM_LINELOOP 0x10
68 #define _3DPRIM_POINTLIST_BF 0x11
69 #define _3DPRIM_LINESTRIP_CONT 0x12
70 #define _3DPRIM_LINESTRIP_BF 0x13
71 #define _3DPRIM_LINESTRIP_CONT_BF 0x14
72 #define _3DPRIM_TRIFAN_NOSTIPPLE 0x16
73 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); })
74
75 /* Bitfields for the URB_WRITE message, DW2 of message header: */
76 #define URB_WRITE_PRIM_END 0x1
77 #define URB_WRITE_PRIM_START 0x2
78 #define URB_WRITE_PRIM_TYPE_SHIFT 2
79
80 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT 0
81 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID 1
82
83 /* Execution Unit (EU) defines
84 */
85
86 #define BRW_ALIGN_1 0
87 #define BRW_ALIGN_16 1
88
89 #define BRW_ADDRESS_DIRECT 0
90 #define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1
91
92 #define BRW_CHANNEL_X 0
93 #define BRW_CHANNEL_Y 1
94 #define BRW_CHANNEL_Z 2
95 #define BRW_CHANNEL_W 3
96
97 enum brw_compression {
98 BRW_COMPRESSION_NONE = 0,
99 BRW_COMPRESSION_2NDHALF = 1,
100 BRW_COMPRESSION_COMPRESSED = 2,
101 };
102
103 #define GEN6_COMPRESSION_1Q 0
104 #define GEN6_COMPRESSION_2Q 1
105 #define GEN6_COMPRESSION_3Q 2
106 #define GEN6_COMPRESSION_4Q 3
107 #define GEN6_COMPRESSION_1H 0
108 #define GEN6_COMPRESSION_2H 2
109
110 enum PACKED brw_conditional_mod {
111 BRW_CONDITIONAL_NONE = 0,
112 BRW_CONDITIONAL_Z = 1,
113 BRW_CONDITIONAL_NZ = 2,
114 BRW_CONDITIONAL_EQ = 1, /* Z */
115 BRW_CONDITIONAL_NEQ = 2, /* NZ */
116 BRW_CONDITIONAL_G = 3,
117 BRW_CONDITIONAL_GE = 4,
118 BRW_CONDITIONAL_L = 5,
119 BRW_CONDITIONAL_LE = 6,
120 BRW_CONDITIONAL_R = 7, /* Gen <= 5 */
121 BRW_CONDITIONAL_O = 8,
122 BRW_CONDITIONAL_U = 9,
123 };
124
125 #define BRW_DEBUG_NONE 0
126 #define BRW_DEBUG_BREAKPOINT 1
127
128 #define BRW_DEPENDENCY_NORMAL 0
129 #define BRW_DEPENDENCY_NOTCLEARED 1
130 #define BRW_DEPENDENCY_NOTCHECKED 2
131 #define BRW_DEPENDENCY_DISABLE 3
132
133 enum PACKED brw_execution_size {
134 BRW_EXECUTE_1 = 0,
135 BRW_EXECUTE_2 = 1,
136 BRW_EXECUTE_4 = 2,
137 BRW_EXECUTE_8 = 3,
138 BRW_EXECUTE_16 = 4,
139 BRW_EXECUTE_32 = 5,
140 };
141
142 enum PACKED brw_horizontal_stride {
143 BRW_HORIZONTAL_STRIDE_0 = 0,
144 BRW_HORIZONTAL_STRIDE_1 = 1,
145 BRW_HORIZONTAL_STRIDE_2 = 2,
146 BRW_HORIZONTAL_STRIDE_4 = 3,
147 };
148
149 #define BRW_INSTRUCTION_NORMAL 0
150 #define BRW_INSTRUCTION_SATURATE 1
151
152 #define BRW_MASK_ENABLE 0
153 #define BRW_MASK_DISABLE 1
154
155 /** @{
156 *
157 * Gen6 has replaced "mask enable/disable" with WECtrl, which is
158 * effectively the same but much simpler to think about. Now, there
159 * are two contributors ANDed together to whether channels are
160 * executed: The predication on the instruction, and the channel write
161 * enable.
162 */
163 /**
164 * This is the default value. It means that a channel's write enable is set
165 * if the per-channel IP is pointing at this instruction.
166 */
167 #define BRW_WE_NORMAL 0
168 /**
169 * This is used like BRW_MASK_DISABLE, and causes all channels to have
170 * their write enable set. Note that predication still contributes to
171 * whether the channel actually gets written.
172 */
173 #define BRW_WE_ALL 1
174 /** @} */
175
176 enum opcode {
177 /* These are the actual hardware opcodes. */
178 BRW_OPCODE_ILLEGAL = 0,
179 BRW_OPCODE_MOV = 1,
180 BRW_OPCODE_SEL = 2,
181 BRW_OPCODE_MOVI = 3, /**< G45+ */
182 BRW_OPCODE_NOT = 4,
183 BRW_OPCODE_AND = 5,
184 BRW_OPCODE_OR = 6,
185 BRW_OPCODE_XOR = 7,
186 BRW_OPCODE_SHR = 8,
187 BRW_OPCODE_SHL = 9,
188 BRW_OPCODE_DIM = 10, /**< Gen7.5 only */ /* Reused */
189 // BRW_OPCODE_SMOV = 10, /**< Gen8+ */ /* Reused */
190 /* Reserved - 11 */
191 BRW_OPCODE_ASR = 12,
192 /* Reserved - 13-15 */
193 BRW_OPCODE_CMP = 16,
194 BRW_OPCODE_CMPN = 17,
195 BRW_OPCODE_CSEL = 18, /**< Gen8+ */
196 BRW_OPCODE_F32TO16 = 19, /**< Gen7 only */
197 BRW_OPCODE_F16TO32 = 20, /**< Gen7 only */
198 /* Reserved - 21-22 */
199 BRW_OPCODE_BFREV = 23, /**< Gen7+ */
200 BRW_OPCODE_BFE = 24, /**< Gen7+ */
201 BRW_OPCODE_BFI1 = 25, /**< Gen7+ */
202 BRW_OPCODE_BFI2 = 26, /**< Gen7+ */
203 /* Reserved - 27-31 */
204 BRW_OPCODE_JMPI = 32,
205 // BRW_OPCODE_BRD = 33, /**< Gen7+ */
206 BRW_OPCODE_IF = 34,
207 BRW_OPCODE_IFF = 35, /**< Pre-Gen6 */ /* Reused */
208 // BRW_OPCODE_BRC = 35, /**< Gen7+ */ /* Reused */
209 BRW_OPCODE_ELSE = 36,
210 BRW_OPCODE_ENDIF = 37,
211 BRW_OPCODE_DO = 38, /**< Pre-Gen6 */ /* Reused */
212 // BRW_OPCODE_CASE = 38, /**< Gen6 only */ /* Reused */
213 BRW_OPCODE_WHILE = 39,
214 BRW_OPCODE_BREAK = 40,
215 BRW_OPCODE_CONTINUE = 41,
216 BRW_OPCODE_HALT = 42,
217 // BRW_OPCODE_CALLA = 43, /**< Gen7.5+ */
218 // BRW_OPCODE_MSAVE = 44, /**< Pre-Gen6 */ /* Reused */
219 // BRW_OPCODE_CALL = 44, /**< Gen6+ */ /* Reused */
220 // BRW_OPCODE_MREST = 45, /**< Pre-Gen6 */ /* Reused */
221 // BRW_OPCODE_RET = 45, /**< Gen6+ */ /* Reused */
222 // BRW_OPCODE_PUSH = 46, /**< Pre-Gen6 */ /* Reused */
223 // BRW_OPCODE_FORK = 46, /**< Gen6 only */ /* Reused */
224 // BRW_OPCODE_GOTO = 46, /**< Gen8+ */ /* Reused */
225 // BRW_OPCODE_POP = 47, /**< Pre-Gen6 */
226 BRW_OPCODE_WAIT = 48,
227 BRW_OPCODE_SEND = 49,
228 BRW_OPCODE_SENDC = 50,
229 BRW_OPCODE_SENDS = 51, /**< Gen9+ */
230 BRW_OPCODE_SENDSC = 52, /**< Gen9+ */
231 /* Reserved 53-55 */
232 BRW_OPCODE_MATH = 56, /**< Gen6+ */
233 /* Reserved 57-63 */
234 BRW_OPCODE_ADD = 64,
235 BRW_OPCODE_MUL = 65,
236 BRW_OPCODE_AVG = 66,
237 BRW_OPCODE_FRC = 67,
238 BRW_OPCODE_RNDU = 68,
239 BRW_OPCODE_RNDD = 69,
240 BRW_OPCODE_RNDE = 70,
241 BRW_OPCODE_RNDZ = 71,
242 BRW_OPCODE_MAC = 72,
243 BRW_OPCODE_MACH = 73,
244 BRW_OPCODE_LZD = 74,
245 BRW_OPCODE_FBH = 75, /**< Gen7+ */
246 BRW_OPCODE_FBL = 76, /**< Gen7+ */
247 BRW_OPCODE_CBIT = 77, /**< Gen7+ */
248 BRW_OPCODE_ADDC = 78, /**< Gen7+ */
249 BRW_OPCODE_SUBB = 79, /**< Gen7+ */
250 BRW_OPCODE_SAD2 = 80,
251 BRW_OPCODE_SADA2 = 81,
252 /* Reserved 82-83 */
253 BRW_OPCODE_DP4 = 84,
254 BRW_OPCODE_DPH = 85,
255 BRW_OPCODE_DP3 = 86,
256 BRW_OPCODE_DP2 = 87,
257 /* Reserved 88 */
258 BRW_OPCODE_LINE = 89,
259 BRW_OPCODE_PLN = 90, /**< G45+ */
260 BRW_OPCODE_MAD = 91, /**< Gen6+ */
261 BRW_OPCODE_LRP = 92, /**< Gen6+ */
262 // BRW_OPCODE_MADM = 93, /**< Gen8+ */
263 /* Reserved 94-124 */
264 BRW_OPCODE_NENOP = 125, /**< G45 only */
265 BRW_OPCODE_NOP = 126,
266 /* Reserved 127 */
267
268 /* These are compiler backend opcodes that get translated into other
269 * instructions.
270 */
271 FS_OPCODE_FB_WRITE = 128,
272
273 /**
274 * Same as FS_OPCODE_FB_WRITE but expects its arguments separately as
275 * individual sources instead of as a single payload blob. The
276 * position/ordering of the arguments are defined by the enum
277 * fb_write_logical_srcs.
278 */
279 FS_OPCODE_FB_WRITE_LOGICAL,
280
281 FS_OPCODE_REP_FB_WRITE,
282
283 FS_OPCODE_FB_READ,
284 FS_OPCODE_FB_READ_LOGICAL,
285
286 SHADER_OPCODE_RCP,
287 SHADER_OPCODE_RSQ,
288 SHADER_OPCODE_SQRT,
289 SHADER_OPCODE_EXP2,
290 SHADER_OPCODE_LOG2,
291 SHADER_OPCODE_POW,
292 SHADER_OPCODE_INT_QUOTIENT,
293 SHADER_OPCODE_INT_REMAINDER,
294 SHADER_OPCODE_SIN,
295 SHADER_OPCODE_COS,
296
297 /**
298 * Texture sampling opcodes.
299 *
300 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
301 * opcode but instead of taking a single payload blob they expect their
302 * arguments separately as individual sources. The position/ordering of the
303 * arguments are defined by the enum tex_logical_srcs.
304 */
305 SHADER_OPCODE_TEX,
306 SHADER_OPCODE_TEX_LOGICAL,
307 SHADER_OPCODE_TXD,
308 SHADER_OPCODE_TXD_LOGICAL,
309 SHADER_OPCODE_TXF,
310 SHADER_OPCODE_TXF_LOGICAL,
311 SHADER_OPCODE_TXF_LZ,
312 SHADER_OPCODE_TXL,
313 SHADER_OPCODE_TXL_LOGICAL,
314 SHADER_OPCODE_TXL_LZ,
315 SHADER_OPCODE_TXS,
316 SHADER_OPCODE_TXS_LOGICAL,
317 FS_OPCODE_TXB,
318 FS_OPCODE_TXB_LOGICAL,
319 SHADER_OPCODE_TXF_CMS,
320 SHADER_OPCODE_TXF_CMS_LOGICAL,
321 SHADER_OPCODE_TXF_CMS_W,
322 SHADER_OPCODE_TXF_CMS_W_LOGICAL,
323 SHADER_OPCODE_TXF_UMS,
324 SHADER_OPCODE_TXF_UMS_LOGICAL,
325 SHADER_OPCODE_TXF_MCS,
326 SHADER_OPCODE_TXF_MCS_LOGICAL,
327 SHADER_OPCODE_LOD,
328 SHADER_OPCODE_LOD_LOGICAL,
329 SHADER_OPCODE_TG4,
330 SHADER_OPCODE_TG4_LOGICAL,
331 SHADER_OPCODE_TG4_OFFSET,
332 SHADER_OPCODE_TG4_OFFSET_LOGICAL,
333 SHADER_OPCODE_SAMPLEINFO,
334 SHADER_OPCODE_SAMPLEINFO_LOGICAL,
335
336 /**
337 * Combines multiple sources of size 1 into a larger virtual GRF.
338 * For example, parameters for a send-from-GRF message. Or, updating
339 * channels of a size 4 VGRF used to store vec4s such as texturing results.
340 *
341 * This will be lowered into MOVs from each source to consecutive offsets
342 * of the destination VGRF.
343 *
344 * src[0] may be BAD_FILE. If so, the lowering pass skips emitting the MOV,
345 * but still reserves the first channel of the destination VGRF. This can be
346 * used to reserve space for, say, a message header set up by the generators.
347 */
348 SHADER_OPCODE_LOAD_PAYLOAD,
349
350 /**
351 * Packs a number of sources into a single value. Unlike LOAD_PAYLOAD, this
352 * acts intra-channel, obtaining the final value for each channel by
353 * combining the sources values for the same channel, the first source
354 * occupying the lowest bits and the last source occupying the highest
355 * bits.
356 */
357 FS_OPCODE_PACK,
358
359 SHADER_OPCODE_SHADER_TIME_ADD,
360
361 /**
362 * Typed and untyped surface access opcodes.
363 *
364 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
365 * opcode but instead of taking a single payload blob they expect their
366 * arguments separately as individual sources:
367 *
368 * Source 0: [required] Surface coordinates.
369 * Source 1: [optional] Operation source.
370 * Source 2: [required] Surface index.
371 * Source 3: [required] Number of coordinate components (as UD immediate).
372 * Source 4: [required] Opcode-specific control immediate, same as source 2
373 * of the matching non-LOGICAL opcode.
374 */
375 SHADER_OPCODE_UNTYPED_ATOMIC,
376 SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
377 SHADER_OPCODE_UNTYPED_SURFACE_READ,
378 SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
379 SHADER_OPCODE_UNTYPED_SURFACE_WRITE,
380 SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
381
382 SHADER_OPCODE_TYPED_ATOMIC,
383 SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
384 SHADER_OPCODE_TYPED_SURFACE_READ,
385 SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
386 SHADER_OPCODE_TYPED_SURFACE_WRITE,
387 SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
388
389 SHADER_OPCODE_MEMORY_FENCE,
390
391 SHADER_OPCODE_GEN4_SCRATCH_READ,
392 SHADER_OPCODE_GEN4_SCRATCH_WRITE,
393 SHADER_OPCODE_GEN7_SCRATCH_READ,
394
395 /**
396 * Gen8+ SIMD8 URB Read messages.
397 */
398 SHADER_OPCODE_URB_READ_SIMD8,
399 SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT,
400
401 SHADER_OPCODE_URB_WRITE_SIMD8,
402 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT,
403 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,
404 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT,
405
406 /**
407 * Return the index of an arbitrary live channel (i.e. one of the channels
408 * enabled in the current execution mask) and assign it to the first
409 * component of the destination. Expected to be used as input for the
410 * BROADCAST pseudo-opcode.
411 */
412 SHADER_OPCODE_FIND_LIVE_CHANNEL,
413
414 /**
415 * Pick the channel from its first source register given by the index
416 * specified as second source. Useful for variable indexing of surfaces.
417 *
418 * Note that because the result of this instruction is by definition
419 * uniform and it can always be splatted to multiple channels using a
420 * scalar regioning mode, only the first channel of the destination region
421 * is guaranteed to be updated, which implies that BROADCAST instructions
422 * should usually be marked force_writemask_all.
423 */
424 SHADER_OPCODE_BROADCAST,
425
426 VEC4_OPCODE_MOV_BYTES,
427 VEC4_OPCODE_PACK_BYTES,
428 VEC4_OPCODE_UNPACK_UNIFORM,
429 VEC4_OPCODE_DOUBLE_TO_F32,
430 VEC4_OPCODE_DOUBLE_TO_D32,
431 VEC4_OPCODE_DOUBLE_TO_U32,
432 VEC4_OPCODE_TO_DOUBLE,
433 VEC4_OPCODE_PICK_LOW_32BIT,
434 VEC4_OPCODE_PICK_HIGH_32BIT,
435 VEC4_OPCODE_SET_LOW_32BIT,
436 VEC4_OPCODE_SET_HIGH_32BIT,
437
438 FS_OPCODE_DDX_COARSE,
439 FS_OPCODE_DDX_FINE,
440 /**
441 * Compute dFdy(), dFdyCoarse(), or dFdyFine().
442 */
443 FS_OPCODE_DDY_COARSE,
444 FS_OPCODE_DDY_FINE,
445 FS_OPCODE_CINTERP,
446 FS_OPCODE_LINTERP,
447 FS_OPCODE_PIXEL_X,
448 FS_OPCODE_PIXEL_Y,
449 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
450 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7,
451 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4,
452 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7,
453 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
454 FS_OPCODE_GET_BUFFER_SIZE,
455 FS_OPCODE_MOV_DISPATCH_TO_FLAGS,
456 FS_OPCODE_DISCARD_JUMP,
457 FS_OPCODE_SET_SAMPLE_ID,
458 FS_OPCODE_PACK_HALF_2x16_SPLIT,
459 FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X,
460 FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y,
461 FS_OPCODE_PLACEHOLDER_HALT,
462 FS_OPCODE_INTERPOLATE_AT_SAMPLE,
463 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
464 FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET,
465
466 VS_OPCODE_URB_WRITE,
467 VS_OPCODE_PULL_CONSTANT_LOAD,
468 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
469 VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
470
471 VS_OPCODE_GET_BUFFER_SIZE,
472
473 VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
474
475 /**
476 * Write geometry shader output data to the URB.
477 *
478 * Unlike VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
479 * R0 to the first MRF. This allows the geometry shader to override the
480 * "Slot {0,1} Offset" fields in the message header.
481 */
482 GS_OPCODE_URB_WRITE,
483
484 /**
485 * Write geometry shader output data to the URB and request a new URB
486 * handle (gen6).
487 *
488 * This opcode doesn't do an implied move from R0 to the first MRF.
489 */
490 GS_OPCODE_URB_WRITE_ALLOCATE,
491
492 /**
493 * Terminate the geometry shader thread by doing an empty URB write.
494 *
495 * This opcode doesn't do an implied move from R0 to the first MRF. This
496 * allows the geometry shader to override the "GS Number of Output Vertices
497 * for Slot {0,1}" fields in the message header.
498 */
499 GS_OPCODE_THREAD_END,
500
501 /**
502 * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header.
503 *
504 * - dst is the MRF containing the message header.
505 *
506 * - src0.x indicates which portion of the URB should be written to (e.g. a
507 * vertex number)
508 *
509 * - src1 is an immediate multiplier which will be applied to src0
510 * (e.g. the size of a single vertex in the URB).
511 *
512 * Note: the hardware will apply this offset *in addition to* the offset in
513 * vec4_instruction::offset.
514 */
515 GS_OPCODE_SET_WRITE_OFFSET,
516
517 /**
518 * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a
519 * URB_WRITE message header.
520 *
521 * - dst is the MRF containing the message header.
522 *
523 * - src0.x is the vertex count. The upper 16 bits will be ignored.
524 */
525 GS_OPCODE_SET_VERTEX_COUNT,
526
527 /**
528 * Set DWORD 2 of dst to the value in src.
529 */
530 GS_OPCODE_SET_DWORD_2,
531
532 /**
533 * Prepare the dst register for storage in the "Channel Mask" fields of a
534 * URB_WRITE message header.
535 *
536 * DWORD 4 of dst is shifted left by 4 bits, so that later,
537 * GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the
538 * final channel mask.
539 *
540 * Note: since GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to
541 * form the final channel mask, DWORDs 0 and 4 of the dst register must not
542 * have any extraneous bits set prior to execution of this opcode (that is,
543 * they should be in the range 0x0 to 0xf).
544 */
545 GS_OPCODE_PREPARE_CHANNEL_MASKS,
546
547 /**
548 * Set the "Channel Mask" fields of a URB_WRITE message header.
549 *
550 * - dst is the MRF containing the message header.
551 *
552 * - src.x is the channel mask, as prepared by
553 * GS_OPCODE_PREPARE_CHANNEL_MASKS. DWORDs 0 and 4 are OR'ed together to
554 * form the final channel mask.
555 */
556 GS_OPCODE_SET_CHANNEL_MASKS,
557
558 /**
559 * Get the "Instance ID" fields from the payload.
560 *
561 * - dst is the GRF for gl_InvocationID.
562 */
563 GS_OPCODE_GET_INSTANCE_ID,
564
565 /**
566 * Send a FF_SYNC message to allocate initial URB handles (gen6).
567 *
568 * - dst will be used as the writeback register for the FF_SYNC operation.
569 *
570 * - src0 is the number of primitives written.
571 *
572 * - src1 is the value to hold in M0.0: number of SO vertices to write
573 * and number of SO primitives needed. Its value will be overwritten
574 * with the SVBI values if transform feedback is enabled.
575 *
576 * Note: This opcode uses an implicit MRF register for the ff_sync message
577 * header, so the caller is expected to set inst->base_mrf and initialize
578 * that MRF register to r0. This opcode will also write to this MRF register
579 * to include the allocated URB handle so it can then be reused directly as
580 * the header in the URB write operation we are allocating the handle for.
581 */
582 GS_OPCODE_FF_SYNC,
583
584 /**
585 * Move r0.1 (which holds PrimitiveID information in gen6) to a separate
586 * register.
587 *
588 * - dst is the GRF where PrimitiveID information will be moved.
589 */
590 GS_OPCODE_SET_PRIMITIVE_ID,
591
592 /**
593 * Write transform feedback data to the SVB by sending a SVB WRITE message.
594 * Used in gen6.
595 *
596 * - dst is the MRF register containing the message header.
597 *
598 * - src0 is the register where the vertex data is going to be copied from.
599 *
600 * - src1 is the destination register when write commit occurs.
601 */
602 GS_OPCODE_SVB_WRITE,
603
604 /**
605 * Set destination index in the SVB write message payload (M0.5). Used
606 * in gen6 for transform feedback.
607 *
608 * - dst is the header to save the destination indices for SVB WRITE.
609 * - src is the register that holds the destination indices value.
610 */
611 GS_OPCODE_SVB_SET_DST_INDEX,
612
613 /**
614 * Prepare Mx.0 subregister for being used in the FF_SYNC message header.
615 * Used in gen6 for transform feedback.
616 *
617 * - dst will hold the register with the final Mx.0 value.
618 *
619 * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite)
620 *
621 * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded)
622 *
623 * - src2 is the value to hold in M0: number of SO vertices to write
624 * and number of SO primitives needed.
625 */
626 GS_OPCODE_FF_SYNC_SET_PRIMITIVES,
627
628 /**
629 * Terminate the compute shader.
630 */
631 CS_OPCODE_CS_TERMINATE,
632
633 /**
634 * GLSL barrier()
635 */
636 SHADER_OPCODE_BARRIER,
637
638 /**
639 * Calculate the high 32-bits of a 32x32 multiply.
640 */
641 SHADER_OPCODE_MULH,
642
643 /**
644 * A MOV that uses VxH indirect addressing.
645 *
646 * Source 0: A register to start from (HW_REG).
647 * Source 1: An indirect offset (in bytes, UD GRF).
648 * Source 2: The length of the region that could be accessed (in bytes,
649 * UD immediate).
650 */
651 SHADER_OPCODE_MOV_INDIRECT,
652
653 VEC4_OPCODE_URB_READ,
654 TCS_OPCODE_GET_INSTANCE_ID,
655 TCS_OPCODE_URB_WRITE,
656 TCS_OPCODE_SET_INPUT_URB_OFFSETS,
657 TCS_OPCODE_SET_OUTPUT_URB_OFFSETS,
658 TCS_OPCODE_GET_PRIMITIVE_ID,
659 TCS_OPCODE_CREATE_BARRIER_HEADER,
660 TCS_OPCODE_SRC0_010_IS_ZERO,
661 TCS_OPCODE_RELEASE_INPUT,
662 TCS_OPCODE_THREAD_END,
663
664 TES_OPCODE_GET_PRIMITIVE_ID,
665 TES_OPCODE_CREATE_INPUT_READ_HEADER,
666 TES_OPCODE_ADD_INDIRECT_URB_OFFSET,
667 };
668
669 enum brw_urb_write_flags {
670 BRW_URB_WRITE_NO_FLAGS = 0,
671
672 /**
673 * Causes a new URB entry to be allocated, and its address stored in the
674 * destination register (gen < 7).
675 */
676 BRW_URB_WRITE_ALLOCATE = 0x1,
677
678 /**
679 * Causes the current URB entry to be deallocated (gen < 7).
680 */
681 BRW_URB_WRITE_UNUSED = 0x2,
682
683 /**
684 * Causes the thread to terminate.
685 */
686 BRW_URB_WRITE_EOT = 0x4,
687
688 /**
689 * Indicates that the given URB entry is complete, and may be sent further
690 * down the 3D pipeline (gen < 7).
691 */
692 BRW_URB_WRITE_COMPLETE = 0x8,
693
694 /**
695 * Indicates that an additional offset (which may be different for the two
696 * vec4 slots) is stored in the message header (gen == 7).
697 */
698 BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10,
699
700 /**
701 * Indicates that the channel masks in the URB_WRITE message header should
702 * not be overridden to 0xff (gen == 7).
703 */
704 BRW_URB_WRITE_USE_CHANNEL_MASKS = 0x20,
705
706 /**
707 * Indicates that the data should be sent to the URB using the
708 * URB_WRITE_OWORD message rather than URB_WRITE_HWORD (gen == 7). This
709 * causes offsets to be interpreted as multiples of an OWORD instead of an
710 * HWORD, and only allows one OWORD to be written.
711 */
712 BRW_URB_WRITE_OWORD = 0x40,
713
714 /**
715 * Convenient combination of flags: end the thread while simultaneously
716 * marking the given URB entry as complete.
717 */
718 BRW_URB_WRITE_EOT_COMPLETE = BRW_URB_WRITE_EOT | BRW_URB_WRITE_COMPLETE,
719
720 /**
721 * Convenient combination of flags: mark the given URB entry as complete
722 * and simultaneously allocate a new one.
723 */
724 BRW_URB_WRITE_ALLOCATE_COMPLETE =
725 BRW_URB_WRITE_ALLOCATE | BRW_URB_WRITE_COMPLETE,
726 };
727
728 enum fb_write_logical_srcs {
729 FB_WRITE_LOGICAL_SRC_COLOR0, /* REQUIRED */
730 FB_WRITE_LOGICAL_SRC_COLOR1, /* for dual source blend messages */
731 FB_WRITE_LOGICAL_SRC_SRC0_ALPHA,
732 FB_WRITE_LOGICAL_SRC_SRC_DEPTH, /* gl_FragDepth */
733 FB_WRITE_LOGICAL_SRC_DST_DEPTH, /* GEN4-5: passthrough from thread */
734 FB_WRITE_LOGICAL_SRC_SRC_STENCIL, /* gl_FragStencilRefARB */
735 FB_WRITE_LOGICAL_SRC_OMASK, /* Sample Mask (gl_SampleMask) */
736 FB_WRITE_LOGICAL_SRC_COMPONENTS, /* REQUIRED */
737 FB_WRITE_LOGICAL_NUM_SRCS
738 };
739
740 enum tex_logical_srcs {
741 /** Texture coordinates */
742 TEX_LOGICAL_SRC_COORDINATE,
743 /** Shadow comparator */
744 TEX_LOGICAL_SRC_SHADOW_C,
745 /** dPdx if the operation takes explicit derivatives, otherwise LOD value */
746 TEX_LOGICAL_SRC_LOD,
747 /** dPdy if the operation takes explicit derivatives */
748 TEX_LOGICAL_SRC_LOD2,
749 /** Sample index */
750 TEX_LOGICAL_SRC_SAMPLE_INDEX,
751 /** MCS data */
752 TEX_LOGICAL_SRC_MCS,
753 /** REQUIRED: Texture surface index */
754 TEX_LOGICAL_SRC_SURFACE,
755 /** Texture sampler index */
756 TEX_LOGICAL_SRC_SAMPLER,
757 /** Texel offset for gathers */
758 TEX_LOGICAL_SRC_TG4_OFFSET,
759 /** REQUIRED: Number of coordinate components (as UD immediate) */
760 TEX_LOGICAL_SRC_COORD_COMPONENTS,
761 /** REQUIRED: Number of derivative components (as UD immediate) */
762 TEX_LOGICAL_SRC_GRAD_COMPONENTS,
763
764 TEX_LOGICAL_NUM_SRCS,
765 };
766
767 #ifdef __cplusplus
768 /**
769 * Allow brw_urb_write_flags enums to be ORed together.
770 */
771 inline brw_urb_write_flags
772 operator|(brw_urb_write_flags x, brw_urb_write_flags y)
773 {
774 return static_cast<brw_urb_write_flags>(static_cast<int>(x) |
775 static_cast<int>(y));
776 }
777 #endif
778
779 enum PACKED brw_predicate {
780 BRW_PREDICATE_NONE = 0,
781 BRW_PREDICATE_NORMAL = 1,
782 BRW_PREDICATE_ALIGN1_ANYV = 2,
783 BRW_PREDICATE_ALIGN1_ALLV = 3,
784 BRW_PREDICATE_ALIGN1_ANY2H = 4,
785 BRW_PREDICATE_ALIGN1_ALL2H = 5,
786 BRW_PREDICATE_ALIGN1_ANY4H = 6,
787 BRW_PREDICATE_ALIGN1_ALL4H = 7,
788 BRW_PREDICATE_ALIGN1_ANY8H = 8,
789 BRW_PREDICATE_ALIGN1_ALL8H = 9,
790 BRW_PREDICATE_ALIGN1_ANY16H = 10,
791 BRW_PREDICATE_ALIGN1_ALL16H = 11,
792 BRW_PREDICATE_ALIGN1_ANY32H = 12,
793 BRW_PREDICATE_ALIGN1_ALL32H = 13,
794 BRW_PREDICATE_ALIGN16_REPLICATE_X = 2,
795 BRW_PREDICATE_ALIGN16_REPLICATE_Y = 3,
796 BRW_PREDICATE_ALIGN16_REPLICATE_Z = 4,
797 BRW_PREDICATE_ALIGN16_REPLICATE_W = 5,
798 BRW_PREDICATE_ALIGN16_ANY4H = 6,
799 BRW_PREDICATE_ALIGN16_ALL4H = 7,
800 };
801
802 enum PACKED brw_reg_file {
803 BRW_ARCHITECTURE_REGISTER_FILE = 0,
804 BRW_GENERAL_REGISTER_FILE = 1,
805 BRW_MESSAGE_REGISTER_FILE = 2,
806 BRW_IMMEDIATE_VALUE = 3,
807
808 ARF = BRW_ARCHITECTURE_REGISTER_FILE,
809 FIXED_GRF = BRW_GENERAL_REGISTER_FILE,
810 MRF = BRW_MESSAGE_REGISTER_FILE,
811 IMM = BRW_IMMEDIATE_VALUE,
812
813 /* These are not hardware values */
814 VGRF,
815 ATTR,
816 UNIFORM, /* prog_data->params[reg] */
817 BAD_FILE,
818 };
819
820 #define BRW_HW_REG_TYPE_UD 0
821 #define BRW_HW_REG_TYPE_D 1
822 #define BRW_HW_REG_TYPE_UW 2
823 #define BRW_HW_REG_TYPE_W 3
824 #define BRW_HW_REG_TYPE_F 7
825 #define GEN8_HW_REG_TYPE_UQ 8
826 #define GEN8_HW_REG_TYPE_Q 9
827
828 #define BRW_HW_REG_NON_IMM_TYPE_UB 4
829 #define BRW_HW_REG_NON_IMM_TYPE_B 5
830 #define GEN7_HW_REG_NON_IMM_TYPE_DF 6
831 #define GEN8_HW_REG_NON_IMM_TYPE_HF 10
832
833 #define BRW_HW_REG_IMM_TYPE_UV 4 /* Gen6+ packed unsigned immediate vector */
834 #define BRW_HW_REG_IMM_TYPE_VF 5 /* packed float immediate vector */
835 #define BRW_HW_REG_IMM_TYPE_V 6 /* packed int imm. vector; uword dest only */
836 #define GEN8_HW_REG_IMM_TYPE_DF 10
837 #define GEN8_HW_REG_IMM_TYPE_HF 11
838
839 /* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so
840 * the types were implied. IVB adds BFE and BFI2 that operate on doublewords
841 * and unsigned doublewords, so a new field is also available in the da3src
842 * struct (part of struct brw_instruction.bits1 in brw_structs.h) to select
843 * dst and shared-src types. The values are different from BRW_REGISTER_TYPE_*.
844 */
845 #define BRW_3SRC_TYPE_F 0
846 #define BRW_3SRC_TYPE_D 1
847 #define BRW_3SRC_TYPE_UD 2
848 #define BRW_3SRC_TYPE_DF 3
849
850 #define BRW_ARF_NULL 0x00
851 #define BRW_ARF_ADDRESS 0x10
852 #define BRW_ARF_ACCUMULATOR 0x20
853 #define BRW_ARF_FLAG 0x30
854 #define BRW_ARF_MASK 0x40
855 #define BRW_ARF_MASK_STACK 0x50
856 #define BRW_ARF_MASK_STACK_DEPTH 0x60
857 #define BRW_ARF_STATE 0x70
858 #define BRW_ARF_CONTROL 0x80
859 #define BRW_ARF_NOTIFICATION_COUNT 0x90
860 #define BRW_ARF_IP 0xA0
861 #define BRW_ARF_TDR 0xB0
862 #define BRW_ARF_TIMESTAMP 0xC0
863
864 #define BRW_MRF_COMPR4 (1 << 7)
865
866 #define BRW_AMASK 0
867 #define BRW_IMASK 1
868 #define BRW_LMASK 2
869 #define BRW_CMASK 3
870
871
872
873 #define BRW_THREAD_NORMAL 0
874 #define BRW_THREAD_ATOMIC 1
875 #define BRW_THREAD_SWITCH 2
876
877 enum PACKED brw_vertical_stride {
878 BRW_VERTICAL_STRIDE_0 = 0,
879 BRW_VERTICAL_STRIDE_1 = 1,
880 BRW_VERTICAL_STRIDE_2 = 2,
881 BRW_VERTICAL_STRIDE_4 = 3,
882 BRW_VERTICAL_STRIDE_8 = 4,
883 BRW_VERTICAL_STRIDE_16 = 5,
884 BRW_VERTICAL_STRIDE_32 = 6,
885 BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF,
886 };
887
888 enum PACKED brw_width {
889 BRW_WIDTH_1 = 0,
890 BRW_WIDTH_2 = 1,
891 BRW_WIDTH_4 = 2,
892 BRW_WIDTH_8 = 3,
893 BRW_WIDTH_16 = 4,
894 };
895
896 /**
897 * Message target: Shared Function ID for where to SEND a message.
898 *
899 * These are enumerated in the ISA reference under "send - Send Message".
900 * In particular, see the following tables:
901 * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition"
902 * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor"
903 * - Ivybridge PRM, Volume 1 Part 1, section 3.2.7 "GPE Function IDs"
904 */
905 enum brw_message_target {
906 BRW_SFID_NULL = 0,
907 BRW_SFID_MATH = 1, /* Only valid on Gen4-5 */
908 BRW_SFID_SAMPLER = 2,
909 BRW_SFID_MESSAGE_GATEWAY = 3,
910 BRW_SFID_DATAPORT_READ = 4,
911 BRW_SFID_DATAPORT_WRITE = 5,
912 BRW_SFID_URB = 6,
913 BRW_SFID_THREAD_SPAWNER = 7,
914 BRW_SFID_VME = 8,
915
916 GEN6_SFID_DATAPORT_SAMPLER_CACHE = 4,
917 GEN6_SFID_DATAPORT_RENDER_CACHE = 5,
918 GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9,
919
920 GEN7_SFID_DATAPORT_DATA_CACHE = 10,
921 GEN7_SFID_PIXEL_INTERPOLATOR = 11,
922 HSW_SFID_DATAPORT_DATA_CACHE_1 = 12,
923 HSW_SFID_CRE = 13,
924 };
925
926 #define GEN7_MESSAGE_TARGET_DP_DATA_CACHE 10
927
928 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0
929 #define BRW_SAMPLER_RETURN_FORMAT_UINT32 2
930 #define BRW_SAMPLER_RETURN_FORMAT_SINT32 3
931
932 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0
933 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0
934 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0
935 #define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1
936 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1
937 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1
938 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2
939 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2
940 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0
941 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2
942 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0
943 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1
944 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE 1
945 #define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2
946 #define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2
947 #define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3
948 #define BRW_SAMPLER_MESSAGE_SIMD8_LD 3
949 #define BRW_SAMPLER_MESSAGE_SIMD16_LD 3
950
951 #define GEN5_SAMPLER_MESSAGE_SAMPLE 0
952 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS 1
953 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD 2
954 #define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE 3
955 #define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS 4
956 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
957 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6
958 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LD 7
959 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4 8
960 #define GEN5_SAMPLER_MESSAGE_LOD 9
961 #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10
962 #define GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO 11
963 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C 16
964 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO 17
965 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
966 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
967 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LZ 24
968 #define GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ 25
969 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ 26
970 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W 28
971 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29
972 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS 30
973 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS 31
974
975 /* for GEN5 only */
976 #define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0
977 #define BRW_SAMPLER_SIMD_MODE_SIMD8 1
978 #define BRW_SAMPLER_SIMD_MODE_SIMD16 2
979 #define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3
980
981 /* GEN9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2
982 * behavior by setting bit 22 of dword 2 in the message header. */
983 #define GEN9_SAMPLER_SIMD_MODE_SIMD8D 0
984 #define GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2 (1 << 22)
985
986 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0
987 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1
988 #define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2
989 #define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3
990 #define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4
991 #define BRW_DATAPORT_OWORD_BLOCK_DWORDS(n) \
992 ((n) == 4 ? BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \
993 (n) == 8 ? BRW_DATAPORT_OWORD_BLOCK_2_OWORDS : \
994 (n) == 16 ? BRW_DATAPORT_OWORD_BLOCK_4_OWORDS : \
995 (n) == 32 ? BRW_DATAPORT_OWORD_BLOCK_8_OWORDS : \
996 (abort(), ~0))
997
998 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0
999 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2
1000
1001 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2
1002 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3
1003
1004 /* This one stays the same across generations. */
1005 #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0
1006 /* GEN4 */
1007 #define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1
1008 #define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2
1009 #define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3
1010 /* G45, GEN5 */
1011 #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1012 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1013 #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ 3
1014 #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1015 #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1016 /* GEN6 */
1017 #define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1018 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1019 #define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1020 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5
1021 #define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1022
1023 #define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0
1024 #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1
1025 #define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2
1026
1027 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0
1028 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1
1029 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2
1030 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3
1031 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4
1032
1033 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0
1034 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1
1035 #define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2
1036 #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3
1037 #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4
1038 #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5
1039 #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7
1040
1041 /* GEN6 */
1042 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7
1043 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8
1044 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 9
1045 #define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 10
1046 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 11
1047 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 12
1048 #define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13
1049 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14
1050
1051 /* GEN7 */
1052 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_READ 4
1053 #define GEN7_DATAPORT_RC_TYPED_SURFACE_READ 5
1054 #define GEN7_DATAPORT_RC_TYPED_ATOMIC_OP 6
1055 #define GEN7_DATAPORT_RC_MEMORY_FENCE 7
1056 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_WRITE 10
1057 #define GEN7_DATAPORT_RC_RENDER_TARGET_WRITE 12
1058 #define GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE 13
1059 #define GEN7_DATAPORT_DC_OWORD_BLOCK_READ 0
1060 #define GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ 1
1061 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ 2
1062 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_READ 3
1063 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_READ 4
1064 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ 5
1065 #define GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP 6
1066 #define GEN7_DATAPORT_DC_MEMORY_FENCE 7
1067 #define GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE 8
1068 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE 10
1069 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE 11
1070 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE 12
1071 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE 13
1072
1073 #define GEN7_DATAPORT_SCRATCH_READ ((1 << 18) | \
1074 (0 << 17))
1075 #define GEN7_DATAPORT_SCRATCH_WRITE ((1 << 18) | \
1076 (1 << 17))
1077 #define GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT 12
1078
1079 #define GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET 0
1080 #define GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE 1
1081 #define GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID 2
1082 #define GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET 3
1083
1084 /* HSW */
1085 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ 0
1086 #define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ 1
1087 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_READ 2
1088 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_READ 3
1089 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ 4
1090 #define HSW_DATAPORT_DC_PORT0_MEMORY_FENCE 7
1091 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_WRITE 8
1092 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_WRITE 10
1093 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_WRITE 11
1094 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE 12
1095
1096 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ 1
1097 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP 2
1098 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2 3
1099 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ 4
1100 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ 5
1101 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP 6
1102 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2 7
1103 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE 9
1104 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE 10
1105 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP 11
1106 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2 12
1107 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE 13
1108
1109 /* GEN9 */
1110 #define GEN9_DATAPORT_RC_RENDER_TARGET_WRITE 12
1111 #define GEN9_DATAPORT_RC_RENDER_TARGET_READ 13
1112
1113 /* Dataport special binding table indices: */
1114 #define BRW_BTI_STATELESS 255
1115 #define GEN7_BTI_SLM 254
1116 /* Note that on Gen8+ BTI 255 was redefined to be IA-coherent according to the
1117 * hardware spec, however because the DRM sets bit 4 of HDC_CHICKEN0 on BDW,
1118 * CHV and at least some pre-production steppings of SKL due to
1119 * WaForceEnableNonCoherent, HDC memory access may have been overridden by the
1120 * kernel to be non-coherent (matching the behavior of the same BTI on
1121 * pre-Gen8 hardware) and BTI 255 may actually be an alias for BTI 253.
1122 */
1123 #define GEN8_BTI_STATELESS_IA_COHERENT 255
1124 #define GEN8_BTI_STATELESS_NON_COHERENT 253
1125
1126 /* dataport atomic operations. */
1127 #define BRW_AOP_AND 1
1128 #define BRW_AOP_OR 2
1129 #define BRW_AOP_XOR 3
1130 #define BRW_AOP_MOV 4
1131 #define BRW_AOP_INC 5
1132 #define BRW_AOP_DEC 6
1133 #define BRW_AOP_ADD 7
1134 #define BRW_AOP_SUB 8
1135 #define BRW_AOP_REVSUB 9
1136 #define BRW_AOP_IMAX 10
1137 #define BRW_AOP_IMIN 11
1138 #define BRW_AOP_UMAX 12
1139 #define BRW_AOP_UMIN 13
1140 #define BRW_AOP_CMPWR 14
1141 #define BRW_AOP_PREDEC 15
1142
1143 #define BRW_MATH_FUNCTION_INV 1
1144 #define BRW_MATH_FUNCTION_LOG 2
1145 #define BRW_MATH_FUNCTION_EXP 3
1146 #define BRW_MATH_FUNCTION_SQRT 4
1147 #define BRW_MATH_FUNCTION_RSQ 5
1148 #define BRW_MATH_FUNCTION_SIN 6
1149 #define BRW_MATH_FUNCTION_COS 7
1150 #define BRW_MATH_FUNCTION_SINCOS 8 /* gen4, gen5 */
1151 #define BRW_MATH_FUNCTION_FDIV 9 /* gen6+ */
1152 #define BRW_MATH_FUNCTION_POW 10
1153 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
1154 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12
1155 #define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13
1156 #define GEN8_MATH_FUNCTION_INVM 14
1157 #define GEN8_MATH_FUNCTION_RSQRTM 15
1158
1159 #define BRW_MATH_INTEGER_UNSIGNED 0
1160 #define BRW_MATH_INTEGER_SIGNED 1
1161
1162 #define BRW_MATH_PRECISION_FULL 0
1163 #define BRW_MATH_PRECISION_PARTIAL 1
1164
1165 #define BRW_MATH_SATURATE_NONE 0
1166 #define BRW_MATH_SATURATE_SATURATE 1
1167
1168 #define BRW_MATH_DATA_VECTOR 0
1169 #define BRW_MATH_DATA_SCALAR 1
1170
1171 #define BRW_URB_OPCODE_WRITE_HWORD 0
1172 #define BRW_URB_OPCODE_WRITE_OWORD 1
1173 #define BRW_URB_OPCODE_READ_HWORD 2
1174 #define BRW_URB_OPCODE_READ_OWORD 3
1175 #define GEN7_URB_OPCODE_ATOMIC_MOV 4
1176 #define GEN7_URB_OPCODE_ATOMIC_INC 5
1177 #define GEN8_URB_OPCODE_ATOMIC_ADD 6
1178 #define GEN8_URB_OPCODE_SIMD8_WRITE 7
1179 #define GEN8_URB_OPCODE_SIMD8_READ 8
1180
1181 #define BRW_URB_SWIZZLE_NONE 0
1182 #define BRW_URB_SWIZZLE_INTERLEAVE 1
1183 #define BRW_URB_SWIZZLE_TRANSPOSE 2
1184
1185 #define BRW_SCRATCH_SPACE_SIZE_1K 0
1186 #define BRW_SCRATCH_SPACE_SIZE_2K 1
1187 #define BRW_SCRATCH_SPACE_SIZE_4K 2
1188 #define BRW_SCRATCH_SPACE_SIZE_8K 3
1189 #define BRW_SCRATCH_SPACE_SIZE_16K 4
1190 #define BRW_SCRATCH_SPACE_SIZE_32K 5
1191 #define BRW_SCRATCH_SPACE_SIZE_64K 6
1192 #define BRW_SCRATCH_SPACE_SIZE_128K 7
1193 #define BRW_SCRATCH_SPACE_SIZE_256K 8
1194 #define BRW_SCRATCH_SPACE_SIZE_512K 9
1195 #define BRW_SCRATCH_SPACE_SIZE_1M 10
1196 #define BRW_SCRATCH_SPACE_SIZE_2M 11
1197
1198 #define BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY 0
1199 #define BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY 1
1200 #define BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG 2
1201 #define BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP 3
1202 #define BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG 4
1203 #define BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE 5
1204 #define BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE 6
1205
1206
1207 /* Gen7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size
1208 * is 2^9, or 512. It's counted in multiples of 64 bytes.
1209 *
1210 * Identical for VS, DS, and HS.
1211 */
1212 #define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES (512*64)
1213 #define GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES (512*64)
1214 #define GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES (512*64)
1215 #define GEN7_MAX_VS_URB_ENTRY_SIZE_BYTES (512*64)
1216
1217 /* Gen6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit
1218 * (128 bytes) URB rows and the maximum allowed value is 5 rows.
1219 */
1220 #define GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES (5*128)
1221
1222 /* GS Thread Payload
1223 */
1224
1225 /* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62. It's
1226 * counted in multiples of 16 bytes.
1227 */
1228 #define GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES (62*16)
1229
1230
1231 /* R0 */
1232 # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27
1233
1234 #endif /* BRW_EU_DEFINES_H */