2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #include "brw_eu_defines.h"
36 #include "util/ralloc.h"
39 * Prior to Sandybridge, the SEND instruction accepted non-MRF source
40 * registers, implicitly moving the operand to a message register.
42 * On Sandybridge, this is no longer the case. This function performs the
43 * explicit move; it should be called before emitting a SEND instruction.
46 gen6_resolve_implied_move(struct brw_codegen
*p
,
50 const struct gen_device_info
*devinfo
= p
->devinfo
;
54 if (src
->file
== BRW_MESSAGE_REGISTER_FILE
)
57 if (src
->file
!= BRW_ARCHITECTURE_REGISTER_FILE
|| src
->nr
!= BRW_ARF_NULL
) {
58 brw_push_insn_state(p
);
59 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
60 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
61 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
62 brw_MOV(p
, retype(brw_message_reg(msg_reg_nr
), BRW_REGISTER_TYPE_UD
),
63 retype(*src
, BRW_REGISTER_TYPE_UD
));
64 brw_pop_insn_state(p
);
66 *src
= brw_message_reg(msg_reg_nr
);
70 gen7_convert_mrf_to_grf(struct brw_codegen
*p
, struct brw_reg
*reg
)
72 /* From the Ivybridge PRM, Volume 4 Part 3, page 218 ("send"):
73 * "The send with EOT should use register space R112-R127 for <src>. This is
74 * to enable loading of a new thread into the same slot while the message
75 * with EOT for current thread is pending dispatch."
77 * Since we're pretending to have 16 MRFs anyway, we may as well use the
78 * registers required for messages with EOT.
80 const struct gen_device_info
*devinfo
= p
->devinfo
;
81 if (devinfo
->gen
>= 7 && reg
->file
== BRW_MESSAGE_REGISTER_FILE
) {
82 reg
->file
= BRW_GENERAL_REGISTER_FILE
;
83 reg
->nr
+= GEN7_MRF_HACK_START
;
88 brw_set_dest(struct brw_codegen
*p
, brw_inst
*inst
, struct brw_reg dest
)
90 const struct gen_device_info
*devinfo
= p
->devinfo
;
92 if (dest
.file
== BRW_MESSAGE_REGISTER_FILE
)
93 assert((dest
.nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
94 else if (dest
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
)
95 assert(dest
.nr
< 128);
97 gen7_convert_mrf_to_grf(p
, &dest
);
99 brw_inst_set_dst_file_type(devinfo
, inst
, dest
.file
, dest
.type
);
100 brw_inst_set_dst_address_mode(devinfo
, inst
, dest
.address_mode
);
102 if (dest
.address_mode
== BRW_ADDRESS_DIRECT
) {
103 brw_inst_set_dst_da_reg_nr(devinfo
, inst
, dest
.nr
);
105 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
) {
106 brw_inst_set_dst_da1_subreg_nr(devinfo
, inst
, dest
.subnr
);
107 if (dest
.hstride
== BRW_HORIZONTAL_STRIDE_0
)
108 dest
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
109 brw_inst_set_dst_hstride(devinfo
, inst
, dest
.hstride
);
111 brw_inst_set_dst_da16_subreg_nr(devinfo
, inst
, dest
.subnr
/ 16);
112 brw_inst_set_da16_writemask(devinfo
, inst
, dest
.writemask
);
113 if (dest
.file
== BRW_GENERAL_REGISTER_FILE
||
114 dest
.file
== BRW_MESSAGE_REGISTER_FILE
) {
115 assert(dest
.writemask
!= 0);
117 /* From the Ivybridge PRM, Vol 4, Part 3, Section 5.2.4.1:
118 * Although Dst.HorzStride is a don't care for Align16, HW needs
119 * this to be programmed as "01".
121 brw_inst_set_dst_hstride(devinfo
, inst
, 1);
124 brw_inst_set_dst_ia_subreg_nr(devinfo
, inst
, dest
.subnr
);
126 /* These are different sizes in align1 vs align16:
128 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
) {
129 brw_inst_set_dst_ia1_addr_imm(devinfo
, inst
,
130 dest
.indirect_offset
);
131 if (dest
.hstride
== BRW_HORIZONTAL_STRIDE_0
)
132 dest
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
133 brw_inst_set_dst_hstride(devinfo
, inst
, dest
.hstride
);
135 brw_inst_set_dst_ia16_addr_imm(devinfo
, inst
,
136 dest
.indirect_offset
);
137 /* even ignored in da16, still need to set as '01' */
138 brw_inst_set_dst_hstride(devinfo
, inst
, 1);
142 /* Generators should set a default exec_size of either 8 (SIMD4x2 or SIMD8)
143 * or 16 (SIMD16), as that's normally correct. However, when dealing with
144 * small registers, it can be useful for us to automatically reduce it to
145 * match the register size.
147 if (p
->automatic_exec_sizes
) {
149 * In platforms that support fp64 we can emit instructions with a width
150 * of 4 that need two SIMD8 registers and an exec_size of 8 or 16. In
151 * these cases we need to make sure that these instructions have their
152 * exec sizes set properly when they are emitted and we can't rely on
153 * this code to fix it.
156 if (devinfo
->gen
>= 6)
157 fix_exec_size
= dest
.width
< BRW_EXECUTE_4
;
159 fix_exec_size
= dest
.width
< BRW_EXECUTE_8
;
162 brw_inst_set_exec_size(devinfo
, inst
, dest
.width
);
167 brw_set_src0(struct brw_codegen
*p
, brw_inst
*inst
, struct brw_reg reg
)
169 const struct gen_device_info
*devinfo
= p
->devinfo
;
171 if (reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
172 assert((reg
.nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
173 else if (reg
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
)
174 assert(reg
.nr
< 128);
176 gen7_convert_mrf_to_grf(p
, ®
);
178 if (devinfo
->gen
>= 6 && (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
||
179 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SENDC
)) {
180 /* Any source modifiers or regions will be ignored, since this just
181 * identifies the MRF/GRF to start reading the message contents from.
182 * Check for some likely failures.
186 assert(reg
.address_mode
== BRW_ADDRESS_DIRECT
);
189 brw_inst_set_src0_file_type(devinfo
, inst
, reg
.file
, reg
.type
);
190 brw_inst_set_src0_abs(devinfo
, inst
, reg
.abs
);
191 brw_inst_set_src0_negate(devinfo
, inst
, reg
.negate
);
192 brw_inst_set_src0_address_mode(devinfo
, inst
, reg
.address_mode
);
194 if (reg
.file
== BRW_IMMEDIATE_VALUE
) {
195 if (reg
.type
== BRW_REGISTER_TYPE_DF
||
196 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_DIM
)
197 brw_inst_set_imm_df(devinfo
, inst
, reg
.df
);
198 else if (reg
.type
== BRW_REGISTER_TYPE_UQ
||
199 reg
.type
== BRW_REGISTER_TYPE_Q
)
200 brw_inst_set_imm_uq(devinfo
, inst
, reg
.u64
);
202 brw_inst_set_imm_ud(devinfo
, inst
, reg
.ud
);
204 if (type_sz(reg
.type
) < 8) {
205 brw_inst_set_src1_reg_file(devinfo
, inst
,
206 BRW_ARCHITECTURE_REGISTER_FILE
);
207 brw_inst_set_src1_reg_hw_type(devinfo
, inst
,
208 brw_inst_src0_reg_hw_type(devinfo
, inst
));
211 if (reg
.address_mode
== BRW_ADDRESS_DIRECT
) {
212 brw_inst_set_src0_da_reg_nr(devinfo
, inst
, reg
.nr
);
213 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
) {
214 brw_inst_set_src0_da1_subreg_nr(devinfo
, inst
, reg
.subnr
);
216 brw_inst_set_src0_da16_subreg_nr(devinfo
, inst
, reg
.subnr
/ 16);
219 brw_inst_set_src0_ia_subreg_nr(devinfo
, inst
, reg
.subnr
);
221 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
) {
222 brw_inst_set_src0_ia1_addr_imm(devinfo
, inst
, reg
.indirect_offset
);
224 brw_inst_set_src0_ia16_addr_imm(devinfo
, inst
, reg
.indirect_offset
);
228 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
) {
229 if (reg
.width
== BRW_WIDTH_1
&&
230 brw_inst_exec_size(devinfo
, inst
) == BRW_EXECUTE_1
) {
231 brw_inst_set_src0_hstride(devinfo
, inst
, BRW_HORIZONTAL_STRIDE_0
);
232 brw_inst_set_src0_width(devinfo
, inst
, BRW_WIDTH_1
);
233 brw_inst_set_src0_vstride(devinfo
, inst
, BRW_VERTICAL_STRIDE_0
);
235 brw_inst_set_src0_hstride(devinfo
, inst
, reg
.hstride
);
236 brw_inst_set_src0_width(devinfo
, inst
, reg
.width
);
237 brw_inst_set_src0_vstride(devinfo
, inst
, reg
.vstride
);
240 brw_inst_set_src0_da16_swiz_x(devinfo
, inst
,
241 BRW_GET_SWZ(reg
.swizzle
, BRW_CHANNEL_X
));
242 brw_inst_set_src0_da16_swiz_y(devinfo
, inst
,
243 BRW_GET_SWZ(reg
.swizzle
, BRW_CHANNEL_Y
));
244 brw_inst_set_src0_da16_swiz_z(devinfo
, inst
,
245 BRW_GET_SWZ(reg
.swizzle
, BRW_CHANNEL_Z
));
246 brw_inst_set_src0_da16_swiz_w(devinfo
, inst
,
247 BRW_GET_SWZ(reg
.swizzle
, BRW_CHANNEL_W
));
249 if (reg
.vstride
== BRW_VERTICAL_STRIDE_8
) {
250 /* This is an oddity of the fact we're using the same
251 * descriptions for registers in align_16 as align_1:
253 brw_inst_set_src0_vstride(devinfo
, inst
, BRW_VERTICAL_STRIDE_4
);
254 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
255 reg
.type
== BRW_REGISTER_TYPE_DF
&&
256 reg
.vstride
== BRW_VERTICAL_STRIDE_2
) {
259 * "For Align16 access mode, only encodings of 0000 and 0011
260 * are allowed. Other codes are reserved."
262 * Presumably the DevSNB behavior applies to IVB as well.
264 brw_inst_set_src0_vstride(devinfo
, inst
, BRW_VERTICAL_STRIDE_4
);
266 brw_inst_set_src0_vstride(devinfo
, inst
, reg
.vstride
);
274 brw_set_src1(struct brw_codegen
*p
, brw_inst
*inst
, struct brw_reg reg
)
276 const struct gen_device_info
*devinfo
= p
->devinfo
;
278 if (reg
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
)
279 assert(reg
.nr
< 128);
281 /* From the IVB PRM Vol. 4, Pt. 3, Section 3.3.3.5:
283 * "Accumulator registers may be accessed explicitly as src0
286 assert(reg
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
||
287 reg
.nr
!= BRW_ARF_ACCUMULATOR
);
289 gen7_convert_mrf_to_grf(p
, ®
);
290 assert(reg
.file
!= BRW_MESSAGE_REGISTER_FILE
);
292 brw_inst_set_src1_file_type(devinfo
, inst
, reg
.file
, reg
.type
);
293 brw_inst_set_src1_abs(devinfo
, inst
, reg
.abs
);
294 brw_inst_set_src1_negate(devinfo
, inst
, reg
.negate
);
296 /* Only src1 can be immediate in two-argument instructions.
298 assert(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
);
300 if (reg
.file
== BRW_IMMEDIATE_VALUE
) {
301 /* two-argument instructions can only use 32-bit immediates */
302 assert(type_sz(reg
.type
) < 8);
303 brw_inst_set_imm_ud(devinfo
, inst
, reg
.ud
);
305 /* This is a hardware restriction, which may or may not be lifted
308 assert (reg
.address_mode
== BRW_ADDRESS_DIRECT
);
309 /* assert (reg.file == BRW_GENERAL_REGISTER_FILE); */
311 brw_inst_set_src1_da_reg_nr(devinfo
, inst
, reg
.nr
);
312 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
) {
313 brw_inst_set_src1_da1_subreg_nr(devinfo
, inst
, reg
.subnr
);
315 brw_inst_set_src1_da16_subreg_nr(devinfo
, inst
, reg
.subnr
/ 16);
318 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
) {
319 if (reg
.width
== BRW_WIDTH_1
&&
320 brw_inst_exec_size(devinfo
, inst
) == BRW_EXECUTE_1
) {
321 brw_inst_set_src1_hstride(devinfo
, inst
, BRW_HORIZONTAL_STRIDE_0
);
322 brw_inst_set_src1_width(devinfo
, inst
, BRW_WIDTH_1
);
323 brw_inst_set_src1_vstride(devinfo
, inst
, BRW_VERTICAL_STRIDE_0
);
325 brw_inst_set_src1_hstride(devinfo
, inst
, reg
.hstride
);
326 brw_inst_set_src1_width(devinfo
, inst
, reg
.width
);
327 brw_inst_set_src1_vstride(devinfo
, inst
, reg
.vstride
);
330 brw_inst_set_src1_da16_swiz_x(devinfo
, inst
,
331 BRW_GET_SWZ(reg
.swizzle
, BRW_CHANNEL_X
));
332 brw_inst_set_src1_da16_swiz_y(devinfo
, inst
,
333 BRW_GET_SWZ(reg
.swizzle
, BRW_CHANNEL_Y
));
334 brw_inst_set_src1_da16_swiz_z(devinfo
, inst
,
335 BRW_GET_SWZ(reg
.swizzle
, BRW_CHANNEL_Z
));
336 brw_inst_set_src1_da16_swiz_w(devinfo
, inst
,
337 BRW_GET_SWZ(reg
.swizzle
, BRW_CHANNEL_W
));
339 if (reg
.vstride
== BRW_VERTICAL_STRIDE_8
) {
340 /* This is an oddity of the fact we're using the same
341 * descriptions for registers in align_16 as align_1:
343 brw_inst_set_src1_vstride(devinfo
, inst
, BRW_VERTICAL_STRIDE_4
);
344 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
345 reg
.type
== BRW_REGISTER_TYPE_DF
&&
346 reg
.vstride
== BRW_VERTICAL_STRIDE_2
) {
349 * "For Align16 access mode, only encodings of 0000 and 0011
350 * are allowed. Other codes are reserved."
352 * Presumably the DevSNB behavior applies to IVB as well.
354 brw_inst_set_src1_vstride(devinfo
, inst
, BRW_VERTICAL_STRIDE_4
);
356 brw_inst_set_src1_vstride(devinfo
, inst
, reg
.vstride
);
363 * Set the Message Descriptor and Extended Message Descriptor fields
366 * \note This zeroes out the Function Control bits, so it must be called
367 * \b before filling out any message-specific data. Callers can
368 * choose not to fill in irrelevant bits; they will be zero.
371 brw_set_message_descriptor(struct brw_codegen
*p
,
373 enum brw_message_target sfid
,
375 unsigned response_length
,
379 const struct gen_device_info
*devinfo
= p
->devinfo
;
381 brw_set_src1(p
, inst
, brw_imm_d(0));
383 /* For indirect sends, `inst` will not be the SEND/SENDC instruction
384 * itself; instead, it will be a MOV/OR into the address register.
386 * In this case, we avoid setting the extended message descriptor bits,
387 * since they go on the later SEND/SENDC instead and if set here would
388 * instead clobber the conditionalmod bits.
390 unsigned opcode
= brw_inst_opcode(devinfo
, inst
);
391 if (opcode
== BRW_OPCODE_SEND
|| opcode
== BRW_OPCODE_SENDC
) {
392 brw_inst_set_sfid(devinfo
, inst
, sfid
);
395 brw_inst_set_mlen(devinfo
, inst
, msg_length
);
396 brw_inst_set_rlen(devinfo
, inst
, response_length
);
397 brw_inst_set_eot(devinfo
, inst
, end_of_thread
);
399 if (devinfo
->gen
>= 5) {
400 brw_inst_set_header_present(devinfo
, inst
, header_present
);
404 static void brw_set_math_message( struct brw_codegen
*p
,
407 unsigned integer_type
,
411 const struct gen_device_info
*devinfo
= p
->devinfo
;
413 unsigned response_length
;
415 /* Infer message length from the function */
417 case BRW_MATH_FUNCTION_POW
:
418 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
:
419 case BRW_MATH_FUNCTION_INT_DIV_REMAINDER
:
420 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
:
428 /* Infer response length from the function */
430 case BRW_MATH_FUNCTION_SINCOS
:
431 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
:
440 brw_set_message_descriptor(p
, inst
, BRW_SFID_MATH
,
441 msg_length
, response_length
, false, false);
442 brw_inst_set_math_msg_function(devinfo
, inst
, function
);
443 brw_inst_set_math_msg_signed_int(devinfo
, inst
, integer_type
);
444 brw_inst_set_math_msg_precision(devinfo
, inst
, low_precision
);
445 brw_inst_set_math_msg_saturate(devinfo
, inst
, brw_inst_saturate(devinfo
, inst
));
446 brw_inst_set_math_msg_data_type(devinfo
, inst
, dataType
);
447 brw_inst_set_saturate(devinfo
, inst
, 0);
451 static void brw_set_ff_sync_message(struct brw_codegen
*p
,
454 unsigned response_length
,
457 const struct gen_device_info
*devinfo
= p
->devinfo
;
459 brw_set_message_descriptor(p
, insn
, BRW_SFID_URB
,
460 1, response_length
, true, end_of_thread
);
461 brw_inst_set_urb_opcode(devinfo
, insn
, 1); /* FF_SYNC */
462 brw_inst_set_urb_allocate(devinfo
, insn
, allocate
);
463 /* The following fields are not used by FF_SYNC: */
464 brw_inst_set_urb_global_offset(devinfo
, insn
, 0);
465 brw_inst_set_urb_swizzle_control(devinfo
, insn
, 0);
466 brw_inst_set_urb_used(devinfo
, insn
, 0);
467 brw_inst_set_urb_complete(devinfo
, insn
, 0);
470 static void brw_set_urb_message( struct brw_codegen
*p
,
472 enum brw_urb_write_flags flags
,
474 unsigned response_length
,
476 unsigned swizzle_control
)
478 const struct gen_device_info
*devinfo
= p
->devinfo
;
480 assert(devinfo
->gen
< 7 || swizzle_control
!= BRW_URB_SWIZZLE_TRANSPOSE
);
481 assert(devinfo
->gen
< 7 || !(flags
& BRW_URB_WRITE_ALLOCATE
));
482 assert(devinfo
->gen
>= 7 || !(flags
& BRW_URB_WRITE_PER_SLOT_OFFSET
));
484 brw_set_message_descriptor(p
, insn
, BRW_SFID_URB
,
485 msg_length
, response_length
, true,
486 flags
& BRW_URB_WRITE_EOT
);
488 if (flags
& BRW_URB_WRITE_OWORD
) {
489 assert(msg_length
== 2); /* header + one OWORD of data */
490 brw_inst_set_urb_opcode(devinfo
, insn
, BRW_URB_OPCODE_WRITE_OWORD
);
492 brw_inst_set_urb_opcode(devinfo
, insn
, BRW_URB_OPCODE_WRITE_HWORD
);
495 brw_inst_set_urb_global_offset(devinfo
, insn
, offset
);
496 brw_inst_set_urb_swizzle_control(devinfo
, insn
, swizzle_control
);
498 if (devinfo
->gen
< 8) {
499 brw_inst_set_urb_complete(devinfo
, insn
, !!(flags
& BRW_URB_WRITE_COMPLETE
));
502 if (devinfo
->gen
< 7) {
503 brw_inst_set_urb_allocate(devinfo
, insn
, !!(flags
& BRW_URB_WRITE_ALLOCATE
));
504 brw_inst_set_urb_used(devinfo
, insn
, !(flags
& BRW_URB_WRITE_UNUSED
));
506 brw_inst_set_urb_per_slot_offset(devinfo
, insn
,
507 !!(flags
& BRW_URB_WRITE_PER_SLOT_OFFSET
));
512 brw_set_dp_write_message(struct brw_codegen
*p
,
514 unsigned binding_table_index
,
515 unsigned msg_control
,
517 unsigned target_cache
,
520 unsigned last_render_target
,
521 unsigned response_length
,
522 unsigned end_of_thread
,
523 unsigned send_commit_msg
)
525 const struct gen_device_info
*devinfo
= p
->devinfo
;
526 const unsigned sfid
= (devinfo
->gen
>= 6 ? target_cache
:
527 BRW_SFID_DATAPORT_WRITE
);
529 brw_set_message_descriptor(p
, insn
, sfid
, msg_length
, response_length
,
530 header_present
, end_of_thread
);
532 brw_inst_set_binding_table_index(devinfo
, insn
, binding_table_index
);
533 brw_inst_set_dp_write_msg_type(devinfo
, insn
, msg_type
);
534 brw_inst_set_dp_write_msg_control(devinfo
, insn
, msg_control
);
535 brw_inst_set_rt_last(devinfo
, insn
, last_render_target
);
536 if (devinfo
->gen
< 7) {
537 brw_inst_set_dp_write_commit(devinfo
, insn
, send_commit_msg
);
542 brw_set_dp_read_message(struct brw_codegen
*p
,
544 unsigned binding_table_index
,
545 unsigned msg_control
,
547 unsigned target_cache
,
550 unsigned response_length
)
552 const struct gen_device_info
*devinfo
= p
->devinfo
;
553 const unsigned sfid
= (devinfo
->gen
>= 6 ? target_cache
:
554 BRW_SFID_DATAPORT_READ
);
556 brw_set_message_descriptor(p
, insn
, sfid
, msg_length
, response_length
,
557 header_present
, false);
559 brw_inst_set_binding_table_index(devinfo
, insn
, binding_table_index
);
560 brw_inst_set_dp_read_msg_type(devinfo
, insn
, msg_type
);
561 brw_inst_set_dp_read_msg_control(devinfo
, insn
, msg_control
);
562 if (devinfo
->gen
< 6)
563 brw_inst_set_dp_read_target_cache(devinfo
, insn
, target_cache
);
567 brw_set_sampler_message(struct brw_codegen
*p
,
569 unsigned binding_table_index
,
572 unsigned response_length
,
574 unsigned header_present
,
576 unsigned return_format
)
578 const struct gen_device_info
*devinfo
= p
->devinfo
;
580 brw_set_message_descriptor(p
, inst
, BRW_SFID_SAMPLER
, msg_length
,
581 response_length
, header_present
, false);
583 brw_inst_set_binding_table_index(devinfo
, inst
, binding_table_index
);
584 brw_inst_set_sampler(devinfo
, inst
, sampler
);
585 brw_inst_set_sampler_msg_type(devinfo
, inst
, msg_type
);
586 if (devinfo
->gen
>= 5) {
587 brw_inst_set_sampler_simd_mode(devinfo
, inst
, simd_mode
);
588 } else if (devinfo
->gen
== 4 && !devinfo
->is_g4x
) {
589 brw_inst_set_sampler_return_format(devinfo
, inst
, return_format
);
594 gen7_set_dp_scratch_message(struct brw_codegen
*p
,
598 bool invalidate_after_read
,
600 unsigned addr_offset
,
605 const struct gen_device_info
*devinfo
= p
->devinfo
;
606 assert(num_regs
== 1 || num_regs
== 2 || num_regs
== 4 ||
607 (devinfo
->gen
>= 8 && num_regs
== 8));
608 const unsigned block_size
= (devinfo
->gen
>= 8 ? _mesa_logbase2(num_regs
) :
611 brw_set_message_descriptor(p
, inst
, GEN7_SFID_DATAPORT_DATA_CACHE
,
612 mlen
, rlen
, header_present
, false);
613 brw_inst_set_dp_category(devinfo
, inst
, 1); /* Scratch Block Read/Write msgs */
614 brw_inst_set_scratch_read_write(devinfo
, inst
, write
);
615 brw_inst_set_scratch_type(devinfo
, inst
, dword
);
616 brw_inst_set_scratch_invalidate_after_read(devinfo
, inst
, invalidate_after_read
);
617 brw_inst_set_scratch_block_size(devinfo
, inst
, block_size
);
618 brw_inst_set_scratch_addr_offset(devinfo
, inst
, addr_offset
);
621 #define next_insn brw_next_insn
623 brw_next_insn(struct brw_codegen
*p
, unsigned opcode
)
625 const struct gen_device_info
*devinfo
= p
->devinfo
;
628 if (p
->nr_insn
+ 1 > p
->store_size
) {
630 p
->store
= reralloc(p
->mem_ctx
, p
->store
, brw_inst
, p
->store_size
);
633 p
->next_insn_offset
+= 16;
634 insn
= &p
->store
[p
->nr_insn
++];
635 memcpy(insn
, p
->current
, sizeof(*insn
));
637 brw_inst_set_opcode(devinfo
, insn
, opcode
);
642 brw_alu1(struct brw_codegen
*p
, unsigned opcode
,
643 struct brw_reg dest
, struct brw_reg src
)
645 brw_inst
*insn
= next_insn(p
, opcode
);
646 brw_set_dest(p
, insn
, dest
);
647 brw_set_src0(p
, insn
, src
);
652 brw_alu2(struct brw_codegen
*p
, unsigned opcode
,
653 struct brw_reg dest
, struct brw_reg src0
, struct brw_reg src1
)
655 /* 64-bit immediates are only supported on 1-src instructions */
656 assert(src0
.file
!= BRW_IMMEDIATE_VALUE
|| type_sz(src0
.type
) <= 4);
657 assert(src1
.file
!= BRW_IMMEDIATE_VALUE
|| type_sz(src1
.type
) <= 4);
659 brw_inst
*insn
= next_insn(p
, opcode
);
660 brw_set_dest(p
, insn
, dest
);
661 brw_set_src0(p
, insn
, src0
);
662 brw_set_src1(p
, insn
, src1
);
667 get_3src_subreg_nr(struct brw_reg reg
)
669 /* Normally, SubRegNum is in bytes (0..31). However, 3-src instructions
670 * use 32-bit units (components 0..7). Since they only support F/D/UD
671 * types, this doesn't lose any flexibility, but uses fewer bits.
673 return reg
.subnr
/ 4;
677 brw_alu3(struct brw_codegen
*p
, unsigned opcode
, struct brw_reg dest
,
678 struct brw_reg src0
, struct brw_reg src1
, struct brw_reg src2
)
680 const struct gen_device_info
*devinfo
= p
->devinfo
;
681 brw_inst
*inst
= next_insn(p
, opcode
);
683 gen7_convert_mrf_to_grf(p
, &dest
);
685 assert(dest
.nr
< 128);
686 assert(src0
.nr
< 128);
687 assert(src1
.nr
< 128);
688 assert(src2
.nr
< 128);
689 assert(dest
.address_mode
== BRW_ADDRESS_DIRECT
);
690 assert(src0
.address_mode
== BRW_ADDRESS_DIRECT
);
691 assert(src1
.address_mode
== BRW_ADDRESS_DIRECT
);
692 assert(src2
.address_mode
== BRW_ADDRESS_DIRECT
);
694 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
) {
695 assert(dest
.file
== BRW_GENERAL_REGISTER_FILE
||
696 dest
.file
== BRW_ARCHITECTURE_REGISTER_FILE
);
698 if (dest
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
699 brw_inst_set_3src_a1_dst_reg_file(devinfo
, inst
,
700 BRW_ALIGN1_3SRC_ACCUMULATOR
);
701 brw_inst_set_3src_dst_reg_nr(devinfo
, inst
, BRW_ARF_ACCUMULATOR
);
703 brw_inst_set_3src_a1_dst_reg_file(devinfo
, inst
,
704 BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE
);
705 brw_inst_set_3src_dst_reg_nr(devinfo
, inst
, dest
.nr
);
707 brw_inst_set_3src_a1_dst_subreg_nr(devinfo
, inst
, dest
.subnr
/ 8);
709 brw_inst_set_3src_a1_dst_hstride(devinfo
, inst
, BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1
);
711 if (brw_reg_type_is_floating_point(dest
.type
)) {
712 brw_inst_set_3src_a1_exec_type(devinfo
, inst
,
713 BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT
);
715 brw_inst_set_3src_a1_exec_type(devinfo
, inst
,
716 BRW_ALIGN1_3SRC_EXEC_TYPE_INT
);
719 brw_inst_set_3src_a1_dst_type(devinfo
, inst
, dest
.type
);
720 brw_inst_set_3src_a1_src0_type(devinfo
, inst
, src0
.type
);
721 brw_inst_set_3src_a1_src1_type(devinfo
, inst
, src1
.type
);
722 brw_inst_set_3src_a1_src2_type(devinfo
, inst
, src2
.type
);
724 assert((src0
.vstride
== BRW_VERTICAL_STRIDE_0
&&
725 src0
.hstride
== BRW_HORIZONTAL_STRIDE_0
) ||
726 (src0
.vstride
== BRW_VERTICAL_STRIDE_8
&&
727 src0
.hstride
== BRW_HORIZONTAL_STRIDE_1
));
728 assert((src1
.vstride
== BRW_VERTICAL_STRIDE_0
&&
729 src1
.hstride
== BRW_HORIZONTAL_STRIDE_0
) ||
730 (src1
.vstride
== BRW_VERTICAL_STRIDE_8
&&
731 src1
.hstride
== BRW_HORIZONTAL_STRIDE_1
));
732 assert((src2
.vstride
== BRW_VERTICAL_STRIDE_0
&&
733 src2
.hstride
== BRW_HORIZONTAL_STRIDE_0
) ||
734 (src2
.vstride
== BRW_VERTICAL_STRIDE_8
&&
735 src2
.hstride
== BRW_HORIZONTAL_STRIDE_1
));
737 brw_inst_set_3src_a1_src0_vstride(devinfo
, inst
,
738 src0
.vstride
== BRW_VERTICAL_STRIDE_0
?
739 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0
:
740 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8
);
741 brw_inst_set_3src_a1_src1_vstride(devinfo
, inst
,
742 src1
.vstride
== BRW_VERTICAL_STRIDE_0
?
743 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0
:
744 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8
);
745 /* no vstride on src2 */
747 brw_inst_set_3src_a1_src0_hstride(devinfo
, inst
,
748 src0
.hstride
== BRW_HORIZONTAL_STRIDE_0
?
749 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0
:
750 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1
);
751 brw_inst_set_3src_a1_src1_hstride(devinfo
, inst
,
752 src1
.hstride
== BRW_HORIZONTAL_STRIDE_0
?
753 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0
:
754 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1
);
755 brw_inst_set_3src_a1_src2_hstride(devinfo
, inst
,
756 src2
.hstride
== BRW_HORIZONTAL_STRIDE_0
?
757 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0
:
758 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1
);
760 brw_inst_set_3src_a1_src0_subreg_nr(devinfo
, inst
, src0
.subnr
);
761 brw_inst_set_3src_src0_reg_nr(devinfo
, inst
, src0
.nr
);
762 brw_inst_set_3src_src0_abs(devinfo
, inst
, src0
.abs
);
763 brw_inst_set_3src_src0_negate(devinfo
, inst
, src0
.negate
);
765 brw_inst_set_3src_a1_src1_subreg_nr(devinfo
, inst
, src1
.subnr
);
766 if (src1
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
767 brw_inst_set_3src_src1_reg_nr(devinfo
, inst
, BRW_ARF_ACCUMULATOR
);
769 brw_inst_set_3src_src1_reg_nr(devinfo
, inst
, src1
.nr
);
771 brw_inst_set_3src_src1_abs(devinfo
, inst
, src1
.abs
);
772 brw_inst_set_3src_src1_negate(devinfo
, inst
, src1
.negate
);
774 brw_inst_set_3src_a1_src2_subreg_nr(devinfo
, inst
, src2
.subnr
);
775 brw_inst_set_3src_src2_reg_nr(devinfo
, inst
, src2
.nr
);
776 brw_inst_set_3src_src2_abs(devinfo
, inst
, src2
.abs
);
777 brw_inst_set_3src_src2_negate(devinfo
, inst
, src2
.negate
);
779 assert(src0
.file
== BRW_GENERAL_REGISTER_FILE
||
780 src0
.file
== BRW_IMMEDIATE_VALUE
);
781 assert(src1
.file
== BRW_GENERAL_REGISTER_FILE
||
782 src1
.file
== BRW_ARCHITECTURE_REGISTER_FILE
);
783 assert(src2
.file
== BRW_GENERAL_REGISTER_FILE
||
784 src2
.file
== BRW_IMMEDIATE_VALUE
);
786 brw_inst_set_3src_a1_src0_reg_file(devinfo
, inst
,
787 src0
.file
== BRW_GENERAL_REGISTER_FILE
?
788 BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE
:
789 BRW_ALIGN1_3SRC_IMMEDIATE_VALUE
);
790 brw_inst_set_3src_a1_src1_reg_file(devinfo
, inst
,
791 src1
.file
== BRW_GENERAL_REGISTER_FILE
?
792 BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE
:
793 BRW_ALIGN1_3SRC_ACCUMULATOR
);
794 brw_inst_set_3src_a1_src2_reg_file(devinfo
, inst
,
795 src2
.file
== BRW_GENERAL_REGISTER_FILE
?
796 BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE
:
797 BRW_ALIGN1_3SRC_IMMEDIATE_VALUE
);
799 assert(dest
.file
== BRW_GENERAL_REGISTER_FILE
||
800 dest
.file
== BRW_MESSAGE_REGISTER_FILE
);
801 assert(dest
.type
== BRW_REGISTER_TYPE_F
||
802 dest
.type
== BRW_REGISTER_TYPE_DF
||
803 dest
.type
== BRW_REGISTER_TYPE_D
||
804 dest
.type
== BRW_REGISTER_TYPE_UD
);
805 if (devinfo
->gen
== 6) {
806 brw_inst_set_3src_a16_dst_reg_file(devinfo
, inst
,
807 dest
.file
== BRW_MESSAGE_REGISTER_FILE
);
809 brw_inst_set_3src_dst_reg_nr(devinfo
, inst
, dest
.nr
);
810 brw_inst_set_3src_a16_dst_subreg_nr(devinfo
, inst
, dest
.subnr
/ 16);
811 brw_inst_set_3src_a16_dst_writemask(devinfo
, inst
, dest
.writemask
);
813 assert(src0
.file
== BRW_GENERAL_REGISTER_FILE
);
814 brw_inst_set_3src_a16_src0_swizzle(devinfo
, inst
, src0
.swizzle
);
815 brw_inst_set_3src_a16_src0_subreg_nr(devinfo
, inst
, get_3src_subreg_nr(src0
));
816 brw_inst_set_3src_src0_reg_nr(devinfo
, inst
, src0
.nr
);
817 brw_inst_set_3src_src0_abs(devinfo
, inst
, src0
.abs
);
818 brw_inst_set_3src_src0_negate(devinfo
, inst
, src0
.negate
);
819 brw_inst_set_3src_a16_src0_rep_ctrl(devinfo
, inst
,
820 src0
.vstride
== BRW_VERTICAL_STRIDE_0
);
822 assert(src1
.file
== BRW_GENERAL_REGISTER_FILE
);
823 brw_inst_set_3src_a16_src1_swizzle(devinfo
, inst
, src1
.swizzle
);
824 brw_inst_set_3src_a16_src1_subreg_nr(devinfo
, inst
, get_3src_subreg_nr(src1
));
825 brw_inst_set_3src_src1_reg_nr(devinfo
, inst
, src1
.nr
);
826 brw_inst_set_3src_src1_abs(devinfo
, inst
, src1
.abs
);
827 brw_inst_set_3src_src1_negate(devinfo
, inst
, src1
.negate
);
828 brw_inst_set_3src_a16_src1_rep_ctrl(devinfo
, inst
,
829 src1
.vstride
== BRW_VERTICAL_STRIDE_0
);
831 assert(src2
.file
== BRW_GENERAL_REGISTER_FILE
);
832 brw_inst_set_3src_a16_src2_swizzle(devinfo
, inst
, src2
.swizzle
);
833 brw_inst_set_3src_a16_src2_subreg_nr(devinfo
, inst
, get_3src_subreg_nr(src2
));
834 brw_inst_set_3src_src2_reg_nr(devinfo
, inst
, src2
.nr
);
835 brw_inst_set_3src_src2_abs(devinfo
, inst
, src2
.abs
);
836 brw_inst_set_3src_src2_negate(devinfo
, inst
, src2
.negate
);
837 brw_inst_set_3src_a16_src2_rep_ctrl(devinfo
, inst
,
838 src2
.vstride
== BRW_VERTICAL_STRIDE_0
);
840 if (devinfo
->gen
>= 7) {
841 /* Set both the source and destination types based on dest.type,
842 * ignoring the source register types. The MAD and LRP emitters ensure
843 * that all four types are float. The BFE and BFI2 emitters, however,
844 * may send us mixed D and UD types and want us to ignore that and use
845 * the destination type.
847 brw_inst_set_3src_a16_src_type(devinfo
, inst
, dest
.type
);
848 brw_inst_set_3src_a16_dst_type(devinfo
, inst
, dest
.type
);
856 /***********************************************************************
857 * Convenience routines.
860 brw_inst *brw_##OP(struct brw_codegen *p, \
861 struct brw_reg dest, \
862 struct brw_reg src0) \
864 return brw_alu1(p, BRW_OPCODE_##OP, dest, src0); \
868 brw_inst *brw_##OP(struct brw_codegen *p, \
869 struct brw_reg dest, \
870 struct brw_reg src0, \
871 struct brw_reg src1) \
873 return brw_alu2(p, BRW_OPCODE_##OP, dest, src0, src1); \
877 brw_inst *brw_##OP(struct brw_codegen *p, \
878 struct brw_reg dest, \
879 struct brw_reg src0, \
880 struct brw_reg src1, \
881 struct brw_reg src2) \
883 return brw_alu3(p, BRW_OPCODE_##OP, dest, src0, src1, src2); \
887 brw_inst *brw_##OP(struct brw_codegen *p, \
888 struct brw_reg dest, \
889 struct brw_reg src0, \
890 struct brw_reg src1, \
891 struct brw_reg src2) \
893 assert(dest.type == BRW_REGISTER_TYPE_F || \
894 dest.type == BRW_REGISTER_TYPE_DF); \
895 if (dest.type == BRW_REGISTER_TYPE_F) { \
896 assert(src0.type == BRW_REGISTER_TYPE_F); \
897 assert(src1.type == BRW_REGISTER_TYPE_F); \
898 assert(src2.type == BRW_REGISTER_TYPE_F); \
899 } else if (dest.type == BRW_REGISTER_TYPE_DF) { \
900 assert(src0.type == BRW_REGISTER_TYPE_DF); \
901 assert(src1.type == BRW_REGISTER_TYPE_DF); \
902 assert(src2.type == BRW_REGISTER_TYPE_DF); \
904 return brw_alu3(p, BRW_OPCODE_##OP, dest, src0, src1, src2); \
907 /* Rounding operations (other than RNDD) require two instructions - the first
908 * stores a rounded value (possibly the wrong way) in the dest register, but
909 * also sets a per-channel "increment bit" in the flag register. A predicated
910 * add of 1.0 fixes dest to contain the desired result.
912 * Sandybridge and later appear to round correctly without an ADD.
915 void brw_##OP(struct brw_codegen *p, \
916 struct brw_reg dest, \
917 struct brw_reg src) \
919 const struct gen_device_info *devinfo = p->devinfo; \
920 brw_inst *rnd, *add; \
921 rnd = next_insn(p, BRW_OPCODE_##OP); \
922 brw_set_dest(p, rnd, dest); \
923 brw_set_src0(p, rnd, src); \
925 if (devinfo->gen < 6) { \
926 /* turn on round-increments */ \
927 brw_inst_set_cond_modifier(devinfo, rnd, BRW_CONDITIONAL_R); \
928 add = brw_ADD(p, dest, dest, brw_imm_f(1.0f)); \
929 brw_inst_set_pred_control(devinfo, add, BRW_PREDICATE_NORMAL); \
968 brw_MOV(struct brw_codegen
*p
, struct brw_reg dest
, struct brw_reg src0
)
970 const struct gen_device_info
*devinfo
= p
->devinfo
;
972 /* When converting F->DF on IVB/BYT, every odd source channel is ignored.
973 * To avoid the problems that causes, we use a <1,2,0> source region to read
974 * each element twice.
976 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
977 brw_inst_access_mode(devinfo
, p
->current
) == BRW_ALIGN_1
&&
978 dest
.type
== BRW_REGISTER_TYPE_DF
&&
979 (src0
.type
== BRW_REGISTER_TYPE_F
||
980 src0
.type
== BRW_REGISTER_TYPE_D
||
981 src0
.type
== BRW_REGISTER_TYPE_UD
) &&
982 !has_scalar_region(src0
)) {
983 assert(src0
.vstride
== BRW_VERTICAL_STRIDE_4
&&
984 src0
.width
== BRW_WIDTH_4
&&
985 src0
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
987 src0
.vstride
= BRW_VERTICAL_STRIDE_1
;
988 src0
.width
= BRW_WIDTH_2
;
989 src0
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
992 return brw_alu1(p
, BRW_OPCODE_MOV
, dest
, src0
);
996 brw_ADD(struct brw_codegen
*p
, struct brw_reg dest
,
997 struct brw_reg src0
, struct brw_reg src1
)
1000 if (src0
.type
== BRW_REGISTER_TYPE_F
||
1001 (src0
.file
== BRW_IMMEDIATE_VALUE
&&
1002 src0
.type
== BRW_REGISTER_TYPE_VF
)) {
1003 assert(src1
.type
!= BRW_REGISTER_TYPE_UD
);
1004 assert(src1
.type
!= BRW_REGISTER_TYPE_D
);
1007 if (src1
.type
== BRW_REGISTER_TYPE_F
||
1008 (src1
.file
== BRW_IMMEDIATE_VALUE
&&
1009 src1
.type
== BRW_REGISTER_TYPE_VF
)) {
1010 assert(src0
.type
!= BRW_REGISTER_TYPE_UD
);
1011 assert(src0
.type
!= BRW_REGISTER_TYPE_D
);
1014 return brw_alu2(p
, BRW_OPCODE_ADD
, dest
, src0
, src1
);
1018 brw_AVG(struct brw_codegen
*p
, struct brw_reg dest
,
1019 struct brw_reg src0
, struct brw_reg src1
)
1021 assert(dest
.type
== src0
.type
);
1022 assert(src0
.type
== src1
.type
);
1023 switch (src0
.type
) {
1024 case BRW_REGISTER_TYPE_B
:
1025 case BRW_REGISTER_TYPE_UB
:
1026 case BRW_REGISTER_TYPE_W
:
1027 case BRW_REGISTER_TYPE_UW
:
1028 case BRW_REGISTER_TYPE_D
:
1029 case BRW_REGISTER_TYPE_UD
:
1032 unreachable("Bad type for brw_AVG");
1035 return brw_alu2(p
, BRW_OPCODE_AVG
, dest
, src0
, src1
);
1039 brw_MUL(struct brw_codegen
*p
, struct brw_reg dest
,
1040 struct brw_reg src0
, struct brw_reg src1
)
1043 if (src0
.type
== BRW_REGISTER_TYPE_D
||
1044 src0
.type
== BRW_REGISTER_TYPE_UD
||
1045 src1
.type
== BRW_REGISTER_TYPE_D
||
1046 src1
.type
== BRW_REGISTER_TYPE_UD
) {
1047 assert(dest
.type
!= BRW_REGISTER_TYPE_F
);
1050 if (src0
.type
== BRW_REGISTER_TYPE_F
||
1051 (src0
.file
== BRW_IMMEDIATE_VALUE
&&
1052 src0
.type
== BRW_REGISTER_TYPE_VF
)) {
1053 assert(src1
.type
!= BRW_REGISTER_TYPE_UD
);
1054 assert(src1
.type
!= BRW_REGISTER_TYPE_D
);
1057 if (src1
.type
== BRW_REGISTER_TYPE_F
||
1058 (src1
.file
== BRW_IMMEDIATE_VALUE
&&
1059 src1
.type
== BRW_REGISTER_TYPE_VF
)) {
1060 assert(src0
.type
!= BRW_REGISTER_TYPE_UD
);
1061 assert(src0
.type
!= BRW_REGISTER_TYPE_D
);
1064 assert(src0
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
||
1065 src0
.nr
!= BRW_ARF_ACCUMULATOR
);
1066 assert(src1
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
||
1067 src1
.nr
!= BRW_ARF_ACCUMULATOR
);
1069 return brw_alu2(p
, BRW_OPCODE_MUL
, dest
, src0
, src1
);
1073 brw_LINE(struct brw_codegen
*p
, struct brw_reg dest
,
1074 struct brw_reg src0
, struct brw_reg src1
)
1076 src0
.vstride
= BRW_VERTICAL_STRIDE_0
;
1077 src0
.width
= BRW_WIDTH_1
;
1078 src0
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1079 return brw_alu2(p
, BRW_OPCODE_LINE
, dest
, src0
, src1
);
1083 brw_PLN(struct brw_codegen
*p
, struct brw_reg dest
,
1084 struct brw_reg src0
, struct brw_reg src1
)
1086 src0
.vstride
= BRW_VERTICAL_STRIDE_0
;
1087 src0
.width
= BRW_WIDTH_1
;
1088 src0
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1089 src1
.vstride
= BRW_VERTICAL_STRIDE_8
;
1090 src1
.width
= BRW_WIDTH_8
;
1091 src1
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
1092 return brw_alu2(p
, BRW_OPCODE_PLN
, dest
, src0
, src1
);
1096 brw_F32TO16(struct brw_codegen
*p
, struct brw_reg dst
, struct brw_reg src
)
1098 const struct gen_device_info
*devinfo
= p
->devinfo
;
1099 const bool align16
= brw_inst_access_mode(devinfo
, p
->current
) == BRW_ALIGN_16
;
1100 /* The F32TO16 instruction doesn't support 32-bit destination types in
1101 * Align1 mode, and neither does the Gen8 implementation in terms of a
1102 * converting MOV. Gen7 does zero out the high 16 bits in Align16 mode as
1103 * an undocumented feature.
1105 const bool needs_zero_fill
= (dst
.type
== BRW_REGISTER_TYPE_UD
&&
1106 (!align16
|| devinfo
->gen
>= 8));
1110 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1112 assert(dst
.type
== BRW_REGISTER_TYPE_UD
||
1113 dst
.type
== BRW_REGISTER_TYPE_W
||
1114 dst
.type
== BRW_REGISTER_TYPE_UW
||
1115 dst
.type
== BRW_REGISTER_TYPE_HF
);
1118 brw_push_insn_state(p
);
1120 if (needs_zero_fill
) {
1121 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1122 dst
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1125 if (devinfo
->gen
>= 8) {
1126 inst
= brw_MOV(p
, retype(dst
, BRW_REGISTER_TYPE_HF
), src
);
1128 assert(devinfo
->gen
== 7);
1129 inst
= brw_alu1(p
, BRW_OPCODE_F32TO16
, dst
, src
);
1132 if (needs_zero_fill
) {
1133 brw_inst_set_no_dd_clear(devinfo
, inst
, true);
1134 inst
= brw_MOV(p
, suboffset(dst
, 1), brw_imm_w(0));
1135 brw_inst_set_no_dd_check(devinfo
, inst
, true);
1138 brw_pop_insn_state(p
);
1143 brw_F16TO32(struct brw_codegen
*p
, struct brw_reg dst
, struct brw_reg src
)
1145 const struct gen_device_info
*devinfo
= p
->devinfo
;
1146 bool align16
= brw_inst_access_mode(devinfo
, p
->current
) == BRW_ALIGN_16
;
1149 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
1151 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1153 * Because this instruction does not have a 16-bit floating-point
1154 * type, the source data type must be Word (W). The destination type
1155 * must be F (Float).
1157 if (src
.type
== BRW_REGISTER_TYPE_UD
)
1158 src
= spread(retype(src
, BRW_REGISTER_TYPE_W
), 2);
1160 assert(src
.type
== BRW_REGISTER_TYPE_W
||
1161 src
.type
== BRW_REGISTER_TYPE_UW
||
1162 src
.type
== BRW_REGISTER_TYPE_HF
);
1165 if (devinfo
->gen
>= 8) {
1166 return brw_MOV(p
, dst
, retype(src
, BRW_REGISTER_TYPE_HF
));
1168 assert(devinfo
->gen
== 7);
1169 return brw_alu1(p
, BRW_OPCODE_F16TO32
, dst
, src
);
1174 void brw_NOP(struct brw_codegen
*p
)
1176 brw_inst
*insn
= next_insn(p
, BRW_OPCODE_NOP
);
1177 memset(insn
, 0, sizeof(*insn
));
1178 brw_inst_set_opcode(p
->devinfo
, insn
, BRW_OPCODE_NOP
);
1185 /***********************************************************************
1186 * Comparisons, if/else/endif
1190 brw_JMPI(struct brw_codegen
*p
, struct brw_reg index
,
1191 unsigned predicate_control
)
1193 const struct gen_device_info
*devinfo
= p
->devinfo
;
1194 struct brw_reg ip
= brw_ip_reg();
1195 brw_inst
*inst
= brw_alu2(p
, BRW_OPCODE_JMPI
, ip
, ip
, index
);
1197 brw_inst_set_exec_size(devinfo
, inst
, BRW_EXECUTE_1
);
1198 brw_inst_set_qtr_control(devinfo
, inst
, BRW_COMPRESSION_NONE
);
1199 brw_inst_set_mask_control(devinfo
, inst
, BRW_MASK_DISABLE
);
1200 brw_inst_set_pred_control(devinfo
, inst
, predicate_control
);
1206 push_if_stack(struct brw_codegen
*p
, brw_inst
*inst
)
1208 p
->if_stack
[p
->if_stack_depth
] = inst
- p
->store
;
1210 p
->if_stack_depth
++;
1211 if (p
->if_stack_array_size
<= p
->if_stack_depth
) {
1212 p
->if_stack_array_size
*= 2;
1213 p
->if_stack
= reralloc(p
->mem_ctx
, p
->if_stack
, int,
1214 p
->if_stack_array_size
);
1219 pop_if_stack(struct brw_codegen
*p
)
1221 p
->if_stack_depth
--;
1222 return &p
->store
[p
->if_stack
[p
->if_stack_depth
]];
1226 push_loop_stack(struct brw_codegen
*p
, brw_inst
*inst
)
1228 if (p
->loop_stack_array_size
<= (p
->loop_stack_depth
+ 1)) {
1229 p
->loop_stack_array_size
*= 2;
1230 p
->loop_stack
= reralloc(p
->mem_ctx
, p
->loop_stack
, int,
1231 p
->loop_stack_array_size
);
1232 p
->if_depth_in_loop
= reralloc(p
->mem_ctx
, p
->if_depth_in_loop
, int,
1233 p
->loop_stack_array_size
);
1236 p
->loop_stack
[p
->loop_stack_depth
] = inst
- p
->store
;
1237 p
->loop_stack_depth
++;
1238 p
->if_depth_in_loop
[p
->loop_stack_depth
] = 0;
1242 get_inner_do_insn(struct brw_codegen
*p
)
1244 return &p
->store
[p
->loop_stack
[p
->loop_stack_depth
- 1]];
1247 /* EU takes the value from the flag register and pushes it onto some
1248 * sort of a stack (presumably merging with any flag value already on
1249 * the stack). Within an if block, the flags at the top of the stack
1250 * control execution on each channel of the unit, eg. on each of the
1251 * 16 pixel values in our wm programs.
1253 * When the matching 'else' instruction is reached (presumably by
1254 * countdown of the instruction count patched in by our ELSE/ENDIF
1255 * functions), the relevant flags are inverted.
1257 * When the matching 'endif' instruction is reached, the flags are
1258 * popped off. If the stack is now empty, normal execution resumes.
1261 brw_IF(struct brw_codegen
*p
, unsigned execute_size
)
1263 const struct gen_device_info
*devinfo
= p
->devinfo
;
1266 insn
= next_insn(p
, BRW_OPCODE_IF
);
1268 /* Override the defaults for this instruction:
1270 if (devinfo
->gen
< 6) {
1271 brw_set_dest(p
, insn
, brw_ip_reg());
1272 brw_set_src0(p
, insn
, brw_ip_reg());
1273 brw_set_src1(p
, insn
, brw_imm_d(0x0));
1274 } else if (devinfo
->gen
== 6) {
1275 brw_set_dest(p
, insn
, brw_imm_w(0));
1276 brw_inst_set_gen6_jump_count(devinfo
, insn
, 0);
1277 brw_set_src0(p
, insn
, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
)));
1278 brw_set_src1(p
, insn
, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
)));
1279 } else if (devinfo
->gen
== 7) {
1280 brw_set_dest(p
, insn
, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
)));
1281 brw_set_src0(p
, insn
, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
)));
1282 brw_set_src1(p
, insn
, brw_imm_w(0));
1283 brw_inst_set_jip(devinfo
, insn
, 0);
1284 brw_inst_set_uip(devinfo
, insn
, 0);
1286 brw_set_dest(p
, insn
, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
)));
1287 brw_set_src0(p
, insn
, brw_imm_d(0));
1288 brw_inst_set_jip(devinfo
, insn
, 0);
1289 brw_inst_set_uip(devinfo
, insn
, 0);
1292 brw_inst_set_exec_size(devinfo
, insn
, execute_size
);
1293 brw_inst_set_qtr_control(devinfo
, insn
, BRW_COMPRESSION_NONE
);
1294 brw_inst_set_pred_control(devinfo
, insn
, BRW_PREDICATE_NORMAL
);
1295 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_ENABLE
);
1296 if (!p
->single_program_flow
&& devinfo
->gen
< 6)
1297 brw_inst_set_thread_control(devinfo
, insn
, BRW_THREAD_SWITCH
);
1299 push_if_stack(p
, insn
);
1300 p
->if_depth_in_loop
[p
->loop_stack_depth
]++;
1304 /* This function is only used for gen6-style IF instructions with an
1305 * embedded comparison (conditional modifier). It is not used on gen7.
1308 gen6_IF(struct brw_codegen
*p
, enum brw_conditional_mod conditional
,
1309 struct brw_reg src0
, struct brw_reg src1
)
1311 const struct gen_device_info
*devinfo
= p
->devinfo
;
1314 insn
= next_insn(p
, BRW_OPCODE_IF
);
1316 brw_set_dest(p
, insn
, brw_imm_w(0));
1317 brw_inst_set_exec_size(devinfo
, insn
,
1318 brw_inst_exec_size(devinfo
, p
->current
));
1319 brw_inst_set_gen6_jump_count(devinfo
, insn
, 0);
1320 brw_set_src0(p
, insn
, src0
);
1321 brw_set_src1(p
, insn
, src1
);
1323 assert(brw_inst_qtr_control(devinfo
, insn
) == BRW_COMPRESSION_NONE
);
1324 assert(brw_inst_pred_control(devinfo
, insn
) == BRW_PREDICATE_NONE
);
1325 brw_inst_set_cond_modifier(devinfo
, insn
, conditional
);
1327 push_if_stack(p
, insn
);
1332 * In single-program-flow (SPF) mode, convert IF and ELSE into ADDs.
1335 convert_IF_ELSE_to_ADD(struct brw_codegen
*p
,
1336 brw_inst
*if_inst
, brw_inst
*else_inst
)
1338 const struct gen_device_info
*devinfo
= p
->devinfo
;
1340 /* The next instruction (where the ENDIF would be, if it existed) */
1341 brw_inst
*next_inst
= &p
->store
[p
->nr_insn
];
1343 assert(p
->single_program_flow
);
1344 assert(if_inst
!= NULL
&& brw_inst_opcode(devinfo
, if_inst
) == BRW_OPCODE_IF
);
1345 assert(else_inst
== NULL
|| brw_inst_opcode(devinfo
, else_inst
) == BRW_OPCODE_ELSE
);
1346 assert(brw_inst_exec_size(devinfo
, if_inst
) == BRW_EXECUTE_1
);
1348 /* Convert IF to an ADD instruction that moves the instruction pointer
1349 * to the first instruction of the ELSE block. If there is no ELSE
1350 * block, point to where ENDIF would be. Reverse the predicate.
1352 * There's no need to execute an ENDIF since we don't need to do any
1353 * stack operations, and if we're currently executing, we just want to
1354 * continue normally.
1356 brw_inst_set_opcode(devinfo
, if_inst
, BRW_OPCODE_ADD
);
1357 brw_inst_set_pred_inv(devinfo
, if_inst
, true);
1359 if (else_inst
!= NULL
) {
1360 /* Convert ELSE to an ADD instruction that points where the ENDIF
1363 brw_inst_set_opcode(devinfo
, else_inst
, BRW_OPCODE_ADD
);
1365 brw_inst_set_imm_ud(devinfo
, if_inst
, (else_inst
- if_inst
+ 1) * 16);
1366 brw_inst_set_imm_ud(devinfo
, else_inst
, (next_inst
- else_inst
) * 16);
1368 brw_inst_set_imm_ud(devinfo
, if_inst
, (next_inst
- if_inst
) * 16);
1373 * Patch IF and ELSE instructions with appropriate jump targets.
1376 patch_IF_ELSE(struct brw_codegen
*p
,
1377 brw_inst
*if_inst
, brw_inst
*else_inst
, brw_inst
*endif_inst
)
1379 const struct gen_device_info
*devinfo
= p
->devinfo
;
1381 /* We shouldn't be patching IF and ELSE instructions in single program flow
1382 * mode when gen < 6, because in single program flow mode on those
1383 * platforms, we convert flow control instructions to conditional ADDs that
1384 * operate on IP (see brw_ENDIF).
1386 * However, on Gen6, writing to IP doesn't work in single program flow mode
1387 * (see the SandyBridge PRM, Volume 4 part 2, p79: "When SPF is ON, IP may
1388 * not be updated by non-flow control instructions."). And on later
1389 * platforms, there is no significant benefit to converting control flow
1390 * instructions to conditional ADDs. So we do patch IF and ELSE
1391 * instructions in single program flow mode on those platforms.
1393 if (devinfo
->gen
< 6)
1394 assert(!p
->single_program_flow
);
1396 assert(if_inst
!= NULL
&& brw_inst_opcode(devinfo
, if_inst
) == BRW_OPCODE_IF
);
1397 assert(endif_inst
!= NULL
);
1398 assert(else_inst
== NULL
|| brw_inst_opcode(devinfo
, else_inst
) == BRW_OPCODE_ELSE
);
1400 unsigned br
= brw_jump_scale(devinfo
);
1402 assert(brw_inst_opcode(devinfo
, endif_inst
) == BRW_OPCODE_ENDIF
);
1403 brw_inst_set_exec_size(devinfo
, endif_inst
, brw_inst_exec_size(devinfo
, if_inst
));
1405 if (else_inst
== NULL
) {
1406 /* Patch IF -> ENDIF */
1407 if (devinfo
->gen
< 6) {
1408 /* Turn it into an IFF, which means no mask stack operations for
1409 * all-false and jumping past the ENDIF.
1411 brw_inst_set_opcode(devinfo
, if_inst
, BRW_OPCODE_IFF
);
1412 brw_inst_set_gen4_jump_count(devinfo
, if_inst
,
1413 br
* (endif_inst
- if_inst
+ 1));
1414 brw_inst_set_gen4_pop_count(devinfo
, if_inst
, 0);
1415 } else if (devinfo
->gen
== 6) {
1416 /* As of gen6, there is no IFF and IF must point to the ENDIF. */
1417 brw_inst_set_gen6_jump_count(devinfo
, if_inst
, br
*(endif_inst
- if_inst
));
1419 brw_inst_set_uip(devinfo
, if_inst
, br
* (endif_inst
- if_inst
));
1420 brw_inst_set_jip(devinfo
, if_inst
, br
* (endif_inst
- if_inst
));
1423 brw_inst_set_exec_size(devinfo
, else_inst
, brw_inst_exec_size(devinfo
, if_inst
));
1425 /* Patch IF -> ELSE */
1426 if (devinfo
->gen
< 6) {
1427 brw_inst_set_gen4_jump_count(devinfo
, if_inst
,
1428 br
* (else_inst
- if_inst
));
1429 brw_inst_set_gen4_pop_count(devinfo
, if_inst
, 0);
1430 } else if (devinfo
->gen
== 6) {
1431 brw_inst_set_gen6_jump_count(devinfo
, if_inst
,
1432 br
* (else_inst
- if_inst
+ 1));
1435 /* Patch ELSE -> ENDIF */
1436 if (devinfo
->gen
< 6) {
1437 /* BRW_OPCODE_ELSE pre-gen6 should point just past the
1440 brw_inst_set_gen4_jump_count(devinfo
, else_inst
,
1441 br
* (endif_inst
- else_inst
+ 1));
1442 brw_inst_set_gen4_pop_count(devinfo
, else_inst
, 1);
1443 } else if (devinfo
->gen
== 6) {
1444 /* BRW_OPCODE_ELSE on gen6 should point to the matching ENDIF. */
1445 brw_inst_set_gen6_jump_count(devinfo
, else_inst
,
1446 br
* (endif_inst
- else_inst
));
1448 /* The IF instruction's JIP should point just past the ELSE */
1449 brw_inst_set_jip(devinfo
, if_inst
, br
* (else_inst
- if_inst
+ 1));
1450 /* The IF instruction's UIP and ELSE's JIP should point to ENDIF */
1451 brw_inst_set_uip(devinfo
, if_inst
, br
* (endif_inst
- if_inst
));
1452 brw_inst_set_jip(devinfo
, else_inst
, br
* (endif_inst
- else_inst
));
1453 if (devinfo
->gen
>= 8) {
1454 /* Since we don't set branch_ctrl, the ELSE's JIP and UIP both
1455 * should point to ENDIF.
1457 brw_inst_set_uip(devinfo
, else_inst
, br
* (endif_inst
- else_inst
));
1464 brw_ELSE(struct brw_codegen
*p
)
1466 const struct gen_device_info
*devinfo
= p
->devinfo
;
1469 insn
= next_insn(p
, BRW_OPCODE_ELSE
);
1471 if (devinfo
->gen
< 6) {
1472 brw_set_dest(p
, insn
, brw_ip_reg());
1473 brw_set_src0(p
, insn
, brw_ip_reg());
1474 brw_set_src1(p
, insn
, brw_imm_d(0x0));
1475 } else if (devinfo
->gen
== 6) {
1476 brw_set_dest(p
, insn
, brw_imm_w(0));
1477 brw_inst_set_gen6_jump_count(devinfo
, insn
, 0);
1478 brw_set_src0(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1479 brw_set_src1(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1480 } else if (devinfo
->gen
== 7) {
1481 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1482 brw_set_src0(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1483 brw_set_src1(p
, insn
, brw_imm_w(0));
1484 brw_inst_set_jip(devinfo
, insn
, 0);
1485 brw_inst_set_uip(devinfo
, insn
, 0);
1487 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1488 brw_set_src0(p
, insn
, brw_imm_d(0));
1489 brw_inst_set_jip(devinfo
, insn
, 0);
1490 brw_inst_set_uip(devinfo
, insn
, 0);
1493 brw_inst_set_qtr_control(devinfo
, insn
, BRW_COMPRESSION_NONE
);
1494 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_ENABLE
);
1495 if (!p
->single_program_flow
&& devinfo
->gen
< 6)
1496 brw_inst_set_thread_control(devinfo
, insn
, BRW_THREAD_SWITCH
);
1498 push_if_stack(p
, insn
);
1502 brw_ENDIF(struct brw_codegen
*p
)
1504 const struct gen_device_info
*devinfo
= p
->devinfo
;
1505 brw_inst
*insn
= NULL
;
1506 brw_inst
*else_inst
= NULL
;
1507 brw_inst
*if_inst
= NULL
;
1509 bool emit_endif
= true;
1511 /* In single program flow mode, we can express IF and ELSE instructions
1512 * equivalently as ADD instructions that operate on IP. On platforms prior
1513 * to Gen6, flow control instructions cause an implied thread switch, so
1514 * this is a significant savings.
1516 * However, on Gen6, writing to IP doesn't work in single program flow mode
1517 * (see the SandyBridge PRM, Volume 4 part 2, p79: "When SPF is ON, IP may
1518 * not be updated by non-flow control instructions."). And on later
1519 * platforms, there is no significant benefit to converting control flow
1520 * instructions to conditional ADDs. So we only do this trick on Gen4 and
1523 if (devinfo
->gen
< 6 && p
->single_program_flow
)
1527 * A single next_insn() may change the base address of instruction store
1528 * memory(p->store), so call it first before referencing the instruction
1529 * store pointer from an index
1532 insn
= next_insn(p
, BRW_OPCODE_ENDIF
);
1534 /* Pop the IF and (optional) ELSE instructions from the stack */
1535 p
->if_depth_in_loop
[p
->loop_stack_depth
]--;
1536 tmp
= pop_if_stack(p
);
1537 if (brw_inst_opcode(devinfo
, tmp
) == BRW_OPCODE_ELSE
) {
1539 tmp
= pop_if_stack(p
);
1544 /* ENDIF is useless; don't bother emitting it. */
1545 convert_IF_ELSE_to_ADD(p
, if_inst
, else_inst
);
1549 if (devinfo
->gen
< 6) {
1550 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1551 brw_set_src0(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1552 brw_set_src1(p
, insn
, brw_imm_d(0x0));
1553 } else if (devinfo
->gen
== 6) {
1554 brw_set_dest(p
, insn
, brw_imm_w(0));
1555 brw_set_src0(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1556 brw_set_src1(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1557 } else if (devinfo
->gen
== 7) {
1558 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1559 brw_set_src0(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1560 brw_set_src1(p
, insn
, brw_imm_w(0));
1562 brw_set_src0(p
, insn
, brw_imm_d(0));
1565 brw_inst_set_qtr_control(devinfo
, insn
, BRW_COMPRESSION_NONE
);
1566 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_ENABLE
);
1567 if (devinfo
->gen
< 6)
1568 brw_inst_set_thread_control(devinfo
, insn
, BRW_THREAD_SWITCH
);
1570 /* Also pop item off the stack in the endif instruction: */
1571 if (devinfo
->gen
< 6) {
1572 brw_inst_set_gen4_jump_count(devinfo
, insn
, 0);
1573 brw_inst_set_gen4_pop_count(devinfo
, insn
, 1);
1574 } else if (devinfo
->gen
== 6) {
1575 brw_inst_set_gen6_jump_count(devinfo
, insn
, 2);
1577 brw_inst_set_jip(devinfo
, insn
, 2);
1579 patch_IF_ELSE(p
, if_inst
, else_inst
, insn
);
1583 brw_BREAK(struct brw_codegen
*p
)
1585 const struct gen_device_info
*devinfo
= p
->devinfo
;
1588 insn
= next_insn(p
, BRW_OPCODE_BREAK
);
1589 if (devinfo
->gen
>= 8) {
1590 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1591 brw_set_src0(p
, insn
, brw_imm_d(0x0));
1592 } else if (devinfo
->gen
>= 6) {
1593 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1594 brw_set_src0(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1595 brw_set_src1(p
, insn
, brw_imm_d(0x0));
1597 brw_set_dest(p
, insn
, brw_ip_reg());
1598 brw_set_src0(p
, insn
, brw_ip_reg());
1599 brw_set_src1(p
, insn
, brw_imm_d(0x0));
1600 brw_inst_set_gen4_pop_count(devinfo
, insn
,
1601 p
->if_depth_in_loop
[p
->loop_stack_depth
]);
1603 brw_inst_set_qtr_control(devinfo
, insn
, BRW_COMPRESSION_NONE
);
1604 brw_inst_set_exec_size(devinfo
, insn
,
1605 brw_inst_exec_size(devinfo
, p
->current
));
1611 brw_CONT(struct brw_codegen
*p
)
1613 const struct gen_device_info
*devinfo
= p
->devinfo
;
1616 insn
= next_insn(p
, BRW_OPCODE_CONTINUE
);
1617 brw_set_dest(p
, insn
, brw_ip_reg());
1618 if (devinfo
->gen
>= 8) {
1619 brw_set_src0(p
, insn
, brw_imm_d(0x0));
1621 brw_set_src0(p
, insn
, brw_ip_reg());
1622 brw_set_src1(p
, insn
, brw_imm_d(0x0));
1625 if (devinfo
->gen
< 6) {
1626 brw_inst_set_gen4_pop_count(devinfo
, insn
,
1627 p
->if_depth_in_loop
[p
->loop_stack_depth
]);
1629 brw_inst_set_qtr_control(devinfo
, insn
, BRW_COMPRESSION_NONE
);
1630 brw_inst_set_exec_size(devinfo
, insn
,
1631 brw_inst_exec_size(devinfo
, p
->current
));
1636 gen6_HALT(struct brw_codegen
*p
)
1638 const struct gen_device_info
*devinfo
= p
->devinfo
;
1641 insn
= next_insn(p
, BRW_OPCODE_HALT
);
1642 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1643 if (devinfo
->gen
>= 8) {
1644 brw_set_src0(p
, insn
, brw_imm_d(0x0));
1646 brw_set_src0(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1647 brw_set_src1(p
, insn
, brw_imm_d(0x0)); /* UIP and JIP, updated later. */
1650 brw_inst_set_qtr_control(devinfo
, insn
, BRW_COMPRESSION_NONE
);
1651 brw_inst_set_exec_size(devinfo
, insn
,
1652 brw_inst_exec_size(devinfo
, p
->current
));
1658 * The DO/WHILE is just an unterminated loop -- break or continue are
1659 * used for control within the loop. We have a few ways they can be
1662 * For uniform control flow, the WHILE is just a jump, so ADD ip, ip,
1663 * jip and no DO instruction.
1665 * For non-uniform control flow pre-gen6, there's a DO instruction to
1666 * push the mask, and a WHILE to jump back, and BREAK to get out and
1669 * For gen6, there's no more mask stack, so no need for DO. WHILE
1670 * just points back to the first instruction of the loop.
1673 brw_DO(struct brw_codegen
*p
, unsigned execute_size
)
1675 const struct gen_device_info
*devinfo
= p
->devinfo
;
1677 if (devinfo
->gen
>= 6 || p
->single_program_flow
) {
1678 push_loop_stack(p
, &p
->store
[p
->nr_insn
]);
1679 return &p
->store
[p
->nr_insn
];
1681 brw_inst
*insn
= next_insn(p
, BRW_OPCODE_DO
);
1683 push_loop_stack(p
, insn
);
1685 /* Override the defaults for this instruction:
1687 brw_set_dest(p
, insn
, brw_null_reg());
1688 brw_set_src0(p
, insn
, brw_null_reg());
1689 brw_set_src1(p
, insn
, brw_null_reg());
1691 brw_inst_set_qtr_control(devinfo
, insn
, BRW_COMPRESSION_NONE
);
1692 brw_inst_set_exec_size(devinfo
, insn
, execute_size
);
1693 brw_inst_set_pred_control(devinfo
, insn
, BRW_PREDICATE_NONE
);
1700 * For pre-gen6, we patch BREAK/CONT instructions to point at the WHILE
1703 * For gen6+, see brw_set_uip_jip(), which doesn't care so much about the loop
1704 * nesting, since it can always just point to the end of the block/current loop.
1707 brw_patch_break_cont(struct brw_codegen
*p
, brw_inst
*while_inst
)
1709 const struct gen_device_info
*devinfo
= p
->devinfo
;
1710 brw_inst
*do_inst
= get_inner_do_insn(p
);
1712 unsigned br
= brw_jump_scale(devinfo
);
1714 assert(devinfo
->gen
< 6);
1716 for (inst
= while_inst
- 1; inst
!= do_inst
; inst
--) {
1717 /* If the jump count is != 0, that means that this instruction has already
1718 * been patched because it's part of a loop inside of the one we're
1721 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_BREAK
&&
1722 brw_inst_gen4_jump_count(devinfo
, inst
) == 0) {
1723 brw_inst_set_gen4_jump_count(devinfo
, inst
, br
*((while_inst
- inst
) + 1));
1724 } else if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_CONTINUE
&&
1725 brw_inst_gen4_jump_count(devinfo
, inst
) == 0) {
1726 brw_inst_set_gen4_jump_count(devinfo
, inst
, br
* (while_inst
- inst
));
1732 brw_WHILE(struct brw_codegen
*p
)
1734 const struct gen_device_info
*devinfo
= p
->devinfo
;
1735 brw_inst
*insn
, *do_insn
;
1736 unsigned br
= brw_jump_scale(devinfo
);
1738 if (devinfo
->gen
>= 6) {
1739 insn
= next_insn(p
, BRW_OPCODE_WHILE
);
1740 do_insn
= get_inner_do_insn(p
);
1742 if (devinfo
->gen
>= 8) {
1743 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1744 brw_set_src0(p
, insn
, brw_imm_d(0));
1745 brw_inst_set_jip(devinfo
, insn
, br
* (do_insn
- insn
));
1746 } else if (devinfo
->gen
== 7) {
1747 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1748 brw_set_src0(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1749 brw_set_src1(p
, insn
, brw_imm_w(0));
1750 brw_inst_set_jip(devinfo
, insn
, br
* (do_insn
- insn
));
1752 brw_set_dest(p
, insn
, brw_imm_w(0));
1753 brw_inst_set_gen6_jump_count(devinfo
, insn
, br
* (do_insn
- insn
));
1754 brw_set_src0(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1755 brw_set_src1(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
1758 brw_inst_set_exec_size(devinfo
, insn
,
1759 brw_inst_exec_size(devinfo
, p
->current
));
1762 if (p
->single_program_flow
) {
1763 insn
= next_insn(p
, BRW_OPCODE_ADD
);
1764 do_insn
= get_inner_do_insn(p
);
1766 brw_set_dest(p
, insn
, brw_ip_reg());
1767 brw_set_src0(p
, insn
, brw_ip_reg());
1768 brw_set_src1(p
, insn
, brw_imm_d((do_insn
- insn
) * 16));
1769 brw_inst_set_exec_size(devinfo
, insn
, BRW_EXECUTE_1
);
1771 insn
= next_insn(p
, BRW_OPCODE_WHILE
);
1772 do_insn
= get_inner_do_insn(p
);
1774 assert(brw_inst_opcode(devinfo
, do_insn
) == BRW_OPCODE_DO
);
1776 brw_set_dest(p
, insn
, brw_ip_reg());
1777 brw_set_src0(p
, insn
, brw_ip_reg());
1778 brw_set_src1(p
, insn
, brw_imm_d(0));
1780 brw_inst_set_exec_size(devinfo
, insn
, brw_inst_exec_size(devinfo
, do_insn
));
1781 brw_inst_set_gen4_jump_count(devinfo
, insn
, br
* (do_insn
- insn
+ 1));
1782 brw_inst_set_gen4_pop_count(devinfo
, insn
, 0);
1784 brw_patch_break_cont(p
, insn
);
1787 brw_inst_set_qtr_control(devinfo
, insn
, BRW_COMPRESSION_NONE
);
1789 p
->loop_stack_depth
--;
1796 void brw_land_fwd_jump(struct brw_codegen
*p
, int jmp_insn_idx
)
1798 const struct gen_device_info
*devinfo
= p
->devinfo
;
1799 brw_inst
*jmp_insn
= &p
->store
[jmp_insn_idx
];
1802 if (devinfo
->gen
>= 5)
1805 assert(brw_inst_opcode(devinfo
, jmp_insn
) == BRW_OPCODE_JMPI
);
1806 assert(brw_inst_src1_reg_file(devinfo
, jmp_insn
) == BRW_IMMEDIATE_VALUE
);
1808 brw_inst_set_gen4_jump_count(devinfo
, jmp_insn
,
1809 jmpi
* (p
->nr_insn
- jmp_insn_idx
- 1));
1812 /* To integrate with the above, it makes sense that the comparison
1813 * instruction should populate the flag register. It might be simpler
1814 * just to use the flag reg for most WM tasks?
1816 void brw_CMP(struct brw_codegen
*p
,
1817 struct brw_reg dest
,
1818 unsigned conditional
,
1819 struct brw_reg src0
,
1820 struct brw_reg src1
)
1822 const struct gen_device_info
*devinfo
= p
->devinfo
;
1823 brw_inst
*insn
= next_insn(p
, BRW_OPCODE_CMP
);
1825 brw_inst_set_cond_modifier(devinfo
, insn
, conditional
);
1826 brw_set_dest(p
, insn
, dest
);
1827 brw_set_src0(p
, insn
, src0
);
1828 brw_set_src1(p
, insn
, src1
);
1830 /* Item WaCMPInstNullDstForcesThreadSwitch in the Haswell Bspec workarounds
1832 * "Any CMP instruction with a null destination must use a {switch}."
1834 * It also applies to other Gen7 platforms (IVB, BYT) even though it isn't
1835 * mentioned on their work-arounds pages.
1837 if (devinfo
->gen
== 7) {
1838 if (dest
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
1839 dest
.nr
== BRW_ARF_NULL
) {
1840 brw_inst_set_thread_control(devinfo
, insn
, BRW_THREAD_SWITCH
);
1845 /***********************************************************************
1846 * Helpers for the various SEND message types:
1849 /** Extended math function, float[8].
1851 void gen4_math(struct brw_codegen
*p
,
1852 struct brw_reg dest
,
1854 unsigned msg_reg_nr
,
1856 unsigned precision
)
1858 const struct gen_device_info
*devinfo
= p
->devinfo
;
1859 brw_inst
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
1861 if (has_scalar_region(src
)) {
1862 data_type
= BRW_MATH_DATA_SCALAR
;
1864 data_type
= BRW_MATH_DATA_VECTOR
;
1867 assert(devinfo
->gen
< 6);
1869 /* Example code doesn't set predicate_control for send
1872 brw_inst_set_pred_control(devinfo
, insn
, 0);
1873 brw_inst_set_base_mrf(devinfo
, insn
, msg_reg_nr
);
1875 brw_set_dest(p
, insn
, dest
);
1876 brw_set_src0(p
, insn
, src
);
1877 brw_set_math_message(p
,
1880 src
.type
== BRW_REGISTER_TYPE_D
,
1885 void gen6_math(struct brw_codegen
*p
,
1886 struct brw_reg dest
,
1888 struct brw_reg src0
,
1889 struct brw_reg src1
)
1891 const struct gen_device_info
*devinfo
= p
->devinfo
;
1892 brw_inst
*insn
= next_insn(p
, BRW_OPCODE_MATH
);
1894 assert(devinfo
->gen
>= 6);
1896 assert(dest
.file
== BRW_GENERAL_REGISTER_FILE
||
1897 (devinfo
->gen
>= 7 && dest
.file
== BRW_MESSAGE_REGISTER_FILE
));
1899 assert(dest
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
1900 if (devinfo
->gen
== 6) {
1901 assert(src0
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
1902 assert(src1
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
1905 if (function
== BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
||
1906 function
== BRW_MATH_FUNCTION_INT_DIV_REMAINDER
||
1907 function
== BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
) {
1908 assert(src0
.type
!= BRW_REGISTER_TYPE_F
);
1909 assert(src1
.type
!= BRW_REGISTER_TYPE_F
);
1910 assert(src1
.file
== BRW_GENERAL_REGISTER_FILE
||
1911 (devinfo
->gen
>= 8 && src1
.file
== BRW_IMMEDIATE_VALUE
));
1913 assert(src0
.type
== BRW_REGISTER_TYPE_F
);
1914 assert(src1
.type
== BRW_REGISTER_TYPE_F
);
1917 /* Source modifiers are ignored for extended math instructions on Gen6. */
1918 if (devinfo
->gen
== 6) {
1919 assert(!src0
.negate
);
1921 assert(!src1
.negate
);
1925 brw_inst_set_math_function(devinfo
, insn
, function
);
1927 brw_set_dest(p
, insn
, dest
);
1928 brw_set_src0(p
, insn
, src0
);
1929 brw_set_src1(p
, insn
, src1
);
1933 * Return the right surface index to access the thread scratch space using
1934 * stateless dataport messages.
1937 brw_scratch_surface_idx(const struct brw_codegen
*p
)
1939 /* The scratch space is thread-local so IA coherency is unnecessary. */
1940 if (p
->devinfo
->gen
>= 8)
1941 return GEN8_BTI_STATELESS_NON_COHERENT
;
1943 return BRW_BTI_STATELESS
;
1947 * Write a block of OWORDs (half a GRF each) from the scratch buffer,
1948 * using a constant offset per channel.
1950 * The offset must be aligned to oword size (16 bytes). Used for
1951 * register spilling.
1953 void brw_oword_block_write_scratch(struct brw_codegen
*p
,
1958 const struct gen_device_info
*devinfo
= p
->devinfo
;
1959 const unsigned target_cache
=
1960 (devinfo
->gen
>= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE
:
1961 devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE
:
1962 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
);
1965 if (devinfo
->gen
>= 6)
1968 mrf
= retype(mrf
, BRW_REGISTER_TYPE_UD
);
1970 const unsigned mlen
= 1 + num_regs
;
1972 /* Set up the message header. This is g0, with g0.2 filled with
1973 * the offset. We don't want to leave our offset around in g0 or
1974 * it'll screw up texture samples, so set it up inside the message
1978 brw_push_insn_state(p
);
1979 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1980 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1981 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1983 brw_MOV(p
, mrf
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1985 /* set message header global offset field (reg 0, element 2) */
1987 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
,
1989 2), BRW_REGISTER_TYPE_UD
),
1990 brw_imm_ud(offset
));
1992 brw_pop_insn_state(p
);
1996 struct brw_reg dest
;
1997 brw_inst
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
1998 int send_commit_msg
;
1999 struct brw_reg src_header
= retype(brw_vec8_grf(0, 0),
2000 BRW_REGISTER_TYPE_UW
);
2002 brw_inst_set_compression(devinfo
, insn
, false);
2004 if (brw_inst_exec_size(devinfo
, insn
) >= 16)
2005 src_header
= vec16(src_header
);
2007 assert(brw_inst_pred_control(devinfo
, insn
) == BRW_PREDICATE_NONE
);
2008 if (devinfo
->gen
< 6)
2009 brw_inst_set_base_mrf(devinfo
, insn
, mrf
.nr
);
2011 /* Until gen6, writes followed by reads from the same location
2012 * are not guaranteed to be ordered unless write_commit is set.
2013 * If set, then a no-op write is issued to the destination
2014 * register to set a dependency, and a read from the destination
2015 * can be used to ensure the ordering.
2017 * For gen6, only writes between different threads need ordering
2018 * protection. Our use of DP writes is all about register
2019 * spilling within a thread.
2021 if (devinfo
->gen
>= 6) {
2022 dest
= retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW
);
2023 send_commit_msg
= 0;
2026 send_commit_msg
= 1;
2029 brw_set_dest(p
, insn
, dest
);
2030 if (devinfo
->gen
>= 6) {
2031 brw_set_src0(p
, insn
, mrf
);
2033 brw_set_src0(p
, insn
, brw_null_reg());
2036 if (devinfo
->gen
>= 6)
2037 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE
;
2039 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE
;
2041 brw_set_dp_write_message(p
,
2043 brw_scratch_surface_idx(p
),
2044 BRW_DATAPORT_OWORD_BLOCK_DWORDS(num_regs
* 8),
2048 true, /* header_present */
2049 0, /* not a render target */
2050 send_commit_msg
, /* response_length */
2058 * Read a block of owords (half a GRF each) from the scratch buffer
2059 * using a constant index per channel.
2061 * Offset must be aligned to oword size (16 bytes). Used for register
2065 brw_oword_block_read_scratch(struct brw_codegen
*p
,
2066 struct brw_reg dest
,
2071 const struct gen_device_info
*devinfo
= p
->devinfo
;
2073 if (devinfo
->gen
>= 6)
2076 if (p
->devinfo
->gen
>= 7) {
2077 /* On gen 7 and above, we no longer have message registers and we can
2078 * send from any register we want. By using the destination register
2079 * for the message, we guarantee that the implied message write won't
2080 * accidentally overwrite anything. This has been a problem because
2081 * the MRF registers and source for the final FB write are both fixed
2084 mrf
= retype(dest
, BRW_REGISTER_TYPE_UD
);
2086 mrf
= retype(mrf
, BRW_REGISTER_TYPE_UD
);
2088 dest
= retype(dest
, BRW_REGISTER_TYPE_UW
);
2090 const unsigned rlen
= num_regs
;
2091 const unsigned target_cache
=
2092 (devinfo
->gen
>= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE
:
2093 devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE
:
2094 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
);
2097 brw_push_insn_state(p
);
2098 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
2099 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
2100 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
2102 brw_MOV(p
, mrf
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2104 /* set message header global offset field (reg 0, element 2) */
2105 brw_MOV(p
, get_element_ud(mrf
, 2), brw_imm_ud(offset
));
2107 brw_pop_insn_state(p
);
2111 brw_inst
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
2113 assert(brw_inst_pred_control(devinfo
, insn
) == 0);
2114 brw_inst_set_compression(devinfo
, insn
, false);
2116 brw_set_dest(p
, insn
, dest
); /* UW? */
2117 if (devinfo
->gen
>= 6) {
2118 brw_set_src0(p
, insn
, mrf
);
2120 brw_set_src0(p
, insn
, brw_null_reg());
2121 brw_inst_set_base_mrf(devinfo
, insn
, mrf
.nr
);
2124 brw_set_dp_read_message(p
,
2126 brw_scratch_surface_idx(p
),
2127 BRW_DATAPORT_OWORD_BLOCK_DWORDS(num_regs
* 8),
2128 BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ
, /* msg_type */
2131 true, /* header_present */
2137 gen7_block_read_scratch(struct brw_codegen
*p
,
2138 struct brw_reg dest
,
2142 brw_inst
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
2143 assert(brw_inst_pred_control(p
->devinfo
, insn
) == BRW_PREDICATE_NONE
);
2145 brw_set_dest(p
, insn
, retype(dest
, BRW_REGISTER_TYPE_UW
));
2147 /* The HW requires that the header is present; this is to get the g0.5
2150 brw_set_src0(p
, insn
, brw_vec8_grf(0, 0));
2152 /* According to the docs, offset is "A 12-bit HWord offset into the memory
2153 * Immediate Memory buffer as specified by binding table 0xFF." An HWORD
2154 * is 32 bytes, which happens to be the size of a register.
2157 assert(offset
< (1 << 12));
2159 gen7_set_dp_scratch_message(p
, insn
,
2160 false, /* scratch read */
2162 false, /* invalidate after read */
2165 1, /* mlen: just g0 */
2166 num_regs
, /* rlen */
2167 true); /* header present */
2171 * Read float[4] vectors from the data port constant cache.
2172 * Location (in buffer) should be a multiple of 16.
2173 * Used for fetching shader constants.
2175 void brw_oword_block_read(struct brw_codegen
*p
,
2176 struct brw_reg dest
,
2179 uint32_t bind_table_index
)
2181 const struct gen_device_info
*devinfo
= p
->devinfo
;
2182 const unsigned target_cache
=
2183 (devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_CONSTANT_CACHE
:
2184 BRW_DATAPORT_READ_TARGET_DATA_CACHE
);
2185 const unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, p
->current
);
2187 /* On newer hardware, offset is in units of owords. */
2188 if (devinfo
->gen
>= 6)
2191 mrf
= retype(mrf
, BRW_REGISTER_TYPE_UD
);
2193 brw_push_insn_state(p
);
2194 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
2195 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
2196 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
2198 brw_push_insn_state(p
);
2199 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
2200 brw_MOV(p
, mrf
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2202 /* set message header global offset field (reg 0, element 2) */
2204 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
,
2206 2), BRW_REGISTER_TYPE_UD
),
2207 brw_imm_ud(offset
));
2208 brw_pop_insn_state(p
);
2210 brw_inst
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
2212 /* cast dest to a uword[8] vector */
2213 dest
= retype(vec8(dest
), BRW_REGISTER_TYPE_UW
);
2215 brw_set_dest(p
, insn
, dest
);
2216 if (devinfo
->gen
>= 6) {
2217 brw_set_src0(p
, insn
, mrf
);
2219 brw_set_src0(p
, insn
, brw_null_reg());
2220 brw_inst_set_base_mrf(devinfo
, insn
, mrf
.nr
);
2223 brw_set_dp_read_message(p
, insn
, bind_table_index
,
2224 BRW_DATAPORT_OWORD_BLOCK_DWORDS(exec_size
),
2225 BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ
,
2228 true, /* header_present */
2229 DIV_ROUND_UP(exec_size
, 8)); /* response_length */
2231 brw_pop_insn_state(p
);
2235 void brw_fb_WRITE(struct brw_codegen
*p
,
2236 struct brw_reg payload
,
2237 struct brw_reg implied_header
,
2238 unsigned msg_control
,
2239 unsigned binding_table_index
,
2240 unsigned msg_length
,
2241 unsigned response_length
,
2243 bool last_render_target
,
2244 bool header_present
)
2246 const struct gen_device_info
*devinfo
= p
->devinfo
;
2247 const unsigned target_cache
=
2248 (devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE
:
2249 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
);
2252 struct brw_reg dest
, src0
;
2254 if (brw_inst_exec_size(devinfo
, p
->current
) >= BRW_EXECUTE_16
)
2255 dest
= retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW
);
2257 dest
= retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
);
2259 if (devinfo
->gen
>= 6) {
2260 insn
= next_insn(p
, BRW_OPCODE_SENDC
);
2262 insn
= next_insn(p
, BRW_OPCODE_SEND
);
2264 brw_inst_set_compression(devinfo
, insn
, false);
2266 if (devinfo
->gen
>= 6) {
2267 /* headerless version, just submit color payload */
2270 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
;
2272 assert(payload
.file
== BRW_MESSAGE_REGISTER_FILE
);
2273 brw_inst_set_base_mrf(devinfo
, insn
, payload
.nr
);
2274 src0
= implied_header
;
2276 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
;
2279 brw_set_dest(p
, insn
, dest
);
2280 brw_set_src0(p
, insn
, src0
);
2281 brw_set_dp_write_message(p
,
2283 binding_table_index
,
2292 0 /* send_commit_msg */);
2296 gen9_fb_READ(struct brw_codegen
*p
,
2298 struct brw_reg payload
,
2299 unsigned binding_table_index
,
2300 unsigned msg_length
,
2301 unsigned response_length
,
2304 const struct gen_device_info
*devinfo
= p
->devinfo
;
2305 assert(devinfo
->gen
>= 9);
2306 const unsigned msg_subtype
=
2307 brw_inst_exec_size(devinfo
, p
->current
) == BRW_EXECUTE_16
? 0 : 1;
2308 brw_inst
*insn
= next_insn(p
, BRW_OPCODE_SENDC
);
2310 brw_set_dest(p
, insn
, dst
);
2311 brw_set_src0(p
, insn
, payload
);
2312 brw_set_dp_read_message(p
, insn
, binding_table_index
,
2313 per_sample
<< 5 | msg_subtype
,
2314 GEN9_DATAPORT_RC_RENDER_TARGET_READ
,
2315 GEN6_SFID_DATAPORT_RENDER_CACHE
,
2316 msg_length
, true /* header_present */,
2318 brw_inst_set_rt_slot_group(devinfo
, insn
,
2319 brw_inst_qtr_control(devinfo
, p
->current
) / 2);
2325 * Texture sample instruction.
2326 * Note: the msg_type plus msg_length values determine exactly what kind
2327 * of sampling operation is performed. See volume 4, page 161 of docs.
2329 void brw_SAMPLE(struct brw_codegen
*p
,
2330 struct brw_reg dest
,
2331 unsigned msg_reg_nr
,
2332 struct brw_reg src0
,
2333 unsigned binding_table_index
,
2336 unsigned response_length
,
2337 unsigned msg_length
,
2338 unsigned header_present
,
2340 unsigned return_format
)
2342 const struct gen_device_info
*devinfo
= p
->devinfo
;
2345 if (msg_reg_nr
!= -1)
2346 gen6_resolve_implied_move(p
, &src0
, msg_reg_nr
);
2348 insn
= next_insn(p
, BRW_OPCODE_SEND
);
2349 brw_inst_set_pred_control(devinfo
, insn
, BRW_PREDICATE_NONE
); /* XXX */
2351 /* From the 965 PRM (volume 4, part 1, section 14.2.41):
2353 * "Instruction compression is not allowed for this instruction (that
2354 * is, send). The hardware behavior is undefined if this instruction is
2355 * set as compressed. However, compress control can be set to "SecHalf"
2356 * to affect the EMask generation."
2358 * No similar wording is found in later PRMs, but there are examples
2359 * utilizing send with SecHalf. More importantly, SIMD8 sampler messages
2360 * are allowed in SIMD16 mode and they could not work without SecHalf. For
2361 * these reasons, we allow BRW_COMPRESSION_2NDHALF here.
2363 brw_inst_set_compression(devinfo
, insn
, false);
2365 if (devinfo
->gen
< 6)
2366 brw_inst_set_base_mrf(devinfo
, insn
, msg_reg_nr
);
2368 brw_set_dest(p
, insn
, dest
);
2369 brw_set_src0(p
, insn
, src0
);
2370 brw_set_sampler_message(p
, insn
,
2371 binding_table_index
,
2381 /* Adjust the message header's sampler state pointer to
2382 * select the correct group of 16 samplers.
2384 void brw_adjust_sampler_state_pointer(struct brw_codegen
*p
,
2385 struct brw_reg header
,
2386 struct brw_reg sampler_index
)
2388 /* The "Sampler Index" field can only store values between 0 and 15.
2389 * However, we can add an offset to the "Sampler State Pointer"
2390 * field, effectively selecting a different set of 16 samplers.
2392 * The "Sampler State Pointer" needs to be aligned to a 32-byte
2393 * offset, and each sampler state is only 16-bytes, so we can't
2394 * exclusively use the offset - we have to use both.
2397 const struct gen_device_info
*devinfo
= p
->devinfo
;
2399 if (sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
2400 const int sampler_state_size
= 16; /* 16 bytes */
2401 uint32_t sampler
= sampler_index
.ud
;
2403 if (sampler
>= 16) {
2404 assert(devinfo
->is_haswell
|| devinfo
->gen
>= 8);
2406 get_element_ud(header
, 3),
2407 get_element_ud(brw_vec8_grf(0, 0), 3),
2408 brw_imm_ud(16 * (sampler
/ 16) * sampler_state_size
));
2411 /* Non-const sampler array indexing case */
2412 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
2416 struct brw_reg temp
= get_element_ud(header
, 3);
2418 brw_AND(p
, temp
, get_element_ud(sampler_index
, 0), brw_imm_ud(0x0f0));
2419 brw_SHL(p
, temp
, temp
, brw_imm_ud(4));
2421 get_element_ud(header
, 3),
2422 get_element_ud(brw_vec8_grf(0, 0), 3),
2427 /* All these variables are pretty confusing - we might be better off
2428 * using bitmasks and macros for this, in the old style. Or perhaps
2429 * just having the caller instantiate the fields in dword3 itself.
2431 void brw_urb_WRITE(struct brw_codegen
*p
,
2432 struct brw_reg dest
,
2433 unsigned msg_reg_nr
,
2434 struct brw_reg src0
,
2435 enum brw_urb_write_flags flags
,
2436 unsigned msg_length
,
2437 unsigned response_length
,
2441 const struct gen_device_info
*devinfo
= p
->devinfo
;
2444 gen6_resolve_implied_move(p
, &src0
, msg_reg_nr
);
2446 if (devinfo
->gen
>= 7 && !(flags
& BRW_URB_WRITE_USE_CHANNEL_MASKS
)) {
2447 /* Enable Channel Masks in the URB_WRITE_HWORD message header */
2448 brw_push_insn_state(p
);
2449 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
2450 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
2451 brw_OR(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, msg_reg_nr
, 5),
2452 BRW_REGISTER_TYPE_UD
),
2453 retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD
),
2454 brw_imm_ud(0xff00));
2455 brw_pop_insn_state(p
);
2458 insn
= next_insn(p
, BRW_OPCODE_SEND
);
2460 assert(msg_length
< BRW_MAX_MRF(devinfo
->gen
));
2462 brw_set_dest(p
, insn
, dest
);
2463 brw_set_src0(p
, insn
, src0
);
2464 brw_set_src1(p
, insn
, brw_imm_d(0));
2466 if (devinfo
->gen
< 6)
2467 brw_inst_set_base_mrf(devinfo
, insn
, msg_reg_nr
);
2469 brw_set_urb_message(p
,
2479 brw_send_indirect_message(struct brw_codegen
*p
,
2482 struct brw_reg payload
,
2483 struct brw_reg desc
)
2485 const struct gen_device_info
*devinfo
= p
->devinfo
;
2486 struct brw_inst
*send
;
2489 dst
= retype(dst
, BRW_REGISTER_TYPE_UW
);
2491 assert(desc
.type
== BRW_REGISTER_TYPE_UD
);
2493 /* We hold on to the setup instruction (the SEND in the direct case, the OR
2494 * in the indirect case) by its index in the instruction store. The
2495 * pointer returned by next_insn() may become invalid if emitting the SEND
2496 * in the indirect case reallocs the store.
2499 if (desc
.file
== BRW_IMMEDIATE_VALUE
) {
2501 send
= next_insn(p
, BRW_OPCODE_SEND
);
2502 brw_set_src1(p
, send
, desc
);
2505 struct brw_reg addr
= retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
);
2507 brw_push_insn_state(p
);
2508 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
2509 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
2510 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
2512 /* Load the indirect descriptor to an address register using OR so the
2513 * caller can specify additional descriptor bits with the usual
2514 * brw_set_*_message() helper functions.
2517 brw_OR(p
, addr
, desc
, brw_imm_ud(0));
2519 brw_pop_insn_state(p
);
2521 send
= next_insn(p
, BRW_OPCODE_SEND
);
2522 brw_set_src1(p
, send
, addr
);
2525 if (dst
.width
< BRW_EXECUTE_8
)
2526 brw_inst_set_exec_size(devinfo
, send
, dst
.width
);
2528 brw_set_dest(p
, send
, dst
);
2529 brw_set_src0(p
, send
, retype(payload
, BRW_REGISTER_TYPE_UD
));
2530 brw_inst_set_sfid(devinfo
, send
, sfid
);
2532 return &p
->store
[setup
];
2535 static struct brw_inst
*
2536 brw_send_indirect_surface_message(struct brw_codegen
*p
,
2539 struct brw_reg payload
,
2540 struct brw_reg surface
,
2541 unsigned message_len
,
2542 unsigned response_len
,
2543 bool header_present
)
2545 const struct gen_device_info
*devinfo
= p
->devinfo
;
2546 struct brw_inst
*insn
;
2548 if (surface
.file
!= BRW_IMMEDIATE_VALUE
) {
2549 struct brw_reg addr
= retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
);
2551 brw_push_insn_state(p
);
2552 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
2553 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
2554 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
2556 /* Mask out invalid bits from the surface index to avoid hangs e.g. when
2557 * some surface array is accessed out of bounds.
2559 insn
= brw_AND(p
, addr
,
2560 suboffset(vec1(retype(surface
, BRW_REGISTER_TYPE_UD
)),
2561 BRW_GET_SWZ(surface
.swizzle
, 0)),
2564 brw_pop_insn_state(p
);
2569 insn
= brw_send_indirect_message(p
, sfid
, dst
, payload
, surface
);
2570 brw_inst_set_mlen(devinfo
, insn
, message_len
);
2571 brw_inst_set_rlen(devinfo
, insn
, response_len
);
2572 brw_inst_set_header_present(devinfo
, insn
, header_present
);
2578 while_jumps_before_offset(const struct gen_device_info
*devinfo
,
2579 brw_inst
*insn
, int while_offset
, int start_offset
)
2581 int scale
= 16 / brw_jump_scale(devinfo
);
2582 int jip
= devinfo
->gen
== 6 ? brw_inst_gen6_jump_count(devinfo
, insn
)
2583 : brw_inst_jip(devinfo
, insn
);
2585 return while_offset
+ jip
* scale
<= start_offset
;
2590 brw_find_next_block_end(struct brw_codegen
*p
, int start_offset
)
2593 void *store
= p
->store
;
2594 const struct gen_device_info
*devinfo
= p
->devinfo
;
2598 for (offset
= next_offset(devinfo
, store
, start_offset
);
2599 offset
< p
->next_insn_offset
;
2600 offset
= next_offset(devinfo
, store
, offset
)) {
2601 brw_inst
*insn
= store
+ offset
;
2603 switch (brw_inst_opcode(devinfo
, insn
)) {
2607 case BRW_OPCODE_ENDIF
:
2612 case BRW_OPCODE_WHILE
:
2613 /* If the while doesn't jump before our instruction, it's the end
2614 * of a sibling do...while loop. Ignore it.
2616 if (!while_jumps_before_offset(devinfo
, insn
, offset
, start_offset
))
2619 case BRW_OPCODE_ELSE
:
2620 case BRW_OPCODE_HALT
:
2629 /* There is no DO instruction on gen6, so to find the end of the loop
2630 * we have to see if the loop is jumping back before our start
2634 brw_find_loop_end(struct brw_codegen
*p
, int start_offset
)
2636 const struct gen_device_info
*devinfo
= p
->devinfo
;
2638 void *store
= p
->store
;
2640 assert(devinfo
->gen
>= 6);
2642 /* Always start after the instruction (such as a WHILE) we're trying to fix
2645 for (offset
= next_offset(devinfo
, store
, start_offset
);
2646 offset
< p
->next_insn_offset
;
2647 offset
= next_offset(devinfo
, store
, offset
)) {
2648 brw_inst
*insn
= store
+ offset
;
2650 if (brw_inst_opcode(devinfo
, insn
) == BRW_OPCODE_WHILE
) {
2651 if (while_jumps_before_offset(devinfo
, insn
, offset
, start_offset
))
2655 assert(!"not reached");
2656 return start_offset
;
2659 /* After program generation, go back and update the UIP and JIP of
2660 * BREAK, CONT, and HALT instructions to their correct locations.
2663 brw_set_uip_jip(struct brw_codegen
*p
, int start_offset
)
2665 const struct gen_device_info
*devinfo
= p
->devinfo
;
2667 int br
= brw_jump_scale(devinfo
);
2668 int scale
= 16 / br
;
2669 void *store
= p
->store
;
2671 if (devinfo
->gen
< 6)
2674 for (offset
= start_offset
; offset
< p
->next_insn_offset
; offset
+= 16) {
2675 brw_inst
*insn
= store
+ offset
;
2676 assert(brw_inst_cmpt_control(devinfo
, insn
) == 0);
2678 int block_end_offset
= brw_find_next_block_end(p
, offset
);
2679 switch (brw_inst_opcode(devinfo
, insn
)) {
2680 case BRW_OPCODE_BREAK
:
2681 assert(block_end_offset
!= 0);
2682 brw_inst_set_jip(devinfo
, insn
, (block_end_offset
- offset
) / scale
);
2683 /* Gen7 UIP points to WHILE; Gen6 points just after it */
2684 brw_inst_set_uip(devinfo
, insn
,
2685 (brw_find_loop_end(p
, offset
) - offset
+
2686 (devinfo
->gen
== 6 ? 16 : 0)) / scale
);
2688 case BRW_OPCODE_CONTINUE
:
2689 assert(block_end_offset
!= 0);
2690 brw_inst_set_jip(devinfo
, insn
, (block_end_offset
- offset
) / scale
);
2691 brw_inst_set_uip(devinfo
, insn
,
2692 (brw_find_loop_end(p
, offset
) - offset
) / scale
);
2694 assert(brw_inst_uip(devinfo
, insn
) != 0);
2695 assert(brw_inst_jip(devinfo
, insn
) != 0);
2698 case BRW_OPCODE_ENDIF
: {
2699 int32_t jump
= (block_end_offset
== 0) ?
2700 1 * br
: (block_end_offset
- offset
) / scale
;
2701 if (devinfo
->gen
>= 7)
2702 brw_inst_set_jip(devinfo
, insn
, jump
);
2704 brw_inst_set_gen6_jump_count(devinfo
, insn
, jump
);
2708 case BRW_OPCODE_HALT
:
2709 /* From the Sandy Bridge PRM (volume 4, part 2, section 8.3.19):
2711 * "In case of the halt instruction not inside any conditional
2712 * code block, the value of <JIP> and <UIP> should be the
2713 * same. In case of the halt instruction inside conditional code
2714 * block, the <UIP> should be the end of the program, and the
2715 * <JIP> should be end of the most inner conditional code block."
2717 * The uip will have already been set by whoever set up the
2720 if (block_end_offset
== 0) {
2721 brw_inst_set_jip(devinfo
, insn
, brw_inst_uip(devinfo
, insn
));
2723 brw_inst_set_jip(devinfo
, insn
, (block_end_offset
- offset
) / scale
);
2725 assert(brw_inst_uip(devinfo
, insn
) != 0);
2726 assert(brw_inst_jip(devinfo
, insn
) != 0);
2732 void brw_ff_sync(struct brw_codegen
*p
,
2733 struct brw_reg dest
,
2734 unsigned msg_reg_nr
,
2735 struct brw_reg src0
,
2737 unsigned response_length
,
2740 const struct gen_device_info
*devinfo
= p
->devinfo
;
2743 gen6_resolve_implied_move(p
, &src0
, msg_reg_nr
);
2745 insn
= next_insn(p
, BRW_OPCODE_SEND
);
2746 brw_set_dest(p
, insn
, dest
);
2747 brw_set_src0(p
, insn
, src0
);
2748 brw_set_src1(p
, insn
, brw_imm_d(0));
2750 if (devinfo
->gen
< 6)
2751 brw_inst_set_base_mrf(devinfo
, insn
, msg_reg_nr
);
2753 brw_set_ff_sync_message(p
,
2761 * Emit the SEND instruction necessary to generate stream output data on Gen6
2762 * (for transform feedback).
2764 * If send_commit_msg is true, this is the last piece of stream output data
2765 * from this thread, so send the data as a committed write. According to the
2766 * Sandy Bridge PRM (volume 2 part 1, section 4.5.1):
2768 * "Prior to End of Thread with a URB_WRITE, the kernel must ensure all
2769 * writes are complete by sending the final write as a committed write."
2772 brw_svb_write(struct brw_codegen
*p
,
2773 struct brw_reg dest
,
2774 unsigned msg_reg_nr
,
2775 struct brw_reg src0
,
2776 unsigned binding_table_index
,
2777 bool send_commit_msg
)
2779 const struct gen_device_info
*devinfo
= p
->devinfo
;
2780 const unsigned target_cache
=
2781 (devinfo
->gen
>= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE
:
2782 devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE
:
2783 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
);
2786 gen6_resolve_implied_move(p
, &src0
, msg_reg_nr
);
2788 insn
= next_insn(p
, BRW_OPCODE_SEND
);
2789 brw_set_dest(p
, insn
, dest
);
2790 brw_set_src0(p
, insn
, src0
);
2791 brw_set_src1(p
, insn
, brw_imm_d(0));
2792 brw_set_dp_write_message(p
, insn
,
2793 binding_table_index
,
2794 0, /* msg_control: ignored */
2795 GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE
,
2798 true, /* header_present */
2799 0, /* last_render_target: ignored */
2800 send_commit_msg
, /* response_length */
2801 0, /* end_of_thread */
2802 send_commit_msg
); /* send_commit_msg */
2806 brw_surface_payload_size(struct brw_codegen
*p
,
2807 unsigned num_channels
,
2812 brw_inst_access_mode(p
->devinfo
, p
->current
) == BRW_ALIGN_16
)
2814 else if (has_simd16
&&
2815 brw_inst_exec_size(p
->devinfo
, p
->current
) == BRW_EXECUTE_16
)
2816 return 2 * num_channels
;
2818 return num_channels
;
2822 brw_set_dp_untyped_atomic_message(struct brw_codegen
*p
,
2825 bool response_expected
)
2827 const struct gen_device_info
*devinfo
= p
->devinfo
;
2828 unsigned msg_control
=
2829 atomic_op
| /* Atomic Operation Type: BRW_AOP_* */
2830 (response_expected
? 1 << 5 : 0); /* Return data expected */
2832 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
2833 if (brw_inst_access_mode(devinfo
, p
->current
) == BRW_ALIGN_1
) {
2834 if (brw_inst_exec_size(devinfo
, p
->current
) != BRW_EXECUTE_16
)
2835 msg_control
|= 1 << 4; /* SIMD8 mode */
2837 brw_inst_set_dp_msg_type(devinfo
, insn
,
2838 HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP
);
2840 brw_inst_set_dp_msg_type(devinfo
, insn
,
2841 HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2
);
2844 brw_inst_set_dp_msg_type(devinfo
, insn
,
2845 GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP
);
2847 if (brw_inst_exec_size(devinfo
, p
->current
) != BRW_EXECUTE_16
)
2848 msg_control
|= 1 << 4; /* SIMD8 mode */
2851 brw_inst_set_dp_msg_control(devinfo
, insn
, msg_control
);
2855 brw_untyped_atomic(struct brw_codegen
*p
,
2857 struct brw_reg payload
,
2858 struct brw_reg surface
,
2860 unsigned msg_length
,
2861 bool response_expected
)
2863 const struct gen_device_info
*devinfo
= p
->devinfo
;
2864 const unsigned sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
2865 HSW_SFID_DATAPORT_DATA_CACHE_1
:
2866 GEN7_SFID_DATAPORT_DATA_CACHE
);
2867 const bool align1
= brw_inst_access_mode(devinfo
, p
->current
) == BRW_ALIGN_1
;
2868 /* Mask out unused components -- This is especially important in Align16
2869 * mode on generations that don't have native support for SIMD4x2 atomics,
2870 * because unused but enabled components will cause the dataport to perform
2871 * additional atomic operations on the addresses that happen to be in the
2872 * uninitialized Y, Z and W coordinates of the payload.
2874 const unsigned mask
= align1
? WRITEMASK_XYZW
: WRITEMASK_X
;
2875 struct brw_inst
*insn
= brw_send_indirect_surface_message(
2876 p
, sfid
, brw_writemask(dst
, mask
), payload
, surface
, msg_length
,
2877 brw_surface_payload_size(p
, response_expected
,
2878 devinfo
->gen
>= 8 || devinfo
->is_haswell
, true),
2881 brw_set_dp_untyped_atomic_message(
2882 p
, insn
, atomic_op
, response_expected
);
2886 brw_set_dp_untyped_surface_read_message(struct brw_codegen
*p
,
2887 struct brw_inst
*insn
,
2888 unsigned num_channels
)
2890 const struct gen_device_info
*devinfo
= p
->devinfo
;
2891 /* Set mask of 32-bit channels to drop. */
2892 unsigned msg_control
= 0xf & (0xf << num_channels
);
2894 if (brw_inst_access_mode(devinfo
, p
->current
) == BRW_ALIGN_1
) {
2895 if (brw_inst_exec_size(devinfo
, p
->current
) == BRW_EXECUTE_16
)
2896 msg_control
|= 1 << 4; /* SIMD16 mode */
2898 msg_control
|= 2 << 4; /* SIMD8 mode */
2901 brw_inst_set_dp_msg_type(devinfo
, insn
,
2902 (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
2903 HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ
:
2904 GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ
));
2905 brw_inst_set_dp_msg_control(devinfo
, insn
, msg_control
);
2909 brw_untyped_surface_read(struct brw_codegen
*p
,
2911 struct brw_reg payload
,
2912 struct brw_reg surface
,
2913 unsigned msg_length
,
2914 unsigned num_channels
)
2916 const struct gen_device_info
*devinfo
= p
->devinfo
;
2917 const unsigned sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
2918 HSW_SFID_DATAPORT_DATA_CACHE_1
:
2919 GEN7_SFID_DATAPORT_DATA_CACHE
);
2920 struct brw_inst
*insn
= brw_send_indirect_surface_message(
2921 p
, sfid
, dst
, payload
, surface
, msg_length
,
2922 brw_surface_payload_size(p
, num_channels
, true, true),
2925 brw_set_dp_untyped_surface_read_message(
2926 p
, insn
, num_channels
);
2930 brw_set_dp_untyped_surface_write_message(struct brw_codegen
*p
,
2931 struct brw_inst
*insn
,
2932 unsigned num_channels
)
2934 const struct gen_device_info
*devinfo
= p
->devinfo
;
2935 /* Set mask of 32-bit channels to drop. */
2936 unsigned msg_control
= 0xf & (0xf << num_channels
);
2938 if (brw_inst_access_mode(devinfo
, p
->current
) == BRW_ALIGN_1
) {
2939 if (brw_inst_exec_size(devinfo
, p
->current
) == BRW_EXECUTE_16
)
2940 msg_control
|= 1 << 4; /* SIMD16 mode */
2942 msg_control
|= 2 << 4; /* SIMD8 mode */
2944 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
)
2945 msg_control
|= 0 << 4; /* SIMD4x2 mode */
2947 msg_control
|= 2 << 4; /* SIMD8 mode */
2950 brw_inst_set_dp_msg_type(devinfo
, insn
,
2951 devinfo
->gen
>= 8 || devinfo
->is_haswell
?
2952 HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE
:
2953 GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE
);
2954 brw_inst_set_dp_msg_control(devinfo
, insn
, msg_control
);
2958 brw_untyped_surface_write(struct brw_codegen
*p
,
2959 struct brw_reg payload
,
2960 struct brw_reg surface
,
2961 unsigned msg_length
,
2962 unsigned num_channels
)
2964 const struct gen_device_info
*devinfo
= p
->devinfo
;
2965 const unsigned sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
2966 HSW_SFID_DATAPORT_DATA_CACHE_1
:
2967 GEN7_SFID_DATAPORT_DATA_CACHE
);
2968 const bool align1
= brw_inst_access_mode(devinfo
, p
->current
) == BRW_ALIGN_1
;
2969 /* Mask out unused components -- See comment in brw_untyped_atomic(). */
2970 const unsigned mask
= devinfo
->gen
== 7 && !devinfo
->is_haswell
&& !align1
?
2971 WRITEMASK_X
: WRITEMASK_XYZW
;
2972 struct brw_inst
*insn
= brw_send_indirect_surface_message(
2973 p
, sfid
, brw_writemask(brw_null_reg(), mask
),
2974 payload
, surface
, msg_length
, 0, align1
);
2976 brw_set_dp_untyped_surface_write_message(
2977 p
, insn
, num_channels
);
2981 brw_set_dp_typed_atomic_message(struct brw_codegen
*p
,
2982 struct brw_inst
*insn
,
2984 bool response_expected
)
2986 const struct gen_device_info
*devinfo
= p
->devinfo
;
2987 unsigned msg_control
=
2988 atomic_op
| /* Atomic Operation Type: BRW_AOP_* */
2989 (response_expected
? 1 << 5 : 0); /* Return data expected */
2991 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
2992 if (brw_inst_access_mode(devinfo
, p
->current
) == BRW_ALIGN_1
) {
2993 if (brw_inst_qtr_control(devinfo
, p
->current
) % 2 == 1)
2994 msg_control
|= 1 << 4; /* Use high 8 slots of the sample mask */
2996 brw_inst_set_dp_msg_type(devinfo
, insn
,
2997 HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP
);
2999 brw_inst_set_dp_msg_type(devinfo
, insn
,
3000 HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2
);
3004 brw_inst_set_dp_msg_type(devinfo
, insn
,
3005 GEN7_DATAPORT_RC_TYPED_ATOMIC_OP
);
3007 if (brw_inst_qtr_control(devinfo
, p
->current
) % 2 == 1)
3008 msg_control
|= 1 << 4; /* Use high 8 slots of the sample mask */
3011 brw_inst_set_dp_msg_control(devinfo
, insn
, msg_control
);
3015 brw_typed_atomic(struct brw_codegen
*p
,
3017 struct brw_reg payload
,
3018 struct brw_reg surface
,
3020 unsigned msg_length
,
3021 bool response_expected
) {
3022 const struct gen_device_info
*devinfo
= p
->devinfo
;
3023 const unsigned sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
3024 HSW_SFID_DATAPORT_DATA_CACHE_1
:
3025 GEN6_SFID_DATAPORT_RENDER_CACHE
);
3026 const bool align1
= (brw_inst_access_mode(devinfo
, p
->current
) == BRW_ALIGN_1
);
3027 /* Mask out unused components -- See comment in brw_untyped_atomic(). */
3028 const unsigned mask
= align1
? WRITEMASK_XYZW
: WRITEMASK_X
;
3029 struct brw_inst
*insn
= brw_send_indirect_surface_message(
3030 p
, sfid
, brw_writemask(dst
, mask
), payload
, surface
, msg_length
,
3031 brw_surface_payload_size(p
, response_expected
,
3032 devinfo
->gen
>= 8 || devinfo
->is_haswell
, false),
3035 brw_set_dp_typed_atomic_message(
3036 p
, insn
, atomic_op
, response_expected
);
3040 brw_set_dp_typed_surface_read_message(struct brw_codegen
*p
,
3041 struct brw_inst
*insn
,
3042 unsigned num_channels
)
3044 const struct gen_device_info
*devinfo
= p
->devinfo
;
3045 /* Set mask of unused channels. */
3046 unsigned msg_control
= 0xf & (0xf << num_channels
);
3048 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
3049 if (brw_inst_access_mode(devinfo
, p
->current
) == BRW_ALIGN_1
) {
3050 if (brw_inst_qtr_control(devinfo
, p
->current
) % 2 == 1)
3051 msg_control
|= 2 << 4; /* Use high 8 slots of the sample mask */
3053 msg_control
|= 1 << 4; /* Use low 8 slots of the sample mask */
3056 brw_inst_set_dp_msg_type(devinfo
, insn
,
3057 HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ
);
3059 if (brw_inst_access_mode(devinfo
, p
->current
) == BRW_ALIGN_1
) {
3060 if (brw_inst_qtr_control(devinfo
, p
->current
) % 2 == 1)
3061 msg_control
|= 1 << 5; /* Use high 8 slots of the sample mask */
3064 brw_inst_set_dp_msg_type(devinfo
, insn
,
3065 GEN7_DATAPORT_RC_TYPED_SURFACE_READ
);
3068 brw_inst_set_dp_msg_control(devinfo
, insn
, msg_control
);
3072 brw_typed_surface_read(struct brw_codegen
*p
,
3074 struct brw_reg payload
,
3075 struct brw_reg surface
,
3076 unsigned msg_length
,
3077 unsigned num_channels
)
3079 const struct gen_device_info
*devinfo
= p
->devinfo
;
3080 const unsigned sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
3081 HSW_SFID_DATAPORT_DATA_CACHE_1
:
3082 GEN6_SFID_DATAPORT_RENDER_CACHE
);
3083 struct brw_inst
*insn
= brw_send_indirect_surface_message(
3084 p
, sfid
, dst
, payload
, surface
, msg_length
,
3085 brw_surface_payload_size(p
, num_channels
,
3086 devinfo
->gen
>= 8 || devinfo
->is_haswell
, false),
3089 brw_set_dp_typed_surface_read_message(
3090 p
, insn
, num_channels
);
3094 brw_set_dp_typed_surface_write_message(struct brw_codegen
*p
,
3095 struct brw_inst
*insn
,
3096 unsigned num_channels
)
3098 const struct gen_device_info
*devinfo
= p
->devinfo
;
3099 /* Set mask of unused channels. */
3100 unsigned msg_control
= 0xf & (0xf << num_channels
);
3102 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
3103 if (brw_inst_access_mode(devinfo
, p
->current
) == BRW_ALIGN_1
) {
3104 if (brw_inst_qtr_control(devinfo
, p
->current
) % 2 == 1)
3105 msg_control
|= 2 << 4; /* Use high 8 slots of the sample mask */
3107 msg_control
|= 1 << 4; /* Use low 8 slots of the sample mask */
3110 brw_inst_set_dp_msg_type(devinfo
, insn
,
3111 HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE
);
3114 if (brw_inst_access_mode(devinfo
, p
->current
) == BRW_ALIGN_1
) {
3115 if (brw_inst_qtr_control(devinfo
, p
->current
) % 2 == 1)
3116 msg_control
|= 1 << 5; /* Use high 8 slots of the sample mask */
3119 brw_inst_set_dp_msg_type(devinfo
, insn
,
3120 GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE
);
3123 brw_inst_set_dp_msg_control(devinfo
, insn
, msg_control
);
3127 brw_typed_surface_write(struct brw_codegen
*p
,
3128 struct brw_reg payload
,
3129 struct brw_reg surface
,
3130 unsigned msg_length
,
3131 unsigned num_channels
)
3133 const struct gen_device_info
*devinfo
= p
->devinfo
;
3134 const unsigned sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
3135 HSW_SFID_DATAPORT_DATA_CACHE_1
:
3136 GEN6_SFID_DATAPORT_RENDER_CACHE
);
3137 const bool align1
= (brw_inst_access_mode(devinfo
, p
->current
) == BRW_ALIGN_1
);
3138 /* Mask out unused components -- See comment in brw_untyped_atomic(). */
3139 const unsigned mask
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&& !align1
?
3140 WRITEMASK_X
: WRITEMASK_XYZW
);
3141 struct brw_inst
*insn
= brw_send_indirect_surface_message(
3142 p
, sfid
, brw_writemask(brw_null_reg(), mask
),
3143 payload
, surface
, msg_length
, 0, true);
3145 brw_set_dp_typed_surface_write_message(
3146 p
, insn
, num_channels
);
3150 brw_set_memory_fence_message(struct brw_codegen
*p
,
3151 struct brw_inst
*insn
,
3152 enum brw_message_target sfid
,
3155 const struct gen_device_info
*devinfo
= p
->devinfo
;
3157 brw_set_message_descriptor(p
, insn
, sfid
,
3158 1 /* message length */,
3159 (commit_enable
? 1 : 0) /* response length */,
3160 true /* header present */,
3164 case GEN6_SFID_DATAPORT_RENDER_CACHE
:
3165 brw_inst_set_dp_msg_type(devinfo
, insn
, GEN7_DATAPORT_RC_MEMORY_FENCE
);
3167 case GEN7_SFID_DATAPORT_DATA_CACHE
:
3168 brw_inst_set_dp_msg_type(devinfo
, insn
, GEN7_DATAPORT_DC_MEMORY_FENCE
);
3171 unreachable("Not reached");
3175 brw_inst_set_dp_msg_control(devinfo
, insn
, 1 << 5);
3179 brw_memory_fence(struct brw_codegen
*p
,
3182 const struct gen_device_info
*devinfo
= p
->devinfo
;
3183 const bool commit_enable
= devinfo
->gen
== 7 && !devinfo
->is_haswell
;
3184 struct brw_inst
*insn
;
3186 brw_push_insn_state(p
);
3187 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
3188 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
3191 /* Set dst as destination for dependency tracking, the MEMORY_FENCE
3192 * message doesn't write anything back.
3194 insn
= next_insn(p
, BRW_OPCODE_SEND
);
3195 dst
= retype(dst
, BRW_REGISTER_TYPE_UW
);
3196 brw_set_dest(p
, insn
, dst
);
3197 brw_set_src0(p
, insn
, dst
);
3198 brw_set_memory_fence_message(p
, insn
, GEN7_SFID_DATAPORT_DATA_CACHE
,
3201 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
3202 /* IVB does typed surface access through the render cache, so we need to
3203 * flush it too. Use a different register so both flushes can be
3204 * pipelined by the hardware.
3206 insn
= next_insn(p
, BRW_OPCODE_SEND
);
3207 brw_set_dest(p
, insn
, offset(dst
, 1));
3208 brw_set_src0(p
, insn
, offset(dst
, 1));
3209 brw_set_memory_fence_message(p
, insn
, GEN6_SFID_DATAPORT_RENDER_CACHE
,
3212 /* Now write the response of the second message into the response of the
3213 * first to trigger a pipeline stall -- This way future render and data
3214 * cache messages will be properly ordered with respect to past data and
3215 * render cache messages.
3217 brw_MOV(p
, dst
, offset(dst
, 1));
3220 brw_pop_insn_state(p
);
3224 brw_pixel_interpolator_query(struct brw_codegen
*p
,
3225 struct brw_reg dest
,
3229 struct brw_reg data
,
3230 unsigned msg_length
,
3231 unsigned response_length
)
3233 const struct gen_device_info
*devinfo
= p
->devinfo
;
3234 struct brw_inst
*insn
;
3235 const uint16_t exec_size
= brw_inst_exec_size(devinfo
, p
->current
);
3237 /* brw_send_indirect_message will automatically use a direct send message
3238 * if data is actually immediate.
3240 insn
= brw_send_indirect_message(p
,
3241 GEN7_SFID_PIXEL_INTERPOLATOR
,
3245 brw_inst_set_mlen(devinfo
, insn
, msg_length
);
3246 brw_inst_set_rlen(devinfo
, insn
, response_length
);
3248 brw_inst_set_pi_simd_mode(devinfo
, insn
, exec_size
== BRW_EXECUTE_16
);
3249 brw_inst_set_pi_slot_group(devinfo
, insn
, 0); /* zero unless 32/64px dispatch */
3250 brw_inst_set_pi_nopersp(devinfo
, insn
, noperspective
);
3251 brw_inst_set_pi_message_type(devinfo
, insn
, mode
);
3255 brw_find_live_channel(struct brw_codegen
*p
, struct brw_reg dst
,
3256 struct brw_reg mask
)
3258 const struct gen_device_info
*devinfo
= p
->devinfo
;
3259 const unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, p
->current
);
3260 const unsigned qtr_control
= brw_inst_qtr_control(devinfo
, p
->current
);
3263 assert(devinfo
->gen
>= 7);
3264 assert(mask
.type
== BRW_REGISTER_TYPE_UD
);
3266 brw_push_insn_state(p
);
3268 if (brw_inst_access_mode(devinfo
, p
->current
) == BRW_ALIGN_1
) {
3269 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
3271 if (devinfo
->gen
>= 8) {
3272 /* Getting the first active channel index is easy on Gen8: Just find
3273 * the first bit set in the execution mask. The register exists on
3274 * HSW already but it reads back as all ones when the current
3275 * instruction has execution masking disabled, so it's kind of
3278 struct brw_reg exec_mask
=
3279 retype(brw_mask_reg(0), BRW_REGISTER_TYPE_UD
);
3281 if (mask
.file
!= BRW_IMMEDIATE_VALUE
|| mask
.ud
!= 0xffffffff) {
3282 /* Unfortunately, ce0 does not take into account the thread
3283 * dispatch mask, which may be a problem in cases where it's not
3284 * tightly packed (i.e. it doesn't have the form '2^n - 1' for
3285 * some n). Combine ce0 with the given dispatch (or vector) mask
3286 * to mask off those channels which were never dispatched by the
3289 brw_SHR(p
, vec1(dst
), mask
, brw_imm_ud(qtr_control
* 8));
3290 brw_AND(p
, vec1(dst
), exec_mask
, vec1(dst
));
3291 exec_mask
= vec1(dst
);
3294 /* Quarter control has the effect of magically shifting the value of
3295 * ce0 so you'll get the first active channel relative to the
3296 * specified quarter control as result.
3298 inst
= brw_FBL(p
, vec1(dst
), exec_mask
);
3300 const struct brw_reg flag
= brw_flag_reg(1, 0);
3302 brw_MOV(p
, retype(flag
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0));
3304 /* Run enough instructions returning zero with execution masking and
3305 * a conditional modifier enabled in order to get the full execution
3306 * mask in f1.0. We could use a single 32-wide move here if it
3307 * weren't because of the hardware bug that causes channel enables to
3308 * be applied incorrectly to the second half of 32-wide instructions
3311 const unsigned lower_size
= MIN2(16, exec_size
);
3312 for (unsigned i
= 0; i
< exec_size
/ lower_size
; i
++) {
3313 inst
= brw_MOV(p
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
),
3315 brw_inst_set_mask_control(devinfo
, inst
, BRW_MASK_ENABLE
);
3316 brw_inst_set_group(devinfo
, inst
, lower_size
* i
+ 8 * qtr_control
);
3317 brw_inst_set_cond_modifier(devinfo
, inst
, BRW_CONDITIONAL_Z
);
3318 brw_inst_set_flag_reg_nr(devinfo
, inst
, 1);
3319 brw_inst_set_exec_size(devinfo
, inst
, cvt(lower_size
) - 1);
3322 /* Find the first bit set in the exec_size-wide portion of the flag
3323 * register that was updated by the last sequence of MOV
3326 const enum brw_reg_type type
= brw_int_type(exec_size
/ 8, false);
3327 brw_FBL(p
, vec1(dst
), byte_offset(retype(flag
, type
), qtr_control
));
3330 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
3332 if (devinfo
->gen
>= 8 &&
3333 mask
.file
== BRW_IMMEDIATE_VALUE
&& mask
.ud
== 0xffffffff) {
3334 /* In SIMD4x2 mode the first active channel index is just the
3335 * negation of the first bit of the mask register. Note that ce0
3336 * doesn't take into account the dispatch mask, so the Gen7 path
3337 * should be used instead unless you have the guarantee that the
3338 * dispatch mask is tightly packed (i.e. it has the form '2^n - 1'
3341 inst
= brw_AND(p
, brw_writemask(dst
, WRITEMASK_X
),
3342 negate(retype(brw_mask_reg(0), BRW_REGISTER_TYPE_UD
)),
3346 /* Overwrite the destination without and with execution masking to
3347 * find out which of the channels is active.
3349 brw_push_insn_state(p
);
3350 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
3351 brw_MOV(p
, brw_writemask(vec4(dst
), WRITEMASK_X
),
3354 inst
= brw_MOV(p
, brw_writemask(vec4(dst
), WRITEMASK_X
),
3356 brw_pop_insn_state(p
);
3357 brw_inst_set_mask_control(devinfo
, inst
, BRW_MASK_ENABLE
);
3361 brw_pop_insn_state(p
);
3365 brw_broadcast(struct brw_codegen
*p
,
3370 const struct gen_device_info
*devinfo
= p
->devinfo
;
3371 const bool align1
= brw_inst_access_mode(devinfo
, p
->current
) == BRW_ALIGN_1
;
3374 brw_push_insn_state(p
);
3375 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
3376 brw_set_default_exec_size(p
, align1
? BRW_EXECUTE_1
: BRW_EXECUTE_4
);
3378 assert(src
.file
== BRW_GENERAL_REGISTER_FILE
&&
3379 src
.address_mode
== BRW_ADDRESS_DIRECT
);
3380 assert(!src
.abs
&& !src
.negate
);
3381 assert(src
.type
== dst
.type
);
3383 if ((src
.vstride
== 0 && (src
.hstride
== 0 || !align1
)) ||
3384 idx
.file
== BRW_IMMEDIATE_VALUE
) {
3385 /* Trivial, the source is already uniform or the index is a constant.
3386 * We will typically not get here if the optimizer is doing its job, but
3387 * asserting would be mean.
3389 const unsigned i
= idx
.file
== BRW_IMMEDIATE_VALUE
? idx
.ud
: 0;
3391 (align1
? stride(suboffset(src
, i
), 0, 1, 0) :
3392 stride(suboffset(src
, 4 * i
), 0, 4, 1)));
3394 /* From the Haswell PRM section "Register Region Restrictions":
3396 * "The lower bits of the AddressImmediate must not overflow to
3397 * change the register address. The lower 5 bits of Address
3398 * Immediate when added to lower 5 bits of address register gives
3399 * the sub-register offset. The upper bits of Address Immediate
3400 * when added to upper bits of address register gives the register
3401 * address. Any overflow from sub-register offset is dropped."
3403 * Fortunately, for broadcast, we never have a sub-register offset so
3404 * this isn't an issue.
3406 assert(src
.subnr
== 0);
3409 const struct brw_reg addr
=
3410 retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
);
3411 unsigned offset
= src
.nr
* REG_SIZE
+ src
.subnr
;
3412 /* Limit in bytes of the signed indirect addressing immediate. */
3413 const unsigned limit
= 512;
3415 brw_push_insn_state(p
);
3416 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
3417 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
3419 /* Take into account the component size and horizontal stride. */
3420 assert(src
.vstride
== src
.hstride
+ src
.width
);
3421 brw_SHL(p
, addr
, vec1(idx
),
3422 brw_imm_ud(_mesa_logbase2(type_sz(src
.type
)) +
3425 /* We can only address up to limit bytes using the indirect
3426 * addressing immediate, account for the difference if the source
3427 * register is above this limit.
3429 if (offset
>= limit
) {
3430 brw_ADD(p
, addr
, addr
, brw_imm_ud(offset
- offset
% limit
));
3431 offset
= offset
% limit
;
3434 brw_pop_insn_state(p
);
3436 /* Use indirect addressing to fetch the specified component. */
3437 if (type_sz(src
.type
) > 4 &&
3438 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
3439 /* From the Cherryview PRM Vol 7. "Register Region Restrictions":
3441 * "When source or destination datatype is 64b or operation is
3442 * integer DWord multiply, indirect addressing must not be
3445 * To work around both of this issue, we do two integer MOVs
3446 * insead of one 64-bit MOV. Because no double value should ever
3447 * cross a register boundary, it's safe to use the immediate
3448 * offset in the indirect here to handle adding 4 bytes to the
3449 * offset and avoid the extra ADD to the register file.
3451 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
3452 retype(brw_vec1_indirect(addr
.subnr
, offset
),
3453 BRW_REGISTER_TYPE_D
));
3454 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
3455 retype(brw_vec1_indirect(addr
.subnr
, offset
+ 4),
3456 BRW_REGISTER_TYPE_D
));
3459 retype(brw_vec1_indirect(addr
.subnr
, offset
), src
.type
));
3462 /* In SIMD4x2 mode the index can be either zero or one, replicate it
3463 * to all bits of a flag register,
3467 stride(brw_swizzle(idx
, BRW_SWIZZLE_XXXX
), 4, 4, 1));
3468 brw_inst_set_pred_control(devinfo
, inst
, BRW_PREDICATE_NONE
);
3469 brw_inst_set_cond_modifier(devinfo
, inst
, BRW_CONDITIONAL_NZ
);
3470 brw_inst_set_flag_reg_nr(devinfo
, inst
, 1);
3472 /* and use predicated SEL to pick the right channel. */
3473 inst
= brw_SEL(p
, dst
,
3474 stride(suboffset(src
, 4), 4, 4, 1),
3475 stride(src
, 4, 4, 1));
3476 brw_inst_set_pred_control(devinfo
, inst
, BRW_PREDICATE_NORMAL
);
3477 brw_inst_set_flag_reg_nr(devinfo
, inst
, 1);
3481 brw_pop_insn_state(p
);
3485 * This instruction is generated as a single-channel align1 instruction by
3486 * both the VS and FS stages when using INTEL_DEBUG=shader_time.
3488 * We can't use the typed atomic op in the FS because that has the execution
3489 * mask ANDed with the pixel mask, but we just want to write the one dword for
3492 * We don't use the SIMD4x2 atomic ops in the VS because want to just write
3493 * one u32. So we use the same untyped atomic write message as the pixel
3496 * The untyped atomic operation requires a BUFFER surface type with RAW
3497 * format, and is only accessible through the legacy DATA_CACHE dataport
3500 void brw_shader_time_add(struct brw_codegen
*p
,
3501 struct brw_reg payload
,
3502 uint32_t surf_index
)
3504 const unsigned sfid
= (p
->devinfo
->gen
>= 8 || p
->devinfo
->is_haswell
?
3505 HSW_SFID_DATAPORT_DATA_CACHE_1
:
3506 GEN7_SFID_DATAPORT_DATA_CACHE
);
3507 assert(p
->devinfo
->gen
>= 7);
3509 brw_push_insn_state(p
);
3510 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
3511 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
3512 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
3513 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
3515 /* We use brw_vec1_reg and unmasked because we want to increment the given
3518 brw_set_dest(p
, send
, brw_vec1_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
3520 brw_set_src0(p
, send
, brw_vec1_reg(payload
.file
,
3522 brw_set_src1(p
, send
, brw_imm_ud(0));
3523 brw_set_message_descriptor(p
, send
, sfid
, 2, 0, false, false);
3524 brw_inst_set_binding_table_index(p
->devinfo
, send
, surf_index
);
3525 brw_set_dp_untyped_atomic_message(p
, send
, BRW_AOP_ADD
, false);
3527 brw_pop_insn_state(p
);
3532 * Emit the SEND message for a barrier
3535 brw_barrier(struct brw_codegen
*p
, struct brw_reg src
)
3537 const struct gen_device_info
*devinfo
= p
->devinfo
;
3538 struct brw_inst
*inst
;
3540 assert(devinfo
->gen
>= 7);
3542 brw_push_insn_state(p
);
3543 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
3544 inst
= next_insn(p
, BRW_OPCODE_SEND
);
3545 brw_set_dest(p
, inst
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
3546 brw_set_src0(p
, inst
, src
);
3547 brw_set_src1(p
, inst
, brw_null_reg());
3549 brw_set_message_descriptor(p
, inst
, BRW_SFID_MESSAGE_GATEWAY
,
3551 0 /* response_length */,
3552 false /* header_present */,
3553 false /* end_of_thread */);
3555 brw_inst_set_gateway_notify(devinfo
, inst
, 1);
3556 brw_inst_set_gateway_subfuncid(devinfo
, inst
,
3557 BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG
);
3559 brw_inst_set_mask_control(devinfo
, inst
, BRW_MASK_DISABLE
);
3560 brw_pop_insn_state(p
);
3565 * Emit the wait instruction for a barrier
3568 brw_WAIT(struct brw_codegen
*p
)
3570 const struct gen_device_info
*devinfo
= p
->devinfo
;
3571 struct brw_inst
*insn
;
3573 struct brw_reg src
= brw_notification_reg();
3575 insn
= next_insn(p
, BRW_OPCODE_WAIT
);
3576 brw_set_dest(p
, insn
, src
);
3577 brw_set_src0(p
, insn
, src
);
3578 brw_set_src1(p
, insn
, brw_null_reg());
3580 brw_inst_set_exec_size(devinfo
, insn
, BRW_EXECUTE_1
);
3581 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);