2 * Copyright © 2015-2019 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_eu_validate.c
26 * This file implements a pass that validates shader assembly.
28 * The restrictions implemented herein are intended to verify that instructions
29 * in shader assembly do not violate restrictions documented in the graphics
30 * programming reference manuals.
32 * The restrictions are difficult for humans to quickly verify due to their
33 * complexity and abundance.
35 * It is critical that this code is thoroughly unit tested because false
36 * results will lead developers astray, which is worse than having no validator
37 * at all. Functional changes to this file without corresponding unit tests (in
38 * test_eu_validate.cpp) will be rejected.
43 /* We're going to do lots of string concatenation, so this should help. */
50 cat(struct string
*dest
, const struct string src
)
52 dest
->str
= realloc(dest
->str
, dest
->len
+ src
.len
+ 1);
53 memcpy(dest
->str
+ dest
->len
, src
.str
, src
.len
);
54 dest
->str
[dest
->len
+ src
.len
] = '\0';
55 dest
->len
= dest
->len
+ src
.len
;
57 #define CAT(dest, src) cat(&dest, (struct string){src, strlen(src)})
60 contains(const struct string haystack
, const struct string needle
)
62 return haystack
.str
&& memmem(haystack
.str
, haystack
.len
,
63 needle
.str
, needle
.len
) != NULL
;
65 #define CONTAINS(haystack, needle) \
66 contains(haystack, (struct string){needle, strlen(needle)})
68 #define error(str) "\tERROR: " str "\n"
69 #define ERROR_INDENT "\t "
71 #define ERROR(msg) ERROR_IF(true, msg)
72 #define ERROR_IF(cond, msg) \
74 if ((cond) && !CONTAINS(error_msg, error(msg))) { \
75 CAT(error_msg, error(msg)); \
79 #define CHECK(func, args...) \
81 struct string __msg = func(devinfo, inst, ##args); \
83 cat(&error_msg, __msg); \
88 #define STRIDE(stride) (stride != 0 ? 1 << ((stride) - 1) : 0)
89 #define WIDTH(width) (1 << (width))
92 inst_is_send(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
94 switch (brw_inst_opcode(devinfo
, inst
)) {
96 case BRW_OPCODE_SENDC
:
97 case BRW_OPCODE_SENDS
:
98 case BRW_OPCODE_SENDSC
:
106 signed_type(unsigned type
)
109 case BRW_REGISTER_TYPE_UD
: return BRW_REGISTER_TYPE_D
;
110 case BRW_REGISTER_TYPE_UW
: return BRW_REGISTER_TYPE_W
;
111 case BRW_REGISTER_TYPE_UB
: return BRW_REGISTER_TYPE_B
;
112 case BRW_REGISTER_TYPE_UQ
: return BRW_REGISTER_TYPE_Q
;
113 default: return type
;
118 inst_is_raw_move(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
120 unsigned dst_type
= signed_type(brw_inst_dst_type(devinfo
, inst
));
121 unsigned src_type
= signed_type(brw_inst_src0_type(devinfo
, inst
));
123 if (brw_inst_src0_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
) {
124 /* FIXME: not strictly true */
125 if (brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_VF
||
126 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UV
||
127 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_V
) {
130 } else if (brw_inst_src0_negate(devinfo
, inst
) ||
131 brw_inst_src0_abs(devinfo
, inst
)) {
135 return brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MOV
&&
136 brw_inst_saturate(devinfo
, inst
) == 0 &&
137 dst_type
== src_type
;
141 dst_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
143 return brw_inst_dst_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
144 brw_inst_dst_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
148 src0_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
150 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
151 brw_inst_src0_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
155 src1_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
157 return brw_inst_src1_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
158 brw_inst_src1_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
162 src0_is_grf(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
164 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_GENERAL_REGISTER_FILE
;
168 src0_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
170 return brw_inst_src0_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
171 brw_inst_src0_width(devinfo
, inst
) == BRW_WIDTH_1
&&
172 brw_inst_src0_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
176 src1_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
178 return brw_inst_src1_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
179 brw_inst_src1_width(devinfo
, inst
) == BRW_WIDTH_1
&&
180 brw_inst_src1_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
184 num_sources_from_inst(const struct gen_device_info
*devinfo
,
185 const brw_inst
*inst
)
187 const struct opcode_desc
*desc
=
188 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
189 unsigned math_function
;
191 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
192 math_function
= brw_inst_math_function(devinfo
, inst
);
193 } else if (devinfo
->gen
< 6 &&
194 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
195 if (brw_inst_sfid(devinfo
, inst
) == BRW_SFID_MATH
) {
196 /* src1 must be a descriptor (including the information to determine
197 * that the SEND is doing an extended math operation), but src0 can
198 * actually be null since it serves as the source of the implicit GRF
201 * If we stop using that functionality, we'll have to revisit this.
205 /* Send instructions are allowed to have null sources since they use
206 * the base_mrf field to specify which message register source.
211 assert(desc
->nsrc
< 4);
215 switch (math_function
) {
216 case BRW_MATH_FUNCTION_INV
:
217 case BRW_MATH_FUNCTION_LOG
:
218 case BRW_MATH_FUNCTION_EXP
:
219 case BRW_MATH_FUNCTION_SQRT
:
220 case BRW_MATH_FUNCTION_RSQ
:
221 case BRW_MATH_FUNCTION_SIN
:
222 case BRW_MATH_FUNCTION_COS
:
223 case BRW_MATH_FUNCTION_SINCOS
:
224 case GEN8_MATH_FUNCTION_INVM
:
225 case GEN8_MATH_FUNCTION_RSQRTM
:
227 case BRW_MATH_FUNCTION_FDIV
:
228 case BRW_MATH_FUNCTION_POW
:
229 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
:
230 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
:
231 case BRW_MATH_FUNCTION_INT_DIV_REMAINDER
:
234 unreachable("not reached");
239 sources_not_null(const struct gen_device_info
*devinfo
,
240 const brw_inst
*inst
)
242 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
243 struct string error_msg
= { .str
= NULL
, .len
= 0 };
245 /* Nothing to test. 3-src instructions can only have GRF sources, and
246 * there's no bit to control the file.
248 if (num_sources
== 3)
249 return (struct string
){};
251 if (num_sources
>= 1)
252 ERROR_IF(src0_is_null(devinfo
, inst
), "src0 is null");
254 if (num_sources
== 2)
255 ERROR_IF(src1_is_null(devinfo
, inst
), "src1 is null");
261 send_restrictions(const struct gen_device_info
*devinfo
,
262 const brw_inst
*inst
)
264 struct string error_msg
= { .str
= NULL
, .len
= 0 };
266 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
||
267 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SENDC
) {
268 ERROR_IF(brw_inst_src0_address_mode(devinfo
, inst
) != BRW_ADDRESS_DIRECT
,
269 "send must use direct addressing");
271 if (devinfo
->gen
>= 7) {
272 ERROR_IF(!src0_is_grf(devinfo
, inst
), "send from non-GRF");
273 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
274 brw_inst_src0_da_reg_nr(devinfo
, inst
) < 112,
275 "send with EOT must use g112-g127");
278 if (devinfo
->gen
>= 8) {
279 ERROR_IF(!dst_is_null(devinfo
, inst
) &&
280 (brw_inst_dst_da_reg_nr(devinfo
, inst
) +
281 brw_inst_rlen(devinfo
, inst
) > 127) &&
282 (brw_inst_src0_da_reg_nr(devinfo
, inst
) +
283 brw_inst_mlen(devinfo
, inst
) >
284 brw_inst_dst_da_reg_nr(devinfo
, inst
)),
285 "r127 must not be used for return address when there is "
286 "a src and dest overlap");
294 is_unsupported_inst(const struct gen_device_info
*devinfo
,
295 const brw_inst
*inst
)
297 return brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
)) == NULL
;
300 static enum brw_reg_type
301 execution_type_for_type(enum brw_reg_type type
)
304 case BRW_REGISTER_TYPE_NF
:
305 case BRW_REGISTER_TYPE_DF
:
306 case BRW_REGISTER_TYPE_F
:
307 case BRW_REGISTER_TYPE_HF
:
310 case BRW_REGISTER_TYPE_VF
:
311 return BRW_REGISTER_TYPE_F
;
313 case BRW_REGISTER_TYPE_Q
:
314 case BRW_REGISTER_TYPE_UQ
:
315 return BRW_REGISTER_TYPE_Q
;
317 case BRW_REGISTER_TYPE_D
:
318 case BRW_REGISTER_TYPE_UD
:
319 return BRW_REGISTER_TYPE_D
;
321 case BRW_REGISTER_TYPE_W
:
322 case BRW_REGISTER_TYPE_UW
:
323 case BRW_REGISTER_TYPE_B
:
324 case BRW_REGISTER_TYPE_UB
:
325 case BRW_REGISTER_TYPE_V
:
326 case BRW_REGISTER_TYPE_UV
:
327 return BRW_REGISTER_TYPE_W
;
329 unreachable("not reached");
333 * Returns the execution type of an instruction \p inst
335 static enum brw_reg_type
336 execution_type(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
338 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
339 enum brw_reg_type src0_exec_type
, src1_exec_type
;
341 /* Execution data type is independent of destination data type, except in
342 * mixed F/HF instructions on CHV and SKL+.
344 enum brw_reg_type dst_exec_type
= brw_inst_dst_type(devinfo
, inst
);
346 src0_exec_type
= execution_type_for_type(brw_inst_src0_type(devinfo
, inst
));
347 if (num_sources
== 1) {
348 if ((devinfo
->gen
>= 9 || devinfo
->is_cherryview
) &&
349 src0_exec_type
== BRW_REGISTER_TYPE_HF
) {
350 return dst_exec_type
;
352 return src0_exec_type
;
355 src1_exec_type
= execution_type_for_type(brw_inst_src1_type(devinfo
, inst
));
356 if (src0_exec_type
== src1_exec_type
)
357 return src0_exec_type
;
359 /* Mixed operand types where one is float is float on Gen < 6
360 * (and not allowed on later platforms)
362 if (devinfo
->gen
< 6 &&
363 (src0_exec_type
== BRW_REGISTER_TYPE_F
||
364 src1_exec_type
== BRW_REGISTER_TYPE_F
))
365 return BRW_REGISTER_TYPE_F
;
367 if (src0_exec_type
== BRW_REGISTER_TYPE_Q
||
368 src1_exec_type
== BRW_REGISTER_TYPE_Q
)
369 return BRW_REGISTER_TYPE_Q
;
371 if (src0_exec_type
== BRW_REGISTER_TYPE_D
||
372 src1_exec_type
== BRW_REGISTER_TYPE_D
)
373 return BRW_REGISTER_TYPE_D
;
375 if (src0_exec_type
== BRW_REGISTER_TYPE_W
||
376 src1_exec_type
== BRW_REGISTER_TYPE_W
)
377 return BRW_REGISTER_TYPE_W
;
379 if (src0_exec_type
== BRW_REGISTER_TYPE_DF
||
380 src1_exec_type
== BRW_REGISTER_TYPE_DF
)
381 return BRW_REGISTER_TYPE_DF
;
383 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
384 if (dst_exec_type
== BRW_REGISTER_TYPE_F
||
385 src0_exec_type
== BRW_REGISTER_TYPE_F
||
386 src1_exec_type
== BRW_REGISTER_TYPE_F
) {
387 return BRW_REGISTER_TYPE_F
;
389 return BRW_REGISTER_TYPE_HF
;
393 assert(src0_exec_type
== BRW_REGISTER_TYPE_F
);
394 return BRW_REGISTER_TYPE_F
;
398 * Returns whether a region is packed
400 * A region is packed if its elements are adjacent in memory, with no
401 * intervening space, no overlap, and no replicated values.
404 is_packed(unsigned vstride
, unsigned width
, unsigned hstride
)
406 if (vstride
== width
) {
418 * Checks restrictions listed in "General Restrictions Based on Operand Types"
419 * in the "Register Region Restrictions" section.
422 general_restrictions_based_on_operand_types(const struct gen_device_info
*devinfo
,
423 const brw_inst
*inst
)
425 const struct opcode_desc
*desc
=
426 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
427 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
428 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
429 struct string error_msg
= { .str
= NULL
, .len
= 0 };
431 if (num_sources
== 3)
432 return (struct string
){};
434 if (inst_is_send(devinfo
, inst
))
435 return (struct string
){};
438 return (struct string
){};
441 return (struct string
){};
445 * Where n is the largest element size in bytes for any source or
446 * destination operand type, ExecSize * n must be <= 64.
448 * But we do not attempt to enforce it, because it is implied by other
451 * - that the destination stride must match the execution data type
452 * - sources may not span more than two adjacent GRF registers
453 * - destination may not span more than two adjacent GRF registers
455 * In fact, checking it would weaken testing of the other rules.
458 unsigned dst_stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
459 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
460 bool dst_type_is_byte
=
461 brw_inst_dst_type(devinfo
, inst
) == BRW_REGISTER_TYPE_B
||
462 brw_inst_dst_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UB
;
464 if (dst_type_is_byte
) {
465 if (is_packed(exec_size
* dst_stride
, exec_size
, dst_stride
)) {
466 if (!inst_is_raw_move(devinfo
, inst
)) {
467 ERROR("Only raw MOV supports a packed-byte destination");
470 return (struct string
){};
475 unsigned exec_type
= execution_type(devinfo
, inst
);
476 unsigned exec_type_size
= brw_reg_type_to_size(exec_type
);
477 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
479 /* On IVB/BYT, region parameters and execution size for DF are in terms of
480 * 32-bit elements, so they are doubled. For evaluating the validity of an
481 * instruction, we halve them.
483 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
484 exec_type_size
== 8 && dst_type_size
== 4)
487 if (exec_type_size
> dst_type_size
) {
488 if (!(dst_type_is_byte
&& inst_is_raw_move(devinfo
, inst
))) {
489 ERROR_IF(dst_stride
* dst_type_size
!= exec_type_size
,
490 "Destination stride must be equal to the ratio of the sizes "
491 "of the execution data type to the destination type");
494 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
496 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
497 brw_inst_dst_address_mode(devinfo
, inst
) == BRW_ADDRESS_DIRECT
) {
498 /* The i965 PRM says:
500 * Implementation Restriction: The relaxed alignment rule for byte
501 * destination (#10.5) is not supported.
503 if ((devinfo
->gen
> 4 || devinfo
->is_g4x
) && dst_type_is_byte
) {
504 ERROR_IF(subreg
% exec_type_size
!= 0 &&
505 subreg
% exec_type_size
!= 1,
506 "Destination subreg must be aligned to the size of the "
507 "execution data type (or to the next lowest byte for byte "
510 ERROR_IF(subreg
% exec_type_size
!= 0,
511 "Destination subreg must be aligned to the size of the "
512 "execution data type");
521 * Checks restrictions listed in "General Restrictions on Regioning Parameters"
522 * in the "Register Region Restrictions" section.
525 general_restrictions_on_region_parameters(const struct gen_device_info
*devinfo
,
526 const brw_inst
*inst
)
528 const struct opcode_desc
*desc
=
529 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
530 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
531 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
532 struct string error_msg
= { .str
= NULL
, .len
= 0 };
534 if (num_sources
== 3)
535 return (struct string
){};
537 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
) {
538 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
))
539 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) != BRW_HORIZONTAL_STRIDE_1
,
540 "Destination Horizontal Stride must be 1");
542 if (num_sources
>= 1) {
543 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
544 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
545 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
546 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
547 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
548 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
550 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
551 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
552 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
553 "In Align16 mode, only VertStride of 0 or 4 is allowed");
557 if (num_sources
== 2) {
558 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
559 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
560 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
561 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
562 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
563 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
565 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
566 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
567 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
568 "In Align16 mode, only VertStride of 0 or 4 is allowed");
575 for (unsigned i
= 0; i
< num_sources
; i
++) {
576 unsigned vstride
, width
, hstride
, element_size
, subreg
;
577 enum brw_reg_type type
;
580 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
581 BRW_IMMEDIATE_VALUE) \
584 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
585 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
586 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
587 type = brw_inst_src ## n ## _type(devinfo, inst); \
588 element_size = brw_reg_type_to_size(type); \
589 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst)
598 /* On IVB/BYT, region parameters and execution size for DF are in terms of
599 * 32-bit elements, so they are doubled. For evaluating the validity of an
600 * instruction, we halve them.
602 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
606 /* ExecSize must be greater than or equal to Width. */
607 ERROR_IF(exec_size
< width
, "ExecSize must be greater than or equal "
610 /* If ExecSize = Width and HorzStride ≠ 0,
611 * VertStride must be set to Width * HorzStride.
613 if (exec_size
== width
&& hstride
!= 0) {
614 ERROR_IF(vstride
!= width
* hstride
,
615 "If ExecSize = Width and HorzStride ≠ 0, "
616 "VertStride must be set to Width * HorzStride");
619 /* If Width = 1, HorzStride must be 0 regardless of the values of
620 * ExecSize and VertStride.
623 ERROR_IF(hstride
!= 0,
624 "If Width = 1, HorzStride must be 0 regardless "
625 "of the values of ExecSize and VertStride");
628 /* If ExecSize = Width = 1, both VertStride and HorzStride must be 0. */
629 if (exec_size
== 1 && width
== 1) {
630 ERROR_IF(vstride
!= 0 || hstride
!= 0,
631 "If ExecSize = Width = 1, both VertStride "
632 "and HorzStride must be 0");
635 /* If VertStride = HorzStride = 0, Width must be 1 regardless of the
638 if (vstride
== 0 && hstride
== 0) {
640 "If VertStride = HorzStride = 0, Width must be "
641 "1 regardless of the value of ExecSize");
644 /* VertStride must be used to cross GRF register boundaries. This rule
645 * implies that elements within a 'Width' cannot cross GRF boundaries.
647 const uint64_t mask
= (1ULL << element_size
) - 1;
648 unsigned rowbase
= subreg
;
650 for (int y
= 0; y
< exec_size
/ width
; y
++) {
651 uint64_t access_mask
= 0;
652 unsigned offset
= rowbase
;
654 for (int x
= 0; x
< width
; x
++) {
655 access_mask
|= mask
<< offset
;
656 offset
+= hstride
* element_size
;
659 rowbase
+= vstride
* element_size
;
661 if ((uint32_t)access_mask
!= 0 && (access_mask
>> 32) != 0) {
662 ERROR("VertStride must be used to cross GRF register boundaries");
668 /* Dst.HorzStride must not be 0. */
669 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
)) {
670 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
,
671 "Destination Horizontal Stride must not be 0");
678 * Creates an \p access_mask for an \p exec_size, \p element_size, and a region
680 * An \p access_mask is a 32-element array of uint64_t, where each uint64_t is
681 * a bitmask of bytes accessed by the region.
683 * For instance the access mask of the source gX.1<4,2,2>F in an exec_size = 4
684 * instruction would be
686 * access_mask[0] = 0x00000000000000F0
687 * access_mask[1] = 0x000000000000F000
688 * access_mask[2] = 0x0000000000F00000
689 * access_mask[3] = 0x00000000F0000000
690 * access_mask[4-31] = 0
692 * because the first execution channel accesses bytes 7-4 and the second
693 * execution channel accesses bytes 15-12, etc.
696 align1_access_mask(uint64_t access_mask
[static 32],
697 unsigned exec_size
, unsigned element_size
, unsigned subreg
,
698 unsigned vstride
, unsigned width
, unsigned hstride
)
700 const uint64_t mask
= (1ULL << element_size
) - 1;
701 unsigned rowbase
= subreg
;
702 unsigned element
= 0;
704 for (int y
= 0; y
< exec_size
/ width
; y
++) {
705 unsigned offset
= rowbase
;
707 for (int x
= 0; x
< width
; x
++) {
708 access_mask
[element
++] = mask
<< offset
;
709 offset
+= hstride
* element_size
;
712 rowbase
+= vstride
* element_size
;
715 assert(element
== 0 || element
== exec_size
);
719 * Returns the number of registers accessed according to the \p access_mask
722 registers_read(const uint64_t access_mask
[static 32])
726 for (unsigned i
= 0; i
< 32; i
++) {
727 if (access_mask
[i
] > 0xFFFFFFFF) {
729 } else if (access_mask
[i
]) {
738 * Checks restrictions listed in "Region Alignment Rules" in the "Register
739 * Region Restrictions" section.
742 region_alignment_rules(const struct gen_device_info
*devinfo
,
743 const brw_inst
*inst
)
745 const struct opcode_desc
*desc
=
746 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
747 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
748 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
749 uint64_t dst_access_mask
[32], src0_access_mask
[32], src1_access_mask
[32];
750 struct string error_msg
= { .str
= NULL
, .len
= 0 };
752 if (num_sources
== 3)
753 return (struct string
){};
755 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
)
756 return (struct string
){};
758 if (inst_is_send(devinfo
, inst
))
759 return (struct string
){};
761 memset(dst_access_mask
, 0, sizeof(dst_access_mask
));
762 memset(src0_access_mask
, 0, sizeof(src0_access_mask
));
763 memset(src1_access_mask
, 0, sizeof(src1_access_mask
));
765 for (unsigned i
= 0; i
< num_sources
; i
++) {
766 unsigned vstride
, width
, hstride
, element_size
, subreg
;
767 enum brw_reg_type type
;
769 /* In Direct Addressing mode, a source cannot span more than 2 adjacent
774 if (brw_inst_src ## n ## _address_mode(devinfo, inst) != \
775 BRW_ADDRESS_DIRECT) \
778 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
779 BRW_IMMEDIATE_VALUE) \
782 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
783 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
784 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
785 type = brw_inst_src ## n ## _type(devinfo, inst); \
786 element_size = brw_reg_type_to_size(type); \
787 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
788 align1_access_mask(src ## n ## _access_mask, \
789 exec_size, element_size, subreg, \
790 vstride, width, hstride)
799 unsigned num_vstride
= exec_size
/ width
;
800 unsigned num_hstride
= width
;
801 unsigned vstride_elements
= (num_vstride
- 1) * vstride
;
802 unsigned hstride_elements
= (num_hstride
- 1) * hstride
;
803 unsigned offset
= (vstride_elements
+ hstride_elements
) * element_size
+
805 ERROR_IF(offset
>= 64,
806 "A source cannot span more than 2 adjacent GRF registers");
809 if (desc
->ndst
== 0 || dst_is_null(devinfo
, inst
))
812 unsigned stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
813 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
814 unsigned element_size
= brw_reg_type_to_size(dst_type
);
815 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
816 unsigned offset
= ((exec_size
- 1) * stride
* element_size
) + subreg
;
817 ERROR_IF(offset
>= 64,
818 "A destination cannot span more than 2 adjacent GRF registers");
823 /* On IVB/BYT, region parameters and execution size for DF are in terms of
824 * 32-bit elements, so they are doubled. For evaluating the validity of an
825 * instruction, we halve them.
827 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
831 align1_access_mask(dst_access_mask
, exec_size
, element_size
, subreg
,
832 exec_size
== 1 ? 0 : exec_size
* stride
,
833 exec_size
== 1 ? 1 : exec_size
,
834 exec_size
== 1 ? 0 : stride
);
836 unsigned dst_regs
= registers_read(dst_access_mask
);
837 unsigned src0_regs
= registers_read(src0_access_mask
);
838 unsigned src1_regs
= registers_read(src1_access_mask
);
840 /* The SNB, IVB, HSW, BDW, and CHV PRMs say:
842 * When an instruction has a source region spanning two registers and a
843 * destination region contained in one register, the number of elements
844 * must be the same between two sources and one of the following must be
847 * 1. The destination region is entirely contained in the lower OWord
849 * 2. The destination region is entirely contained in the upper OWord
851 * 3. The destination elements are evenly split between the two OWords
854 if (devinfo
->gen
<= 8) {
855 if (dst_regs
== 1 && (src0_regs
== 2 || src1_regs
== 2)) {
856 unsigned upper_oword_writes
= 0, lower_oword_writes
= 0;
858 for (unsigned i
= 0; i
< exec_size
; i
++) {
859 if (dst_access_mask
[i
] > 0x0000FFFF) {
860 upper_oword_writes
++;
862 assert(dst_access_mask
[i
] != 0);
863 lower_oword_writes
++;
867 ERROR_IF(lower_oword_writes
!= 0 &&
868 upper_oword_writes
!= 0 &&
869 upper_oword_writes
!= lower_oword_writes
,
870 "Writes must be to only one OWord or "
871 "evenly split between OWords");
875 /* The IVB and HSW PRMs say:
877 * When an instruction has a source region that spans two registers and
878 * the destination spans two registers, the destination elements must be
879 * evenly split between the two registers [...]
881 * The SNB PRM contains similar wording (but written in a much more
886 * When destination spans two registers, the source may be one or two
887 * registers. The destination elements must be evenly split between the
892 * When destination of MATH instruction spans two registers, the
893 * destination elements must be evenly split between the two registers.
895 * It is not known whether this restriction applies to KBL other Gens after
898 if (devinfo
->gen
<= 8 ||
899 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
901 /* Nothing explicitly states that on Gen < 8 elements must be evenly
902 * split between two destination registers in the two exceptional
903 * source-region-spans-one-register cases, but since Broadwell requires
904 * evenly split writes regardless of source region, we assume that it was
905 * an oversight and require it.
908 unsigned upper_reg_writes
= 0, lower_reg_writes
= 0;
910 for (unsigned i
= 0; i
< exec_size
; i
++) {
911 if (dst_access_mask
[i
] > 0xFFFFFFFF) {
914 assert(dst_access_mask
[i
] != 0);
919 ERROR_IF(upper_reg_writes
!= lower_reg_writes
,
920 "Writes must be evenly split between the two "
921 "destination registers");
925 /* The IVB and HSW PRMs say:
927 * When an instruction has a source region that spans two registers and
928 * the destination spans two registers, the destination elements must be
929 * evenly split between the two registers and each destination register
930 * must be entirely derived from one source register.
932 * Note: In such cases, the regioning parameters must ensure that the
933 * offset from the two source registers is the same.
935 * The SNB PRM contains similar wording (but written in a much more
938 * There are effectively three rules stated here:
940 * For an instruction with a source and a destination spanning two
943 * (1) destination elements must be evenly split between the two
945 * (2) all destination elements in a register must be derived
946 * from one source register
947 * (3) the offset (i.e. the starting location in each of the two
948 * registers spanned by a region) must be the same in the two
949 * registers spanned by a region
951 * It is impossible to violate rule (1) without violating (2) or (3), so we
952 * do not attempt to validate it.
954 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
955 for (unsigned i
= 0; i
< num_sources
; i
++) {
957 if (src ## n ## _regs <= 1) \
960 for (unsigned i = 0; i < exec_size; i++) { \
961 if ((dst_access_mask[i] > 0xFFFFFFFF) != \
962 (src ## n ## _access_mask[i] > 0xFFFFFFFF)) { \
963 ERROR("Each destination register must be entirely derived " \
964 "from one source register"); \
969 unsigned offset_0 = \
970 brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
971 unsigned offset_1 = offset_0; \
973 for (unsigned i = 0; i < exec_size; i++) { \
974 if (src ## n ## _access_mask[i] > 0xFFFFFFFF) { \
975 offset_1 = __builtin_ctzll(src ## n ## _access_mask[i]) - 32; \
980 ERROR_IF(num_sources == 2 && offset_0 != offset_1, \
981 "The offset from the two source registers " \
993 /* The IVB and HSW PRMs say:
995 * When destination spans two registers, the source MUST span two
996 * registers. The exception to the above rule:
997 * 1. When source is scalar, the source registers are not
999 * 2. When source is packed integer Word and destination is packed
1000 * integer DWord, the source register is not incremented by the
1001 * source sub register is incremented.
1003 * The SNB PRM does not contain this rule, but the internal documentation
1004 * indicates that it applies to SNB as well. We assume that the rule applies
1005 * to Gen <= 5 although their PRMs do not state it.
1007 * While the documentation explicitly says in exception (2) that the
1008 * destination must be an integer DWord, the hardware allows at least a
1009 * float destination type as well. We emit such instructions from
1011 * fs_visitor::emit_interpolation_setup_gen6
1012 * fs_visitor::emit_fragcoord_interpolation
1014 * and have for years with no ill effects.
1016 * Additionally the simulator source code indicates that the real condition
1017 * is that the size of the destination type is 4 bytes.
1019 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
1020 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1021 bool dst_is_packed_dword
=
1022 is_packed(exec_size
* stride
, exec_size
, stride
) &&
1023 brw_reg_type_to_size(dst_type
) == 4;
1025 for (unsigned i
= 0; i
< num_sources
; i
++) {
1027 unsigned vstride, width, hstride; \
1028 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
1029 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
1030 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
1031 bool src ## n ## _is_packed_word = \
1032 is_packed(vstride, width, hstride) && \
1033 (brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_W || \
1034 brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_UW); \
1036 ERROR_IF(src ## n ## _regs == 1 && \
1037 !src ## n ## _has_scalar_region(devinfo, inst) && \
1038 !(dst_is_packed_dword && src ## n ## _is_packed_word), \
1039 "When the destination spans two registers, the source must " \
1040 "span two registers\n" ERROR_INDENT "(exceptions for scalar " \
1041 "source and packed-word to packed-dword expansion)")
1055 static struct string
1056 vector_immediate_restrictions(const struct gen_device_info
*devinfo
,
1057 const brw_inst
*inst
)
1059 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1060 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1062 if (num_sources
== 3 || num_sources
== 0)
1063 return (struct string
){};
1065 unsigned file
= num_sources
== 1 ?
1066 brw_inst_src0_reg_file(devinfo
, inst
) :
1067 brw_inst_src1_reg_file(devinfo
, inst
);
1068 if (file
!= BRW_IMMEDIATE_VALUE
)
1069 return (struct string
){};
1071 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1072 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
1073 unsigned dst_subreg
= brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
?
1074 brw_inst_dst_da1_subreg_nr(devinfo
, inst
) : 0;
1075 unsigned dst_stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
1076 enum brw_reg_type type
= num_sources
== 1 ?
1077 brw_inst_src0_type(devinfo
, inst
) :
1078 brw_inst_src1_type(devinfo
, inst
);
1082 * When an immediate vector is used in an instruction, the destination
1083 * must be 128-bit aligned with destination horizontal stride equivalent
1084 * to a word for an immediate integer vector (v) and equivalent to a
1085 * DWord for an immediate float vector (vf).
1087 * The text has not been updated for the addition of the immediate unsigned
1088 * integer vector type (uv) on SNB, but presumably the same restriction
1092 case BRW_REGISTER_TYPE_V
:
1093 case BRW_REGISTER_TYPE_UV
:
1094 case BRW_REGISTER_TYPE_VF
:
1095 ERROR_IF(dst_subreg
% (128 / 8) != 0,
1096 "Destination must be 128-bit aligned in order to use immediate "
1099 if (type
== BRW_REGISTER_TYPE_VF
) {
1100 ERROR_IF(dst_type_size
* dst_stride
!= 4,
1101 "Destination must have stride equivalent to dword in order "
1102 "to use the VF type");
1104 ERROR_IF(dst_type_size
* dst_stride
!= 2,
1105 "Destination must have stride equivalent to word in order "
1106 "to use the V or UV type");
1116 static struct string
1117 special_requirements_for_handling_double_precision_data_types(
1118 const struct gen_device_info
*devinfo
,
1119 const brw_inst
*inst
)
1121 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1122 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1124 if (num_sources
== 3 || num_sources
== 0)
1125 return (struct string
){};
1127 enum brw_reg_type exec_type
= execution_type(devinfo
, inst
);
1128 unsigned exec_type_size
= brw_reg_type_to_size(exec_type
);
1130 enum brw_reg_file dst_file
= brw_inst_dst_reg_file(devinfo
, inst
);
1131 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1132 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
1133 unsigned dst_hstride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
1134 unsigned dst_reg
= brw_inst_dst_da_reg_nr(devinfo
, inst
);
1135 unsigned dst_subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
1136 unsigned dst_address_mode
= brw_inst_dst_address_mode(devinfo
, inst
);
1138 bool is_integer_dword_multiply
=
1139 devinfo
->gen
>= 8 &&
1140 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MUL
&&
1141 (brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_D
||
1142 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UD
) &&
1143 (brw_inst_src1_type(devinfo
, inst
) == BRW_REGISTER_TYPE_D
||
1144 brw_inst_src1_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UD
);
1146 if (dst_type_size
!= 8 && exec_type_size
!= 8 && !is_integer_dword_multiply
)
1147 return (struct string
){};
1149 for (unsigned i
= 0; i
< num_sources
; i
++) {
1150 unsigned vstride
, width
, hstride
, type_size
, reg
, subreg
, address_mode
;
1151 bool is_scalar_region
;
1152 enum brw_reg_file file
;
1153 enum brw_reg_type type
;
1156 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
1157 BRW_IMMEDIATE_VALUE) \
1160 is_scalar_region = src ## n ## _has_scalar_region(devinfo, inst); \
1161 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
1162 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
1163 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
1164 file = brw_inst_src ## n ## _reg_file(devinfo, inst); \
1165 type = brw_inst_src ## n ## _type(devinfo, inst); \
1166 type_size = brw_reg_type_to_size(type); \
1167 reg = brw_inst_src ## n ## _da_reg_nr(devinfo, inst); \
1168 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
1169 address_mode = brw_inst_src ## n ## _address_mode(devinfo, inst)
1178 /* The PRMs say that for CHV, BXT:
1180 * When source or destination datatype is 64b or operation is integer
1181 * DWord multiply, regioning in Align1 must follow these rules:
1183 * 1. Source and Destination horizontal stride must be aligned to the
1185 * 2. Regioning must ensure Src.Vstride = Src.Width * Src.Hstride.
1186 * 3. Source and Destination offset must be the same, except the case
1189 * We assume that the restriction applies to GLK as well.
1191 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
1192 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
1193 unsigned src_stride
= hstride
* type_size
;
1194 unsigned dst_stride
= dst_hstride
* dst_type_size
;
1196 ERROR_IF(!is_scalar_region
&&
1197 (src_stride
% 8 != 0 ||
1198 dst_stride
% 8 != 0 ||
1199 src_stride
!= dst_stride
),
1200 "Source and destination horizontal stride must equal and a "
1201 "multiple of a qword when the execution type is 64-bit");
1203 ERROR_IF(vstride
!= width
* hstride
,
1204 "Vstride must be Width * Hstride when the execution type is "
1207 ERROR_IF(!is_scalar_region
&& dst_subreg
!= subreg
,
1208 "Source and destination offset must be the same when the "
1209 "execution type is 64-bit");
1212 /* The PRMs say that for CHV, BXT:
1214 * When source or destination datatype is 64b or operation is integer
1215 * DWord multiply, indirect addressing must not be used.
1217 * We assume that the restriction applies to GLK as well.
1219 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1220 ERROR_IF(BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
== address_mode
||
1221 BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
== dst_address_mode
,
1222 "Indirect addressing is not allowed when the execution type "
1226 /* The PRMs say that for CHV, BXT:
1228 * ARF registers must never be used with 64b datatype or when
1229 * operation is integer DWord multiply.
1231 * We assume that the restriction applies to GLK as well.
1233 * We assume that the restriction does not apply to the null register.
1235 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1236 ERROR_IF(brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MAC
||
1237 brw_inst_acc_wr_control(devinfo
, inst
) ||
1238 (BRW_ARCHITECTURE_REGISTER_FILE
== file
&&
1239 reg
!= BRW_ARF_NULL
) ||
1240 (BRW_ARCHITECTURE_REGISTER_FILE
== dst_file
&&
1241 dst_reg
!= BRW_ARF_NULL
),
1242 "Architecture registers cannot be used when the execution "
1247 /* The PRMs say that for BDW, SKL:
1249 * If Align16 is required for an operation with QW destination and non-QW
1250 * source datatypes, the execution size cannot exceed 2.
1252 * We assume that the restriction applies to all Gen8+ parts.
1254 if (devinfo
->gen
>= 8) {
1255 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
1256 enum brw_reg_type src1_type
=
1257 num_sources
> 1 ? brw_inst_src1_type(devinfo
, inst
) : src0_type
;
1258 unsigned src0_type_size
= brw_reg_type_to_size(src0_type
);
1259 unsigned src1_type_size
= brw_reg_type_to_size(src1_type
);
1261 ERROR_IF(brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
&&
1262 dst_type_size
== 8 &&
1263 (src0_type_size
!= 8 || src1_type_size
!= 8) &&
1264 brw_inst_exec_size(devinfo
, inst
) > BRW_EXECUTE_2
,
1265 "In Align16 exec size cannot exceed 2 with a QWord destination "
1266 "and a non-QWord source");
1269 /* The PRMs say that for CHV, BXT:
1271 * When source or destination datatype is 64b or operation is integer
1272 * DWord multiply, DepCtrl must not be used.
1274 * We assume that the restriction applies to GLK as well.
1276 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1277 ERROR_IF(brw_inst_no_dd_check(devinfo
, inst
) ||
1278 brw_inst_no_dd_clear(devinfo
, inst
),
1279 "DepCtrl is not allowed when the execution type is 64-bit");
1286 brw_validate_instructions(const struct gen_device_info
*devinfo
,
1287 const void *assembly
, int start_offset
, int end_offset
,
1288 struct disasm_info
*disasm
)
1292 for (int src_offset
= start_offset
; src_offset
< end_offset
;) {
1293 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1294 const brw_inst
*inst
= assembly
+ src_offset
;
1295 bool is_compact
= brw_inst_cmpt_control(devinfo
, inst
);
1296 brw_inst uncompacted
;
1299 brw_compact_inst
*compacted
= (void *)inst
;
1300 brw_uncompact_instruction(devinfo
, &uncompacted
, compacted
);
1301 inst
= &uncompacted
;
1304 if (is_unsupported_inst(devinfo
, inst
)) {
1305 ERROR("Instruction not supported on this Gen");
1307 CHECK(sources_not_null
);
1308 CHECK(send_restrictions
);
1309 CHECK(general_restrictions_based_on_operand_types
);
1310 CHECK(general_restrictions_on_region_parameters
);
1311 CHECK(region_alignment_rules
);
1312 CHECK(vector_immediate_restrictions
);
1313 CHECK(special_requirements_for_handling_double_precision_data_types
);
1316 if (error_msg
.str
&& disasm
) {
1317 disasm_insert_error(disasm
, src_offset
, error_msg
.str
);
1319 valid
= valid
&& error_msg
.len
== 0;
1320 free(error_msg
.str
);
1323 src_offset
+= sizeof(brw_compact_inst
);
1325 src_offset
+= sizeof(brw_inst
);