2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_eu_validate.c
26 * This file implements a pass that validates shader assembly.
31 /* We're going to do lots of string concatenation, so this should help. */
38 cat(struct string
*dest
, const struct string src
)
40 dest
->str
= realloc(dest
->str
, dest
->len
+ src
.len
+ 1);
41 memcpy(dest
->str
+ dest
->len
, src
.str
, src
.len
);
42 dest
->str
[dest
->len
+ src
.len
] = '\0';
43 dest
->len
= dest
->len
+ src
.len
;
45 #define CAT(dest, src) cat(&dest, (struct string){src, strlen(src)})
48 contains(const struct string haystack
, const struct string needle
)
50 return haystack
.str
&& memmem(haystack
.str
, haystack
.len
,
51 needle
.str
, needle
.len
) != NULL
;
53 #define CONTAINS(haystack, needle) \
54 contains(haystack, (struct string){needle, strlen(needle)})
56 #define error(str) "\tERROR: " str "\n"
57 #define ERROR_INDENT "\t "
59 #define ERROR(msg) ERROR_IF(true, msg)
60 #define ERROR_IF(cond, msg) \
62 if ((cond) && !CONTAINS(error_msg, error(msg))) { \
63 CAT(error_msg, error(msg)); \
67 #define CHECK(func, args...) \
69 struct string __msg = func(devinfo, inst, ##args); \
71 cat(&error_msg, __msg); \
76 #define STRIDE(stride) (stride != 0 ? 1 << ((stride) - 1) : 0)
77 #define WIDTH(width) (1 << (width))
80 inst_is_send(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
82 switch (brw_inst_opcode(devinfo
, inst
)) {
84 case BRW_OPCODE_SENDC
:
85 case BRW_OPCODE_SENDS
:
86 case BRW_OPCODE_SENDSC
:
94 signed_type(unsigned type
)
97 case BRW_REGISTER_TYPE_UD
: return BRW_REGISTER_TYPE_D
;
98 case BRW_REGISTER_TYPE_UW
: return BRW_REGISTER_TYPE_W
;
99 case BRW_REGISTER_TYPE_UB
: return BRW_REGISTER_TYPE_B
;
100 case BRW_REGISTER_TYPE_UQ
: return BRW_REGISTER_TYPE_Q
;
101 default: return type
;
106 inst_is_raw_move(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
108 unsigned dst_type
= signed_type(brw_inst_dst_type(devinfo
, inst
));
109 unsigned src_type
= signed_type(brw_inst_src0_type(devinfo
, inst
));
111 if (brw_inst_src0_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
) {
112 /* FIXME: not strictly true */
113 if (brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_VF
||
114 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UV
||
115 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_V
) {
118 } else if (brw_inst_src0_negate(devinfo
, inst
) ||
119 brw_inst_src0_abs(devinfo
, inst
)) {
123 return brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MOV
&&
124 brw_inst_saturate(devinfo
, inst
) == 0 &&
125 dst_type
== src_type
;
129 dst_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
131 return brw_inst_dst_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
132 brw_inst_dst_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
136 src0_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
138 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
139 brw_inst_src0_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
143 src1_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
145 return brw_inst_src1_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
146 brw_inst_src1_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
150 src0_is_grf(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
152 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_GENERAL_REGISTER_FILE
;
156 src0_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
158 return brw_inst_src0_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
159 brw_inst_src0_width(devinfo
, inst
) == BRW_WIDTH_1
&&
160 brw_inst_src0_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
164 src1_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
166 return brw_inst_src1_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
167 brw_inst_src1_width(devinfo
, inst
) == BRW_WIDTH_1
&&
168 brw_inst_src1_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
172 num_sources_from_inst(const struct gen_device_info
*devinfo
,
173 const brw_inst
*inst
)
175 const struct opcode_desc
*desc
=
176 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
177 unsigned math_function
;
179 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
180 math_function
= brw_inst_math_function(devinfo
, inst
);
181 } else if (devinfo
->gen
< 6 &&
182 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
183 if (brw_inst_sfid(devinfo
, inst
) == BRW_SFID_MATH
) {
184 /* src1 must be a descriptor (including the information to determine
185 * that the SEND is doing an extended math operation), but src0 can
186 * actually be null since it serves as the source of the implicit GRF
189 * If we stop using that functionality, we'll have to revisit this.
193 /* Send instructions are allowed to have null sources since they use
194 * the base_mrf field to specify which message register source.
199 assert(desc
->nsrc
< 4);
203 switch (math_function
) {
204 case BRW_MATH_FUNCTION_INV
:
205 case BRW_MATH_FUNCTION_LOG
:
206 case BRW_MATH_FUNCTION_EXP
:
207 case BRW_MATH_FUNCTION_SQRT
:
208 case BRW_MATH_FUNCTION_RSQ
:
209 case BRW_MATH_FUNCTION_SIN
:
210 case BRW_MATH_FUNCTION_COS
:
211 case BRW_MATH_FUNCTION_SINCOS
:
212 case GEN8_MATH_FUNCTION_INVM
:
213 case GEN8_MATH_FUNCTION_RSQRTM
:
215 case BRW_MATH_FUNCTION_FDIV
:
216 case BRW_MATH_FUNCTION_POW
:
217 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
:
218 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
:
219 case BRW_MATH_FUNCTION_INT_DIV_REMAINDER
:
222 unreachable("not reached");
227 sources_not_null(const struct gen_device_info
*devinfo
,
228 const brw_inst
*inst
)
230 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
231 struct string error_msg
= { .str
= NULL
, .len
= 0 };
233 /* Nothing to test. 3-src instructions can only have GRF sources, and
234 * there's no bit to control the file.
236 if (num_sources
== 3)
237 return (struct string
){};
239 if (num_sources
>= 1)
240 ERROR_IF(src0_is_null(devinfo
, inst
), "src0 is null");
242 if (num_sources
== 2)
243 ERROR_IF(src1_is_null(devinfo
, inst
), "src1 is null");
249 send_restrictions(const struct gen_device_info
*devinfo
,
250 const brw_inst
*inst
)
252 struct string error_msg
= { .str
= NULL
, .len
= 0 };
254 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
255 ERROR_IF(brw_inst_src0_address_mode(devinfo
, inst
) != BRW_ADDRESS_DIRECT
,
256 "send must use direct addressing");
258 if (devinfo
->gen
>= 7) {
259 ERROR_IF(!src0_is_grf(devinfo
, inst
), "send from non-GRF");
260 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
261 brw_inst_src0_da_reg_nr(devinfo
, inst
) < 112,
262 "send with EOT must use g112-g127");
265 if (devinfo
->gen
>= 8) {
266 ERROR_IF(!dst_is_null(devinfo
, inst
) &&
267 (brw_inst_dst_da_reg_nr(devinfo
, inst
) +
268 brw_inst_rlen(devinfo
, inst
) > 127) &&
269 (brw_inst_src0_da_reg_nr(devinfo
, inst
) +
270 brw_inst_mlen(devinfo
, inst
) >
271 brw_inst_dst_da_reg_nr(devinfo
, inst
)),
272 "r127 must not be used for return address when there is "
273 "a src and dest overlap");
281 is_unsupported_inst(const struct gen_device_info
*devinfo
,
282 const brw_inst
*inst
)
284 return brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
)) == NULL
;
287 static enum brw_reg_type
288 execution_type_for_type(enum brw_reg_type type
)
291 case BRW_REGISTER_TYPE_NF
:
292 case BRW_REGISTER_TYPE_DF
:
293 case BRW_REGISTER_TYPE_F
:
294 case BRW_REGISTER_TYPE_HF
:
297 case BRW_REGISTER_TYPE_VF
:
298 return BRW_REGISTER_TYPE_F
;
300 case BRW_REGISTER_TYPE_Q
:
301 case BRW_REGISTER_TYPE_UQ
:
302 return BRW_REGISTER_TYPE_Q
;
304 case BRW_REGISTER_TYPE_D
:
305 case BRW_REGISTER_TYPE_UD
:
306 return BRW_REGISTER_TYPE_D
;
308 case BRW_REGISTER_TYPE_W
:
309 case BRW_REGISTER_TYPE_UW
:
310 case BRW_REGISTER_TYPE_B
:
311 case BRW_REGISTER_TYPE_UB
:
312 case BRW_REGISTER_TYPE_V
:
313 case BRW_REGISTER_TYPE_UV
:
314 return BRW_REGISTER_TYPE_W
;
316 unreachable("not reached");
320 * Returns the execution type of an instruction \p inst
322 static enum brw_reg_type
323 execution_type(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
325 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
326 enum brw_reg_type src0_exec_type
, src1_exec_type
;
328 /* Execution data type is independent of destination data type, except in
329 * mixed F/HF instructions on CHV and SKL+.
331 enum brw_reg_type dst_exec_type
= brw_inst_dst_type(devinfo
, inst
);
333 src0_exec_type
= execution_type_for_type(brw_inst_src0_type(devinfo
, inst
));
334 if (num_sources
== 1) {
335 if ((devinfo
->gen
>= 9 || devinfo
->is_cherryview
) &&
336 src0_exec_type
== BRW_REGISTER_TYPE_HF
) {
337 return dst_exec_type
;
339 return src0_exec_type
;
342 src1_exec_type
= execution_type_for_type(brw_inst_src1_type(devinfo
, inst
));
343 if (src0_exec_type
== src1_exec_type
)
344 return src0_exec_type
;
346 /* Mixed operand types where one is float is float on Gen < 6
347 * (and not allowed on later platforms)
349 if (devinfo
->gen
< 6 &&
350 (src0_exec_type
== BRW_REGISTER_TYPE_F
||
351 src1_exec_type
== BRW_REGISTER_TYPE_F
))
352 return BRW_REGISTER_TYPE_F
;
354 if (src0_exec_type
== BRW_REGISTER_TYPE_Q
||
355 src1_exec_type
== BRW_REGISTER_TYPE_Q
)
356 return BRW_REGISTER_TYPE_Q
;
358 if (src0_exec_type
== BRW_REGISTER_TYPE_D
||
359 src1_exec_type
== BRW_REGISTER_TYPE_D
)
360 return BRW_REGISTER_TYPE_D
;
362 if (src0_exec_type
== BRW_REGISTER_TYPE_W
||
363 src1_exec_type
== BRW_REGISTER_TYPE_W
)
364 return BRW_REGISTER_TYPE_W
;
366 if (src0_exec_type
== BRW_REGISTER_TYPE_DF
||
367 src1_exec_type
== BRW_REGISTER_TYPE_DF
)
368 return BRW_REGISTER_TYPE_DF
;
370 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
371 if (dst_exec_type
== BRW_REGISTER_TYPE_F
||
372 src0_exec_type
== BRW_REGISTER_TYPE_F
||
373 src1_exec_type
== BRW_REGISTER_TYPE_F
) {
374 return BRW_REGISTER_TYPE_F
;
376 return BRW_REGISTER_TYPE_HF
;
380 assert(src0_exec_type
== BRW_REGISTER_TYPE_F
);
381 return BRW_REGISTER_TYPE_F
;
385 * Returns whether a region is packed
387 * A region is packed if its elements are adjacent in memory, with no
388 * intervening space, no overlap, and no replicated values.
391 is_packed(unsigned vstride
, unsigned width
, unsigned hstride
)
393 if (vstride
== width
) {
405 * Checks restrictions listed in "General Restrictions Based on Operand Types"
406 * in the "Register Region Restrictions" section.
409 general_restrictions_based_on_operand_types(const struct gen_device_info
*devinfo
,
410 const brw_inst
*inst
)
412 const struct opcode_desc
*desc
=
413 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
414 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
415 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
416 struct string error_msg
= { .str
= NULL
, .len
= 0 };
418 if (num_sources
== 3)
419 return (struct string
){};
421 if (inst_is_send(devinfo
, inst
))
422 return (struct string
){};
425 return (struct string
){};
428 return (struct string
){};
432 * Where n is the largest element size in bytes for any source or
433 * destination operand type, ExecSize * n must be <= 64.
435 * But we do not attempt to enforce it, because it is implied by other
438 * - that the destination stride must match the execution data type
439 * - sources may not span more than two adjacent GRF registers
440 * - destination may not span more than two adjacent GRF registers
442 * In fact, checking it would weaken testing of the other rules.
445 unsigned dst_stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
446 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
447 bool dst_type_is_byte
=
448 brw_inst_dst_type(devinfo
, inst
) == BRW_REGISTER_TYPE_B
||
449 brw_inst_dst_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UB
;
451 if (dst_type_is_byte
) {
452 if (is_packed(exec_size
* dst_stride
, exec_size
, dst_stride
)) {
453 if (!inst_is_raw_move(devinfo
, inst
)) {
454 ERROR("Only raw MOV supports a packed-byte destination");
457 return (struct string
){};
462 unsigned exec_type
= execution_type(devinfo
, inst
);
463 unsigned exec_type_size
= brw_reg_type_to_size(exec_type
);
464 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
466 /* On IVB/BYT, region parameters and execution size for DF are in terms of
467 * 32-bit elements, so they are doubled. For evaluating the validity of an
468 * instruction, we halve them.
470 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
471 exec_type_size
== 8 && dst_type_size
== 4)
474 if (exec_type_size
> dst_type_size
) {
475 if (!(dst_type_is_byte
&& inst_is_raw_move(devinfo
, inst
))) {
476 ERROR_IF(dst_stride
* dst_type_size
!= exec_type_size
,
477 "Destination stride must be equal to the ratio of the sizes "
478 "of the execution data type to the destination type");
481 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
483 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
484 brw_inst_dst_address_mode(devinfo
, inst
) == BRW_ADDRESS_DIRECT
) {
485 /* The i965 PRM says:
487 * Implementation Restriction: The relaxed alignment rule for byte
488 * destination (#10.5) is not supported.
490 if ((devinfo
->gen
> 4 || devinfo
->is_g4x
) && dst_type_is_byte
) {
491 ERROR_IF(subreg
% exec_type_size
!= 0 &&
492 subreg
% exec_type_size
!= 1,
493 "Destination subreg must be aligned to the size of the "
494 "execution data type (or to the next lowest byte for byte "
497 ERROR_IF(subreg
% exec_type_size
!= 0,
498 "Destination subreg must be aligned to the size of the "
499 "execution data type");
508 * Checks restrictions listed in "General Restrictions on Regioning Parameters"
509 * in the "Register Region Restrictions" section.
512 general_restrictions_on_region_parameters(const struct gen_device_info
*devinfo
,
513 const brw_inst
*inst
)
515 const struct opcode_desc
*desc
=
516 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
517 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
518 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
519 struct string error_msg
= { .str
= NULL
, .len
= 0 };
521 if (num_sources
== 3)
522 return (struct string
){};
524 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
) {
525 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
))
526 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) != BRW_HORIZONTAL_STRIDE_1
,
527 "Destination Horizontal Stride must be 1");
529 if (num_sources
>= 1) {
530 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
531 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
532 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
533 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
534 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
535 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
537 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
538 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
539 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
540 "In Align16 mode, only VertStride of 0 or 4 is allowed");
544 if (num_sources
== 2) {
545 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
546 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
547 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
548 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
549 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
550 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
552 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
553 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
554 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
555 "In Align16 mode, only VertStride of 0 or 4 is allowed");
562 for (unsigned i
= 0; i
< num_sources
; i
++) {
563 unsigned vstride
, width
, hstride
, element_size
, subreg
;
564 enum brw_reg_type type
;
567 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
568 BRW_IMMEDIATE_VALUE) \
571 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
572 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
573 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
574 type = brw_inst_src ## n ## _type(devinfo, inst); \
575 element_size = brw_reg_type_to_size(type); \
576 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst)
585 /* On IVB/BYT, region parameters and execution size for DF are in terms of
586 * 32-bit elements, so they are doubled. For evaluating the validity of an
587 * instruction, we halve them.
589 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
593 /* ExecSize must be greater than or equal to Width. */
594 ERROR_IF(exec_size
< width
, "ExecSize must be greater than or equal "
597 /* If ExecSize = Width and HorzStride ≠ 0,
598 * VertStride must be set to Width * HorzStride.
600 if (exec_size
== width
&& hstride
!= 0) {
601 ERROR_IF(vstride
!= width
* hstride
,
602 "If ExecSize = Width and HorzStride ≠ 0, "
603 "VertStride must be set to Width * HorzStride");
606 /* If Width = 1, HorzStride must be 0 regardless of the values of
607 * ExecSize and VertStride.
610 ERROR_IF(hstride
!= 0,
611 "If Width = 1, HorzStride must be 0 regardless "
612 "of the values of ExecSize and VertStride");
615 /* If ExecSize = Width = 1, both VertStride and HorzStride must be 0. */
616 if (exec_size
== 1 && width
== 1) {
617 ERROR_IF(vstride
!= 0 || hstride
!= 0,
618 "If ExecSize = Width = 1, both VertStride "
619 "and HorzStride must be 0");
622 /* If VertStride = HorzStride = 0, Width must be 1 regardless of the
625 if (vstride
== 0 && hstride
== 0) {
627 "If VertStride = HorzStride = 0, Width must be "
628 "1 regardless of the value of ExecSize");
631 /* VertStride must be used to cross GRF register boundaries. This rule
632 * implies that elements within a 'Width' cannot cross GRF boundaries.
634 const uint64_t mask
= (1ULL << element_size
) - 1;
635 unsigned rowbase
= subreg
;
637 for (int y
= 0; y
< exec_size
/ width
; y
++) {
638 uint64_t access_mask
= 0;
639 unsigned offset
= rowbase
;
641 for (int x
= 0; x
< width
; x
++) {
642 access_mask
|= mask
<< offset
;
643 offset
+= hstride
* element_size
;
646 rowbase
+= vstride
* element_size
;
648 if ((uint32_t)access_mask
!= 0 && (access_mask
>> 32) != 0) {
649 ERROR("VertStride must be used to cross GRF register boundaries");
655 /* Dst.HorzStride must not be 0. */
656 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
)) {
657 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
,
658 "Destination Horizontal Stride must not be 0");
665 * Creates an \p access_mask for an \p exec_size, \p element_size, and a region
667 * An \p access_mask is a 32-element array of uint64_t, where each uint64_t is
668 * a bitmask of bytes accessed by the region.
670 * For instance the access mask of the source gX.1<4,2,2>F in an exec_size = 4
671 * instruction would be
673 * access_mask[0] = 0x00000000000000F0
674 * access_mask[1] = 0x000000000000F000
675 * access_mask[2] = 0x0000000000F00000
676 * access_mask[3] = 0x00000000F0000000
677 * access_mask[4-31] = 0
679 * because the first execution channel accesses bytes 7-4 and the second
680 * execution channel accesses bytes 15-12, etc.
683 align1_access_mask(uint64_t access_mask
[static 32],
684 unsigned exec_size
, unsigned element_size
, unsigned subreg
,
685 unsigned vstride
, unsigned width
, unsigned hstride
)
687 const uint64_t mask
= (1ULL << element_size
) - 1;
688 unsigned rowbase
= subreg
;
689 unsigned element
= 0;
691 for (int y
= 0; y
< exec_size
/ width
; y
++) {
692 unsigned offset
= rowbase
;
694 for (int x
= 0; x
< width
; x
++) {
695 access_mask
[element
++] = mask
<< offset
;
696 offset
+= hstride
* element_size
;
699 rowbase
+= vstride
* element_size
;
702 assert(element
== 0 || element
== exec_size
);
706 * Returns the number of registers accessed according to the \p access_mask
709 registers_read(const uint64_t access_mask
[static 32])
713 for (unsigned i
= 0; i
< 32; i
++) {
714 if (access_mask
[i
] > 0xFFFFFFFF) {
716 } else if (access_mask
[i
]) {
725 * Checks restrictions listed in "Region Alignment Rules" in the "Register
726 * Region Restrictions" section.
729 region_alignment_rules(const struct gen_device_info
*devinfo
,
730 const brw_inst
*inst
)
732 const struct opcode_desc
*desc
=
733 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
734 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
735 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
736 uint64_t dst_access_mask
[32], src0_access_mask
[32], src1_access_mask
[32];
737 struct string error_msg
= { .str
= NULL
, .len
= 0 };
739 if (num_sources
== 3)
740 return (struct string
){};
742 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
)
743 return (struct string
){};
745 if (inst_is_send(devinfo
, inst
))
746 return (struct string
){};
748 memset(dst_access_mask
, 0, sizeof(dst_access_mask
));
749 memset(src0_access_mask
, 0, sizeof(src0_access_mask
));
750 memset(src1_access_mask
, 0, sizeof(src1_access_mask
));
752 for (unsigned i
= 0; i
< num_sources
; i
++) {
753 unsigned vstride
, width
, hstride
, element_size
, subreg
;
754 enum brw_reg_type type
;
756 /* In Direct Addressing mode, a source cannot span more than 2 adjacent
761 if (brw_inst_src ## n ## _address_mode(devinfo, inst) != \
762 BRW_ADDRESS_DIRECT) \
765 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
766 BRW_IMMEDIATE_VALUE) \
769 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
770 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
771 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
772 type = brw_inst_src ## n ## _type(devinfo, inst); \
773 element_size = brw_reg_type_to_size(type); \
774 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
775 align1_access_mask(src ## n ## _access_mask, \
776 exec_size, element_size, subreg, \
777 vstride, width, hstride)
786 unsigned num_vstride
= exec_size
/ width
;
787 unsigned num_hstride
= width
;
788 unsigned vstride_elements
= (num_vstride
- 1) * vstride
;
789 unsigned hstride_elements
= (num_hstride
- 1) * hstride
;
790 unsigned offset
= (vstride_elements
+ hstride_elements
) * element_size
+
792 ERROR_IF(offset
>= 64,
793 "A source cannot span more than 2 adjacent GRF registers");
796 if (desc
->ndst
== 0 || dst_is_null(devinfo
, inst
))
799 unsigned stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
800 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
801 unsigned element_size
= brw_reg_type_to_size(dst_type
);
802 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
803 unsigned offset
= ((exec_size
- 1) * stride
* element_size
) + subreg
;
804 ERROR_IF(offset
>= 64,
805 "A destination cannot span more than 2 adjacent GRF registers");
810 /* On IVB/BYT, region parameters and execution size for DF are in terms of
811 * 32-bit elements, so they are doubled. For evaluating the validity of an
812 * instruction, we halve them.
814 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
818 align1_access_mask(dst_access_mask
, exec_size
, element_size
, subreg
,
819 exec_size
== 1 ? 0 : exec_size
* stride
,
820 exec_size
== 1 ? 1 : exec_size
,
821 exec_size
== 1 ? 0 : stride
);
823 unsigned dst_regs
= registers_read(dst_access_mask
);
824 unsigned src0_regs
= registers_read(src0_access_mask
);
825 unsigned src1_regs
= registers_read(src1_access_mask
);
827 /* The SNB, IVB, HSW, BDW, and CHV PRMs say:
829 * When an instruction has a source region spanning two registers and a
830 * destination region contained in one register, the number of elements
831 * must be the same between two sources and one of the following must be
834 * 1. The destination region is entirely contained in the lower OWord
836 * 2. The destination region is entirely contained in the upper OWord
838 * 3. The destination elements are evenly split between the two OWords
841 if (devinfo
->gen
<= 8) {
842 if (dst_regs
== 1 && (src0_regs
== 2 || src1_regs
== 2)) {
843 unsigned upper_oword_writes
= 0, lower_oword_writes
= 0;
845 for (unsigned i
= 0; i
< exec_size
; i
++) {
846 if (dst_access_mask
[i
] > 0x0000FFFF) {
847 upper_oword_writes
++;
849 assert(dst_access_mask
[i
] != 0);
850 lower_oword_writes
++;
854 ERROR_IF(lower_oword_writes
!= 0 &&
855 upper_oword_writes
!= 0 &&
856 upper_oword_writes
!= lower_oword_writes
,
857 "Writes must be to only one OWord or "
858 "evenly split between OWords");
862 /* The IVB and HSW PRMs say:
864 * When an instruction has a source region that spans two registers and
865 * the destination spans two registers, the destination elements must be
866 * evenly split between the two registers [...]
868 * The SNB PRM contains similar wording (but written in a much more
873 * When destination spans two registers, the source may be one or two
874 * registers. The destination elements must be evenly split between the
879 * When destination of MATH instruction spans two registers, the
880 * destination elements must be evenly split between the two registers.
882 * It is not known whether this restriction applies to KBL other Gens after
885 if (devinfo
->gen
<= 8 ||
886 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
888 /* Nothing explicitly states that on Gen < 8 elements must be evenly
889 * split between two destination registers in the two exceptional
890 * source-region-spans-one-register cases, but since Broadwell requires
891 * evenly split writes regardless of source region, we assume that it was
892 * an oversight and require it.
895 unsigned upper_reg_writes
= 0, lower_reg_writes
= 0;
897 for (unsigned i
= 0; i
< exec_size
; i
++) {
898 if (dst_access_mask
[i
] > 0xFFFFFFFF) {
901 assert(dst_access_mask
[i
] != 0);
906 ERROR_IF(upper_reg_writes
!= lower_reg_writes
,
907 "Writes must be evenly split between the two "
908 "destination registers");
912 /* The IVB and HSW PRMs say:
914 * When an instruction has a source region that spans two registers and
915 * the destination spans two registers, the destination elements must be
916 * evenly split between the two registers and each destination register
917 * must be entirely derived from one source register.
919 * Note: In such cases, the regioning parameters must ensure that the
920 * offset from the two source registers is the same.
922 * The SNB PRM contains similar wording (but written in a much more
925 * There are effectively three rules stated here:
927 * For an instruction with a source and a destination spanning two
930 * (1) destination elements must be evenly split between the two
932 * (2) all destination elements in a register must be derived
933 * from one source register
934 * (3) the offset (i.e. the starting location in each of the two
935 * registers spanned by a region) must be the same in the two
936 * registers spanned by a region
938 * It is impossible to violate rule (1) without violating (2) or (3), so we
939 * do not attempt to validate it.
941 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
942 for (unsigned i
= 0; i
< num_sources
; i
++) {
944 if (src ## n ## _regs <= 1) \
947 for (unsigned i = 0; i < exec_size; i++) { \
948 if ((dst_access_mask[i] > 0xFFFFFFFF) != \
949 (src ## n ## _access_mask[i] > 0xFFFFFFFF)) { \
950 ERROR("Each destination register must be entirely derived " \
951 "from one source register"); \
956 unsigned offset_0 = \
957 brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
958 unsigned offset_1 = offset_0; \
960 for (unsigned i = 0; i < exec_size; i++) { \
961 if (src ## n ## _access_mask[i] > 0xFFFFFFFF) { \
962 offset_1 = __builtin_ctzll(src ## n ## _access_mask[i]) - 32; \
967 ERROR_IF(num_sources == 2 && offset_0 != offset_1, \
968 "The offset from the two source registers " \
980 /* The IVB and HSW PRMs say:
982 * When destination spans two registers, the source MUST span two
983 * registers. The exception to the above rule:
984 * 1. When source is scalar, the source registers are not
986 * 2. When source is packed integer Word and destination is packed
987 * integer DWord, the source register is not incremented by the
988 * source sub register is incremented.
990 * The SNB PRM does not contain this rule, but the internal documentation
991 * indicates that it applies to SNB as well. We assume that the rule applies
992 * to Gen <= 5 although their PRMs do not state it.
994 * While the documentation explicitly says in exception (2) that the
995 * destination must be an integer DWord, the hardware allows at least a
996 * float destination type as well. We emit such instructions from
998 * fs_visitor::emit_interpolation_setup_gen6
999 * fs_visitor::emit_fragcoord_interpolation
1001 * and have for years with no ill effects.
1003 * Additionally the simulator source code indicates that the real condition
1004 * is that the size of the destination type is 4 bytes.
1006 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
1007 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1008 bool dst_is_packed_dword
=
1009 is_packed(exec_size
* stride
, exec_size
, stride
) &&
1010 brw_reg_type_to_size(dst_type
) == 4;
1012 for (unsigned i
= 0; i
< num_sources
; i
++) {
1014 unsigned vstride, width, hstride; \
1015 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
1016 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
1017 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
1018 bool src ## n ## _is_packed_word = \
1019 is_packed(vstride, width, hstride) && \
1020 (brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_W || \
1021 brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_UW); \
1023 ERROR_IF(src ## n ## _regs == 1 && \
1024 !src ## n ## _has_scalar_region(devinfo, inst) && \
1025 !(dst_is_packed_dword && src ## n ## _is_packed_word), \
1026 "When the destination spans two registers, the source must " \
1027 "span two registers\n" ERROR_INDENT "(exceptions for scalar " \
1028 "source and packed-word to packed-dword expansion)")
1042 static struct string
1043 vector_immediate_restrictions(const struct gen_device_info
*devinfo
,
1044 const brw_inst
*inst
)
1046 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1047 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1049 if (num_sources
== 3 || num_sources
== 0)
1050 return (struct string
){};
1052 unsigned file
= num_sources
== 1 ?
1053 brw_inst_src0_reg_file(devinfo
, inst
) :
1054 brw_inst_src1_reg_file(devinfo
, inst
);
1055 if (file
!= BRW_IMMEDIATE_VALUE
)
1056 return (struct string
){};
1058 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1059 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
1060 unsigned dst_subreg
= brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
?
1061 brw_inst_dst_da1_subreg_nr(devinfo
, inst
) : 0;
1062 unsigned dst_stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
1063 enum brw_reg_type type
= num_sources
== 1 ?
1064 brw_inst_src0_type(devinfo
, inst
) :
1065 brw_inst_src1_type(devinfo
, inst
);
1069 * When an immediate vector is used in an instruction, the destination
1070 * must be 128-bit aligned with destination horizontal stride equivalent
1071 * to a word for an immediate integer vector (v) and equivalent to a
1072 * DWord for an immediate float vector (vf).
1074 * The text has not been updated for the addition of the immediate unsigned
1075 * integer vector type (uv) on SNB, but presumably the same restriction
1079 case BRW_REGISTER_TYPE_V
:
1080 case BRW_REGISTER_TYPE_UV
:
1081 case BRW_REGISTER_TYPE_VF
:
1082 ERROR_IF(dst_subreg
% (128 / 8) != 0,
1083 "Destination must be 128-bit aligned in order to use immediate "
1086 if (type
== BRW_REGISTER_TYPE_VF
) {
1087 ERROR_IF(dst_type_size
* dst_stride
!= 4,
1088 "Destination must have stride equivalent to dword in order "
1089 "to use the VF type");
1091 ERROR_IF(dst_type_size
* dst_stride
!= 2,
1092 "Destination must have stride equivalent to word in order "
1093 "to use the V or UV type");
1103 static struct string
1104 special_requirements_for_handling_double_precision_data_types(
1105 const struct gen_device_info
*devinfo
,
1106 const brw_inst
*inst
)
1108 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1109 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1111 if (num_sources
== 3 || num_sources
== 0)
1112 return (struct string
){};
1114 enum brw_reg_type exec_type
= execution_type(devinfo
, inst
);
1115 unsigned exec_type_size
= brw_reg_type_to_size(exec_type
);
1117 enum brw_reg_file dst_file
= brw_inst_dst_reg_file(devinfo
, inst
);
1118 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1119 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
1120 unsigned dst_hstride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
1121 unsigned dst_reg
= brw_inst_dst_da_reg_nr(devinfo
, inst
);
1122 unsigned dst_subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
1123 unsigned dst_address_mode
= brw_inst_dst_address_mode(devinfo
, inst
);
1125 bool is_integer_dword_multiply
=
1126 devinfo
->gen
>= 8 &&
1127 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MUL
&&
1128 (brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_D
||
1129 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UD
) &&
1130 (brw_inst_src1_type(devinfo
, inst
) == BRW_REGISTER_TYPE_D
||
1131 brw_inst_src1_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UD
);
1133 if (dst_type_size
!= 8 && exec_type_size
!= 8 && !is_integer_dword_multiply
)
1134 return (struct string
){};
1136 for (unsigned i
= 0; i
< num_sources
; i
++) {
1137 unsigned vstride
, width
, hstride
, type_size
, reg
, subreg
, address_mode
;
1138 bool is_scalar_region
;
1139 enum brw_reg_file file
;
1140 enum brw_reg_type type
;
1143 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
1144 BRW_IMMEDIATE_VALUE) \
1147 is_scalar_region = src ## n ## _has_scalar_region(devinfo, inst); \
1148 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
1149 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
1150 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
1151 file = brw_inst_src ## n ## _reg_file(devinfo, inst); \
1152 type = brw_inst_src ## n ## _type(devinfo, inst); \
1153 type_size = brw_reg_type_to_size(type); \
1154 reg = brw_inst_src ## n ## _da_reg_nr(devinfo, inst); \
1155 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
1156 address_mode = brw_inst_src ## n ## _address_mode(devinfo, inst)
1165 /* The PRMs say that for CHV, BXT:
1167 * When source or destination datatype is 64b or operation is integer
1168 * DWord multiply, regioning in Align1 must follow these rules:
1170 * 1. Source and Destination horizontal stride must be aligned to the
1172 * 2. Regioning must ensure Src.Vstride = Src.Width * Src.Hstride.
1173 * 3. Source and Destination offset must be the same, except the case
1176 * We assume that the restriction applies to GLK as well.
1178 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
1179 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
1180 unsigned src_stride
= hstride
* type_size
;
1181 unsigned dst_stride
= dst_hstride
* dst_type_size
;
1183 ERROR_IF(!is_scalar_region
&&
1184 (src_stride
% 8 != 0 ||
1185 dst_stride
% 8 != 0 ||
1186 src_stride
!= dst_stride
),
1187 "Source and destination horizontal stride must equal and a "
1188 "multiple of a qword when the execution type is 64-bit");
1190 ERROR_IF(vstride
!= width
* hstride
,
1191 "Vstride must be Width * Hstride when the execution type is "
1194 ERROR_IF(!is_scalar_region
&& dst_subreg
!= subreg
,
1195 "Source and destination offset must be the same when the "
1196 "execution type is 64-bit");
1199 /* The PRMs say that for CHV, BXT:
1201 * When source or destination datatype is 64b or operation is integer
1202 * DWord multiply, indirect addressing must not be used.
1204 * We assume that the restriction applies to GLK as well.
1206 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1207 ERROR_IF(BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
== address_mode
||
1208 BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
== dst_address_mode
,
1209 "Indirect addressing is not allowed when the execution type "
1213 /* The PRMs say that for CHV, BXT:
1215 * ARF registers must never be used with 64b datatype or when
1216 * operation is integer DWord multiply.
1218 * We assume that the restriction applies to GLK as well.
1220 * We assume that the restriction does not apply to the null register.
1222 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1223 ERROR_IF(brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MAC
||
1224 brw_inst_acc_wr_control(devinfo
, inst
) ||
1225 (BRW_ARCHITECTURE_REGISTER_FILE
== file
&&
1226 reg
!= BRW_ARF_NULL
) ||
1227 (BRW_ARCHITECTURE_REGISTER_FILE
== dst_file
&&
1228 dst_reg
!= BRW_ARF_NULL
),
1229 "Architecture registers cannot be used when the execution "
1234 /* The PRMs say that for BDW, SKL:
1236 * If Align16 is required for an operation with QW destination and non-QW
1237 * source datatypes, the execution size cannot exceed 2.
1239 * We assume that the restriction applies to all Gen8+ parts.
1241 if (devinfo
->gen
>= 8) {
1242 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
1243 enum brw_reg_type src1_type
=
1244 num_sources
> 1 ? brw_inst_src1_type(devinfo
, inst
) : src0_type
;
1245 unsigned src0_type_size
= brw_reg_type_to_size(src0_type
);
1246 unsigned src1_type_size
= brw_reg_type_to_size(src1_type
);
1248 ERROR_IF(brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
&&
1249 dst_type_size
== 8 &&
1250 (src0_type_size
!= 8 || src1_type_size
!= 8) &&
1251 brw_inst_exec_size(devinfo
, inst
) > BRW_EXECUTE_2
,
1252 "In Align16 exec size cannot exceed 2 with a QWord destination "
1253 "and a non-QWord source");
1256 /* The PRMs say that for CHV, BXT:
1258 * When source or destination datatype is 64b or operation is integer
1259 * DWord multiply, DepCtrl must not be used.
1261 * We assume that the restriction applies to GLK as well.
1263 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1264 ERROR_IF(brw_inst_no_dd_check(devinfo
, inst
) ||
1265 brw_inst_no_dd_clear(devinfo
, inst
),
1266 "DepCtrl is not allowed when the execution type is 64-bit");
1273 brw_validate_instructions(const struct gen_device_info
*devinfo
,
1274 const void *assembly
, int start_offset
, int end_offset
,
1275 struct disasm_info
*disasm
)
1279 for (int src_offset
= start_offset
; src_offset
< end_offset
;) {
1280 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1281 const brw_inst
*inst
= assembly
+ src_offset
;
1282 bool is_compact
= brw_inst_cmpt_control(devinfo
, inst
);
1283 brw_inst uncompacted
;
1286 brw_compact_inst
*compacted
= (void *)inst
;
1287 brw_uncompact_instruction(devinfo
, &uncompacted
, compacted
);
1288 inst
= &uncompacted
;
1291 if (is_unsupported_inst(devinfo
, inst
)) {
1292 ERROR("Instruction not supported on this Gen");
1294 CHECK(sources_not_null
);
1295 CHECK(send_restrictions
);
1296 CHECK(general_restrictions_based_on_operand_types
);
1297 CHECK(general_restrictions_on_region_parameters
);
1298 CHECK(region_alignment_rules
);
1299 CHECK(vector_immediate_restrictions
);
1300 CHECK(special_requirements_for_handling_double_precision_data_types
);
1303 if (error_msg
.str
&& disasm
) {
1304 disasm_insert_error(disasm
, src_offset
, error_msg
.str
);
1306 valid
= valid
&& error_msg
.len
== 0;
1307 free(error_msg
.str
);
1310 src_offset
+= sizeof(brw_compact_inst
);
1312 src_offset
+= sizeof(brw_inst
);