2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_eu_validate.c
26 * This file implements a pass that validates shader assembly.
31 /* We're going to do lots of string concatenation, so this should help. */
38 cat(struct string
*dest
, const struct string src
)
40 dest
->str
= realloc(dest
->str
, dest
->len
+ src
.len
+ 1);
41 memcpy(dest
->str
+ dest
->len
, src
.str
, src
.len
);
42 dest
->str
[dest
->len
+ src
.len
] = '\0';
43 dest
->len
= dest
->len
+ src
.len
;
45 #define CAT(dest, src) cat(&dest, (struct string){src, strlen(src)})
48 contains(const struct string haystack
, const struct string needle
)
50 return haystack
.str
&& memmem(haystack
.str
, haystack
.len
,
51 needle
.str
, needle
.len
) != NULL
;
53 #define CONTAINS(haystack, needle) \
54 contains(haystack, (struct string){needle, strlen(needle)})
56 #define error(str) "\tERROR: " str "\n"
57 #define ERROR_INDENT "\t "
59 #define ERROR(msg) ERROR_IF(true, msg)
60 #define ERROR_IF(cond, msg) \
62 if ((cond) && !CONTAINS(error_msg, error(msg))) { \
63 CAT(error_msg, error(msg)); \
67 #define CHECK(func, args...) \
69 struct string __msg = func(devinfo, inst, ##args); \
71 cat(&error_msg, __msg); \
76 #define STRIDE(stride) (stride != 0 ? 1 << ((stride) - 1) : 0)
77 #define WIDTH(width) (1 << (width))
80 inst_is_send(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
82 switch (brw_inst_opcode(devinfo
, inst
)) {
84 case BRW_OPCODE_SENDC
:
85 case BRW_OPCODE_SENDS
:
86 case BRW_OPCODE_SENDSC
:
94 signed_type(unsigned type
)
97 case BRW_REGISTER_TYPE_UD
: return BRW_REGISTER_TYPE_D
;
98 case BRW_REGISTER_TYPE_UW
: return BRW_REGISTER_TYPE_W
;
99 case BRW_REGISTER_TYPE_UB
: return BRW_REGISTER_TYPE_B
;
100 case BRW_REGISTER_TYPE_UQ
: return BRW_REGISTER_TYPE_Q
;
101 default: return type
;
106 inst_is_raw_move(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
108 unsigned dst_type
= signed_type(brw_inst_dst_type(devinfo
, inst
));
109 unsigned src_type
= signed_type(brw_inst_src0_type(devinfo
, inst
));
111 if (brw_inst_src0_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
) {
112 /* FIXME: not strictly true */
113 if (brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_VF
||
114 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UV
||
115 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_V
) {
118 } else if (brw_inst_src0_negate(devinfo
, inst
) ||
119 brw_inst_src0_abs(devinfo
, inst
)) {
123 return brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MOV
&&
124 brw_inst_saturate(devinfo
, inst
) == 0 &&
125 dst_type
== src_type
;
129 dst_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
131 return brw_inst_dst_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
132 brw_inst_dst_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
136 src0_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
138 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
139 brw_inst_src0_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
143 src1_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
145 return brw_inst_src1_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
146 brw_inst_src1_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
150 src0_is_grf(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
152 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_GENERAL_REGISTER_FILE
;
156 src0_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
158 return brw_inst_src0_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
159 brw_inst_src0_width(devinfo
, inst
) == BRW_WIDTH_1
&&
160 brw_inst_src0_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
164 src1_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
166 return brw_inst_src1_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
167 brw_inst_src1_width(devinfo
, inst
) == BRW_WIDTH_1
&&
168 brw_inst_src1_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
172 num_sources_from_inst(const struct gen_device_info
*devinfo
,
173 const brw_inst
*inst
)
175 const struct opcode_desc
*desc
=
176 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
177 unsigned math_function
;
179 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
180 math_function
= brw_inst_math_function(devinfo
, inst
);
181 } else if (devinfo
->gen
< 6 &&
182 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
183 if (brw_inst_sfid(devinfo
, inst
) == BRW_SFID_MATH
) {
184 /* src1 must be a descriptor (including the information to determine
185 * that the SEND is doing an extended math operation), but src0 can
186 * actually be null since it serves as the source of the implicit GRF
189 * If we stop using that functionality, we'll have to revisit this.
193 /* Send instructions are allowed to have null sources since they use
194 * the base_mrf field to specify which message register source.
199 assert(desc
->nsrc
< 4);
203 switch (math_function
) {
204 case BRW_MATH_FUNCTION_INV
:
205 case BRW_MATH_FUNCTION_LOG
:
206 case BRW_MATH_FUNCTION_EXP
:
207 case BRW_MATH_FUNCTION_SQRT
:
208 case BRW_MATH_FUNCTION_RSQ
:
209 case BRW_MATH_FUNCTION_SIN
:
210 case BRW_MATH_FUNCTION_COS
:
211 case BRW_MATH_FUNCTION_SINCOS
:
212 case GEN8_MATH_FUNCTION_INVM
:
213 case GEN8_MATH_FUNCTION_RSQRTM
:
215 case BRW_MATH_FUNCTION_FDIV
:
216 case BRW_MATH_FUNCTION_POW
:
217 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
:
218 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
:
219 case BRW_MATH_FUNCTION_INT_DIV_REMAINDER
:
222 unreachable("not reached");
227 sources_not_null(const struct gen_device_info
*devinfo
,
228 const brw_inst
*inst
)
230 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
231 struct string error_msg
= { .str
= NULL
, .len
= 0 };
233 /* Nothing to test. 3-src instructions can only have GRF sources, and
234 * there's no bit to control the file.
236 if (num_sources
== 3)
237 return (struct string
){};
239 if (num_sources
>= 1)
240 ERROR_IF(src0_is_null(devinfo
, inst
), "src0 is null");
242 if (num_sources
== 2)
243 ERROR_IF(src1_is_null(devinfo
, inst
), "src1 is null");
249 send_restrictions(const struct gen_device_info
*devinfo
,
250 const brw_inst
*inst
)
252 struct string error_msg
= { .str
= NULL
, .len
= 0 };
254 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
255 ERROR_IF(brw_inst_src0_address_mode(devinfo
, inst
) != BRW_ADDRESS_DIRECT
,
256 "send must use direct addressing");
258 if (devinfo
->gen
>= 7) {
259 ERROR_IF(!src0_is_grf(devinfo
, inst
), "send from non-GRF");
260 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
261 brw_inst_src0_da_reg_nr(devinfo
, inst
) < 112,
262 "send with EOT must use g112-g127");
270 is_unsupported_inst(const struct gen_device_info
*devinfo
,
271 const brw_inst
*inst
)
273 return brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
)) == NULL
;
276 static enum brw_reg_type
277 execution_type_for_type(enum brw_reg_type type
)
280 case BRW_REGISTER_TYPE_NF
:
281 case BRW_REGISTER_TYPE_DF
:
282 case BRW_REGISTER_TYPE_F
:
283 case BRW_REGISTER_TYPE_HF
:
286 case BRW_REGISTER_TYPE_VF
:
287 return BRW_REGISTER_TYPE_F
;
289 case BRW_REGISTER_TYPE_Q
:
290 case BRW_REGISTER_TYPE_UQ
:
291 return BRW_REGISTER_TYPE_Q
;
293 case BRW_REGISTER_TYPE_D
:
294 case BRW_REGISTER_TYPE_UD
:
295 return BRW_REGISTER_TYPE_D
;
297 case BRW_REGISTER_TYPE_W
:
298 case BRW_REGISTER_TYPE_UW
:
299 case BRW_REGISTER_TYPE_B
:
300 case BRW_REGISTER_TYPE_UB
:
301 case BRW_REGISTER_TYPE_V
:
302 case BRW_REGISTER_TYPE_UV
:
303 return BRW_REGISTER_TYPE_W
;
305 unreachable("not reached");
309 * Returns the execution type of an instruction \p inst
311 static enum brw_reg_type
312 execution_type(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
314 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
315 enum brw_reg_type src0_exec_type
, src1_exec_type
;
317 /* Execution data type is independent of destination data type, except in
318 * mixed F/HF instructions on CHV and SKL+.
320 enum brw_reg_type dst_exec_type
= brw_inst_dst_type(devinfo
, inst
);
322 src0_exec_type
= execution_type_for_type(brw_inst_src0_type(devinfo
, inst
));
323 if (num_sources
== 1) {
324 if ((devinfo
->gen
>= 9 || devinfo
->is_cherryview
) &&
325 src0_exec_type
== BRW_REGISTER_TYPE_HF
) {
326 return dst_exec_type
;
328 return src0_exec_type
;
331 src1_exec_type
= execution_type_for_type(brw_inst_src1_type(devinfo
, inst
));
332 if (src0_exec_type
== src1_exec_type
)
333 return src0_exec_type
;
335 /* Mixed operand types where one is float is float on Gen < 6
336 * (and not allowed on later platforms)
338 if (devinfo
->gen
< 6 &&
339 (src0_exec_type
== BRW_REGISTER_TYPE_F
||
340 src1_exec_type
== BRW_REGISTER_TYPE_F
))
341 return BRW_REGISTER_TYPE_F
;
343 if (src0_exec_type
== BRW_REGISTER_TYPE_Q
||
344 src1_exec_type
== BRW_REGISTER_TYPE_Q
)
345 return BRW_REGISTER_TYPE_Q
;
347 if (src0_exec_type
== BRW_REGISTER_TYPE_D
||
348 src1_exec_type
== BRW_REGISTER_TYPE_D
)
349 return BRW_REGISTER_TYPE_D
;
351 if (src0_exec_type
== BRW_REGISTER_TYPE_W
||
352 src1_exec_type
== BRW_REGISTER_TYPE_W
)
353 return BRW_REGISTER_TYPE_W
;
355 if (src0_exec_type
== BRW_REGISTER_TYPE_DF
||
356 src1_exec_type
== BRW_REGISTER_TYPE_DF
)
357 return BRW_REGISTER_TYPE_DF
;
359 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
360 if (dst_exec_type
== BRW_REGISTER_TYPE_F
||
361 src0_exec_type
== BRW_REGISTER_TYPE_F
||
362 src1_exec_type
== BRW_REGISTER_TYPE_F
) {
363 return BRW_REGISTER_TYPE_F
;
365 return BRW_REGISTER_TYPE_HF
;
369 assert(src0_exec_type
== BRW_REGISTER_TYPE_F
);
370 return BRW_REGISTER_TYPE_F
;
374 * Returns whether a region is packed
376 * A region is packed if its elements are adjacent in memory, with no
377 * intervening space, no overlap, and no replicated values.
380 is_packed(unsigned vstride
, unsigned width
, unsigned hstride
)
382 if (vstride
== width
) {
394 * Checks restrictions listed in "General Restrictions Based on Operand Types"
395 * in the "Register Region Restrictions" section.
398 general_restrictions_based_on_operand_types(const struct gen_device_info
*devinfo
,
399 const brw_inst
*inst
)
401 const struct opcode_desc
*desc
=
402 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
403 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
404 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
405 struct string error_msg
= { .str
= NULL
, .len
= 0 };
407 if (num_sources
== 3)
408 return (struct string
){};
410 if (inst_is_send(devinfo
, inst
))
411 return (struct string
){};
414 return (struct string
){};
417 return (struct string
){};
421 * Where n is the largest element size in bytes for any source or
422 * destination operand type, ExecSize * n must be <= 64.
424 * But we do not attempt to enforce it, because it is implied by other
427 * - that the destination stride must match the execution data type
428 * - sources may not span more than two adjacent GRF registers
429 * - destination may not span more than two adjacent GRF registers
431 * In fact, checking it would weaken testing of the other rules.
434 unsigned dst_stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
435 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
436 bool dst_type_is_byte
=
437 brw_inst_dst_type(devinfo
, inst
) == BRW_REGISTER_TYPE_B
||
438 brw_inst_dst_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UB
;
440 if (dst_type_is_byte
) {
441 if (is_packed(exec_size
* dst_stride
, exec_size
, dst_stride
)) {
442 if (!inst_is_raw_move(devinfo
, inst
)) {
443 ERROR("Only raw MOV supports a packed-byte destination");
446 return (struct string
){};
451 unsigned exec_type
= execution_type(devinfo
, inst
);
452 unsigned exec_type_size
= brw_reg_type_to_size(exec_type
);
453 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
455 /* On IVB/BYT, region parameters and execution size for DF are in terms of
456 * 32-bit elements, so they are doubled. For evaluating the validity of an
457 * instruction, we halve them.
459 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
460 exec_type_size
== 8 && dst_type_size
== 4)
463 if (exec_type_size
> dst_type_size
) {
464 ERROR_IF(dst_stride
* dst_type_size
!= exec_type_size
,
465 "Destination stride must be equal to the ratio of the sizes of "
466 "the execution data type to the destination type");
468 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
470 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
471 brw_inst_dst_address_mode(devinfo
, inst
) == BRW_ADDRESS_DIRECT
) {
472 /* The i965 PRM says:
474 * Implementation Restriction: The relaxed alignment rule for byte
475 * destination (#10.5) is not supported.
477 if ((devinfo
->gen
> 4 || devinfo
->is_g4x
) && dst_type_is_byte
) {
478 ERROR_IF(subreg
% exec_type_size
!= 0 &&
479 subreg
% exec_type_size
!= 1,
480 "Destination subreg must be aligned to the size of the "
481 "execution data type (or to the next lowest byte for byte "
484 ERROR_IF(subreg
% exec_type_size
!= 0,
485 "Destination subreg must be aligned to the size of the "
486 "execution data type");
495 * Checks restrictions listed in "General Restrictions on Regioning Parameters"
496 * in the "Register Region Restrictions" section.
499 general_restrictions_on_region_parameters(const struct gen_device_info
*devinfo
,
500 const brw_inst
*inst
)
502 const struct opcode_desc
*desc
=
503 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
504 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
505 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
506 struct string error_msg
= { .str
= NULL
, .len
= 0 };
508 if (num_sources
== 3)
509 return (struct string
){};
511 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
) {
512 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
))
513 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) != BRW_HORIZONTAL_STRIDE_1
,
514 "Destination Horizontal Stride must be 1");
516 if (num_sources
>= 1) {
517 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
518 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
519 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
520 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
521 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
522 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
524 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
525 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
526 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
527 "In Align16 mode, only VertStride of 0 or 4 is allowed");
531 if (num_sources
== 2) {
532 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
533 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
534 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
535 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
536 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
537 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
539 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
540 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
541 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
542 "In Align16 mode, only VertStride of 0 or 4 is allowed");
549 for (unsigned i
= 0; i
< num_sources
; i
++) {
550 unsigned vstride
, width
, hstride
, element_size
, subreg
;
551 enum brw_reg_type type
;
554 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
555 BRW_IMMEDIATE_VALUE) \
558 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
559 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
560 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
561 type = brw_inst_src ## n ## _type(devinfo, inst); \
562 element_size = brw_reg_type_to_size(type); \
563 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst)
572 /* On IVB/BYT, region parameters and execution size for DF are in terms of
573 * 32-bit elements, so they are doubled. For evaluating the validity of an
574 * instruction, we halve them.
576 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
580 /* ExecSize must be greater than or equal to Width. */
581 ERROR_IF(exec_size
< width
, "ExecSize must be greater than or equal "
584 /* If ExecSize = Width and HorzStride ≠ 0,
585 * VertStride must be set to Width * HorzStride.
587 if (exec_size
== width
&& hstride
!= 0) {
588 ERROR_IF(vstride
!= width
* hstride
,
589 "If ExecSize = Width and HorzStride ≠ 0, "
590 "VertStride must be set to Width * HorzStride");
593 /* If Width = 1, HorzStride must be 0 regardless of the values of
594 * ExecSize and VertStride.
597 ERROR_IF(hstride
!= 0,
598 "If Width = 1, HorzStride must be 0 regardless "
599 "of the values of ExecSize and VertStride");
602 /* If ExecSize = Width = 1, both VertStride and HorzStride must be 0. */
603 if (exec_size
== 1 && width
== 1) {
604 ERROR_IF(vstride
!= 0 || hstride
!= 0,
605 "If ExecSize = Width = 1, both VertStride "
606 "and HorzStride must be 0");
609 /* If VertStride = HorzStride = 0, Width must be 1 regardless of the
612 if (vstride
== 0 && hstride
== 0) {
614 "If VertStride = HorzStride = 0, Width must be "
615 "1 regardless of the value of ExecSize");
618 /* VertStride must be used to cross GRF register boundaries. This rule
619 * implies that elements within a 'Width' cannot cross GRF boundaries.
621 const uint64_t mask
= (1ULL << element_size
) - 1;
622 unsigned rowbase
= subreg
;
624 for (int y
= 0; y
< exec_size
/ width
; y
++) {
625 uint64_t access_mask
= 0;
626 unsigned offset
= rowbase
;
628 for (int x
= 0; x
< width
; x
++) {
629 access_mask
|= mask
<< offset
;
630 offset
+= hstride
* element_size
;
633 rowbase
+= vstride
* element_size
;
635 if ((uint32_t)access_mask
!= 0 && (access_mask
>> 32) != 0) {
636 ERROR("VertStride must be used to cross GRF register boundaries");
642 /* Dst.HorzStride must not be 0. */
643 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
)) {
644 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
,
645 "Destination Horizontal Stride must not be 0");
652 * Creates an \p access_mask for an \p exec_size, \p element_size, and a region
654 * An \p access_mask is a 32-element array of uint64_t, where each uint64_t is
655 * a bitmask of bytes accessed by the region.
657 * For instance the access mask of the source gX.1<4,2,2>F in an exec_size = 4
658 * instruction would be
660 * access_mask[0] = 0x00000000000000F0
661 * access_mask[1] = 0x000000000000F000
662 * access_mask[2] = 0x0000000000F00000
663 * access_mask[3] = 0x00000000F0000000
664 * access_mask[4-31] = 0
666 * because the first execution channel accesses bytes 7-4 and the second
667 * execution channel accesses bytes 15-12, etc.
670 align1_access_mask(uint64_t access_mask
[static 32],
671 unsigned exec_size
, unsigned element_size
, unsigned subreg
,
672 unsigned vstride
, unsigned width
, unsigned hstride
)
674 const uint64_t mask
= (1ULL << element_size
) - 1;
675 unsigned rowbase
= subreg
;
676 unsigned element
= 0;
678 for (int y
= 0; y
< exec_size
/ width
; y
++) {
679 unsigned offset
= rowbase
;
681 for (int x
= 0; x
< width
; x
++) {
682 access_mask
[element
++] = mask
<< offset
;
683 offset
+= hstride
* element_size
;
686 rowbase
+= vstride
* element_size
;
689 assert(element
== 0 || element
== exec_size
);
693 * Returns the number of registers accessed according to the \p access_mask
696 registers_read(const uint64_t access_mask
[static 32])
700 for (unsigned i
= 0; i
< 32; i
++) {
701 if (access_mask
[i
] > 0xFFFFFFFF) {
703 } else if (access_mask
[i
]) {
712 * Checks restrictions listed in "Region Alignment Rules" in the "Register
713 * Region Restrictions" section.
716 region_alignment_rules(const struct gen_device_info
*devinfo
,
717 const brw_inst
*inst
)
719 const struct opcode_desc
*desc
=
720 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
721 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
722 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
723 uint64_t dst_access_mask
[32], src0_access_mask
[32], src1_access_mask
[32];
724 struct string error_msg
= { .str
= NULL
, .len
= 0 };
726 if (num_sources
== 3)
727 return (struct string
){};
729 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
)
730 return (struct string
){};
732 if (inst_is_send(devinfo
, inst
))
733 return (struct string
){};
735 memset(dst_access_mask
, 0, sizeof(dst_access_mask
));
736 memset(src0_access_mask
, 0, sizeof(src0_access_mask
));
737 memset(src1_access_mask
, 0, sizeof(src1_access_mask
));
739 for (unsigned i
= 0; i
< num_sources
; i
++) {
740 unsigned vstride
, width
, hstride
, element_size
, subreg
;
741 enum brw_reg_type type
;
743 /* In Direct Addressing mode, a source cannot span more than 2 adjacent
748 if (brw_inst_src ## n ## _address_mode(devinfo, inst) != \
749 BRW_ADDRESS_DIRECT) \
752 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
753 BRW_IMMEDIATE_VALUE) \
756 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
757 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
758 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
759 type = brw_inst_src ## n ## _type(devinfo, inst); \
760 element_size = brw_reg_type_to_size(type); \
761 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
762 align1_access_mask(src ## n ## _access_mask, \
763 exec_size, element_size, subreg, \
764 vstride, width, hstride)
773 unsigned num_vstride
= exec_size
/ width
;
774 unsigned num_hstride
= width
;
775 unsigned vstride_elements
= (num_vstride
- 1) * vstride
;
776 unsigned hstride_elements
= (num_hstride
- 1) * hstride
;
777 unsigned offset
= (vstride_elements
+ hstride_elements
) * element_size
+
779 ERROR_IF(offset
>= 64,
780 "A source cannot span more than 2 adjacent GRF registers");
783 if (desc
->ndst
== 0 || dst_is_null(devinfo
, inst
))
786 unsigned stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
787 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
788 unsigned element_size
= brw_reg_type_to_size(dst_type
);
789 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
790 unsigned offset
= ((exec_size
- 1) * stride
* element_size
) + subreg
;
791 ERROR_IF(offset
>= 64,
792 "A destination cannot span more than 2 adjacent GRF registers");
797 /* On IVB/BYT, region parameters and execution size for DF are in terms of
798 * 32-bit elements, so they are doubled. For evaluating the validity of an
799 * instruction, we halve them.
801 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
805 align1_access_mask(dst_access_mask
, exec_size
, element_size
, subreg
,
806 exec_size
== 1 ? 0 : exec_size
* stride
,
807 exec_size
== 1 ? 1 : exec_size
,
808 exec_size
== 1 ? 0 : stride
);
810 unsigned dst_regs
= registers_read(dst_access_mask
);
811 unsigned src0_regs
= registers_read(src0_access_mask
);
812 unsigned src1_regs
= registers_read(src1_access_mask
);
814 /* The SNB, IVB, HSW, BDW, and CHV PRMs say:
816 * When an instruction has a source region spanning two registers and a
817 * destination region contained in one register, the number of elements
818 * must be the same between two sources and one of the following must be
821 * 1. The destination region is entirely contained in the lower OWord
823 * 2. The destination region is entirely contained in the upper OWord
825 * 3. The destination elements are evenly split between the two OWords
828 if (devinfo
->gen
<= 8) {
829 if (dst_regs
== 1 && (src0_regs
== 2 || src1_regs
== 2)) {
830 unsigned upper_oword_writes
= 0, lower_oword_writes
= 0;
832 for (unsigned i
= 0; i
< exec_size
; i
++) {
833 if (dst_access_mask
[i
] > 0x0000FFFF) {
834 upper_oword_writes
++;
836 assert(dst_access_mask
[i
] != 0);
837 lower_oword_writes
++;
841 ERROR_IF(lower_oword_writes
!= 0 &&
842 upper_oword_writes
!= 0 &&
843 upper_oword_writes
!= lower_oword_writes
,
844 "Writes must be to only one OWord or "
845 "evenly split between OWords");
849 /* The IVB and HSW PRMs say:
851 * When an instruction has a source region that spans two registers and
852 * the destination spans two registers, the destination elements must be
853 * evenly split between the two registers [...]
855 * The SNB PRM contains similar wording (but written in a much more
860 * When destination spans two registers, the source may be one or two
861 * registers. The destination elements must be evenly split between the
866 * When destination of MATH instruction spans two registers, the
867 * destination elements must be evenly split between the two registers.
869 * It is not known whether this restriction applies to KBL other Gens after
872 if (devinfo
->gen
<= 8 ||
873 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
875 /* Nothing explicitly states that on Gen < 8 elements must be evenly
876 * split between two destination registers in the two exceptional
877 * source-region-spans-one-register cases, but since Broadwell requires
878 * evenly split writes regardless of source region, we assume that it was
879 * an oversight and require it.
882 unsigned upper_reg_writes
= 0, lower_reg_writes
= 0;
884 for (unsigned i
= 0; i
< exec_size
; i
++) {
885 if (dst_access_mask
[i
] > 0xFFFFFFFF) {
888 assert(dst_access_mask
[i
] != 0);
893 ERROR_IF(upper_reg_writes
!= lower_reg_writes
,
894 "Writes must be evenly split between the two "
895 "destination registers");
899 /* The IVB and HSW PRMs say:
901 * When an instruction has a source region that spans two registers and
902 * the destination spans two registers, the destination elements must be
903 * evenly split between the two registers and each destination register
904 * must be entirely derived from one source register.
906 * Note: In such cases, the regioning parameters must ensure that the
907 * offset from the two source registers is the same.
909 * The SNB PRM contains similar wording (but written in a much more
912 * There are effectively three rules stated here:
914 * For an instruction with a source and a destination spanning two
917 * (1) destination elements must be evenly split between the two
919 * (2) all destination elements in a register must be derived
920 * from one source register
921 * (3) the offset (i.e. the starting location in each of the two
922 * registers spanned by a region) must be the same in the two
923 * registers spanned by a region
925 * It is impossible to violate rule (1) without violating (2) or (3), so we
926 * do not attempt to validate it.
928 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
929 for (unsigned i
= 0; i
< num_sources
; i
++) {
931 if (src ## n ## _regs <= 1) \
934 for (unsigned i = 0; i < exec_size; i++) { \
935 if ((dst_access_mask[i] > 0xFFFFFFFF) != \
936 (src ## n ## _access_mask[i] > 0xFFFFFFFF)) { \
937 ERROR("Each destination register must be entirely derived " \
938 "from one source register"); \
943 unsigned offset_0 = \
944 brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
945 unsigned offset_1 = offset_0; \
947 for (unsigned i = 0; i < exec_size; i++) { \
948 if (src ## n ## _access_mask[i] > 0xFFFFFFFF) { \
949 offset_1 = __builtin_ctzll(src ## n ## _access_mask[i]) - 32; \
954 ERROR_IF(num_sources == 2 && offset_0 != offset_1, \
955 "The offset from the two source registers " \
967 /* The IVB and HSW PRMs say:
969 * When destination spans two registers, the source MUST span two
970 * registers. The exception to the above rule:
971 * 1. When source is scalar, the source registers are not
973 * 2. When source is packed integer Word and destination is packed
974 * integer DWord, the source register is not incremented by the
975 * source sub register is incremented.
977 * The SNB PRM does not contain this rule, but the internal documentation
978 * indicates that it applies to SNB as well. We assume that the rule applies
979 * to Gen <= 5 although their PRMs do not state it.
981 * While the documentation explicitly says in exception (2) that the
982 * destination must be an integer DWord, the hardware allows at least a
983 * float destination type as well. We emit such instructions from
985 * fs_visitor::emit_interpolation_setup_gen6
986 * fs_visitor::emit_fragcoord_interpolation
988 * and have for years with no ill effects.
990 * Additionally the simulator source code indicates that the real condition
991 * is that the size of the destination type is 4 bytes.
993 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
994 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
995 bool dst_is_packed_dword
=
996 is_packed(exec_size
* stride
, exec_size
, stride
) &&
997 brw_reg_type_to_size(dst_type
) == 4;
999 for (unsigned i
= 0; i
< num_sources
; i
++) {
1001 unsigned vstride, width, hstride; \
1002 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
1003 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
1004 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
1005 bool src ## n ## _is_packed_word = \
1006 is_packed(vstride, width, hstride) && \
1007 (brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_W || \
1008 brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_UW); \
1010 ERROR_IF(src ## n ## _regs == 1 && \
1011 !src ## n ## _has_scalar_region(devinfo, inst) && \
1012 !(dst_is_packed_dword && src ## n ## _is_packed_word), \
1013 "When the destination spans two registers, the source must " \
1014 "span two registers\n" ERROR_INDENT "(exceptions for scalar " \
1015 "source and packed-word to packed-dword expansion)")
1029 static struct string
1030 vector_immediate_restrictions(const struct gen_device_info
*devinfo
,
1031 const brw_inst
*inst
)
1033 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1034 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1036 if (num_sources
== 3 || num_sources
== 0)
1037 return (struct string
){};
1039 unsigned file
= num_sources
== 1 ?
1040 brw_inst_src0_reg_file(devinfo
, inst
) :
1041 brw_inst_src1_reg_file(devinfo
, inst
);
1042 if (file
!= BRW_IMMEDIATE_VALUE
)
1043 return (struct string
){};
1045 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1046 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
1047 unsigned dst_subreg
= brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
?
1048 brw_inst_dst_da1_subreg_nr(devinfo
, inst
) : 0;
1049 unsigned dst_stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
1050 enum brw_reg_type type
= num_sources
== 1 ?
1051 brw_inst_src0_type(devinfo
, inst
) :
1052 brw_inst_src1_type(devinfo
, inst
);
1056 * When an immediate vector is used in an instruction, the destination
1057 * must be 128-bit aligned with destination horizontal stride equivalent
1058 * to a word for an immediate integer vector (v) and equivalent to a
1059 * DWord for an immediate float vector (vf).
1061 * The text has not been updated for the addition of the immediate unsigned
1062 * integer vector type (uv) on SNB, but presumably the same restriction
1066 case BRW_REGISTER_TYPE_V
:
1067 case BRW_REGISTER_TYPE_UV
:
1068 case BRW_REGISTER_TYPE_VF
:
1069 ERROR_IF(dst_subreg
% (128 / 8) != 0,
1070 "Destination must be 128-bit aligned in order to use immediate "
1073 if (type
== BRW_REGISTER_TYPE_VF
) {
1074 ERROR_IF(dst_type_size
* dst_stride
!= 4,
1075 "Destination must have stride equivalent to dword in order "
1076 "to use the VF type");
1078 ERROR_IF(dst_type_size
* dst_stride
!= 2,
1079 "Destination must have stride equivalent to word in order "
1080 "to use the V or UV type");
1090 static struct string
1091 special_requirements_for_handling_double_precision_data_types(
1092 const struct gen_device_info
*devinfo
,
1093 const brw_inst
*inst
)
1095 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1096 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1098 if (num_sources
== 3 || num_sources
== 0)
1099 return (struct string
){};
1101 enum brw_reg_type exec_type
= execution_type(devinfo
, inst
);
1102 unsigned exec_type_size
= brw_reg_type_to_size(exec_type
);
1104 enum brw_reg_file dst_file
= brw_inst_dst_reg_file(devinfo
, inst
);
1105 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1106 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
1107 unsigned dst_hstride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
1108 unsigned dst_reg
= brw_inst_dst_da_reg_nr(devinfo
, inst
);
1109 unsigned dst_subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
1110 unsigned dst_address_mode
= brw_inst_dst_address_mode(devinfo
, inst
);
1112 bool is_integer_dword_multiply
=
1113 devinfo
->gen
>= 8 &&
1114 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MUL
&&
1115 (brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_D
||
1116 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UD
) &&
1117 (brw_inst_src1_type(devinfo
, inst
) == BRW_REGISTER_TYPE_D
||
1118 brw_inst_src1_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UD
);
1120 if (dst_type_size
!= 8 && exec_type_size
!= 8 && !is_integer_dword_multiply
)
1121 return (struct string
){};
1123 for (unsigned i
= 0; i
< num_sources
; i
++) {
1124 unsigned vstride
, width
, hstride
, type_size
, reg
, subreg
, address_mode
;
1125 bool is_scalar_region
;
1126 enum brw_reg_file file
;
1127 enum brw_reg_type type
;
1130 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
1131 BRW_IMMEDIATE_VALUE) \
1134 is_scalar_region = src ## n ## _has_scalar_region(devinfo, inst); \
1135 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
1136 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
1137 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
1138 file = brw_inst_src ## n ## _reg_file(devinfo, inst); \
1139 type = brw_inst_src ## n ## _type(devinfo, inst); \
1140 type_size = brw_reg_type_to_size(type); \
1141 reg = brw_inst_src ## n ## _da_reg_nr(devinfo, inst); \
1142 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
1143 address_mode = brw_inst_src ## n ## _address_mode(devinfo, inst)
1152 /* The PRMs say that for CHV, BXT:
1154 * When source or destination datatype is 64b or operation is integer
1155 * DWord multiply, regioning in Align1 must follow these rules:
1157 * 1. Source and Destination horizontal stride must be aligned to the
1159 * 2. Regioning must ensure Src.Vstride = Src.Width * Src.Hstride.
1160 * 3. Source and Destination offset must be the same, except the case
1163 * We assume that the restriction applies to GLK as well.
1165 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
1166 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
1167 unsigned src_stride
= hstride
* type_size
;
1168 unsigned dst_stride
= dst_hstride
* dst_type_size
;
1170 ERROR_IF(!is_scalar_region
&&
1171 (src_stride
% 8 != 0 ||
1172 dst_stride
% 8 != 0 ||
1173 src_stride
!= dst_stride
),
1174 "Source and destination horizontal stride must equal and a "
1175 "multiple of a qword when the execution type is 64-bit");
1177 ERROR_IF(vstride
!= width
* hstride
,
1178 "Vstride must be Width * Hstride when the execution type is "
1181 ERROR_IF(!is_scalar_region
&& dst_subreg
!= subreg
,
1182 "Source and destination offset must be the same when the "
1183 "execution type is 64-bit");
1186 /* The PRMs say that for CHV, BXT:
1188 * When source or destination datatype is 64b or operation is integer
1189 * DWord multiply, indirect addressing must not be used.
1191 * We assume that the restriction applies to GLK as well.
1193 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1194 ERROR_IF(BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
== address_mode
||
1195 BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
== dst_address_mode
,
1196 "Indirect addressing is not allowed when the execution type "
1200 /* The PRMs say that for CHV, BXT:
1202 * ARF registers must never be used with 64b datatype or when
1203 * operation is integer DWord multiply.
1205 * We assume that the restriction applies to GLK as well.
1207 * We assume that the restriction does not apply to the null register.
1209 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1210 ERROR_IF(brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MAC
||
1211 brw_inst_acc_wr_control(devinfo
, inst
) ||
1212 (BRW_ARCHITECTURE_REGISTER_FILE
== file
&&
1213 reg
!= BRW_ARF_NULL
) ||
1214 (BRW_ARCHITECTURE_REGISTER_FILE
== dst_file
&&
1215 dst_reg
!= BRW_ARF_NULL
),
1216 "Architecture registers cannot be used when the execution "
1221 /* The PRMs say that for BDW, SKL:
1223 * If Align16 is required for an operation with QW destination and non-QW
1224 * source datatypes, the execution size cannot exceed 2.
1226 * We assume that the restriction applies to all Gen8+ parts.
1228 if (devinfo
->gen
>= 8) {
1229 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
1230 enum brw_reg_type src1_type
=
1231 num_sources
> 1 ? brw_inst_src1_type(devinfo
, inst
) : src0_type
;
1232 unsigned src0_type_size
= brw_reg_type_to_size(src0_type
);
1233 unsigned src1_type_size
= brw_reg_type_to_size(src1_type
);
1235 ERROR_IF(brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
&&
1236 dst_type_size
== 8 &&
1237 (src0_type_size
!= 8 || src1_type_size
!= 8) &&
1238 brw_inst_exec_size(devinfo
, inst
) > BRW_EXECUTE_2
,
1239 "In Align16 exec size cannot exceed 2 with a QWord destination "
1240 "and a non-QWord source");
1243 /* The PRMs say that for CHV, BXT:
1245 * When source or destination datatype is 64b or operation is integer
1246 * DWord multiply, DepCtrl must not be used.
1248 * We assume that the restriction applies to GLK as well.
1250 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1251 ERROR_IF(brw_inst_no_dd_check(devinfo
, inst
) ||
1252 brw_inst_no_dd_clear(devinfo
, inst
),
1253 "DepCtrl is not allowed when the execution type is 64-bit");
1260 brw_validate_instructions(const struct gen_device_info
*devinfo
,
1261 const void *assembly
, int start_offset
, int end_offset
,
1262 struct disasm_info
*disasm
)
1266 for (int src_offset
= start_offset
; src_offset
< end_offset
;) {
1267 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1268 const brw_inst
*inst
= assembly
+ src_offset
;
1269 bool is_compact
= brw_inst_cmpt_control(devinfo
, inst
);
1270 brw_inst uncompacted
;
1273 brw_compact_inst
*compacted
= (void *)inst
;
1274 brw_uncompact_instruction(devinfo
, &uncompacted
, compacted
);
1275 inst
= &uncompacted
;
1278 if (is_unsupported_inst(devinfo
, inst
)) {
1279 ERROR("Instruction not supported on this Gen");
1281 CHECK(sources_not_null
);
1282 CHECK(send_restrictions
);
1283 CHECK(general_restrictions_based_on_operand_types
);
1284 CHECK(general_restrictions_on_region_parameters
);
1285 CHECK(region_alignment_rules
);
1286 CHECK(vector_immediate_restrictions
);
1287 CHECK(special_requirements_for_handling_double_precision_data_types
);
1290 if (error_msg
.str
&& disasm
) {
1291 disasm_insert_error(disasm
, src_offset
, error_msg
.str
);
1293 valid
= valid
&& error_msg
.len
== 0;
1294 free(error_msg
.str
);
1297 src_offset
+= sizeof(brw_compact_inst
);
1299 src_offset
+= sizeof(brw_inst
);