2 * Copyright © 2015-2019 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_eu_validate.c
26 * This file implements a pass that validates shader assembly.
28 * The restrictions implemented herein are intended to verify that instructions
29 * in shader assembly do not violate restrictions documented in the graphics
30 * programming reference manuals.
32 * The restrictions are difficult for humans to quickly verify due to their
33 * complexity and abundance.
35 * It is critical that this code is thoroughly unit tested because false
36 * results will lead developers astray, which is worse than having no validator
37 * at all. Functional changes to this file without corresponding unit tests (in
38 * test_eu_validate.cpp) will be rejected.
43 /* We're going to do lots of string concatenation, so this should help. */
50 cat(struct string
*dest
, const struct string src
)
52 dest
->str
= realloc(dest
->str
, dest
->len
+ src
.len
+ 1);
53 memcpy(dest
->str
+ dest
->len
, src
.str
, src
.len
);
54 dest
->str
[dest
->len
+ src
.len
] = '\0';
55 dest
->len
= dest
->len
+ src
.len
;
57 #define CAT(dest, src) cat(&dest, (struct string){src, strlen(src)})
60 contains(const struct string haystack
, const struct string needle
)
62 return haystack
.str
&& memmem(haystack
.str
, haystack
.len
,
63 needle
.str
, needle
.len
) != NULL
;
65 #define CONTAINS(haystack, needle) \
66 contains(haystack, (struct string){needle, strlen(needle)})
68 #define error(str) "\tERROR: " str "\n"
69 #define ERROR_INDENT "\t "
71 #define ERROR(msg) ERROR_IF(true, msg)
72 #define ERROR_IF(cond, msg) \
74 if ((cond) && !CONTAINS(error_msg, error(msg))) { \
75 CAT(error_msg, error(msg)); \
79 #define CHECK(func, args...) \
81 struct string __msg = func(devinfo, inst, ##args); \
83 cat(&error_msg, __msg); \
88 #define STRIDE(stride) (stride != 0 ? 1 << ((stride) - 1) : 0)
89 #define WIDTH(width) (1 << (width))
92 inst_is_send(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
94 switch (brw_inst_opcode(devinfo
, inst
)) {
96 case BRW_OPCODE_SENDC
:
97 case BRW_OPCODE_SENDS
:
98 case BRW_OPCODE_SENDSC
:
106 inst_is_split_send(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
108 switch (brw_inst_opcode(devinfo
, inst
)) {
109 case BRW_OPCODE_SENDS
:
110 case BRW_OPCODE_SENDSC
:
118 signed_type(unsigned type
)
121 case BRW_REGISTER_TYPE_UD
: return BRW_REGISTER_TYPE_D
;
122 case BRW_REGISTER_TYPE_UW
: return BRW_REGISTER_TYPE_W
;
123 case BRW_REGISTER_TYPE_UB
: return BRW_REGISTER_TYPE_B
;
124 case BRW_REGISTER_TYPE_UQ
: return BRW_REGISTER_TYPE_Q
;
125 default: return type
;
130 inst_is_raw_move(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
132 unsigned dst_type
= signed_type(brw_inst_dst_type(devinfo
, inst
));
133 unsigned src_type
= signed_type(brw_inst_src0_type(devinfo
, inst
));
135 if (brw_inst_src0_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
) {
136 /* FIXME: not strictly true */
137 if (brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_VF
||
138 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UV
||
139 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_V
) {
142 } else if (brw_inst_src0_negate(devinfo
, inst
) ||
143 brw_inst_src0_abs(devinfo
, inst
)) {
147 return brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MOV
&&
148 brw_inst_saturate(devinfo
, inst
) == 0 &&
149 dst_type
== src_type
;
153 dst_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
155 return brw_inst_dst_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
156 brw_inst_dst_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
160 src0_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
162 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
163 brw_inst_src0_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
167 src1_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
169 return brw_inst_src1_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
170 brw_inst_src1_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
174 src0_is_grf(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
176 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_GENERAL_REGISTER_FILE
;
180 src0_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
182 return brw_inst_src0_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
183 brw_inst_src0_width(devinfo
, inst
) == BRW_WIDTH_1
&&
184 brw_inst_src0_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
188 src1_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
190 return brw_inst_src1_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
191 brw_inst_src1_width(devinfo
, inst
) == BRW_WIDTH_1
&&
192 brw_inst_src1_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
196 num_sources_from_inst(const struct gen_device_info
*devinfo
,
197 const brw_inst
*inst
)
199 const struct opcode_desc
*desc
=
200 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
201 unsigned math_function
;
203 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
204 math_function
= brw_inst_math_function(devinfo
, inst
);
205 } else if (devinfo
->gen
< 6 &&
206 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
207 if (brw_inst_sfid(devinfo
, inst
) == BRW_SFID_MATH
) {
208 /* src1 must be a descriptor (including the information to determine
209 * that the SEND is doing an extended math operation), but src0 can
210 * actually be null since it serves as the source of the implicit GRF
213 * If we stop using that functionality, we'll have to revisit this.
217 /* Send instructions are allowed to have null sources since they use
218 * the base_mrf field to specify which message register source.
223 assert(desc
->nsrc
< 4);
227 switch (math_function
) {
228 case BRW_MATH_FUNCTION_INV
:
229 case BRW_MATH_FUNCTION_LOG
:
230 case BRW_MATH_FUNCTION_EXP
:
231 case BRW_MATH_FUNCTION_SQRT
:
232 case BRW_MATH_FUNCTION_RSQ
:
233 case BRW_MATH_FUNCTION_SIN
:
234 case BRW_MATH_FUNCTION_COS
:
235 case BRW_MATH_FUNCTION_SINCOS
:
236 case GEN8_MATH_FUNCTION_INVM
:
237 case GEN8_MATH_FUNCTION_RSQRTM
:
239 case BRW_MATH_FUNCTION_FDIV
:
240 case BRW_MATH_FUNCTION_POW
:
241 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
:
242 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
:
243 case BRW_MATH_FUNCTION_INT_DIV_REMAINDER
:
246 unreachable("not reached");
251 sources_not_null(const struct gen_device_info
*devinfo
,
252 const brw_inst
*inst
)
254 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
255 struct string error_msg
= { .str
= NULL
, .len
= 0 };
257 /* Nothing to test. 3-src instructions can only have GRF sources, and
258 * there's no bit to control the file.
260 if (num_sources
== 3)
261 return (struct string
){};
263 /* Nothing to test. Split sends can only encode a file in sources that are
264 * allowed to be NULL.
266 if (inst_is_split_send(devinfo
, inst
))
267 return (struct string
){};
269 if (num_sources
>= 1)
270 ERROR_IF(src0_is_null(devinfo
, inst
), "src0 is null");
272 if (num_sources
== 2)
273 ERROR_IF(src1_is_null(devinfo
, inst
), "src1 is null");
279 send_restrictions(const struct gen_device_info
*devinfo
,
280 const brw_inst
*inst
)
282 struct string error_msg
= { .str
= NULL
, .len
= 0 };
284 if (inst_is_split_send(devinfo
, inst
)) {
285 ERROR_IF(brw_inst_send_src1_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
286 brw_inst_send_src1_reg_nr(devinfo
, inst
) != BRW_ARF_NULL
,
287 "src1 of split send must be a GRF or NULL");
289 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
290 brw_inst_src0_da_reg_nr(devinfo
, inst
) < 112,
291 "send with EOT must use g112-g127");
292 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
293 brw_inst_send_src1_reg_file(devinfo
, inst
) == BRW_GENERAL_REGISTER_FILE
&&
294 brw_inst_send_src1_reg_nr(devinfo
, inst
) < 112,
295 "send with EOT must use g112-g127");
297 if (brw_inst_send_src1_reg_file(devinfo
, inst
) == BRW_GENERAL_REGISTER_FILE
) {
298 /* Assume minimums if we don't know */
300 if (!brw_inst_send_sel_reg32_desc(devinfo
, inst
)) {
301 const uint32_t desc
= brw_inst_send_desc(devinfo
, inst
);
302 mlen
= brw_message_desc_mlen(devinfo
, desc
);
305 unsigned ex_mlen
= 1;
306 if (!brw_inst_send_sel_reg32_ex_desc(devinfo
, inst
)) {
307 const uint32_t ex_desc
= brw_inst_send_ex_desc(devinfo
, inst
);
308 ex_mlen
= brw_message_ex_desc_ex_mlen(devinfo
, ex_desc
);
310 const unsigned src0_reg_nr
= brw_inst_src0_da_reg_nr(devinfo
, inst
);
311 const unsigned src1_reg_nr
= brw_inst_send_src1_reg_nr(devinfo
, inst
);
312 ERROR_IF((src0_reg_nr
<= src1_reg_nr
&&
313 src1_reg_nr
< src0_reg_nr
+ mlen
) ||
314 (src1_reg_nr
<= src0_reg_nr
&&
315 src0_reg_nr
< src1_reg_nr
+ ex_mlen
),
316 "split send payloads must not overlap");
318 } else if (inst_is_send(devinfo
, inst
)) {
319 ERROR_IF(brw_inst_src0_address_mode(devinfo
, inst
) != BRW_ADDRESS_DIRECT
,
320 "send must use direct addressing");
322 if (devinfo
->gen
>= 7) {
323 ERROR_IF(!src0_is_grf(devinfo
, inst
), "send from non-GRF");
324 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
325 brw_inst_src0_da_reg_nr(devinfo
, inst
) < 112,
326 "send with EOT must use g112-g127");
329 if (devinfo
->gen
>= 8) {
330 ERROR_IF(!dst_is_null(devinfo
, inst
) &&
331 (brw_inst_dst_da_reg_nr(devinfo
, inst
) +
332 brw_inst_rlen(devinfo
, inst
) > 127) &&
333 (brw_inst_src0_da_reg_nr(devinfo
, inst
) +
334 brw_inst_mlen(devinfo
, inst
) >
335 brw_inst_dst_da_reg_nr(devinfo
, inst
)),
336 "r127 must not be used for return address when there is "
337 "a src and dest overlap");
345 is_unsupported_inst(const struct gen_device_info
*devinfo
,
346 const brw_inst
*inst
)
348 return brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
)) == NULL
;
352 * Returns whether a combination of two types would qualify as mixed float
356 types_are_mixed_float(enum brw_reg_type t0
, enum brw_reg_type t1
)
358 return (t0
== BRW_REGISTER_TYPE_F
&& t1
== BRW_REGISTER_TYPE_HF
) ||
359 (t1
== BRW_REGISTER_TYPE_F
&& t0
== BRW_REGISTER_TYPE_HF
);
362 static enum brw_reg_type
363 execution_type_for_type(enum brw_reg_type type
)
366 case BRW_REGISTER_TYPE_NF
:
367 case BRW_REGISTER_TYPE_DF
:
368 case BRW_REGISTER_TYPE_F
:
369 case BRW_REGISTER_TYPE_HF
:
372 case BRW_REGISTER_TYPE_VF
:
373 return BRW_REGISTER_TYPE_F
;
375 case BRW_REGISTER_TYPE_Q
:
376 case BRW_REGISTER_TYPE_UQ
:
377 return BRW_REGISTER_TYPE_Q
;
379 case BRW_REGISTER_TYPE_D
:
380 case BRW_REGISTER_TYPE_UD
:
381 return BRW_REGISTER_TYPE_D
;
383 case BRW_REGISTER_TYPE_W
:
384 case BRW_REGISTER_TYPE_UW
:
385 case BRW_REGISTER_TYPE_B
:
386 case BRW_REGISTER_TYPE_UB
:
387 case BRW_REGISTER_TYPE_V
:
388 case BRW_REGISTER_TYPE_UV
:
389 return BRW_REGISTER_TYPE_W
;
391 unreachable("not reached");
395 * Returns the execution type of an instruction \p inst
397 static enum brw_reg_type
398 execution_type(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
400 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
401 enum brw_reg_type src0_exec_type
, src1_exec_type
;
403 /* Execution data type is independent of destination data type, except in
404 * mixed F/HF instructions.
406 enum brw_reg_type dst_exec_type
= brw_inst_dst_type(devinfo
, inst
);
408 src0_exec_type
= execution_type_for_type(brw_inst_src0_type(devinfo
, inst
));
409 if (num_sources
== 1) {
410 if (src0_exec_type
== BRW_REGISTER_TYPE_HF
)
411 return dst_exec_type
;
412 return src0_exec_type
;
415 src1_exec_type
= execution_type_for_type(brw_inst_src1_type(devinfo
, inst
));
416 if (types_are_mixed_float(src0_exec_type
, src1_exec_type
) ||
417 types_are_mixed_float(src0_exec_type
, dst_exec_type
) ||
418 types_are_mixed_float(src1_exec_type
, dst_exec_type
)) {
419 return BRW_REGISTER_TYPE_F
;
422 if (src0_exec_type
== src1_exec_type
)
423 return src0_exec_type
;
425 /* Mixed operand types where one is float is float on Gen < 6
426 * (and not allowed on later platforms)
428 if (devinfo
->gen
< 6 &&
429 (src0_exec_type
== BRW_REGISTER_TYPE_F
||
430 src1_exec_type
== BRW_REGISTER_TYPE_F
))
431 return BRW_REGISTER_TYPE_F
;
433 if (src0_exec_type
== BRW_REGISTER_TYPE_Q
||
434 src1_exec_type
== BRW_REGISTER_TYPE_Q
)
435 return BRW_REGISTER_TYPE_Q
;
437 if (src0_exec_type
== BRW_REGISTER_TYPE_D
||
438 src1_exec_type
== BRW_REGISTER_TYPE_D
)
439 return BRW_REGISTER_TYPE_D
;
441 if (src0_exec_type
== BRW_REGISTER_TYPE_W
||
442 src1_exec_type
== BRW_REGISTER_TYPE_W
)
443 return BRW_REGISTER_TYPE_W
;
445 if (src0_exec_type
== BRW_REGISTER_TYPE_DF
||
446 src1_exec_type
== BRW_REGISTER_TYPE_DF
)
447 return BRW_REGISTER_TYPE_DF
;
449 unreachable("not reached");
453 * Returns whether a region is packed
455 * A region is packed if its elements are adjacent in memory, with no
456 * intervening space, no overlap, and no replicated values.
459 is_packed(unsigned vstride
, unsigned width
, unsigned hstride
)
461 if (vstride
== width
) {
473 * Checks restrictions listed in "General Restrictions Based on Operand Types"
474 * in the "Register Region Restrictions" section.
477 general_restrictions_based_on_operand_types(const struct gen_device_info
*devinfo
,
478 const brw_inst
*inst
)
480 const struct opcode_desc
*desc
=
481 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
482 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
483 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
484 struct string error_msg
= { .str
= NULL
, .len
= 0 };
486 if (num_sources
== 3)
487 return (struct string
){};
489 if (inst_is_send(devinfo
, inst
))
490 return (struct string
){};
493 return (struct string
){};
496 return (struct string
){};
500 * Where n is the largest element size in bytes for any source or
501 * destination operand type, ExecSize * n must be <= 64.
503 * But we do not attempt to enforce it, because it is implied by other
506 * - that the destination stride must match the execution data type
507 * - sources may not span more than two adjacent GRF registers
508 * - destination may not span more than two adjacent GRF registers
510 * In fact, checking it would weaken testing of the other rules.
513 unsigned dst_stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
514 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
515 bool dst_type_is_byte
=
516 brw_inst_dst_type(devinfo
, inst
) == BRW_REGISTER_TYPE_B
||
517 brw_inst_dst_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UB
;
519 if (dst_type_is_byte
) {
520 if (is_packed(exec_size
* dst_stride
, exec_size
, dst_stride
)) {
521 if (!inst_is_raw_move(devinfo
, inst
)) {
522 ERROR("Only raw MOV supports a packed-byte destination");
525 return (struct string
){};
530 unsigned exec_type
= execution_type(devinfo
, inst
);
531 unsigned exec_type_size
= brw_reg_type_to_size(exec_type
);
532 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
534 /* On IVB/BYT, region parameters and execution size for DF are in terms of
535 * 32-bit elements, so they are doubled. For evaluating the validity of an
536 * instruction, we halve them.
538 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
539 exec_type_size
== 8 && dst_type_size
== 4)
542 if (exec_type_size
> dst_type_size
) {
543 if (!(dst_type_is_byte
&& inst_is_raw_move(devinfo
, inst
))) {
544 ERROR_IF(dst_stride
* dst_type_size
!= exec_type_size
,
545 "Destination stride must be equal to the ratio of the sizes "
546 "of the execution data type to the destination type");
549 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
551 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
552 brw_inst_dst_address_mode(devinfo
, inst
) == BRW_ADDRESS_DIRECT
) {
553 /* The i965 PRM says:
555 * Implementation Restriction: The relaxed alignment rule for byte
556 * destination (#10.5) is not supported.
558 if ((devinfo
->gen
> 4 || devinfo
->is_g4x
) && dst_type_is_byte
) {
559 ERROR_IF(subreg
% exec_type_size
!= 0 &&
560 subreg
% exec_type_size
!= 1,
561 "Destination subreg must be aligned to the size of the "
562 "execution data type (or to the next lowest byte for byte "
565 ERROR_IF(subreg
% exec_type_size
!= 0,
566 "Destination subreg must be aligned to the size of the "
567 "execution data type");
576 * Checks restrictions listed in "General Restrictions on Regioning Parameters"
577 * in the "Register Region Restrictions" section.
580 general_restrictions_on_region_parameters(const struct gen_device_info
*devinfo
,
581 const brw_inst
*inst
)
583 const struct opcode_desc
*desc
=
584 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
585 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
586 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
587 struct string error_msg
= { .str
= NULL
, .len
= 0 };
589 if (num_sources
== 3)
590 return (struct string
){};
592 /* Split sends don't have the bits in the instruction to encode regions so
593 * there's nothing to check.
595 if (inst_is_split_send(devinfo
, inst
))
596 return (struct string
){};
598 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
) {
599 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
))
600 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) != BRW_HORIZONTAL_STRIDE_1
,
601 "Destination Horizontal Stride must be 1");
603 if (num_sources
>= 1) {
604 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
605 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
606 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
607 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
608 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
609 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
611 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
612 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
613 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
614 "In Align16 mode, only VertStride of 0 or 4 is allowed");
618 if (num_sources
== 2) {
619 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
620 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
621 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
622 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
623 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
624 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
626 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
627 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
628 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
629 "In Align16 mode, only VertStride of 0 or 4 is allowed");
636 for (unsigned i
= 0; i
< num_sources
; i
++) {
637 unsigned vstride
, width
, hstride
, element_size
, subreg
;
638 enum brw_reg_type type
;
641 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
642 BRW_IMMEDIATE_VALUE) \
645 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
646 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
647 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
648 type = brw_inst_src ## n ## _type(devinfo, inst); \
649 element_size = brw_reg_type_to_size(type); \
650 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst)
659 /* On IVB/BYT, region parameters and execution size for DF are in terms of
660 * 32-bit elements, so they are doubled. For evaluating the validity of an
661 * instruction, we halve them.
663 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
667 /* ExecSize must be greater than or equal to Width. */
668 ERROR_IF(exec_size
< width
, "ExecSize must be greater than or equal "
671 /* If ExecSize = Width and HorzStride ≠ 0,
672 * VertStride must be set to Width * HorzStride.
674 if (exec_size
== width
&& hstride
!= 0) {
675 ERROR_IF(vstride
!= width
* hstride
,
676 "If ExecSize = Width and HorzStride ≠ 0, "
677 "VertStride must be set to Width * HorzStride");
680 /* If Width = 1, HorzStride must be 0 regardless of the values of
681 * ExecSize and VertStride.
684 ERROR_IF(hstride
!= 0,
685 "If Width = 1, HorzStride must be 0 regardless "
686 "of the values of ExecSize and VertStride");
689 /* If ExecSize = Width = 1, both VertStride and HorzStride must be 0. */
690 if (exec_size
== 1 && width
== 1) {
691 ERROR_IF(vstride
!= 0 || hstride
!= 0,
692 "If ExecSize = Width = 1, both VertStride "
693 "and HorzStride must be 0");
696 /* If VertStride = HorzStride = 0, Width must be 1 regardless of the
699 if (vstride
== 0 && hstride
== 0) {
701 "If VertStride = HorzStride = 0, Width must be "
702 "1 regardless of the value of ExecSize");
705 /* VertStride must be used to cross GRF register boundaries. This rule
706 * implies that elements within a 'Width' cannot cross GRF boundaries.
708 const uint64_t mask
= (1ULL << element_size
) - 1;
709 unsigned rowbase
= subreg
;
711 for (int y
= 0; y
< exec_size
/ width
; y
++) {
712 uint64_t access_mask
= 0;
713 unsigned offset
= rowbase
;
715 for (int x
= 0; x
< width
; x
++) {
716 access_mask
|= mask
<< offset
;
717 offset
+= hstride
* element_size
;
720 rowbase
+= vstride
* element_size
;
722 if ((uint32_t)access_mask
!= 0 && (access_mask
>> 32) != 0) {
723 ERROR("VertStride must be used to cross GRF register boundaries");
729 /* Dst.HorzStride must not be 0. */
730 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
)) {
731 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
,
732 "Destination Horizontal Stride must not be 0");
739 * Creates an \p access_mask for an \p exec_size, \p element_size, and a region
741 * An \p access_mask is a 32-element array of uint64_t, where each uint64_t is
742 * a bitmask of bytes accessed by the region.
744 * For instance the access mask of the source gX.1<4,2,2>F in an exec_size = 4
745 * instruction would be
747 * access_mask[0] = 0x00000000000000F0
748 * access_mask[1] = 0x000000000000F000
749 * access_mask[2] = 0x0000000000F00000
750 * access_mask[3] = 0x00000000F0000000
751 * access_mask[4-31] = 0
753 * because the first execution channel accesses bytes 7-4 and the second
754 * execution channel accesses bytes 15-12, etc.
757 align1_access_mask(uint64_t access_mask
[static 32],
758 unsigned exec_size
, unsigned element_size
, unsigned subreg
,
759 unsigned vstride
, unsigned width
, unsigned hstride
)
761 const uint64_t mask
= (1ULL << element_size
) - 1;
762 unsigned rowbase
= subreg
;
763 unsigned element
= 0;
765 for (int y
= 0; y
< exec_size
/ width
; y
++) {
766 unsigned offset
= rowbase
;
768 for (int x
= 0; x
< width
; x
++) {
769 access_mask
[element
++] = mask
<< offset
;
770 offset
+= hstride
* element_size
;
773 rowbase
+= vstride
* element_size
;
776 assert(element
== 0 || element
== exec_size
);
780 * Returns the number of registers accessed according to the \p access_mask
783 registers_read(const uint64_t access_mask
[static 32])
787 for (unsigned i
= 0; i
< 32; i
++) {
788 if (access_mask
[i
] > 0xFFFFFFFF) {
790 } else if (access_mask
[i
]) {
799 * Checks restrictions listed in "Region Alignment Rules" in the "Register
800 * Region Restrictions" section.
803 region_alignment_rules(const struct gen_device_info
*devinfo
,
804 const brw_inst
*inst
)
806 const struct opcode_desc
*desc
=
807 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
808 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
809 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
810 uint64_t dst_access_mask
[32], src0_access_mask
[32], src1_access_mask
[32];
811 struct string error_msg
= { .str
= NULL
, .len
= 0 };
813 if (num_sources
== 3)
814 return (struct string
){};
816 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
)
817 return (struct string
){};
819 if (inst_is_send(devinfo
, inst
))
820 return (struct string
){};
822 memset(dst_access_mask
, 0, sizeof(dst_access_mask
));
823 memset(src0_access_mask
, 0, sizeof(src0_access_mask
));
824 memset(src1_access_mask
, 0, sizeof(src1_access_mask
));
826 for (unsigned i
= 0; i
< num_sources
; i
++) {
827 unsigned vstride
, width
, hstride
, element_size
, subreg
;
828 enum brw_reg_type type
;
830 /* In Direct Addressing mode, a source cannot span more than 2 adjacent
835 if (brw_inst_src ## n ## _address_mode(devinfo, inst) != \
836 BRW_ADDRESS_DIRECT) \
839 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
840 BRW_IMMEDIATE_VALUE) \
843 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
844 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
845 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
846 type = brw_inst_src ## n ## _type(devinfo, inst); \
847 element_size = brw_reg_type_to_size(type); \
848 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
849 align1_access_mask(src ## n ## _access_mask, \
850 exec_size, element_size, subreg, \
851 vstride, width, hstride)
860 unsigned num_vstride
= exec_size
/ width
;
861 unsigned num_hstride
= width
;
862 unsigned vstride_elements
= (num_vstride
- 1) * vstride
;
863 unsigned hstride_elements
= (num_hstride
- 1) * hstride
;
864 unsigned offset
= (vstride_elements
+ hstride_elements
) * element_size
+
866 ERROR_IF(offset
>= 64,
867 "A source cannot span more than 2 adjacent GRF registers");
870 if (desc
->ndst
== 0 || dst_is_null(devinfo
, inst
))
873 unsigned stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
874 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
875 unsigned element_size
= brw_reg_type_to_size(dst_type
);
876 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
877 unsigned offset
= ((exec_size
- 1) * stride
* element_size
) + subreg
;
878 ERROR_IF(offset
>= 64,
879 "A destination cannot span more than 2 adjacent GRF registers");
884 /* On IVB/BYT, region parameters and execution size for DF are in terms of
885 * 32-bit elements, so they are doubled. For evaluating the validity of an
886 * instruction, we halve them.
888 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
892 align1_access_mask(dst_access_mask
, exec_size
, element_size
, subreg
,
893 exec_size
== 1 ? 0 : exec_size
* stride
,
894 exec_size
== 1 ? 1 : exec_size
,
895 exec_size
== 1 ? 0 : stride
);
897 unsigned dst_regs
= registers_read(dst_access_mask
);
898 unsigned src0_regs
= registers_read(src0_access_mask
);
899 unsigned src1_regs
= registers_read(src1_access_mask
);
901 /* The SNB, IVB, HSW, BDW, and CHV PRMs say:
903 * When an instruction has a source region spanning two registers and a
904 * destination region contained in one register, the number of elements
905 * must be the same between two sources and one of the following must be
908 * 1. The destination region is entirely contained in the lower OWord
910 * 2. The destination region is entirely contained in the upper OWord
912 * 3. The destination elements are evenly split between the two OWords
915 if (devinfo
->gen
<= 8) {
916 if (dst_regs
== 1 && (src0_regs
== 2 || src1_regs
== 2)) {
917 unsigned upper_oword_writes
= 0, lower_oword_writes
= 0;
919 for (unsigned i
= 0; i
< exec_size
; i
++) {
920 if (dst_access_mask
[i
] > 0x0000FFFF) {
921 upper_oword_writes
++;
923 assert(dst_access_mask
[i
] != 0);
924 lower_oword_writes
++;
928 ERROR_IF(lower_oword_writes
!= 0 &&
929 upper_oword_writes
!= 0 &&
930 upper_oword_writes
!= lower_oword_writes
,
931 "Writes must be to only one OWord or "
932 "evenly split between OWords");
936 /* The IVB and HSW PRMs say:
938 * When an instruction has a source region that spans two registers and
939 * the destination spans two registers, the destination elements must be
940 * evenly split between the two registers [...]
942 * The SNB PRM contains similar wording (but written in a much more
947 * When destination spans two registers, the source may be one or two
948 * registers. The destination elements must be evenly split between the
953 * When destination of MATH instruction spans two registers, the
954 * destination elements must be evenly split between the two registers.
956 * It is not known whether this restriction applies to KBL other Gens after
959 if (devinfo
->gen
<= 8 ||
960 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
962 /* Nothing explicitly states that on Gen < 8 elements must be evenly
963 * split between two destination registers in the two exceptional
964 * source-region-spans-one-register cases, but since Broadwell requires
965 * evenly split writes regardless of source region, we assume that it was
966 * an oversight and require it.
969 unsigned upper_reg_writes
= 0, lower_reg_writes
= 0;
971 for (unsigned i
= 0; i
< exec_size
; i
++) {
972 if (dst_access_mask
[i
] > 0xFFFFFFFF) {
975 assert(dst_access_mask
[i
] != 0);
980 ERROR_IF(upper_reg_writes
!= lower_reg_writes
,
981 "Writes must be evenly split between the two "
982 "destination registers");
986 /* The IVB and HSW PRMs say:
988 * When an instruction has a source region that spans two registers and
989 * the destination spans two registers, the destination elements must be
990 * evenly split between the two registers and each destination register
991 * must be entirely derived from one source register.
993 * Note: In such cases, the regioning parameters must ensure that the
994 * offset from the two source registers is the same.
996 * The SNB PRM contains similar wording (but written in a much more
999 * There are effectively three rules stated here:
1001 * For an instruction with a source and a destination spanning two
1004 * (1) destination elements must be evenly split between the two
1006 * (2) all destination elements in a register must be derived
1007 * from one source register
1008 * (3) the offset (i.e. the starting location in each of the two
1009 * registers spanned by a region) must be the same in the two
1010 * registers spanned by a region
1012 * It is impossible to violate rule (1) without violating (2) or (3), so we
1013 * do not attempt to validate it.
1015 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
1016 for (unsigned i
= 0; i
< num_sources
; i
++) {
1018 if (src ## n ## _regs <= 1) \
1021 for (unsigned i = 0; i < exec_size; i++) { \
1022 if ((dst_access_mask[i] > 0xFFFFFFFF) != \
1023 (src ## n ## _access_mask[i] > 0xFFFFFFFF)) { \
1024 ERROR("Each destination register must be entirely derived " \
1025 "from one source register"); \
1030 unsigned offset_0 = \
1031 brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
1032 unsigned offset_1 = offset_0; \
1034 for (unsigned i = 0; i < exec_size; i++) { \
1035 if (src ## n ## _access_mask[i] > 0xFFFFFFFF) { \
1036 offset_1 = __builtin_ctzll(src ## n ## _access_mask[i]) - 32; \
1041 ERROR_IF(num_sources == 2 && offset_0 != offset_1, \
1042 "The offset from the two source registers " \
1054 /* The IVB and HSW PRMs say:
1056 * When destination spans two registers, the source MUST span two
1057 * registers. The exception to the above rule:
1058 * 1. When source is scalar, the source registers are not
1060 * 2. When source is packed integer Word and destination is packed
1061 * integer DWord, the source register is not incremented by the
1062 * source sub register is incremented.
1064 * The SNB PRM does not contain this rule, but the internal documentation
1065 * indicates that it applies to SNB as well. We assume that the rule applies
1066 * to Gen <= 5 although their PRMs do not state it.
1068 * While the documentation explicitly says in exception (2) that the
1069 * destination must be an integer DWord, the hardware allows at least a
1070 * float destination type as well. We emit such instructions from
1072 * fs_visitor::emit_interpolation_setup_gen6
1073 * fs_visitor::emit_fragcoord_interpolation
1075 * and have for years with no ill effects.
1077 * Additionally the simulator source code indicates that the real condition
1078 * is that the size of the destination type is 4 bytes.
1080 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
1081 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1082 bool dst_is_packed_dword
=
1083 is_packed(exec_size
* stride
, exec_size
, stride
) &&
1084 brw_reg_type_to_size(dst_type
) == 4;
1086 for (unsigned i
= 0; i
< num_sources
; i
++) {
1088 unsigned vstride, width, hstride; \
1089 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
1090 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
1091 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
1092 bool src ## n ## _is_packed_word = \
1093 is_packed(vstride, width, hstride) && \
1094 (brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_W || \
1095 brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_UW); \
1097 ERROR_IF(src ## n ## _regs == 1 && \
1098 !src ## n ## _has_scalar_region(devinfo, inst) && \
1099 !(dst_is_packed_dword && src ## n ## _is_packed_word), \
1100 "When the destination spans two registers, the source must " \
1101 "span two registers\n" ERROR_INDENT "(exceptions for scalar " \
1102 "source and packed-word to packed-dword expansion)")
1116 static struct string
1117 vector_immediate_restrictions(const struct gen_device_info
*devinfo
,
1118 const brw_inst
*inst
)
1120 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1121 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1123 if (num_sources
== 3 || num_sources
== 0)
1124 return (struct string
){};
1126 unsigned file
= num_sources
== 1 ?
1127 brw_inst_src0_reg_file(devinfo
, inst
) :
1128 brw_inst_src1_reg_file(devinfo
, inst
);
1129 if (file
!= BRW_IMMEDIATE_VALUE
)
1130 return (struct string
){};
1132 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1133 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
1134 unsigned dst_subreg
= brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
?
1135 brw_inst_dst_da1_subreg_nr(devinfo
, inst
) : 0;
1136 unsigned dst_stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
1137 enum brw_reg_type type
= num_sources
== 1 ?
1138 brw_inst_src0_type(devinfo
, inst
) :
1139 brw_inst_src1_type(devinfo
, inst
);
1143 * When an immediate vector is used in an instruction, the destination
1144 * must be 128-bit aligned with destination horizontal stride equivalent
1145 * to a word for an immediate integer vector (v) and equivalent to a
1146 * DWord for an immediate float vector (vf).
1148 * The text has not been updated for the addition of the immediate unsigned
1149 * integer vector type (uv) on SNB, but presumably the same restriction
1153 case BRW_REGISTER_TYPE_V
:
1154 case BRW_REGISTER_TYPE_UV
:
1155 case BRW_REGISTER_TYPE_VF
:
1156 ERROR_IF(dst_subreg
% (128 / 8) != 0,
1157 "Destination must be 128-bit aligned in order to use immediate "
1160 if (type
== BRW_REGISTER_TYPE_VF
) {
1161 ERROR_IF(dst_type_size
* dst_stride
!= 4,
1162 "Destination must have stride equivalent to dword in order "
1163 "to use the VF type");
1165 ERROR_IF(dst_type_size
* dst_stride
!= 2,
1166 "Destination must have stride equivalent to word in order "
1167 "to use the V or UV type");
1177 static struct string
1178 special_requirements_for_handling_double_precision_data_types(
1179 const struct gen_device_info
*devinfo
,
1180 const brw_inst
*inst
)
1182 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1183 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1185 if (num_sources
== 3 || num_sources
== 0)
1186 return (struct string
){};
1188 /* Split sends don't have types so there's no doubles there. */
1189 if (inst_is_split_send(devinfo
, inst
))
1190 return (struct string
){};
1192 enum brw_reg_type exec_type
= execution_type(devinfo
, inst
);
1193 unsigned exec_type_size
= brw_reg_type_to_size(exec_type
);
1195 enum brw_reg_file dst_file
= brw_inst_dst_reg_file(devinfo
, inst
);
1196 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1197 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
1198 unsigned dst_hstride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
1199 unsigned dst_reg
= brw_inst_dst_da_reg_nr(devinfo
, inst
);
1200 unsigned dst_subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
1201 unsigned dst_address_mode
= brw_inst_dst_address_mode(devinfo
, inst
);
1203 bool is_integer_dword_multiply
=
1204 devinfo
->gen
>= 8 &&
1205 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MUL
&&
1206 (brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_D
||
1207 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UD
) &&
1208 (brw_inst_src1_type(devinfo
, inst
) == BRW_REGISTER_TYPE_D
||
1209 brw_inst_src1_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UD
);
1211 if (dst_type_size
!= 8 && exec_type_size
!= 8 && !is_integer_dword_multiply
)
1212 return (struct string
){};
1214 for (unsigned i
= 0; i
< num_sources
; i
++) {
1215 unsigned vstride
, width
, hstride
, type_size
, reg
, subreg
, address_mode
;
1216 bool is_scalar_region
;
1217 enum brw_reg_file file
;
1218 enum brw_reg_type type
;
1221 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
1222 BRW_IMMEDIATE_VALUE) \
1225 is_scalar_region = src ## n ## _has_scalar_region(devinfo, inst); \
1226 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
1227 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
1228 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
1229 file = brw_inst_src ## n ## _reg_file(devinfo, inst); \
1230 type = brw_inst_src ## n ## _type(devinfo, inst); \
1231 type_size = brw_reg_type_to_size(type); \
1232 reg = brw_inst_src ## n ## _da_reg_nr(devinfo, inst); \
1233 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
1234 address_mode = brw_inst_src ## n ## _address_mode(devinfo, inst)
1243 /* The PRMs say that for CHV, BXT:
1245 * When source or destination datatype is 64b or operation is integer
1246 * DWord multiply, regioning in Align1 must follow these rules:
1248 * 1. Source and Destination horizontal stride must be aligned to the
1250 * 2. Regioning must ensure Src.Vstride = Src.Width * Src.Hstride.
1251 * 3. Source and Destination offset must be the same, except the case
1254 * We assume that the restriction applies to GLK as well.
1256 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
1257 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
1258 unsigned src_stride
= hstride
* type_size
;
1259 unsigned dst_stride
= dst_hstride
* dst_type_size
;
1261 ERROR_IF(!is_scalar_region
&&
1262 (src_stride
% 8 != 0 ||
1263 dst_stride
% 8 != 0 ||
1264 src_stride
!= dst_stride
),
1265 "Source and destination horizontal stride must equal and a "
1266 "multiple of a qword when the execution type is 64-bit");
1268 ERROR_IF(vstride
!= width
* hstride
,
1269 "Vstride must be Width * Hstride when the execution type is "
1272 ERROR_IF(!is_scalar_region
&& dst_subreg
!= subreg
,
1273 "Source and destination offset must be the same when the "
1274 "execution type is 64-bit");
1277 /* The PRMs say that for CHV, BXT:
1279 * When source or destination datatype is 64b or operation is integer
1280 * DWord multiply, indirect addressing must not be used.
1282 * We assume that the restriction applies to GLK as well.
1284 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1285 ERROR_IF(BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
== address_mode
||
1286 BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
== dst_address_mode
,
1287 "Indirect addressing is not allowed when the execution type "
1291 /* The PRMs say that for CHV, BXT:
1293 * ARF registers must never be used with 64b datatype or when
1294 * operation is integer DWord multiply.
1296 * We assume that the restriction applies to GLK as well.
1298 * We assume that the restriction does not apply to the null register.
1300 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1301 ERROR_IF(brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MAC
||
1302 brw_inst_acc_wr_control(devinfo
, inst
) ||
1303 (BRW_ARCHITECTURE_REGISTER_FILE
== file
&&
1304 reg
!= BRW_ARF_NULL
) ||
1305 (BRW_ARCHITECTURE_REGISTER_FILE
== dst_file
&&
1306 dst_reg
!= BRW_ARF_NULL
),
1307 "Architecture registers cannot be used when the execution "
1312 /* The PRMs say that for BDW, SKL:
1314 * If Align16 is required for an operation with QW destination and non-QW
1315 * source datatypes, the execution size cannot exceed 2.
1317 * We assume that the restriction applies to all Gen8+ parts.
1319 if (devinfo
->gen
>= 8) {
1320 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
1321 enum brw_reg_type src1_type
=
1322 num_sources
> 1 ? brw_inst_src1_type(devinfo
, inst
) : src0_type
;
1323 unsigned src0_type_size
= brw_reg_type_to_size(src0_type
);
1324 unsigned src1_type_size
= brw_reg_type_to_size(src1_type
);
1326 ERROR_IF(brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
&&
1327 dst_type_size
== 8 &&
1328 (src0_type_size
!= 8 || src1_type_size
!= 8) &&
1329 brw_inst_exec_size(devinfo
, inst
) > BRW_EXECUTE_2
,
1330 "In Align16 exec size cannot exceed 2 with a QWord destination "
1331 "and a non-QWord source");
1334 /* The PRMs say that for CHV, BXT:
1336 * When source or destination datatype is 64b or operation is integer
1337 * DWord multiply, DepCtrl must not be used.
1339 * We assume that the restriction applies to GLK as well.
1341 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1342 ERROR_IF(brw_inst_no_dd_check(devinfo
, inst
) ||
1343 brw_inst_no_dd_clear(devinfo
, inst
),
1344 "DepCtrl is not allowed when the execution type is 64-bit");
1351 brw_validate_instructions(const struct gen_device_info
*devinfo
,
1352 const void *assembly
, int start_offset
, int end_offset
,
1353 struct disasm_info
*disasm
)
1357 for (int src_offset
= start_offset
; src_offset
< end_offset
;) {
1358 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1359 const brw_inst
*inst
= assembly
+ src_offset
;
1360 bool is_compact
= brw_inst_cmpt_control(devinfo
, inst
);
1361 brw_inst uncompacted
;
1364 brw_compact_inst
*compacted
= (void *)inst
;
1365 brw_uncompact_instruction(devinfo
, &uncompacted
, compacted
);
1366 inst
= &uncompacted
;
1369 if (is_unsupported_inst(devinfo
, inst
)) {
1370 ERROR("Instruction not supported on this Gen");
1372 CHECK(sources_not_null
);
1373 CHECK(send_restrictions
);
1374 CHECK(general_restrictions_based_on_operand_types
);
1375 CHECK(general_restrictions_on_region_parameters
);
1376 CHECK(region_alignment_rules
);
1377 CHECK(vector_immediate_restrictions
);
1378 CHECK(special_requirements_for_handling_double_precision_data_types
);
1381 if (error_msg
.str
&& disasm
) {
1382 disasm_insert_error(disasm
, src_offset
, error_msg
.str
);
1384 valid
= valid
&& error_msg
.len
== 0;
1385 free(error_msg
.str
);
1388 src_offset
+= sizeof(brw_compact_inst
);
1390 src_offset
+= sizeof(brw_inst
);