2 * Copyright © 2015-2019 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_eu_validate.c
26 * This file implements a pass that validates shader assembly.
28 * The restrictions implemented herein are intended to verify that instructions
29 * in shader assembly do not violate restrictions documented in the graphics
30 * programming reference manuals.
32 * The restrictions are difficult for humans to quickly verify due to their
33 * complexity and abundance.
35 * It is critical that this code is thoroughly unit tested because false
36 * results will lead developers astray, which is worse than having no validator
37 * at all. Functional changes to this file without corresponding unit tests (in
38 * test_eu_validate.cpp) will be rejected.
43 /* We're going to do lots of string concatenation, so this should help. */
50 cat(struct string
*dest
, const struct string src
)
52 dest
->str
= realloc(dest
->str
, dest
->len
+ src
.len
+ 1);
53 memcpy(dest
->str
+ dest
->len
, src
.str
, src
.len
);
54 dest
->str
[dest
->len
+ src
.len
] = '\0';
55 dest
->len
= dest
->len
+ src
.len
;
57 #define CAT(dest, src) cat(&dest, (struct string){src, strlen(src)})
60 contains(const struct string haystack
, const struct string needle
)
62 return haystack
.str
&& memmem(haystack
.str
, haystack
.len
,
63 needle
.str
, needle
.len
) != NULL
;
65 #define CONTAINS(haystack, needle) \
66 contains(haystack, (struct string){needle, strlen(needle)})
68 #define error(str) "\tERROR: " str "\n"
69 #define ERROR_INDENT "\t "
71 #define ERROR(msg) ERROR_IF(true, msg)
72 #define ERROR_IF(cond, msg) \
74 if ((cond) && !CONTAINS(error_msg, error(msg))) { \
75 CAT(error_msg, error(msg)); \
79 #define CHECK(func, args...) \
81 struct string __msg = func(devinfo, inst, ##args); \
83 cat(&error_msg, __msg); \
88 #define STRIDE(stride) (stride != 0 ? 1 << ((stride) - 1) : 0)
89 #define WIDTH(width) (1 << (width))
92 inst_is_send(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
94 switch (brw_inst_opcode(devinfo
, inst
)) {
96 case BRW_OPCODE_SENDC
:
97 case BRW_OPCODE_SENDS
:
98 case BRW_OPCODE_SENDSC
:
106 inst_is_split_send(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
108 switch (brw_inst_opcode(devinfo
, inst
)) {
109 case BRW_OPCODE_SENDS
:
110 case BRW_OPCODE_SENDSC
:
118 signed_type(unsigned type
)
121 case BRW_REGISTER_TYPE_UD
: return BRW_REGISTER_TYPE_D
;
122 case BRW_REGISTER_TYPE_UW
: return BRW_REGISTER_TYPE_W
;
123 case BRW_REGISTER_TYPE_UB
: return BRW_REGISTER_TYPE_B
;
124 case BRW_REGISTER_TYPE_UQ
: return BRW_REGISTER_TYPE_Q
;
125 default: return type
;
130 inst_is_raw_move(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
132 unsigned dst_type
= signed_type(brw_inst_dst_type(devinfo
, inst
));
133 unsigned src_type
= signed_type(brw_inst_src0_type(devinfo
, inst
));
135 if (brw_inst_src0_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
) {
136 /* FIXME: not strictly true */
137 if (brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_VF
||
138 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UV
||
139 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_V
) {
142 } else if (brw_inst_src0_negate(devinfo
, inst
) ||
143 brw_inst_src0_abs(devinfo
, inst
)) {
147 return brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MOV
&&
148 brw_inst_saturate(devinfo
, inst
) == 0 &&
149 dst_type
== src_type
;
153 dst_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
155 return brw_inst_dst_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
156 brw_inst_dst_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
160 src0_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
162 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
163 brw_inst_src0_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
167 src1_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
169 return brw_inst_src1_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
170 brw_inst_src1_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
174 src0_is_acc(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
176 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
177 (brw_inst_src0_da_reg_nr(devinfo
, inst
) & 0xF0) == BRW_ARF_ACCUMULATOR
;
181 src1_is_acc(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
183 return brw_inst_src1_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
184 (brw_inst_src1_da_reg_nr(devinfo
, inst
) & 0xF0) == BRW_ARF_ACCUMULATOR
;
188 src0_is_grf(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
190 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_GENERAL_REGISTER_FILE
;
194 src0_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
196 return brw_inst_src0_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
197 brw_inst_src0_width(devinfo
, inst
) == BRW_WIDTH_1
&&
198 brw_inst_src0_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
202 src1_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
204 return brw_inst_src1_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
205 brw_inst_src1_width(devinfo
, inst
) == BRW_WIDTH_1
&&
206 brw_inst_src1_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
210 num_sources_from_inst(const struct gen_device_info
*devinfo
,
211 const brw_inst
*inst
)
213 const struct opcode_desc
*desc
=
214 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
215 unsigned math_function
;
217 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
218 math_function
= brw_inst_math_function(devinfo
, inst
);
219 } else if (devinfo
->gen
< 6 &&
220 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
221 if (brw_inst_sfid(devinfo
, inst
) == BRW_SFID_MATH
) {
222 /* src1 must be a descriptor (including the information to determine
223 * that the SEND is doing an extended math operation), but src0 can
224 * actually be null since it serves as the source of the implicit GRF
227 * If we stop using that functionality, we'll have to revisit this.
231 /* Send instructions are allowed to have null sources since they use
232 * the base_mrf field to specify which message register source.
237 assert(desc
->nsrc
< 4);
241 switch (math_function
) {
242 case BRW_MATH_FUNCTION_INV
:
243 case BRW_MATH_FUNCTION_LOG
:
244 case BRW_MATH_FUNCTION_EXP
:
245 case BRW_MATH_FUNCTION_SQRT
:
246 case BRW_MATH_FUNCTION_RSQ
:
247 case BRW_MATH_FUNCTION_SIN
:
248 case BRW_MATH_FUNCTION_COS
:
249 case BRW_MATH_FUNCTION_SINCOS
:
250 case GEN8_MATH_FUNCTION_INVM
:
251 case GEN8_MATH_FUNCTION_RSQRTM
:
253 case BRW_MATH_FUNCTION_FDIV
:
254 case BRW_MATH_FUNCTION_POW
:
255 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
:
256 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
:
257 case BRW_MATH_FUNCTION_INT_DIV_REMAINDER
:
260 unreachable("not reached");
265 sources_not_null(const struct gen_device_info
*devinfo
,
266 const brw_inst
*inst
)
268 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
269 struct string error_msg
= { .str
= NULL
, .len
= 0 };
271 /* Nothing to test. 3-src instructions can only have GRF sources, and
272 * there's no bit to control the file.
274 if (num_sources
== 3)
275 return (struct string
){};
277 /* Nothing to test. Split sends can only encode a file in sources that are
278 * allowed to be NULL.
280 if (inst_is_split_send(devinfo
, inst
))
281 return (struct string
){};
283 if (num_sources
>= 1 && brw_inst_opcode(devinfo
, inst
) != BRW_OPCODE_SYNC
)
284 ERROR_IF(src0_is_null(devinfo
, inst
), "src0 is null");
286 if (num_sources
== 2)
287 ERROR_IF(src1_is_null(devinfo
, inst
), "src1 is null");
293 alignment_supported(const struct gen_device_info
*devinfo
,
294 const brw_inst
*inst
)
296 struct string error_msg
= { .str
= NULL
, .len
= 0 };
298 ERROR_IF(devinfo
->gen
>= 11 && brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
,
299 "Align16 not supported");
305 inst_uses_src_acc(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
307 /* Check instructions that use implicit accumulator sources */
308 switch (brw_inst_opcode(devinfo
, inst
)) {
310 case BRW_OPCODE_MACH
:
311 case BRW_OPCODE_SADA2
:
317 /* FIXME: support 3-src instructions */
318 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
319 assert(num_sources
< 3);
321 return src0_is_acc(devinfo
, inst
) || (num_sources
> 1 && src1_is_acc(devinfo
, inst
));
325 send_restrictions(const struct gen_device_info
*devinfo
,
326 const brw_inst
*inst
)
328 struct string error_msg
= { .str
= NULL
, .len
= 0 };
330 if (inst_is_split_send(devinfo
, inst
)) {
331 ERROR_IF(brw_inst_send_src1_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
332 brw_inst_send_src1_reg_nr(devinfo
, inst
) != BRW_ARF_NULL
,
333 "src1 of split send must be a GRF or NULL");
335 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
336 brw_inst_src0_da_reg_nr(devinfo
, inst
) < 112,
337 "send with EOT must use g112-g127");
338 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
339 brw_inst_send_src1_reg_file(devinfo
, inst
) == BRW_GENERAL_REGISTER_FILE
&&
340 brw_inst_send_src1_reg_nr(devinfo
, inst
) < 112,
341 "send with EOT must use g112-g127");
343 if (brw_inst_send_src1_reg_file(devinfo
, inst
) == BRW_GENERAL_REGISTER_FILE
) {
344 /* Assume minimums if we don't know */
346 if (!brw_inst_send_sel_reg32_desc(devinfo
, inst
)) {
347 const uint32_t desc
= brw_inst_send_desc(devinfo
, inst
);
348 mlen
= brw_message_desc_mlen(devinfo
, desc
);
351 unsigned ex_mlen
= 1;
352 if (!brw_inst_send_sel_reg32_ex_desc(devinfo
, inst
)) {
353 const uint32_t ex_desc
= brw_inst_sends_ex_desc(devinfo
, inst
);
354 ex_mlen
= brw_message_ex_desc_ex_mlen(devinfo
, ex_desc
);
356 const unsigned src0_reg_nr
= brw_inst_src0_da_reg_nr(devinfo
, inst
);
357 const unsigned src1_reg_nr
= brw_inst_send_src1_reg_nr(devinfo
, inst
);
358 ERROR_IF((src0_reg_nr
<= src1_reg_nr
&&
359 src1_reg_nr
< src0_reg_nr
+ mlen
) ||
360 (src1_reg_nr
<= src0_reg_nr
&&
361 src0_reg_nr
< src1_reg_nr
+ ex_mlen
),
362 "split send payloads must not overlap");
364 } else if (inst_is_send(devinfo
, inst
)) {
365 ERROR_IF(brw_inst_src0_address_mode(devinfo
, inst
) != BRW_ADDRESS_DIRECT
,
366 "send must use direct addressing");
368 if (devinfo
->gen
>= 7) {
369 ERROR_IF(!src0_is_grf(devinfo
, inst
), "send from non-GRF");
370 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
371 brw_inst_src0_da_reg_nr(devinfo
, inst
) < 112,
372 "send with EOT must use g112-g127");
375 if (devinfo
->gen
>= 8) {
376 ERROR_IF(!dst_is_null(devinfo
, inst
) &&
377 (brw_inst_dst_da_reg_nr(devinfo
, inst
) +
378 brw_inst_rlen(devinfo
, inst
) > 127) &&
379 (brw_inst_src0_da_reg_nr(devinfo
, inst
) +
380 brw_inst_mlen(devinfo
, inst
) >
381 brw_inst_dst_da_reg_nr(devinfo
, inst
)),
382 "r127 must not be used for return address when there is "
383 "a src and dest overlap");
391 is_unsupported_inst(const struct gen_device_info
*devinfo
,
392 const brw_inst
*inst
)
394 return brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_ILLEGAL
;
398 * Returns whether a combination of two types would qualify as mixed float
402 types_are_mixed_float(enum brw_reg_type t0
, enum brw_reg_type t1
)
404 return (t0
== BRW_REGISTER_TYPE_F
&& t1
== BRW_REGISTER_TYPE_HF
) ||
405 (t1
== BRW_REGISTER_TYPE_F
&& t0
== BRW_REGISTER_TYPE_HF
);
408 static enum brw_reg_type
409 execution_type_for_type(enum brw_reg_type type
)
412 case BRW_REGISTER_TYPE_NF
:
413 case BRW_REGISTER_TYPE_DF
:
414 case BRW_REGISTER_TYPE_F
:
415 case BRW_REGISTER_TYPE_HF
:
418 case BRW_REGISTER_TYPE_VF
:
419 return BRW_REGISTER_TYPE_F
;
421 case BRW_REGISTER_TYPE_Q
:
422 case BRW_REGISTER_TYPE_UQ
:
423 return BRW_REGISTER_TYPE_Q
;
425 case BRW_REGISTER_TYPE_D
:
426 case BRW_REGISTER_TYPE_UD
:
427 return BRW_REGISTER_TYPE_D
;
429 case BRW_REGISTER_TYPE_W
:
430 case BRW_REGISTER_TYPE_UW
:
431 case BRW_REGISTER_TYPE_B
:
432 case BRW_REGISTER_TYPE_UB
:
433 case BRW_REGISTER_TYPE_V
:
434 case BRW_REGISTER_TYPE_UV
:
435 return BRW_REGISTER_TYPE_W
;
437 unreachable("not reached");
441 * Returns the execution type of an instruction \p inst
443 static enum brw_reg_type
444 execution_type(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
446 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
447 enum brw_reg_type src0_exec_type
, src1_exec_type
;
449 /* Execution data type is independent of destination data type, except in
450 * mixed F/HF instructions.
452 enum brw_reg_type dst_exec_type
= brw_inst_dst_type(devinfo
, inst
);
454 src0_exec_type
= execution_type_for_type(brw_inst_src0_type(devinfo
, inst
));
455 if (num_sources
== 1) {
456 if (src0_exec_type
== BRW_REGISTER_TYPE_HF
)
457 return dst_exec_type
;
458 return src0_exec_type
;
461 src1_exec_type
= execution_type_for_type(brw_inst_src1_type(devinfo
, inst
));
462 if (types_are_mixed_float(src0_exec_type
, src1_exec_type
) ||
463 types_are_mixed_float(src0_exec_type
, dst_exec_type
) ||
464 types_are_mixed_float(src1_exec_type
, dst_exec_type
)) {
465 return BRW_REGISTER_TYPE_F
;
468 if (src0_exec_type
== src1_exec_type
)
469 return src0_exec_type
;
471 /* Mixed operand types where one is float is float on Gen < 6
472 * (and not allowed on later platforms)
474 if (devinfo
->gen
< 6 &&
475 (src0_exec_type
== BRW_REGISTER_TYPE_F
||
476 src1_exec_type
== BRW_REGISTER_TYPE_F
))
477 return BRW_REGISTER_TYPE_F
;
479 if (src0_exec_type
== BRW_REGISTER_TYPE_Q
||
480 src1_exec_type
== BRW_REGISTER_TYPE_Q
)
481 return BRW_REGISTER_TYPE_Q
;
483 if (src0_exec_type
== BRW_REGISTER_TYPE_D
||
484 src1_exec_type
== BRW_REGISTER_TYPE_D
)
485 return BRW_REGISTER_TYPE_D
;
487 if (src0_exec_type
== BRW_REGISTER_TYPE_W
||
488 src1_exec_type
== BRW_REGISTER_TYPE_W
)
489 return BRW_REGISTER_TYPE_W
;
491 if (src0_exec_type
== BRW_REGISTER_TYPE_DF
||
492 src1_exec_type
== BRW_REGISTER_TYPE_DF
)
493 return BRW_REGISTER_TYPE_DF
;
495 unreachable("not reached");
499 * Returns whether a region is packed
501 * A region is packed if its elements are adjacent in memory, with no
502 * intervening space, no overlap, and no replicated values.
505 is_packed(unsigned vstride
, unsigned width
, unsigned hstride
)
507 if (vstride
== width
) {
519 * Returns whether an instruction is an explicit or implicit conversion
520 * to/from half-float.
523 is_half_float_conversion(const struct gen_device_info
*devinfo
,
524 const brw_inst
*inst
)
526 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
528 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
529 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
531 if (dst_type
!= src0_type
&&
532 (dst_type
== BRW_REGISTER_TYPE_HF
|| src0_type
== BRW_REGISTER_TYPE_HF
)) {
534 } else if (num_sources
> 1) {
535 enum brw_reg_type src1_type
= brw_inst_src1_type(devinfo
, inst
);
536 return dst_type
!= src1_type
&&
537 (dst_type
== BRW_REGISTER_TYPE_HF
||
538 src1_type
== BRW_REGISTER_TYPE_HF
);
545 * Returns whether an instruction is using mixed float operation mode
548 is_mixed_float(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
550 if (devinfo
->gen
< 8)
553 if (inst_is_send(devinfo
, inst
))
556 unsigned opcode
= brw_inst_opcode(devinfo
, inst
);
557 const struct opcode_desc
*desc
= brw_opcode_desc(devinfo
, opcode
);
561 /* FIXME: support 3-src instructions */
562 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
563 assert(num_sources
< 3);
565 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
566 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
568 if (num_sources
== 1)
569 return types_are_mixed_float(src0_type
, dst_type
);
571 enum brw_reg_type src1_type
= brw_inst_src1_type(devinfo
, inst
);
573 return types_are_mixed_float(src0_type
, src1_type
) ||
574 types_are_mixed_float(src0_type
, dst_type
) ||
575 types_are_mixed_float(src1_type
, dst_type
);
579 * Returns whether an instruction is an explicit or implicit conversion
583 is_byte_conversion(const struct gen_device_info
*devinfo
,
584 const brw_inst
*inst
)
586 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
588 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
589 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
591 if (dst_type
!= src0_type
&&
592 (type_sz(dst_type
) == 1 || type_sz(src0_type
) == 1)) {
594 } else if (num_sources
> 1) {
595 enum brw_reg_type src1_type
= brw_inst_src1_type(devinfo
, inst
);
596 return dst_type
!= src1_type
&&
597 (type_sz(dst_type
) == 1 || type_sz(src1_type
) == 1);
604 * Checks restrictions listed in "General Restrictions Based on Operand Types"
605 * in the "Register Region Restrictions" section.
608 general_restrictions_based_on_operand_types(const struct gen_device_info
*devinfo
,
609 const brw_inst
*inst
)
611 const struct opcode_desc
*desc
=
612 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
613 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
614 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
615 struct string error_msg
= { .str
= NULL
, .len
= 0 };
617 if (devinfo
->gen
>= 11) {
618 if (num_sources
== 3) {
619 ERROR_IF(brw_reg_type_to_size(brw_inst_3src_a1_src1_type(devinfo
, inst
)) == 1 ||
620 brw_reg_type_to_size(brw_inst_3src_a1_src2_type(devinfo
, inst
)) == 1,
621 "Byte data type is not supported for src1/2 register regioning. This includes "
622 "byte broadcast as well.");
624 if (num_sources
== 2) {
625 ERROR_IF(brw_reg_type_to_size(brw_inst_src1_type(devinfo
, inst
)) == 1,
626 "Byte data type is not supported for src1 register regioning. This includes "
627 "byte broadcast as well.");
631 if (num_sources
== 3)
634 if (inst_is_send(devinfo
, inst
))
645 * Where n is the largest element size in bytes for any source or
646 * destination operand type, ExecSize * n must be <= 64.
648 * But we do not attempt to enforce it, because it is implied by other
651 * - that the destination stride must match the execution data type
652 * - sources may not span more than two adjacent GRF registers
653 * - destination may not span more than two adjacent GRF registers
655 * In fact, checking it would weaken testing of the other rules.
658 unsigned dst_stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
659 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
660 bool dst_type_is_byte
=
661 brw_inst_dst_type(devinfo
, inst
) == BRW_REGISTER_TYPE_B
||
662 brw_inst_dst_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UB
;
664 if (dst_type_is_byte
) {
665 if (is_packed(exec_size
* dst_stride
, exec_size
, dst_stride
)) {
666 if (!inst_is_raw_move(devinfo
, inst
))
667 ERROR("Only raw MOV supports a packed-byte destination");
672 unsigned exec_type
= execution_type(devinfo
, inst
);
673 unsigned exec_type_size
= brw_reg_type_to_size(exec_type
);
674 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
676 /* On IVB/BYT, region parameters and execution size for DF are in terms of
677 * 32-bit elements, so they are doubled. For evaluating the validity of an
678 * instruction, we halve them.
680 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
681 exec_type_size
== 8 && dst_type_size
== 4)
684 if (is_byte_conversion(devinfo
, inst
)) {
685 /* From the BDW+ PRM, Volume 2a, Command Reference, Instructions - MOV:
687 * "There is no direct conversion from B/UB to DF or DF to B/UB.
688 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB."
690 * Even if these restrictions are listed for the MOV instruction, we
691 * validate this more generally, since there is the possibility
692 * of implicit conversions from other instructions.
694 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
695 enum brw_reg_type src1_type
= num_sources
> 1 ?
696 brw_inst_src1_type(devinfo
, inst
) : 0;
698 ERROR_IF(type_sz(dst_type
) == 1 &&
699 (type_sz(src0_type
) == 8 ||
700 (num_sources
> 1 && type_sz(src1_type
) == 8)),
701 "There are no direct conversions between 64-bit types and B/UB");
703 ERROR_IF(type_sz(dst_type
) == 8 &&
704 (type_sz(src0_type
) == 1 ||
705 (num_sources
> 1 && type_sz(src1_type
) == 1)),
706 "There are no direct conversions between 64-bit types and B/UB");
709 if (is_half_float_conversion(devinfo
, inst
)) {
711 * A helper to validate used in the validation of the following restriction
712 * from the BDW+ PRM, Volume 2a, Command Reference, Instructions - MOV:
714 * "There is no direct conversion from HF to DF or DF to HF.
715 * There is no direct conversion from HF to Q/UQ or Q/UQ to HF."
717 * Even if these restrictions are listed for the MOV instruction, we
718 * validate this more generally, since there is the possibility
719 * of implicit conversions from other instructions, such us implicit
720 * conversion from integer to HF with the ADD instruction in SKL+.
722 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
723 enum brw_reg_type src1_type
= num_sources
> 1 ?
724 brw_inst_src1_type(devinfo
, inst
) : 0;
725 ERROR_IF(dst_type
== BRW_REGISTER_TYPE_HF
&&
726 (type_sz(src0_type
) == 8 ||
727 (num_sources
> 1 && type_sz(src1_type
) == 8)),
728 "There are no direct conversions between 64-bit types and HF");
730 ERROR_IF(type_sz(dst_type
) == 8 &&
731 (src0_type
== BRW_REGISTER_TYPE_HF
||
732 (num_sources
> 1 && src1_type
== BRW_REGISTER_TYPE_HF
)),
733 "There are no direct conversions between 64-bit types and HF");
735 /* From the BDW+ PRM:
737 * "Conversion between Integer and HF (Half Float) must be
738 * DWord-aligned and strided by a DWord on the destination."
740 * Also, the above restrictions seems to be expanded on CHV and SKL+ by:
742 * "There is a relaxed alignment rule for word destinations. When
743 * the destination type is word (UW, W, HF), destination data types
744 * can be aligned to either the lowest word or the second lowest
745 * word of the execution channel. This means the destination data
746 * words can be either all in the even word locations or all in the
747 * odd word locations."
749 * We do not implement the second rule as is though, since empirical
750 * testing shows inconsistencies:
751 * - It suggests that packed 16-bit is not allowed, which is not true.
752 * - It suggests that conversions from Q/DF to W (which need to be
753 * 64-bit aligned on the destination) are not possible, which is
756 * So from this rule we only validate the implication that conversions
757 * from F to HF need to be DWord strided (except in Align1 mixed
758 * float mode where packed fp16 destination is allowed so long as the
759 * destination is oword-aligned).
761 * Finally, we only validate this for Align1 because Align16 always
762 * requires packed destinations, so these restrictions can't possibly
763 * apply to Align16 mode.
765 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
) {
766 if ((dst_type
== BRW_REGISTER_TYPE_HF
&&
767 (brw_reg_type_is_integer(src0_type
) ||
768 (num_sources
> 1 && brw_reg_type_is_integer(src1_type
)))) ||
769 (brw_reg_type_is_integer(dst_type
) &&
770 (src0_type
== BRW_REGISTER_TYPE_HF
||
771 (num_sources
> 1 && src1_type
== BRW_REGISTER_TYPE_HF
)))) {
772 ERROR_IF(dst_stride
* dst_type_size
!= 4,
773 "Conversions between integer and half-float must be "
774 "strided by a DWord on the destination");
776 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
777 ERROR_IF(subreg
% 4 != 0,
778 "Conversions between integer and half-float must be "
779 "aligned to a DWord on the destination");
780 } else if ((devinfo
->is_cherryview
|| devinfo
->gen
>= 9) &&
781 dst_type
== BRW_REGISTER_TYPE_HF
) {
782 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
783 ERROR_IF(dst_stride
!= 2 &&
784 !(is_mixed_float(devinfo
, inst
) &&
785 dst_stride
== 1 && subreg
% 16 == 0),
786 "Conversions to HF must have either all words in even "
787 "word locations or all words in odd word locations or "
788 "be mixed-float with Oword-aligned packed destination");
793 /* There are special regioning rules for mixed-float mode in CHV and SKL that
794 * override the general rule for the ratio of sizes of the destination type
795 * and the execution type. We will add validation for those in a later patch.
797 bool validate_dst_size_and_exec_size_ratio
=
798 !is_mixed_float(devinfo
, inst
) ||
799 !(devinfo
->is_cherryview
|| devinfo
->gen
>= 9);
801 if (validate_dst_size_and_exec_size_ratio
&&
802 exec_type_size
> dst_type_size
) {
803 if (!(dst_type_is_byte
&& inst_is_raw_move(devinfo
, inst
))) {
804 ERROR_IF(dst_stride
* dst_type_size
!= exec_type_size
,
805 "Destination stride must be equal to the ratio of the sizes "
806 "of the execution data type to the destination type");
809 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
811 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
812 brw_inst_dst_address_mode(devinfo
, inst
) == BRW_ADDRESS_DIRECT
) {
813 /* The i965 PRM says:
815 * Implementation Restriction: The relaxed alignment rule for byte
816 * destination (#10.5) is not supported.
818 if ((devinfo
->gen
> 4 || devinfo
->is_g4x
) && dst_type_is_byte
) {
819 ERROR_IF(subreg
% exec_type_size
!= 0 &&
820 subreg
% exec_type_size
!= 1,
821 "Destination subreg must be aligned to the size of the "
822 "execution data type (or to the next lowest byte for byte "
825 ERROR_IF(subreg
% exec_type_size
!= 0,
826 "Destination subreg must be aligned to the size of the "
827 "execution data type");
836 * Checks restrictions listed in "General Restrictions on Regioning Parameters"
837 * in the "Register Region Restrictions" section.
840 general_restrictions_on_region_parameters(const struct gen_device_info
*devinfo
,
841 const brw_inst
*inst
)
843 const struct opcode_desc
*desc
=
844 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
845 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
846 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
847 struct string error_msg
= { .str
= NULL
, .len
= 0 };
849 if (num_sources
== 3)
850 return (struct string
){};
852 /* Split sends don't have the bits in the instruction to encode regions so
853 * there's nothing to check.
855 if (inst_is_split_send(devinfo
, inst
))
856 return (struct string
){};
858 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
) {
859 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
))
860 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) != BRW_HORIZONTAL_STRIDE_1
,
861 "Destination Horizontal Stride must be 1");
863 if (num_sources
>= 1) {
864 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
865 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
866 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
867 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
868 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
869 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
871 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
872 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
873 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
874 "In Align16 mode, only VertStride of 0 or 4 is allowed");
878 if (num_sources
== 2) {
879 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
880 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
881 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
882 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
883 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
884 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
886 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
887 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
888 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
889 "In Align16 mode, only VertStride of 0 or 4 is allowed");
896 for (unsigned i
= 0; i
< num_sources
; i
++) {
897 unsigned vstride
, width
, hstride
, element_size
, subreg
;
898 enum brw_reg_type type
;
901 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
902 BRW_IMMEDIATE_VALUE) \
905 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
906 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
907 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
908 type = brw_inst_src ## n ## _type(devinfo, inst); \
909 element_size = brw_reg_type_to_size(type); \
910 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst)
919 /* On IVB/BYT, region parameters and execution size for DF are in terms of
920 * 32-bit elements, so they are doubled. For evaluating the validity of an
921 * instruction, we halve them.
923 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
927 /* ExecSize must be greater than or equal to Width. */
928 ERROR_IF(exec_size
< width
, "ExecSize must be greater than or equal "
931 /* If ExecSize = Width and HorzStride ≠ 0,
932 * VertStride must be set to Width * HorzStride.
934 if (exec_size
== width
&& hstride
!= 0) {
935 ERROR_IF(vstride
!= width
* hstride
,
936 "If ExecSize = Width and HorzStride ≠ 0, "
937 "VertStride must be set to Width * HorzStride");
940 /* If Width = 1, HorzStride must be 0 regardless of the values of
941 * ExecSize and VertStride.
944 ERROR_IF(hstride
!= 0,
945 "If Width = 1, HorzStride must be 0 regardless "
946 "of the values of ExecSize and VertStride");
949 /* If ExecSize = Width = 1, both VertStride and HorzStride must be 0. */
950 if (exec_size
== 1 && width
== 1) {
951 ERROR_IF(vstride
!= 0 || hstride
!= 0,
952 "If ExecSize = Width = 1, both VertStride "
953 "and HorzStride must be 0");
956 /* If VertStride = HorzStride = 0, Width must be 1 regardless of the
959 if (vstride
== 0 && hstride
== 0) {
961 "If VertStride = HorzStride = 0, Width must be "
962 "1 regardless of the value of ExecSize");
965 /* VertStride must be used to cross GRF register boundaries. This rule
966 * implies that elements within a 'Width' cannot cross GRF boundaries.
968 const uint64_t mask
= (1ULL << element_size
) - 1;
969 unsigned rowbase
= subreg
;
971 for (int y
= 0; y
< exec_size
/ width
; y
++) {
972 uint64_t access_mask
= 0;
973 unsigned offset
= rowbase
;
975 for (int x
= 0; x
< width
; x
++) {
976 access_mask
|= mask
<< offset
;
977 offset
+= hstride
* element_size
;
980 rowbase
+= vstride
* element_size
;
982 if ((uint32_t)access_mask
!= 0 && (access_mask
>> 32) != 0) {
983 ERROR("VertStride must be used to cross GRF register boundaries");
989 /* Dst.HorzStride must not be 0. */
990 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
)) {
991 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
,
992 "Destination Horizontal Stride must not be 0");
999 special_restrictions_for_mixed_float_mode(const struct gen_device_info
*devinfo
,
1000 const brw_inst
*inst
)
1002 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1004 const unsigned opcode
= brw_inst_opcode(devinfo
, inst
);
1005 const unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1006 if (num_sources
>= 3)
1009 if (!is_mixed_float(devinfo
, inst
))
1012 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
1013 bool is_align16
= brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
;
1015 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
1016 enum brw_reg_type src1_type
= num_sources
> 1 ?
1017 brw_inst_src1_type(devinfo
, inst
) : 0;
1018 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1020 unsigned dst_stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
1021 bool dst_is_packed
= is_packed(exec_size
* dst_stride
, exec_size
, dst_stride
);
1023 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1026 * "Indirect addressing on source is not supported when source and
1027 * destination data types are mixed float."
1029 ERROR_IF(brw_inst_src0_address_mode(devinfo
, inst
) != BRW_ADDRESS_DIRECT
||
1031 brw_inst_src1_address_mode(devinfo
, inst
) != BRW_ADDRESS_DIRECT
),
1032 "Indirect addressing on source is not supported when source and "
1033 "destination data types are mixed float");
1035 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1038 * "No SIMD16 in mixed mode when destination is f32. Instruction
1039 * execution size must be no more than 8."
1041 ERROR_IF(exec_size
> 8 && dst_type
== BRW_REGISTER_TYPE_F
,
1042 "Mixed float mode with 32-bit float destination is limited "
1046 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1049 * "In Align16 mode, when half float and float data types are mixed
1050 * between source operands OR between source and destination operands,
1051 * the register content are assumed to be packed."
1053 * Since Align16 doesn't have a concept of horizontal stride (or width),
1054 * it means that vertical stride must always be 4, since 0 and 2 would
1055 * lead to replicated data, and any other value is disallowed in Align16.
1057 ERROR_IF(brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
1058 "Align16 mixed float mode assumes packed data (vstride must be 4");
1060 ERROR_IF(num_sources
>= 2 &&
1061 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
1062 "Align16 mixed float mode assumes packed data (vstride must be 4");
1064 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1067 * "For Align16 mixed mode, both input and output packed f16 data
1068 * must be oword aligned, no oword crossing in packed f16."
1070 * The previous rule requires that Align16 operands are always packed,
1071 * and since there is only one bit for Align16 subnr, which represents
1072 * offsets 0B and 16B, this rule is always enforced and we don't need to
1076 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1079 * "No SIMD16 in mixed mode when destination is packed f16 for both
1080 * Align1 and Align16."
1084 * "In Align16 mode, when half float and float data types are mixed
1085 * between source operands OR between source and destination operands,
1086 * the register content are assumed to be packed."
1088 * Which implies that SIMD16 is not available in Align16. This is further
1091 * "For Align16 mixed mode, both input and output packed f16 data
1092 * must be oword aligned, no oword crossing in packed f16"
1094 * Since oword-aligned packed f16 data would cross oword boundaries when
1095 * the execution size is larger than 8.
1097 ERROR_IF(exec_size
> 8, "Align16 mixed float mode is limited to SIMD8");
1099 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1102 * "No accumulator read access for Align16 mixed float."
1104 ERROR_IF(inst_uses_src_acc(devinfo
, inst
),
1105 "No accumulator read access for Align16 mixed float");
1107 assert(!is_align16
);
1109 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1112 * "No SIMD16 in mixed mode when destination is packed f16 for both
1113 * Align1 and Align16."
1115 ERROR_IF(exec_size
> 8 && dst_is_packed
&&
1116 dst_type
== BRW_REGISTER_TYPE_HF
,
1117 "Align1 mixed float mode is limited to SIMD8 when destination "
1118 "is packed half-float");
1120 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1123 * "Math operations for mixed mode:
1124 * - In Align1, f16 inputs need to be strided"
1126 if (opcode
== BRW_OPCODE_MATH
) {
1127 if (src0_type
== BRW_REGISTER_TYPE_HF
) {
1128 ERROR_IF(STRIDE(brw_inst_src0_hstride(devinfo
, inst
)) <= 1,
1129 "Align1 mixed mode math needs strided half-float inputs");
1132 if (num_sources
>= 2 && src1_type
== BRW_REGISTER_TYPE_HF
) {
1133 ERROR_IF(STRIDE(brw_inst_src1_hstride(devinfo
, inst
)) <= 1,
1134 "Align1 mixed mode math needs strided half-float inputs");
1138 if (dst_type
== BRW_REGISTER_TYPE_HF
&& dst_stride
== 1) {
1139 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1142 * "In Align1, destination stride can be smaller than execution
1143 * type. When destination is stride of 1, 16 bit packed data is
1144 * updated on the destination. However, output packed f16 data
1145 * must be oword aligned, no oword crossing in packed f16."
1147 * The requirement of not crossing oword boundaries for 16-bit oword
1148 * aligned data means that execution size is limited to 8.
1151 if (brw_inst_dst_address_mode(devinfo
, inst
) == BRW_ADDRESS_DIRECT
)
1152 subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
1154 subreg
= brw_inst_dst_ia_subreg_nr(devinfo
, inst
);
1155 ERROR_IF(subreg
% 16 != 0,
1156 "Align1 mixed mode packed half-float output must be "
1158 ERROR_IF(exec_size
> 8,
1159 "Align1 mixed mode packed half-float output must not "
1160 "cross oword boundaries (max exec size is 8)");
1162 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1165 * "When source is float or half float from accumulator register and
1166 * destination is half float with a stride of 1, the source must
1167 * register aligned. i.e., source must have offset zero."
1169 * Align16 mixed float mode doesn't allow accumulator access on sources,
1170 * so we only need to check this for Align1.
1172 if (src0_is_acc(devinfo
, inst
) &&
1173 (src0_type
== BRW_REGISTER_TYPE_F
||
1174 src0_type
== BRW_REGISTER_TYPE_HF
)) {
1175 ERROR_IF(brw_inst_src0_da1_subreg_nr(devinfo
, inst
) != 0,
1176 "Mixed float mode requires register-aligned accumulator "
1177 "source reads when destination is packed half-float");
1181 if (num_sources
> 1 &&
1182 src1_is_acc(devinfo
, inst
) &&
1183 (src1_type
== BRW_REGISTER_TYPE_F
||
1184 src1_type
== BRW_REGISTER_TYPE_HF
)) {
1185 ERROR_IF(brw_inst_src1_da1_subreg_nr(devinfo
, inst
) != 0,
1186 "Mixed float mode requires register-aligned accumulator "
1187 "source reads when destination is packed half-float");
1191 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1194 * "No swizzle is allowed when an accumulator is used as an implicit
1195 * source or an explicit source in an instruction. i.e. when
1196 * destination is half float with an implicit accumulator source,
1197 * destination stride needs to be 2."
1199 * FIXME: it is not quite clear what the first sentence actually means
1200 * or its link to the implication described after it, so we only
1201 * validate the explicit implication, which is clearly described.
1203 if (dst_type
== BRW_REGISTER_TYPE_HF
&&
1204 inst_uses_src_acc(devinfo
, inst
)) {
1205 ERROR_IF(dst_stride
!= 2,
1206 "Mixed float mode with implicit/explicit accumulator "
1207 "source and half-float destination requires a stride "
1208 "of 2 on the destination");
1216 * Creates an \p access_mask for an \p exec_size, \p element_size, and a region
1218 * An \p access_mask is a 32-element array of uint64_t, where each uint64_t is
1219 * a bitmask of bytes accessed by the region.
1221 * For instance the access mask of the source gX.1<4,2,2>F in an exec_size = 4
1222 * instruction would be
1224 * access_mask[0] = 0x00000000000000F0
1225 * access_mask[1] = 0x000000000000F000
1226 * access_mask[2] = 0x0000000000F00000
1227 * access_mask[3] = 0x00000000F0000000
1228 * access_mask[4-31] = 0
1230 * because the first execution channel accesses bytes 7-4 and the second
1231 * execution channel accesses bytes 15-12, etc.
1234 align1_access_mask(uint64_t access_mask
[static 32],
1235 unsigned exec_size
, unsigned element_size
, unsigned subreg
,
1236 unsigned vstride
, unsigned width
, unsigned hstride
)
1238 const uint64_t mask
= (1ULL << element_size
) - 1;
1239 unsigned rowbase
= subreg
;
1240 unsigned element
= 0;
1242 for (int y
= 0; y
< exec_size
/ width
; y
++) {
1243 unsigned offset
= rowbase
;
1245 for (int x
= 0; x
< width
; x
++) {
1246 access_mask
[element
++] = mask
<< offset
;
1247 offset
+= hstride
* element_size
;
1250 rowbase
+= vstride
* element_size
;
1253 assert(element
== 0 || element
== exec_size
);
1257 * Returns the number of registers accessed according to the \p access_mask
1260 registers_read(const uint64_t access_mask
[static 32])
1264 for (unsigned i
= 0; i
< 32; i
++) {
1265 if (access_mask
[i
] > 0xFFFFFFFF) {
1267 } else if (access_mask
[i
]) {
1276 * Checks restrictions listed in "Region Alignment Rules" in the "Register
1277 * Region Restrictions" section.
1279 static struct string
1280 region_alignment_rules(const struct gen_device_info
*devinfo
,
1281 const brw_inst
*inst
)
1283 const struct opcode_desc
*desc
=
1284 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
1285 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1286 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
1287 uint64_t dst_access_mask
[32], src0_access_mask
[32], src1_access_mask
[32];
1288 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1290 if (num_sources
== 3)
1291 return (struct string
){};
1293 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
)
1294 return (struct string
){};
1296 if (inst_is_send(devinfo
, inst
))
1297 return (struct string
){};
1299 memset(dst_access_mask
, 0, sizeof(dst_access_mask
));
1300 memset(src0_access_mask
, 0, sizeof(src0_access_mask
));
1301 memset(src1_access_mask
, 0, sizeof(src1_access_mask
));
1303 for (unsigned i
= 0; i
< num_sources
; i
++) {
1304 unsigned vstride
, width
, hstride
, element_size
, subreg
;
1305 enum brw_reg_type type
;
1307 /* In Direct Addressing mode, a source cannot span more than 2 adjacent
1312 if (brw_inst_src ## n ## _address_mode(devinfo, inst) != \
1313 BRW_ADDRESS_DIRECT) \
1316 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
1317 BRW_IMMEDIATE_VALUE) \
1320 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
1321 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
1322 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
1323 type = brw_inst_src ## n ## _type(devinfo, inst); \
1324 element_size = brw_reg_type_to_size(type); \
1325 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
1326 align1_access_mask(src ## n ## _access_mask, \
1327 exec_size, element_size, subreg, \
1328 vstride, width, hstride)
1337 unsigned num_vstride
= exec_size
/ width
;
1338 unsigned num_hstride
= width
;
1339 unsigned vstride_elements
= (num_vstride
- 1) * vstride
;
1340 unsigned hstride_elements
= (num_hstride
- 1) * hstride
;
1341 unsigned offset
= (vstride_elements
+ hstride_elements
) * element_size
+
1343 ERROR_IF(offset
>= 64,
1344 "A source cannot span more than 2 adjacent GRF registers");
1347 if (desc
->ndst
== 0 || dst_is_null(devinfo
, inst
))
1350 unsigned stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
1351 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1352 unsigned element_size
= brw_reg_type_to_size(dst_type
);
1353 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
1354 unsigned offset
= ((exec_size
- 1) * stride
* element_size
) + subreg
;
1355 ERROR_IF(offset
>= 64,
1356 "A destination cannot span more than 2 adjacent GRF registers");
1361 /* On IVB/BYT, region parameters and execution size for DF are in terms of
1362 * 32-bit elements, so they are doubled. For evaluating the validity of an
1363 * instruction, we halve them.
1365 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1369 align1_access_mask(dst_access_mask
, exec_size
, element_size
, subreg
,
1370 exec_size
== 1 ? 0 : exec_size
* stride
,
1371 exec_size
== 1 ? 1 : exec_size
,
1372 exec_size
== 1 ? 0 : stride
);
1374 unsigned dst_regs
= registers_read(dst_access_mask
);
1375 unsigned src0_regs
= registers_read(src0_access_mask
);
1376 unsigned src1_regs
= registers_read(src1_access_mask
);
1378 /* The SNB, IVB, HSW, BDW, and CHV PRMs say:
1380 * When an instruction has a source region spanning two registers and a
1381 * destination region contained in one register, the number of elements
1382 * must be the same between two sources and one of the following must be
1385 * 1. The destination region is entirely contained in the lower OWord
1387 * 2. The destination region is entirely contained in the upper OWord
1389 * 3. The destination elements are evenly split between the two OWords
1392 if (devinfo
->gen
<= 8) {
1393 if (dst_regs
== 1 && (src0_regs
== 2 || src1_regs
== 2)) {
1394 unsigned upper_oword_writes
= 0, lower_oword_writes
= 0;
1396 for (unsigned i
= 0; i
< exec_size
; i
++) {
1397 if (dst_access_mask
[i
] > 0x0000FFFF) {
1398 upper_oword_writes
++;
1400 assert(dst_access_mask
[i
] != 0);
1401 lower_oword_writes
++;
1405 ERROR_IF(lower_oword_writes
!= 0 &&
1406 upper_oword_writes
!= 0 &&
1407 upper_oword_writes
!= lower_oword_writes
,
1408 "Writes must be to only one OWord or "
1409 "evenly split between OWords");
1413 /* The IVB and HSW PRMs say:
1415 * When an instruction has a source region that spans two registers and
1416 * the destination spans two registers, the destination elements must be
1417 * evenly split between the two registers [...]
1419 * The SNB PRM contains similar wording (but written in a much more
1420 * confusing manner).
1424 * When destination spans two registers, the source may be one or two
1425 * registers. The destination elements must be evenly split between the
1430 * When destination of MATH instruction spans two registers, the
1431 * destination elements must be evenly split between the two registers.
1433 * It is not known whether this restriction applies to KBL other Gens after
1436 if (devinfo
->gen
<= 8 ||
1437 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
1439 /* Nothing explicitly states that on Gen < 8 elements must be evenly
1440 * split between two destination registers in the two exceptional
1441 * source-region-spans-one-register cases, but since Broadwell requires
1442 * evenly split writes regardless of source region, we assume that it was
1443 * an oversight and require it.
1445 if (dst_regs
== 2) {
1446 unsigned upper_reg_writes
= 0, lower_reg_writes
= 0;
1448 for (unsigned i
= 0; i
< exec_size
; i
++) {
1449 if (dst_access_mask
[i
] > 0xFFFFFFFF) {
1452 assert(dst_access_mask
[i
] != 0);
1457 ERROR_IF(upper_reg_writes
!= lower_reg_writes
,
1458 "Writes must be evenly split between the two "
1459 "destination registers");
1463 /* The IVB and HSW PRMs say:
1465 * When an instruction has a source region that spans two registers and
1466 * the destination spans two registers, the destination elements must be
1467 * evenly split between the two registers and each destination register
1468 * must be entirely derived from one source register.
1470 * Note: In such cases, the regioning parameters must ensure that the
1471 * offset from the two source registers is the same.
1473 * The SNB PRM contains similar wording (but written in a much more
1474 * confusing manner).
1476 * There are effectively three rules stated here:
1478 * For an instruction with a source and a destination spanning two
1481 * (1) destination elements must be evenly split between the two
1483 * (2) all destination elements in a register must be derived
1484 * from one source register
1485 * (3) the offset (i.e. the starting location in each of the two
1486 * registers spanned by a region) must be the same in the two
1487 * registers spanned by a region
1489 * It is impossible to violate rule (1) without violating (2) or (3), so we
1490 * do not attempt to validate it.
1492 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
1493 for (unsigned i
= 0; i
< num_sources
; i
++) {
1495 if (src ## n ## _regs <= 1) \
1498 for (unsigned i = 0; i < exec_size; i++) { \
1499 if ((dst_access_mask[i] > 0xFFFFFFFF) != \
1500 (src ## n ## _access_mask[i] > 0xFFFFFFFF)) { \
1501 ERROR("Each destination register must be entirely derived " \
1502 "from one source register"); \
1507 unsigned offset_0 = \
1508 brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
1509 unsigned offset_1 = offset_0; \
1511 for (unsigned i = 0; i < exec_size; i++) { \
1512 if (src ## n ## _access_mask[i] > 0xFFFFFFFF) { \
1513 offset_1 = __builtin_ctzll(src ## n ## _access_mask[i]) - 32; \
1518 ERROR_IF(num_sources == 2 && offset_0 != offset_1, \
1519 "The offset from the two source registers " \
1531 /* The IVB and HSW PRMs say:
1533 * When destination spans two registers, the source MUST span two
1534 * registers. The exception to the above rule:
1535 * 1. When source is scalar, the source registers are not
1537 * 2. When source is packed integer Word and destination is packed
1538 * integer DWord, the source register is not incremented by the
1539 * source sub register is incremented.
1541 * The SNB PRM does not contain this rule, but the internal documentation
1542 * indicates that it applies to SNB as well. We assume that the rule applies
1543 * to Gen <= 5 although their PRMs do not state it.
1545 * While the documentation explicitly says in exception (2) that the
1546 * destination must be an integer DWord, the hardware allows at least a
1547 * float destination type as well. We emit such instructions from
1549 * fs_visitor::emit_interpolation_setup_gen6
1550 * fs_visitor::emit_fragcoord_interpolation
1552 * and have for years with no ill effects.
1554 * Additionally the simulator source code indicates that the real condition
1555 * is that the size of the destination type is 4 bytes.
1557 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
1558 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1559 bool dst_is_packed_dword
=
1560 is_packed(exec_size
* stride
, exec_size
, stride
) &&
1561 brw_reg_type_to_size(dst_type
) == 4;
1563 for (unsigned i
= 0; i
< num_sources
; i
++) {
1565 unsigned vstride, width, hstride; \
1566 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
1567 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
1568 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
1569 bool src ## n ## _is_packed_word = \
1570 is_packed(vstride, width, hstride) && \
1571 (brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_W || \
1572 brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_UW); \
1574 ERROR_IF(src ## n ## _regs == 1 && \
1575 !src ## n ## _has_scalar_region(devinfo, inst) && \
1576 !(dst_is_packed_dword && src ## n ## _is_packed_word), \
1577 "When the destination spans two registers, the source must " \
1578 "span two registers\n" ERROR_INDENT "(exceptions for scalar " \
1579 "source and packed-word to packed-dword expansion)")
1593 static struct string
1594 vector_immediate_restrictions(const struct gen_device_info
*devinfo
,
1595 const brw_inst
*inst
)
1597 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1598 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1600 if (num_sources
== 3 || num_sources
== 0)
1601 return (struct string
){};
1603 unsigned file
= num_sources
== 1 ?
1604 brw_inst_src0_reg_file(devinfo
, inst
) :
1605 brw_inst_src1_reg_file(devinfo
, inst
);
1606 if (file
!= BRW_IMMEDIATE_VALUE
)
1607 return (struct string
){};
1609 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1610 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
1611 unsigned dst_subreg
= brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
?
1612 brw_inst_dst_da1_subreg_nr(devinfo
, inst
) : 0;
1613 unsigned dst_stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
1614 enum brw_reg_type type
= num_sources
== 1 ?
1615 brw_inst_src0_type(devinfo
, inst
) :
1616 brw_inst_src1_type(devinfo
, inst
);
1620 * When an immediate vector is used in an instruction, the destination
1621 * must be 128-bit aligned with destination horizontal stride equivalent
1622 * to a word for an immediate integer vector (v) and equivalent to a
1623 * DWord for an immediate float vector (vf).
1625 * The text has not been updated for the addition of the immediate unsigned
1626 * integer vector type (uv) on SNB, but presumably the same restriction
1630 case BRW_REGISTER_TYPE_V
:
1631 case BRW_REGISTER_TYPE_UV
:
1632 case BRW_REGISTER_TYPE_VF
:
1633 ERROR_IF(dst_subreg
% (128 / 8) != 0,
1634 "Destination must be 128-bit aligned in order to use immediate "
1637 if (type
== BRW_REGISTER_TYPE_VF
) {
1638 ERROR_IF(dst_type_size
* dst_stride
!= 4,
1639 "Destination must have stride equivalent to dword in order "
1640 "to use the VF type");
1642 ERROR_IF(dst_type_size
* dst_stride
!= 2,
1643 "Destination must have stride equivalent to word in order "
1644 "to use the V or UV type");
1654 static struct string
1655 special_requirements_for_handling_double_precision_data_types(
1656 const struct gen_device_info
*devinfo
,
1657 const brw_inst
*inst
)
1659 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1660 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1662 if (num_sources
== 3 || num_sources
== 0)
1663 return (struct string
){};
1665 /* Split sends don't have types so there's no doubles there. */
1666 if (inst_is_split_send(devinfo
, inst
))
1667 return (struct string
){};
1669 enum brw_reg_type exec_type
= execution_type(devinfo
, inst
);
1670 unsigned exec_type_size
= brw_reg_type_to_size(exec_type
);
1672 enum brw_reg_file dst_file
= brw_inst_dst_reg_file(devinfo
, inst
);
1673 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1674 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
1675 unsigned dst_hstride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
1676 unsigned dst_reg
= brw_inst_dst_da_reg_nr(devinfo
, inst
);
1677 unsigned dst_subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
1678 unsigned dst_address_mode
= brw_inst_dst_address_mode(devinfo
, inst
);
1680 bool is_integer_dword_multiply
=
1681 devinfo
->gen
>= 8 &&
1682 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MUL
&&
1683 (brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_D
||
1684 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UD
) &&
1685 (brw_inst_src1_type(devinfo
, inst
) == BRW_REGISTER_TYPE_D
||
1686 brw_inst_src1_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UD
);
1688 if (dst_type_size
!= 8 && exec_type_size
!= 8 && !is_integer_dword_multiply
)
1689 return (struct string
){};
1691 for (unsigned i
= 0; i
< num_sources
; i
++) {
1692 unsigned vstride
, width
, hstride
, type_size
, reg
, subreg
, address_mode
;
1693 bool is_scalar_region
;
1694 enum brw_reg_file file
;
1695 enum brw_reg_type type
;
1698 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
1699 BRW_IMMEDIATE_VALUE) \
1702 is_scalar_region = src ## n ## _has_scalar_region(devinfo, inst); \
1703 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
1704 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
1705 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
1706 file = brw_inst_src ## n ## _reg_file(devinfo, inst); \
1707 type = brw_inst_src ## n ## _type(devinfo, inst); \
1708 type_size = brw_reg_type_to_size(type); \
1709 reg = brw_inst_src ## n ## _da_reg_nr(devinfo, inst); \
1710 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
1711 address_mode = brw_inst_src ## n ## _address_mode(devinfo, inst)
1720 /* The PRMs say that for CHV, BXT:
1722 * When source or destination datatype is 64b or operation is integer
1723 * DWord multiply, regioning in Align1 must follow these rules:
1725 * 1. Source and Destination horizontal stride must be aligned to the
1727 * 2. Regioning must ensure Src.Vstride = Src.Width * Src.Hstride.
1728 * 3. Source and Destination offset must be the same, except the case
1731 * We assume that the restriction applies to GLK as well.
1733 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
1734 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
1735 unsigned src_stride
= hstride
* type_size
;
1736 unsigned dst_stride
= dst_hstride
* dst_type_size
;
1738 ERROR_IF(!is_scalar_region
&&
1739 (src_stride
% 8 != 0 ||
1740 dst_stride
% 8 != 0 ||
1741 src_stride
!= dst_stride
),
1742 "Source and destination horizontal stride must equal and a "
1743 "multiple of a qword when the execution type is 64-bit");
1745 ERROR_IF(vstride
!= width
* hstride
,
1746 "Vstride must be Width * Hstride when the execution type is "
1749 ERROR_IF(!is_scalar_region
&& dst_subreg
!= subreg
,
1750 "Source and destination offset must be the same when the "
1751 "execution type is 64-bit");
1754 /* The PRMs say that for CHV, BXT:
1756 * When source or destination datatype is 64b or operation is integer
1757 * DWord multiply, indirect addressing must not be used.
1759 * We assume that the restriction applies to GLK as well.
1761 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1762 ERROR_IF(BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
== address_mode
||
1763 BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
== dst_address_mode
,
1764 "Indirect addressing is not allowed when the execution type "
1768 /* The PRMs say that for CHV, BXT:
1770 * ARF registers must never be used with 64b datatype or when
1771 * operation is integer DWord multiply.
1773 * We assume that the restriction applies to GLK as well.
1775 * We assume that the restriction does not apply to the null register.
1777 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1778 ERROR_IF(brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MAC
||
1779 brw_inst_acc_wr_control(devinfo
, inst
) ||
1780 (BRW_ARCHITECTURE_REGISTER_FILE
== file
&&
1781 reg
!= BRW_ARF_NULL
) ||
1782 (BRW_ARCHITECTURE_REGISTER_FILE
== dst_file
&&
1783 dst_reg
!= BRW_ARF_NULL
),
1784 "Architecture registers cannot be used when the execution "
1789 /* The PRMs say that for BDW, SKL:
1791 * If Align16 is required for an operation with QW destination and non-QW
1792 * source datatypes, the execution size cannot exceed 2.
1794 * We assume that the restriction applies to all Gen8+ parts.
1796 if (devinfo
->gen
>= 8) {
1797 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
1798 enum brw_reg_type src1_type
=
1799 num_sources
> 1 ? brw_inst_src1_type(devinfo
, inst
) : src0_type
;
1800 unsigned src0_type_size
= brw_reg_type_to_size(src0_type
);
1801 unsigned src1_type_size
= brw_reg_type_to_size(src1_type
);
1803 ERROR_IF(brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
&&
1804 dst_type_size
== 8 &&
1805 (src0_type_size
!= 8 || src1_type_size
!= 8) &&
1806 brw_inst_exec_size(devinfo
, inst
) > BRW_EXECUTE_2
,
1807 "In Align16 exec size cannot exceed 2 with a QWord destination "
1808 "and a non-QWord source");
1811 /* The PRMs say that for CHV, BXT:
1813 * When source or destination datatype is 64b or operation is integer
1814 * DWord multiply, DepCtrl must not be used.
1816 * We assume that the restriction applies to GLK as well.
1818 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1819 ERROR_IF(brw_inst_no_dd_check(devinfo
, inst
) ||
1820 brw_inst_no_dd_clear(devinfo
, inst
),
1821 "DepCtrl is not allowed when the execution type is 64-bit");
1827 static struct string
1828 instruction_restrictions(const struct gen_device_info
*devinfo
,
1829 const brw_inst
*inst
)
1831 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1833 /* From GEN:BUG:1604601757:
1835 * "When multiplying a DW and any lower precision integer, source modifier
1836 * is not supported."
1838 if (devinfo
->gen
>= 12 &&
1839 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MUL
) {
1840 enum brw_reg_type exec_type
= execution_type(devinfo
, inst
);
1841 const bool src0_valid
= type_sz(brw_inst_src0_type(devinfo
, inst
)) == 4 ||
1842 brw_inst_src0_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
||
1843 !(brw_inst_src0_negate(devinfo
, inst
) ||
1844 brw_inst_src0_abs(devinfo
, inst
));
1845 const bool src1_valid
= type_sz(brw_inst_src1_type(devinfo
, inst
)) == 4 ||
1846 brw_inst_src1_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
||
1847 !(brw_inst_src1_negate(devinfo
, inst
) ||
1848 brw_inst_src1_abs(devinfo
, inst
));
1850 ERROR_IF(!brw_reg_type_is_floating_point(exec_type
) &&
1851 type_sz(exec_type
) == 4 && !(src0_valid
&& src1_valid
),
1852 "When multiplying a DW and any lower precision integer, source "
1853 "modifier is not supported.");
1860 brw_validate_instructions(const struct gen_device_info
*devinfo
,
1861 const void *assembly
, int start_offset
, int end_offset
,
1862 struct disasm_info
*disasm
)
1866 for (int src_offset
= start_offset
; src_offset
< end_offset
;) {
1867 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1868 const brw_inst
*inst
= assembly
+ src_offset
;
1869 bool is_compact
= brw_inst_cmpt_control(devinfo
, inst
);
1870 brw_inst uncompacted
;
1873 brw_compact_inst
*compacted
= (void *)inst
;
1874 brw_uncompact_instruction(devinfo
, &uncompacted
, compacted
);
1875 inst
= &uncompacted
;
1878 if (is_unsupported_inst(devinfo
, inst
)) {
1879 ERROR("Instruction not supported on this Gen");
1881 CHECK(sources_not_null
);
1882 CHECK(send_restrictions
);
1883 CHECK(alignment_supported
);
1884 CHECK(general_restrictions_based_on_operand_types
);
1885 CHECK(general_restrictions_on_region_parameters
);
1886 CHECK(special_restrictions_for_mixed_float_mode
);
1887 CHECK(region_alignment_rules
);
1888 CHECK(vector_immediate_restrictions
);
1889 CHECK(special_requirements_for_handling_double_precision_data_types
);
1890 CHECK(instruction_restrictions
);
1893 if (error_msg
.str
&& disasm
) {
1894 disasm_insert_error(disasm
, src_offset
, error_msg
.str
);
1896 valid
= valid
&& error_msg
.len
== 0;
1897 free(error_msg
.str
);
1900 src_offset
+= sizeof(brw_compact_inst
);
1902 src_offset
+= sizeof(brw_inst
);