2 * Copyright © 2015-2019 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_eu_validate.c
26 * This file implements a pass that validates shader assembly.
28 * The restrictions implemented herein are intended to verify that instructions
29 * in shader assembly do not violate restrictions documented in the graphics
30 * programming reference manuals.
32 * The restrictions are difficult for humans to quickly verify due to their
33 * complexity and abundance.
35 * It is critical that this code is thoroughly unit tested because false
36 * results will lead developers astray, which is worse than having no validator
37 * at all. Functional changes to this file without corresponding unit tests (in
38 * test_eu_validate.cpp) will be rejected.
43 /* We're going to do lots of string concatenation, so this should help. */
50 cat(struct string
*dest
, const struct string src
)
52 dest
->str
= realloc(dest
->str
, dest
->len
+ src
.len
+ 1);
53 memcpy(dest
->str
+ dest
->len
, src
.str
, src
.len
);
54 dest
->str
[dest
->len
+ src
.len
] = '\0';
55 dest
->len
= dest
->len
+ src
.len
;
57 #define CAT(dest, src) cat(&dest, (struct string){src, strlen(src)})
60 contains(const struct string haystack
, const struct string needle
)
62 return haystack
.str
&& memmem(haystack
.str
, haystack
.len
,
63 needle
.str
, needle
.len
) != NULL
;
65 #define CONTAINS(haystack, needle) \
66 contains(haystack, (struct string){needle, strlen(needle)})
68 #define error(str) "\tERROR: " str "\n"
69 #define ERROR_INDENT "\t "
71 #define ERROR(msg) ERROR_IF(true, msg)
72 #define ERROR_IF(cond, msg) \
74 if ((cond) && !CONTAINS(error_msg, error(msg))) { \
75 CAT(error_msg, error(msg)); \
79 #define CHECK(func, args...) \
81 struct string __msg = func(devinfo, inst, ##args); \
83 cat(&error_msg, __msg); \
88 #define STRIDE(stride) (stride != 0 ? 1 << ((stride) - 1) : 0)
89 #define WIDTH(width) (1 << (width))
92 inst_is_send(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
94 switch (brw_inst_opcode(devinfo
, inst
)) {
96 case BRW_OPCODE_SENDC
:
97 case BRW_OPCODE_SENDS
:
98 case BRW_OPCODE_SENDSC
:
106 inst_is_split_send(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
108 if (devinfo
->gen
>= 12) {
109 return inst_is_send(devinfo
, inst
);
111 switch (brw_inst_opcode(devinfo
, inst
)) {
112 case BRW_OPCODE_SENDS
:
113 case BRW_OPCODE_SENDSC
:
122 signed_type(unsigned type
)
125 case BRW_REGISTER_TYPE_UD
: return BRW_REGISTER_TYPE_D
;
126 case BRW_REGISTER_TYPE_UW
: return BRW_REGISTER_TYPE_W
;
127 case BRW_REGISTER_TYPE_UB
: return BRW_REGISTER_TYPE_B
;
128 case BRW_REGISTER_TYPE_UQ
: return BRW_REGISTER_TYPE_Q
;
129 default: return type
;
133 static enum brw_reg_type
134 inst_dst_type(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
136 return (devinfo
->gen
< 12 || !inst_is_send(devinfo
, inst
)) ?
137 brw_inst_dst_type(devinfo
, inst
) : BRW_REGISTER_TYPE_D
;
141 inst_is_raw_move(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
143 unsigned dst_type
= signed_type(inst_dst_type(devinfo
, inst
));
144 unsigned src_type
= signed_type(brw_inst_src0_type(devinfo
, inst
));
146 if (brw_inst_src0_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
) {
147 /* FIXME: not strictly true */
148 if (brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_VF
||
149 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UV
||
150 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_V
) {
153 } else if (brw_inst_src0_negate(devinfo
, inst
) ||
154 brw_inst_src0_abs(devinfo
, inst
)) {
158 return brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MOV
&&
159 brw_inst_saturate(devinfo
, inst
) == 0 &&
160 dst_type
== src_type
;
164 dst_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
166 return brw_inst_dst_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
167 brw_inst_dst_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
171 src0_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
173 return brw_inst_src0_address_mode(devinfo
, inst
) == BRW_ADDRESS_DIRECT
&&
174 brw_inst_src0_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
175 brw_inst_src0_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
179 src1_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
181 return brw_inst_src1_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
182 brw_inst_src1_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
186 src0_is_acc(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
188 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
189 (brw_inst_src0_da_reg_nr(devinfo
, inst
) & 0xF0) == BRW_ARF_ACCUMULATOR
;
193 src1_is_acc(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
195 return brw_inst_src1_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
196 (brw_inst_src1_da_reg_nr(devinfo
, inst
) & 0xF0) == BRW_ARF_ACCUMULATOR
;
200 src0_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
202 return brw_inst_src0_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
203 brw_inst_src0_width(devinfo
, inst
) == BRW_WIDTH_1
&&
204 brw_inst_src0_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
208 src1_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
210 return brw_inst_src1_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
211 brw_inst_src1_width(devinfo
, inst
) == BRW_WIDTH_1
&&
212 brw_inst_src1_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
216 num_sources_from_inst(const struct gen_device_info
*devinfo
,
217 const brw_inst
*inst
)
219 const struct opcode_desc
*desc
=
220 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
221 unsigned math_function
;
223 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
224 math_function
= brw_inst_math_function(devinfo
, inst
);
225 } else if (devinfo
->gen
< 6 &&
226 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
227 if (brw_inst_sfid(devinfo
, inst
) == BRW_SFID_MATH
) {
228 /* src1 must be a descriptor (including the information to determine
229 * that the SEND is doing an extended math operation), but src0 can
230 * actually be null since it serves as the source of the implicit GRF
233 * If we stop using that functionality, we'll have to revisit this.
237 /* Send instructions are allowed to have null sources since they use
238 * the base_mrf field to specify which message register source.
243 assert(desc
->nsrc
< 4);
247 switch (math_function
) {
248 case BRW_MATH_FUNCTION_INV
:
249 case BRW_MATH_FUNCTION_LOG
:
250 case BRW_MATH_FUNCTION_EXP
:
251 case BRW_MATH_FUNCTION_SQRT
:
252 case BRW_MATH_FUNCTION_RSQ
:
253 case BRW_MATH_FUNCTION_SIN
:
254 case BRW_MATH_FUNCTION_COS
:
255 case BRW_MATH_FUNCTION_SINCOS
:
256 case GEN8_MATH_FUNCTION_INVM
:
257 case GEN8_MATH_FUNCTION_RSQRTM
:
259 case BRW_MATH_FUNCTION_FDIV
:
260 case BRW_MATH_FUNCTION_POW
:
261 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
:
262 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
:
263 case BRW_MATH_FUNCTION_INT_DIV_REMAINDER
:
266 unreachable("not reached");
271 sources_not_null(const struct gen_device_info
*devinfo
,
272 const brw_inst
*inst
)
274 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
275 struct string error_msg
= { .str
= NULL
, .len
= 0 };
277 /* Nothing to test. 3-src instructions can only have GRF sources, and
278 * there's no bit to control the file.
280 if (num_sources
== 3)
281 return (struct string
){};
283 /* Nothing to test. Split sends can only encode a file in sources that are
284 * allowed to be NULL.
286 if (inst_is_split_send(devinfo
, inst
))
287 return (struct string
){};
289 if (num_sources
>= 1 && brw_inst_opcode(devinfo
, inst
) != BRW_OPCODE_SYNC
)
290 ERROR_IF(src0_is_null(devinfo
, inst
), "src0 is null");
292 if (num_sources
== 2)
293 ERROR_IF(src1_is_null(devinfo
, inst
), "src1 is null");
299 alignment_supported(const struct gen_device_info
*devinfo
,
300 const brw_inst
*inst
)
302 struct string error_msg
= { .str
= NULL
, .len
= 0 };
304 ERROR_IF(devinfo
->gen
>= 11 && brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
,
305 "Align16 not supported");
311 inst_uses_src_acc(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
313 /* Check instructions that use implicit accumulator sources */
314 switch (brw_inst_opcode(devinfo
, inst
)) {
316 case BRW_OPCODE_MACH
:
317 case BRW_OPCODE_SADA2
:
323 /* FIXME: support 3-src instructions */
324 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
325 assert(num_sources
< 3);
327 return src0_is_acc(devinfo
, inst
) || (num_sources
> 1 && src1_is_acc(devinfo
, inst
));
331 send_restrictions(const struct gen_device_info
*devinfo
,
332 const brw_inst
*inst
)
334 struct string error_msg
= { .str
= NULL
, .len
= 0 };
336 if (inst_is_split_send(devinfo
, inst
)) {
337 ERROR_IF(brw_inst_send_src1_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
338 brw_inst_send_src1_reg_nr(devinfo
, inst
) != BRW_ARF_NULL
,
339 "src1 of split send must be a GRF or NULL");
341 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
342 brw_inst_src0_da_reg_nr(devinfo
, inst
) < 112,
343 "send with EOT must use g112-g127");
344 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
345 brw_inst_send_src1_reg_file(devinfo
, inst
) == BRW_GENERAL_REGISTER_FILE
&&
346 brw_inst_send_src1_reg_nr(devinfo
, inst
) < 112,
347 "send with EOT must use g112-g127");
349 if (brw_inst_send_src1_reg_file(devinfo
, inst
) == BRW_GENERAL_REGISTER_FILE
) {
350 /* Assume minimums if we don't know */
352 if (!brw_inst_send_sel_reg32_desc(devinfo
, inst
)) {
353 const uint32_t desc
= brw_inst_send_desc(devinfo
, inst
);
354 mlen
= brw_message_desc_mlen(devinfo
, desc
);
357 unsigned ex_mlen
= 1;
358 if (!brw_inst_send_sel_reg32_ex_desc(devinfo
, inst
)) {
359 const uint32_t ex_desc
= brw_inst_sends_ex_desc(devinfo
, inst
);
360 ex_mlen
= brw_message_ex_desc_ex_mlen(devinfo
, ex_desc
);
362 const unsigned src0_reg_nr
= brw_inst_src0_da_reg_nr(devinfo
, inst
);
363 const unsigned src1_reg_nr
= brw_inst_send_src1_reg_nr(devinfo
, inst
);
364 ERROR_IF((src0_reg_nr
<= src1_reg_nr
&&
365 src1_reg_nr
< src0_reg_nr
+ mlen
) ||
366 (src1_reg_nr
<= src0_reg_nr
&&
367 src0_reg_nr
< src1_reg_nr
+ ex_mlen
),
368 "split send payloads must not overlap");
370 } else if (inst_is_send(devinfo
, inst
)) {
371 ERROR_IF(brw_inst_src0_address_mode(devinfo
, inst
) != BRW_ADDRESS_DIRECT
,
372 "send must use direct addressing");
374 if (devinfo
->gen
>= 7) {
375 ERROR_IF(brw_inst_send_src0_reg_file(devinfo
, inst
) != BRW_GENERAL_REGISTER_FILE
,
376 "send from non-GRF");
377 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
378 brw_inst_src0_da_reg_nr(devinfo
, inst
) < 112,
379 "send with EOT must use g112-g127");
382 if (devinfo
->gen
>= 8) {
383 ERROR_IF(!dst_is_null(devinfo
, inst
) &&
384 (brw_inst_dst_da_reg_nr(devinfo
, inst
) +
385 brw_inst_rlen(devinfo
, inst
) > 127) &&
386 (brw_inst_src0_da_reg_nr(devinfo
, inst
) +
387 brw_inst_mlen(devinfo
, inst
) >
388 brw_inst_dst_da_reg_nr(devinfo
, inst
)),
389 "r127 must not be used for return address when there is "
390 "a src and dest overlap");
398 is_unsupported_inst(const struct gen_device_info
*devinfo
,
399 const brw_inst
*inst
)
401 return brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_ILLEGAL
;
405 * Returns whether a combination of two types would qualify as mixed float
409 types_are_mixed_float(enum brw_reg_type t0
, enum brw_reg_type t1
)
411 return (t0
== BRW_REGISTER_TYPE_F
&& t1
== BRW_REGISTER_TYPE_HF
) ||
412 (t1
== BRW_REGISTER_TYPE_F
&& t0
== BRW_REGISTER_TYPE_HF
);
415 static enum brw_reg_type
416 execution_type_for_type(enum brw_reg_type type
)
419 case BRW_REGISTER_TYPE_NF
:
420 case BRW_REGISTER_TYPE_DF
:
421 case BRW_REGISTER_TYPE_F
:
422 case BRW_REGISTER_TYPE_HF
:
425 case BRW_REGISTER_TYPE_VF
:
426 return BRW_REGISTER_TYPE_F
;
428 case BRW_REGISTER_TYPE_Q
:
429 case BRW_REGISTER_TYPE_UQ
:
430 return BRW_REGISTER_TYPE_Q
;
432 case BRW_REGISTER_TYPE_D
:
433 case BRW_REGISTER_TYPE_UD
:
434 return BRW_REGISTER_TYPE_D
;
436 case BRW_REGISTER_TYPE_W
:
437 case BRW_REGISTER_TYPE_UW
:
438 case BRW_REGISTER_TYPE_B
:
439 case BRW_REGISTER_TYPE_UB
:
440 case BRW_REGISTER_TYPE_V
:
441 case BRW_REGISTER_TYPE_UV
:
442 return BRW_REGISTER_TYPE_W
;
444 unreachable("not reached");
448 * Returns the execution type of an instruction \p inst
450 static enum brw_reg_type
451 execution_type(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
453 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
454 enum brw_reg_type src0_exec_type
, src1_exec_type
;
456 /* Execution data type is independent of destination data type, except in
457 * mixed F/HF instructions.
459 enum brw_reg_type dst_exec_type
= inst_dst_type(devinfo
, inst
);
461 src0_exec_type
= execution_type_for_type(brw_inst_src0_type(devinfo
, inst
));
462 if (num_sources
== 1) {
463 if (src0_exec_type
== BRW_REGISTER_TYPE_HF
)
464 return dst_exec_type
;
465 return src0_exec_type
;
468 src1_exec_type
= execution_type_for_type(brw_inst_src1_type(devinfo
, inst
));
469 if (types_are_mixed_float(src0_exec_type
, src1_exec_type
) ||
470 types_are_mixed_float(src0_exec_type
, dst_exec_type
) ||
471 types_are_mixed_float(src1_exec_type
, dst_exec_type
)) {
472 return BRW_REGISTER_TYPE_F
;
475 if (src0_exec_type
== src1_exec_type
)
476 return src0_exec_type
;
478 if (src0_exec_type
== BRW_REGISTER_TYPE_NF
||
479 src1_exec_type
== BRW_REGISTER_TYPE_NF
)
480 return BRW_REGISTER_TYPE_NF
;
482 /* Mixed operand types where one is float is float on Gen < 6
483 * (and not allowed on later platforms)
485 if (devinfo
->gen
< 6 &&
486 (src0_exec_type
== BRW_REGISTER_TYPE_F
||
487 src1_exec_type
== BRW_REGISTER_TYPE_F
))
488 return BRW_REGISTER_TYPE_F
;
490 if (src0_exec_type
== BRW_REGISTER_TYPE_Q
||
491 src1_exec_type
== BRW_REGISTER_TYPE_Q
)
492 return BRW_REGISTER_TYPE_Q
;
494 if (src0_exec_type
== BRW_REGISTER_TYPE_D
||
495 src1_exec_type
== BRW_REGISTER_TYPE_D
)
496 return BRW_REGISTER_TYPE_D
;
498 if (src0_exec_type
== BRW_REGISTER_TYPE_W
||
499 src1_exec_type
== BRW_REGISTER_TYPE_W
)
500 return BRW_REGISTER_TYPE_W
;
502 if (src0_exec_type
== BRW_REGISTER_TYPE_DF
||
503 src1_exec_type
== BRW_REGISTER_TYPE_DF
)
504 return BRW_REGISTER_TYPE_DF
;
506 unreachable("not reached");
510 * Returns whether a region is packed
512 * A region is packed if its elements are adjacent in memory, with no
513 * intervening space, no overlap, and no replicated values.
516 is_packed(unsigned vstride
, unsigned width
, unsigned hstride
)
518 if (vstride
== width
) {
530 * Returns whether an instruction is an explicit or implicit conversion
531 * to/from half-float.
534 is_half_float_conversion(const struct gen_device_info
*devinfo
,
535 const brw_inst
*inst
)
537 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
539 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
540 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
542 if (dst_type
!= src0_type
&&
543 (dst_type
== BRW_REGISTER_TYPE_HF
|| src0_type
== BRW_REGISTER_TYPE_HF
)) {
545 } else if (num_sources
> 1) {
546 enum brw_reg_type src1_type
= brw_inst_src1_type(devinfo
, inst
);
547 return dst_type
!= src1_type
&&
548 (dst_type
== BRW_REGISTER_TYPE_HF
||
549 src1_type
== BRW_REGISTER_TYPE_HF
);
556 * Returns whether an instruction is using mixed float operation mode
559 is_mixed_float(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
561 if (devinfo
->gen
< 8)
564 if (inst_is_send(devinfo
, inst
))
567 unsigned opcode
= brw_inst_opcode(devinfo
, inst
);
568 const struct opcode_desc
*desc
= brw_opcode_desc(devinfo
, opcode
);
572 /* FIXME: support 3-src instructions */
573 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
574 assert(num_sources
< 3);
576 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
577 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
579 if (num_sources
== 1)
580 return types_are_mixed_float(src0_type
, dst_type
);
582 enum brw_reg_type src1_type
= brw_inst_src1_type(devinfo
, inst
);
584 return types_are_mixed_float(src0_type
, src1_type
) ||
585 types_are_mixed_float(src0_type
, dst_type
) ||
586 types_are_mixed_float(src1_type
, dst_type
);
590 * Returns whether an instruction is an explicit or implicit conversion
594 is_byte_conversion(const struct gen_device_info
*devinfo
,
595 const brw_inst
*inst
)
597 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
599 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
600 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
602 if (dst_type
!= src0_type
&&
603 (type_sz(dst_type
) == 1 || type_sz(src0_type
) == 1)) {
605 } else if (num_sources
> 1) {
606 enum brw_reg_type src1_type
= brw_inst_src1_type(devinfo
, inst
);
607 return dst_type
!= src1_type
&&
608 (type_sz(dst_type
) == 1 || type_sz(src1_type
) == 1);
615 * Checks restrictions listed in "General Restrictions Based on Operand Types"
616 * in the "Register Region Restrictions" section.
619 general_restrictions_based_on_operand_types(const struct gen_device_info
*devinfo
,
620 const brw_inst
*inst
)
622 const struct opcode_desc
*desc
=
623 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
624 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
625 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
626 struct string error_msg
= { .str
= NULL
, .len
= 0 };
628 if (devinfo
->gen
>= 11) {
629 if (num_sources
== 3) {
630 ERROR_IF(brw_reg_type_to_size(brw_inst_3src_a1_src1_type(devinfo
, inst
)) == 1 ||
631 brw_reg_type_to_size(brw_inst_3src_a1_src2_type(devinfo
, inst
)) == 1,
632 "Byte data type is not supported for src1/2 register regioning. This includes "
633 "byte broadcast as well.");
635 if (num_sources
== 2) {
636 ERROR_IF(brw_reg_type_to_size(brw_inst_src1_type(devinfo
, inst
)) == 1,
637 "Byte data type is not supported for src1 register regioning. This includes "
638 "byte broadcast as well.");
642 if (num_sources
== 3)
645 if (inst_is_send(devinfo
, inst
))
656 * Where n is the largest element size in bytes for any source or
657 * destination operand type, ExecSize * n must be <= 64.
659 * But we do not attempt to enforce it, because it is implied by other
662 * - that the destination stride must match the execution data type
663 * - sources may not span more than two adjacent GRF registers
664 * - destination may not span more than two adjacent GRF registers
666 * In fact, checking it would weaken testing of the other rules.
669 unsigned dst_stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
670 enum brw_reg_type dst_type
= inst_dst_type(devinfo
, inst
);
671 bool dst_type_is_byte
=
672 inst_dst_type(devinfo
, inst
) == BRW_REGISTER_TYPE_B
||
673 inst_dst_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UB
;
675 if (dst_type_is_byte
) {
676 if (is_packed(exec_size
* dst_stride
, exec_size
, dst_stride
)) {
677 if (!inst_is_raw_move(devinfo
, inst
))
678 ERROR("Only raw MOV supports a packed-byte destination");
683 unsigned exec_type
= execution_type(devinfo
, inst
);
684 unsigned exec_type_size
= brw_reg_type_to_size(exec_type
);
685 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
687 /* On IVB/BYT, region parameters and execution size for DF are in terms of
688 * 32-bit elements, so they are doubled. For evaluating the validity of an
689 * instruction, we halve them.
691 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
692 exec_type_size
== 8 && dst_type_size
== 4)
695 if (is_byte_conversion(devinfo
, inst
)) {
696 /* From the BDW+ PRM, Volume 2a, Command Reference, Instructions - MOV:
698 * "There is no direct conversion from B/UB to DF or DF to B/UB.
699 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB."
701 * Even if these restrictions are listed for the MOV instruction, we
702 * validate this more generally, since there is the possibility
703 * of implicit conversions from other instructions.
705 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
706 enum brw_reg_type src1_type
= num_sources
> 1 ?
707 brw_inst_src1_type(devinfo
, inst
) : 0;
709 ERROR_IF(type_sz(dst_type
) == 1 &&
710 (type_sz(src0_type
) == 8 ||
711 (num_sources
> 1 && type_sz(src1_type
) == 8)),
712 "There are no direct conversions between 64-bit types and B/UB");
714 ERROR_IF(type_sz(dst_type
) == 8 &&
715 (type_sz(src0_type
) == 1 ||
716 (num_sources
> 1 && type_sz(src1_type
) == 1)),
717 "There are no direct conversions between 64-bit types and B/UB");
720 if (is_half_float_conversion(devinfo
, inst
)) {
722 * A helper to validate used in the validation of the following restriction
723 * from the BDW+ PRM, Volume 2a, Command Reference, Instructions - MOV:
725 * "There is no direct conversion from HF to DF or DF to HF.
726 * There is no direct conversion from HF to Q/UQ or Q/UQ to HF."
728 * Even if these restrictions are listed for the MOV instruction, we
729 * validate this more generally, since there is the possibility
730 * of implicit conversions from other instructions, such us implicit
731 * conversion from integer to HF with the ADD instruction in SKL+.
733 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
734 enum brw_reg_type src1_type
= num_sources
> 1 ?
735 brw_inst_src1_type(devinfo
, inst
) : 0;
736 ERROR_IF(dst_type
== BRW_REGISTER_TYPE_HF
&&
737 (type_sz(src0_type
) == 8 ||
738 (num_sources
> 1 && type_sz(src1_type
) == 8)),
739 "There are no direct conversions between 64-bit types and HF");
741 ERROR_IF(type_sz(dst_type
) == 8 &&
742 (src0_type
== BRW_REGISTER_TYPE_HF
||
743 (num_sources
> 1 && src1_type
== BRW_REGISTER_TYPE_HF
)),
744 "There are no direct conversions between 64-bit types and HF");
746 /* From the BDW+ PRM:
748 * "Conversion between Integer and HF (Half Float) must be
749 * DWord-aligned and strided by a DWord on the destination."
751 * Also, the above restrictions seems to be expanded on CHV and SKL+ by:
753 * "There is a relaxed alignment rule for word destinations. When
754 * the destination type is word (UW, W, HF), destination data types
755 * can be aligned to either the lowest word or the second lowest
756 * word of the execution channel. This means the destination data
757 * words can be either all in the even word locations or all in the
758 * odd word locations."
760 * We do not implement the second rule as is though, since empirical
761 * testing shows inconsistencies:
762 * - It suggests that packed 16-bit is not allowed, which is not true.
763 * - It suggests that conversions from Q/DF to W (which need to be
764 * 64-bit aligned on the destination) are not possible, which is
767 * So from this rule we only validate the implication that conversions
768 * from F to HF need to be DWord strided (except in Align1 mixed
769 * float mode where packed fp16 destination is allowed so long as the
770 * destination is oword-aligned).
772 * Finally, we only validate this for Align1 because Align16 always
773 * requires packed destinations, so these restrictions can't possibly
774 * apply to Align16 mode.
776 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
) {
777 if ((dst_type
== BRW_REGISTER_TYPE_HF
&&
778 (brw_reg_type_is_integer(src0_type
) ||
779 (num_sources
> 1 && brw_reg_type_is_integer(src1_type
)))) ||
780 (brw_reg_type_is_integer(dst_type
) &&
781 (src0_type
== BRW_REGISTER_TYPE_HF
||
782 (num_sources
> 1 && src1_type
== BRW_REGISTER_TYPE_HF
)))) {
783 ERROR_IF(dst_stride
* dst_type_size
!= 4,
784 "Conversions between integer and half-float must be "
785 "strided by a DWord on the destination");
787 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
788 ERROR_IF(subreg
% 4 != 0,
789 "Conversions between integer and half-float must be "
790 "aligned to a DWord on the destination");
791 } else if ((devinfo
->is_cherryview
|| devinfo
->gen
>= 9) &&
792 dst_type
== BRW_REGISTER_TYPE_HF
) {
793 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
794 ERROR_IF(dst_stride
!= 2 &&
795 !(is_mixed_float(devinfo
, inst
) &&
796 dst_stride
== 1 && subreg
% 16 == 0),
797 "Conversions to HF must have either all words in even "
798 "word locations or all words in odd word locations or "
799 "be mixed-float with Oword-aligned packed destination");
804 /* There are special regioning rules for mixed-float mode in CHV and SKL that
805 * override the general rule for the ratio of sizes of the destination type
806 * and the execution type. We will add validation for those in a later patch.
808 bool validate_dst_size_and_exec_size_ratio
=
809 !is_mixed_float(devinfo
, inst
) ||
810 !(devinfo
->is_cherryview
|| devinfo
->gen
>= 9);
812 if (validate_dst_size_and_exec_size_ratio
&&
813 exec_type_size
> dst_type_size
) {
814 if (!(dst_type_is_byte
&& inst_is_raw_move(devinfo
, inst
))) {
815 ERROR_IF(dst_stride
* dst_type_size
!= exec_type_size
,
816 "Destination stride must be equal to the ratio of the sizes "
817 "of the execution data type to the destination type");
820 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
822 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
823 brw_inst_dst_address_mode(devinfo
, inst
) == BRW_ADDRESS_DIRECT
) {
824 /* The i965 PRM says:
826 * Implementation Restriction: The relaxed alignment rule for byte
827 * destination (#10.5) is not supported.
829 if ((devinfo
->gen
> 4 || devinfo
->is_g4x
) && dst_type_is_byte
) {
830 ERROR_IF(subreg
% exec_type_size
!= 0 &&
831 subreg
% exec_type_size
!= 1,
832 "Destination subreg must be aligned to the size of the "
833 "execution data type (or to the next lowest byte for byte "
836 ERROR_IF(subreg
% exec_type_size
!= 0,
837 "Destination subreg must be aligned to the size of the "
838 "execution data type");
847 * Checks restrictions listed in "General Restrictions on Regioning Parameters"
848 * in the "Register Region Restrictions" section.
851 general_restrictions_on_region_parameters(const struct gen_device_info
*devinfo
,
852 const brw_inst
*inst
)
854 const struct opcode_desc
*desc
=
855 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
856 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
857 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
858 struct string error_msg
= { .str
= NULL
, .len
= 0 };
860 if (num_sources
== 3)
861 return (struct string
){};
863 /* Split sends don't have the bits in the instruction to encode regions so
864 * there's nothing to check.
866 if (inst_is_split_send(devinfo
, inst
))
867 return (struct string
){};
869 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
) {
870 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
))
871 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) != BRW_HORIZONTAL_STRIDE_1
,
872 "Destination Horizontal Stride must be 1");
874 if (num_sources
>= 1) {
875 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
876 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
877 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
878 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
879 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
880 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
882 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
883 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
884 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
885 "In Align16 mode, only VertStride of 0 or 4 is allowed");
889 if (num_sources
== 2) {
890 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
891 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
892 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
893 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
894 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
895 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
897 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
898 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
899 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
900 "In Align16 mode, only VertStride of 0 or 4 is allowed");
907 for (unsigned i
= 0; i
< num_sources
; i
++) {
908 unsigned vstride
, width
, hstride
, element_size
, subreg
;
909 enum brw_reg_type type
;
912 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
913 BRW_IMMEDIATE_VALUE) \
916 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
917 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
918 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
919 type = brw_inst_src ## n ## _type(devinfo, inst); \
920 element_size = brw_reg_type_to_size(type); \
921 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst)
930 /* On IVB/BYT, region parameters and execution size for DF are in terms of
931 * 32-bit elements, so they are doubled. For evaluating the validity of an
932 * instruction, we halve them.
934 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
938 /* ExecSize must be greater than or equal to Width. */
939 ERROR_IF(exec_size
< width
, "ExecSize must be greater than or equal "
942 /* If ExecSize = Width and HorzStride ≠ 0,
943 * VertStride must be set to Width * HorzStride.
945 if (exec_size
== width
&& hstride
!= 0) {
946 ERROR_IF(vstride
!= width
* hstride
,
947 "If ExecSize = Width and HorzStride ≠ 0, "
948 "VertStride must be set to Width * HorzStride");
951 /* If Width = 1, HorzStride must be 0 regardless of the values of
952 * ExecSize and VertStride.
955 ERROR_IF(hstride
!= 0,
956 "If Width = 1, HorzStride must be 0 regardless "
957 "of the values of ExecSize and VertStride");
960 /* If ExecSize = Width = 1, both VertStride and HorzStride must be 0. */
961 if (exec_size
== 1 && width
== 1) {
962 ERROR_IF(vstride
!= 0 || hstride
!= 0,
963 "If ExecSize = Width = 1, both VertStride "
964 "and HorzStride must be 0");
967 /* If VertStride = HorzStride = 0, Width must be 1 regardless of the
970 if (vstride
== 0 && hstride
== 0) {
972 "If VertStride = HorzStride = 0, Width must be "
973 "1 regardless of the value of ExecSize");
976 /* VertStride must be used to cross GRF register boundaries. This rule
977 * implies that elements within a 'Width' cannot cross GRF boundaries.
979 const uint64_t mask
= (1ULL << element_size
) - 1;
980 unsigned rowbase
= subreg
;
982 for (int y
= 0; y
< exec_size
/ width
; y
++) {
983 uint64_t access_mask
= 0;
984 unsigned offset
= rowbase
;
986 for (int x
= 0; x
< width
; x
++) {
987 access_mask
|= mask
<< (offset
% 64);
988 offset
+= hstride
* element_size
;
991 rowbase
+= vstride
* element_size
;
993 if ((uint32_t)access_mask
!= 0 && (access_mask
>> 32) != 0) {
994 ERROR("VertStride must be used to cross GRF register boundaries");
1000 /* Dst.HorzStride must not be 0. */
1001 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
)) {
1002 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
,
1003 "Destination Horizontal Stride must not be 0");
1009 static struct string
1010 special_restrictions_for_mixed_float_mode(const struct gen_device_info
*devinfo
,
1011 const brw_inst
*inst
)
1013 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1015 const unsigned opcode
= brw_inst_opcode(devinfo
, inst
);
1016 const unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1017 if (num_sources
>= 3)
1020 if (!is_mixed_float(devinfo
, inst
))
1023 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
1024 bool is_align16
= brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
;
1026 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
1027 enum brw_reg_type src1_type
= num_sources
> 1 ?
1028 brw_inst_src1_type(devinfo
, inst
) : 0;
1029 enum brw_reg_type dst_type
= brw_inst_dst_type(devinfo
, inst
);
1031 unsigned dst_stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
1032 bool dst_is_packed
= is_packed(exec_size
* dst_stride
, exec_size
, dst_stride
);
1034 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1037 * "Indirect addressing on source is not supported when source and
1038 * destination data types are mixed float."
1040 ERROR_IF(brw_inst_src0_address_mode(devinfo
, inst
) != BRW_ADDRESS_DIRECT
||
1042 brw_inst_src1_address_mode(devinfo
, inst
) != BRW_ADDRESS_DIRECT
),
1043 "Indirect addressing on source is not supported when source and "
1044 "destination data types are mixed float");
1046 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1049 * "No SIMD16 in mixed mode when destination is f32. Instruction
1050 * execution size must be no more than 8."
1052 ERROR_IF(exec_size
> 8 && dst_type
== BRW_REGISTER_TYPE_F
,
1053 "Mixed float mode with 32-bit float destination is limited "
1057 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1060 * "In Align16 mode, when half float and float data types are mixed
1061 * between source operands OR between source and destination operands,
1062 * the register content are assumed to be packed."
1064 * Since Align16 doesn't have a concept of horizontal stride (or width),
1065 * it means that vertical stride must always be 4, since 0 and 2 would
1066 * lead to replicated data, and any other value is disallowed in Align16.
1068 ERROR_IF(brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
1069 "Align16 mixed float mode assumes packed data (vstride must be 4");
1071 ERROR_IF(num_sources
>= 2 &&
1072 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
1073 "Align16 mixed float mode assumes packed data (vstride must be 4");
1075 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1078 * "For Align16 mixed mode, both input and output packed f16 data
1079 * must be oword aligned, no oword crossing in packed f16."
1081 * The previous rule requires that Align16 operands are always packed,
1082 * and since there is only one bit for Align16 subnr, which represents
1083 * offsets 0B and 16B, this rule is always enforced and we don't need to
1087 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1090 * "No SIMD16 in mixed mode when destination is packed f16 for both
1091 * Align1 and Align16."
1095 * "In Align16 mode, when half float and float data types are mixed
1096 * between source operands OR between source and destination operands,
1097 * the register content are assumed to be packed."
1099 * Which implies that SIMD16 is not available in Align16. This is further
1102 * "For Align16 mixed mode, both input and output packed f16 data
1103 * must be oword aligned, no oword crossing in packed f16"
1105 * Since oword-aligned packed f16 data would cross oword boundaries when
1106 * the execution size is larger than 8.
1108 ERROR_IF(exec_size
> 8, "Align16 mixed float mode is limited to SIMD8");
1110 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1113 * "No accumulator read access for Align16 mixed float."
1115 ERROR_IF(inst_uses_src_acc(devinfo
, inst
),
1116 "No accumulator read access for Align16 mixed float");
1118 assert(!is_align16
);
1120 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1123 * "No SIMD16 in mixed mode when destination is packed f16 for both
1124 * Align1 and Align16."
1126 ERROR_IF(exec_size
> 8 && dst_is_packed
&&
1127 dst_type
== BRW_REGISTER_TYPE_HF
,
1128 "Align1 mixed float mode is limited to SIMD8 when destination "
1129 "is packed half-float");
1131 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1134 * "Math operations for mixed mode:
1135 * - In Align1, f16 inputs need to be strided"
1137 if (opcode
== BRW_OPCODE_MATH
) {
1138 if (src0_type
== BRW_REGISTER_TYPE_HF
) {
1139 ERROR_IF(STRIDE(brw_inst_src0_hstride(devinfo
, inst
)) <= 1,
1140 "Align1 mixed mode math needs strided half-float inputs");
1143 if (num_sources
>= 2 && src1_type
== BRW_REGISTER_TYPE_HF
) {
1144 ERROR_IF(STRIDE(brw_inst_src1_hstride(devinfo
, inst
)) <= 1,
1145 "Align1 mixed mode math needs strided half-float inputs");
1149 if (dst_type
== BRW_REGISTER_TYPE_HF
&& dst_stride
== 1) {
1150 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1153 * "In Align1, destination stride can be smaller than execution
1154 * type. When destination is stride of 1, 16 bit packed data is
1155 * updated on the destination. However, output packed f16 data
1156 * must be oword aligned, no oword crossing in packed f16."
1158 * The requirement of not crossing oword boundaries for 16-bit oword
1159 * aligned data means that execution size is limited to 8.
1162 if (brw_inst_dst_address_mode(devinfo
, inst
) == BRW_ADDRESS_DIRECT
)
1163 subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
1165 subreg
= brw_inst_dst_ia_subreg_nr(devinfo
, inst
);
1166 ERROR_IF(subreg
% 16 != 0,
1167 "Align1 mixed mode packed half-float output must be "
1169 ERROR_IF(exec_size
> 8,
1170 "Align1 mixed mode packed half-float output must not "
1171 "cross oword boundaries (max exec size is 8)");
1173 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1176 * "When source is float or half float from accumulator register and
1177 * destination is half float with a stride of 1, the source must
1178 * register aligned. i.e., source must have offset zero."
1180 * Align16 mixed float mode doesn't allow accumulator access on sources,
1181 * so we only need to check this for Align1.
1183 if (src0_is_acc(devinfo
, inst
) &&
1184 (src0_type
== BRW_REGISTER_TYPE_F
||
1185 src0_type
== BRW_REGISTER_TYPE_HF
)) {
1186 ERROR_IF(brw_inst_src0_da1_subreg_nr(devinfo
, inst
) != 0,
1187 "Mixed float mode requires register-aligned accumulator "
1188 "source reads when destination is packed half-float");
1192 if (num_sources
> 1 &&
1193 src1_is_acc(devinfo
, inst
) &&
1194 (src1_type
== BRW_REGISTER_TYPE_F
||
1195 src1_type
== BRW_REGISTER_TYPE_HF
)) {
1196 ERROR_IF(brw_inst_src1_da1_subreg_nr(devinfo
, inst
) != 0,
1197 "Mixed float mode requires register-aligned accumulator "
1198 "source reads when destination is packed half-float");
1202 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
1205 * "No swizzle is allowed when an accumulator is used as an implicit
1206 * source or an explicit source in an instruction. i.e. when
1207 * destination is half float with an implicit accumulator source,
1208 * destination stride needs to be 2."
1210 * FIXME: it is not quite clear what the first sentence actually means
1211 * or its link to the implication described after it, so we only
1212 * validate the explicit implication, which is clearly described.
1214 if (dst_type
== BRW_REGISTER_TYPE_HF
&&
1215 inst_uses_src_acc(devinfo
, inst
)) {
1216 ERROR_IF(dst_stride
!= 2,
1217 "Mixed float mode with implicit/explicit accumulator "
1218 "source and half-float destination requires a stride "
1219 "of 2 on the destination");
1227 * Creates an \p access_mask for an \p exec_size, \p element_size, and a region
1229 * An \p access_mask is a 32-element array of uint64_t, where each uint64_t is
1230 * a bitmask of bytes accessed by the region.
1232 * For instance the access mask of the source gX.1<4,2,2>F in an exec_size = 4
1233 * instruction would be
1235 * access_mask[0] = 0x00000000000000F0
1236 * access_mask[1] = 0x000000000000F000
1237 * access_mask[2] = 0x0000000000F00000
1238 * access_mask[3] = 0x00000000F0000000
1239 * access_mask[4-31] = 0
1241 * because the first execution channel accesses bytes 7-4 and the second
1242 * execution channel accesses bytes 15-12, etc.
1245 align1_access_mask(uint64_t access_mask
[static 32],
1246 unsigned exec_size
, unsigned element_size
, unsigned subreg
,
1247 unsigned vstride
, unsigned width
, unsigned hstride
)
1249 const uint64_t mask
= (1ULL << element_size
) - 1;
1250 unsigned rowbase
= subreg
;
1251 unsigned element
= 0;
1253 for (int y
= 0; y
< exec_size
/ width
; y
++) {
1254 unsigned offset
= rowbase
;
1256 for (int x
= 0; x
< width
; x
++) {
1257 access_mask
[element
++] = mask
<< (offset
% 64);
1258 offset
+= hstride
* element_size
;
1261 rowbase
+= vstride
* element_size
;
1264 assert(element
== 0 || element
== exec_size
);
1268 * Returns the number of registers accessed according to the \p access_mask
1271 registers_read(const uint64_t access_mask
[static 32])
1275 for (unsigned i
= 0; i
< 32; i
++) {
1276 if (access_mask
[i
] > 0xFFFFFFFF) {
1278 } else if (access_mask
[i
]) {
1287 * Checks restrictions listed in "Region Alignment Rules" in the "Register
1288 * Region Restrictions" section.
1290 static struct string
1291 region_alignment_rules(const struct gen_device_info
*devinfo
,
1292 const brw_inst
*inst
)
1294 const struct opcode_desc
*desc
=
1295 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
1296 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1297 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
1298 uint64_t dst_access_mask
[32], src0_access_mask
[32], src1_access_mask
[32];
1299 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1301 if (num_sources
== 3)
1302 return (struct string
){};
1304 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
)
1305 return (struct string
){};
1307 if (inst_is_send(devinfo
, inst
))
1308 return (struct string
){};
1310 memset(dst_access_mask
, 0, sizeof(dst_access_mask
));
1311 memset(src0_access_mask
, 0, sizeof(src0_access_mask
));
1312 memset(src1_access_mask
, 0, sizeof(src1_access_mask
));
1314 for (unsigned i
= 0; i
< num_sources
; i
++) {
1315 unsigned vstride
, width
, hstride
, element_size
, subreg
;
1316 enum brw_reg_type type
;
1318 /* In Direct Addressing mode, a source cannot span more than 2 adjacent
1323 if (brw_inst_src ## n ## _address_mode(devinfo, inst) != \
1324 BRW_ADDRESS_DIRECT) \
1327 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
1328 BRW_IMMEDIATE_VALUE) \
1331 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
1332 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
1333 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
1334 type = brw_inst_src ## n ## _type(devinfo, inst); \
1335 element_size = brw_reg_type_to_size(type); \
1336 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
1337 align1_access_mask(src ## n ## _access_mask, \
1338 exec_size, element_size, subreg, \
1339 vstride, width, hstride)
1348 unsigned num_vstride
= exec_size
/ width
;
1349 unsigned num_hstride
= width
;
1350 unsigned vstride_elements
= (num_vstride
- 1) * vstride
;
1351 unsigned hstride_elements
= (num_hstride
- 1) * hstride
;
1352 unsigned offset
= (vstride_elements
+ hstride_elements
) * element_size
+
1354 ERROR_IF(offset
>= 64,
1355 "A source cannot span more than 2 adjacent GRF registers");
1358 if (desc
->ndst
== 0 || dst_is_null(devinfo
, inst
))
1361 unsigned stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
1362 enum brw_reg_type dst_type
= inst_dst_type(devinfo
, inst
);
1363 unsigned element_size
= brw_reg_type_to_size(dst_type
);
1364 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
1365 unsigned offset
= ((exec_size
- 1) * stride
* element_size
) + subreg
;
1366 ERROR_IF(offset
>= 64,
1367 "A destination cannot span more than 2 adjacent GRF registers");
1372 /* On IVB/BYT, region parameters and execution size for DF are in terms of
1373 * 32-bit elements, so they are doubled. For evaluating the validity of an
1374 * instruction, we halve them.
1376 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1380 align1_access_mask(dst_access_mask
, exec_size
, element_size
, subreg
,
1381 exec_size
== 1 ? 0 : exec_size
* stride
,
1382 exec_size
== 1 ? 1 : exec_size
,
1383 exec_size
== 1 ? 0 : stride
);
1385 unsigned dst_regs
= registers_read(dst_access_mask
);
1386 unsigned src0_regs
= registers_read(src0_access_mask
);
1387 unsigned src1_regs
= registers_read(src1_access_mask
);
1389 /* The SNB, IVB, HSW, BDW, and CHV PRMs say:
1391 * When an instruction has a source region spanning two registers and a
1392 * destination region contained in one register, the number of elements
1393 * must be the same between two sources and one of the following must be
1396 * 1. The destination region is entirely contained in the lower OWord
1398 * 2. The destination region is entirely contained in the upper OWord
1400 * 3. The destination elements are evenly split between the two OWords
1403 if (devinfo
->gen
<= 8) {
1404 if (dst_regs
== 1 && (src0_regs
== 2 || src1_regs
== 2)) {
1405 unsigned upper_oword_writes
= 0, lower_oword_writes
= 0;
1407 for (unsigned i
= 0; i
< exec_size
; i
++) {
1408 if (dst_access_mask
[i
] > 0x0000FFFF) {
1409 upper_oword_writes
++;
1411 assert(dst_access_mask
[i
] != 0);
1412 lower_oword_writes
++;
1416 ERROR_IF(lower_oword_writes
!= 0 &&
1417 upper_oword_writes
!= 0 &&
1418 upper_oword_writes
!= lower_oword_writes
,
1419 "Writes must be to only one OWord or "
1420 "evenly split between OWords");
1424 /* The IVB and HSW PRMs say:
1426 * When an instruction has a source region that spans two registers and
1427 * the destination spans two registers, the destination elements must be
1428 * evenly split between the two registers [...]
1430 * The SNB PRM contains similar wording (but written in a much more
1431 * confusing manner).
1435 * When destination spans two registers, the source may be one or two
1436 * registers. The destination elements must be evenly split between the
1441 * When destination of MATH instruction spans two registers, the
1442 * destination elements must be evenly split between the two registers.
1444 * It is not known whether this restriction applies to KBL other Gens after
1447 if (devinfo
->gen
<= 8 ||
1448 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
1450 /* Nothing explicitly states that on Gen < 8 elements must be evenly
1451 * split between two destination registers in the two exceptional
1452 * source-region-spans-one-register cases, but since Broadwell requires
1453 * evenly split writes regardless of source region, we assume that it was
1454 * an oversight and require it.
1456 if (dst_regs
== 2) {
1457 unsigned upper_reg_writes
= 0, lower_reg_writes
= 0;
1459 for (unsigned i
= 0; i
< exec_size
; i
++) {
1460 if (dst_access_mask
[i
] > 0xFFFFFFFF) {
1463 assert(dst_access_mask
[i
] != 0);
1468 ERROR_IF(upper_reg_writes
!= lower_reg_writes
,
1469 "Writes must be evenly split between the two "
1470 "destination registers");
1474 /* The IVB and HSW PRMs say:
1476 * When an instruction has a source region that spans two registers and
1477 * the destination spans two registers, the destination elements must be
1478 * evenly split between the two registers and each destination register
1479 * must be entirely derived from one source register.
1481 * Note: In such cases, the regioning parameters must ensure that the
1482 * offset from the two source registers is the same.
1484 * The SNB PRM contains similar wording (but written in a much more
1485 * confusing manner).
1487 * There are effectively three rules stated here:
1489 * For an instruction with a source and a destination spanning two
1492 * (1) destination elements must be evenly split between the two
1494 * (2) all destination elements in a register must be derived
1495 * from one source register
1496 * (3) the offset (i.e. the starting location in each of the two
1497 * registers spanned by a region) must be the same in the two
1498 * registers spanned by a region
1500 * It is impossible to violate rule (1) without violating (2) or (3), so we
1501 * do not attempt to validate it.
1503 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
1504 for (unsigned i
= 0; i
< num_sources
; i
++) {
1506 if (src ## n ## _regs <= 1) \
1509 for (unsigned i = 0; i < exec_size; i++) { \
1510 if ((dst_access_mask[i] > 0xFFFFFFFF) != \
1511 (src ## n ## _access_mask[i] > 0xFFFFFFFF)) { \
1512 ERROR("Each destination register must be entirely derived " \
1513 "from one source register"); \
1518 unsigned offset_0 = \
1519 brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
1520 unsigned offset_1 = offset_0; \
1522 for (unsigned i = 0; i < exec_size; i++) { \
1523 if (src ## n ## _access_mask[i] > 0xFFFFFFFF) { \
1524 offset_1 = __builtin_ctzll(src ## n ## _access_mask[i]) - 32; \
1529 ERROR_IF(num_sources == 2 && offset_0 != offset_1, \
1530 "The offset from the two source registers " \
1542 /* The IVB and HSW PRMs say:
1544 * When destination spans two registers, the source MUST span two
1545 * registers. The exception to the above rule:
1546 * 1. When source is scalar, the source registers are not
1548 * 2. When source is packed integer Word and destination is packed
1549 * integer DWord, the source register is not incremented by the
1550 * source sub register is incremented.
1552 * The SNB PRM does not contain this rule, but the internal documentation
1553 * indicates that it applies to SNB as well. We assume that the rule applies
1554 * to Gen <= 5 although their PRMs do not state it.
1556 * While the documentation explicitly says in exception (2) that the
1557 * destination must be an integer DWord, the hardware allows at least a
1558 * float destination type as well. We emit such instructions from
1560 * fs_visitor::emit_interpolation_setup_gen6
1561 * fs_visitor::emit_fragcoord_interpolation
1563 * and have for years with no ill effects.
1565 * Additionally the simulator source code indicates that the real condition
1566 * is that the size of the destination type is 4 bytes.
1568 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
1569 enum brw_reg_type dst_type
= inst_dst_type(devinfo
, inst
);
1570 bool dst_is_packed_dword
=
1571 is_packed(exec_size
* stride
, exec_size
, stride
) &&
1572 brw_reg_type_to_size(dst_type
) == 4;
1574 for (unsigned i
= 0; i
< num_sources
; i
++) {
1576 unsigned vstride, width, hstride; \
1577 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
1578 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
1579 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
1580 bool src ## n ## _is_packed_word = \
1581 is_packed(vstride, width, hstride) && \
1582 (brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_W || \
1583 brw_inst_src ## n ## _type(devinfo, inst) == BRW_REGISTER_TYPE_UW); \
1585 ERROR_IF(src ## n ## _regs == 1 && \
1586 !src ## n ## _has_scalar_region(devinfo, inst) && \
1587 !(dst_is_packed_dword && src ## n ## _is_packed_word), \
1588 "When the destination spans two registers, the source must " \
1589 "span two registers\n" ERROR_INDENT "(exceptions for scalar " \
1590 "source and packed-word to packed-dword expansion)")
1604 static struct string
1605 vector_immediate_restrictions(const struct gen_device_info
*devinfo
,
1606 const brw_inst
*inst
)
1608 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1609 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1611 if (num_sources
== 3 || num_sources
== 0)
1612 return (struct string
){};
1614 unsigned file
= num_sources
== 1 ?
1615 brw_inst_src0_reg_file(devinfo
, inst
) :
1616 brw_inst_src1_reg_file(devinfo
, inst
);
1617 if (file
!= BRW_IMMEDIATE_VALUE
)
1618 return (struct string
){};
1620 enum brw_reg_type dst_type
= inst_dst_type(devinfo
, inst
);
1621 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
1622 unsigned dst_subreg
= brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
?
1623 brw_inst_dst_da1_subreg_nr(devinfo
, inst
) : 0;
1624 unsigned dst_stride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
1625 enum brw_reg_type type
= num_sources
== 1 ?
1626 brw_inst_src0_type(devinfo
, inst
) :
1627 brw_inst_src1_type(devinfo
, inst
);
1631 * When an immediate vector is used in an instruction, the destination
1632 * must be 128-bit aligned with destination horizontal stride equivalent
1633 * to a word for an immediate integer vector (v) and equivalent to a
1634 * DWord for an immediate float vector (vf).
1636 * The text has not been updated for the addition of the immediate unsigned
1637 * integer vector type (uv) on SNB, but presumably the same restriction
1641 case BRW_REGISTER_TYPE_V
:
1642 case BRW_REGISTER_TYPE_UV
:
1643 case BRW_REGISTER_TYPE_VF
:
1644 ERROR_IF(dst_subreg
% (128 / 8) != 0,
1645 "Destination must be 128-bit aligned in order to use immediate "
1648 if (type
== BRW_REGISTER_TYPE_VF
) {
1649 ERROR_IF(dst_type_size
* dst_stride
!= 4,
1650 "Destination must have stride equivalent to dword in order "
1651 "to use the VF type");
1653 ERROR_IF(dst_type_size
* dst_stride
!= 2,
1654 "Destination must have stride equivalent to word in order "
1655 "to use the V or UV type");
1665 static struct string
1666 special_requirements_for_handling_double_precision_data_types(
1667 const struct gen_device_info
*devinfo
,
1668 const brw_inst
*inst
)
1670 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
1671 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1673 if (num_sources
== 3 || num_sources
== 0)
1674 return (struct string
){};
1676 /* Split sends don't have types so there's no doubles there. */
1677 if (inst_is_split_send(devinfo
, inst
))
1678 return (struct string
){};
1680 enum brw_reg_type exec_type
= execution_type(devinfo
, inst
);
1681 unsigned exec_type_size
= brw_reg_type_to_size(exec_type
);
1683 enum brw_reg_file dst_file
= brw_inst_dst_reg_file(devinfo
, inst
);
1684 enum brw_reg_type dst_type
= inst_dst_type(devinfo
, inst
);
1685 unsigned dst_type_size
= brw_reg_type_to_size(dst_type
);
1686 unsigned dst_hstride
= STRIDE(brw_inst_dst_hstride(devinfo
, inst
));
1687 unsigned dst_reg
= brw_inst_dst_da_reg_nr(devinfo
, inst
);
1688 unsigned dst_subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
1689 unsigned dst_address_mode
= brw_inst_dst_address_mode(devinfo
, inst
);
1691 bool is_integer_dword_multiply
=
1692 devinfo
->gen
>= 8 &&
1693 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MUL
&&
1694 (brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_D
||
1695 brw_inst_src0_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UD
) &&
1696 (brw_inst_src1_type(devinfo
, inst
) == BRW_REGISTER_TYPE_D
||
1697 brw_inst_src1_type(devinfo
, inst
) == BRW_REGISTER_TYPE_UD
);
1699 if (dst_type_size
!= 8 && exec_type_size
!= 8 && !is_integer_dword_multiply
)
1700 return (struct string
){};
1702 for (unsigned i
= 0; i
< num_sources
; i
++) {
1703 unsigned vstride
, width
, hstride
, type_size
, reg
, subreg
, address_mode
;
1704 bool is_scalar_region
;
1705 enum brw_reg_file file
;
1706 enum brw_reg_type type
;
1709 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
1710 BRW_IMMEDIATE_VALUE) \
1713 is_scalar_region = src ## n ## _has_scalar_region(devinfo, inst); \
1714 vstride = STRIDE(brw_inst_src ## n ## _vstride(devinfo, inst)); \
1715 width = WIDTH(brw_inst_src ## n ## _width(devinfo, inst)); \
1716 hstride = STRIDE(brw_inst_src ## n ## _hstride(devinfo, inst)); \
1717 file = brw_inst_src ## n ## _reg_file(devinfo, inst); \
1718 type = brw_inst_src ## n ## _type(devinfo, inst); \
1719 type_size = brw_reg_type_to_size(type); \
1720 reg = brw_inst_src ## n ## _da_reg_nr(devinfo, inst); \
1721 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
1722 address_mode = brw_inst_src ## n ## _address_mode(devinfo, inst)
1731 /* The PRMs say that for CHV, BXT:
1733 * When source or destination datatype is 64b or operation is integer
1734 * DWord multiply, regioning in Align1 must follow these rules:
1736 * 1. Source and Destination horizontal stride must be aligned to the
1738 * 2. Regioning must ensure Src.Vstride = Src.Width * Src.Hstride.
1739 * 3. Source and Destination offset must be the same, except the case
1742 * We assume that the restriction applies to GLK as well.
1744 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
1745 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
1746 unsigned src_stride
= hstride
* type_size
;
1747 unsigned dst_stride
= dst_hstride
* dst_type_size
;
1749 ERROR_IF(!is_scalar_region
&&
1750 (src_stride
% 8 != 0 ||
1751 dst_stride
% 8 != 0 ||
1752 src_stride
!= dst_stride
),
1753 "Source and destination horizontal stride must equal and a "
1754 "multiple of a qword when the execution type is 64-bit");
1756 ERROR_IF(vstride
!= width
* hstride
,
1757 "Vstride must be Width * Hstride when the execution type is "
1760 ERROR_IF(!is_scalar_region
&& dst_subreg
!= subreg
,
1761 "Source and destination offset must be the same when the "
1762 "execution type is 64-bit");
1765 /* The PRMs say that for CHV, BXT:
1767 * When source or destination datatype is 64b or operation is integer
1768 * DWord multiply, indirect addressing must not be used.
1770 * We assume that the restriction applies to GLK as well.
1772 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1773 ERROR_IF(BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
== address_mode
||
1774 BRW_ADDRESS_REGISTER_INDIRECT_REGISTER
== dst_address_mode
,
1775 "Indirect addressing is not allowed when the execution type "
1779 /* The PRMs say that for CHV, BXT:
1781 * ARF registers must never be used with 64b datatype or when
1782 * operation is integer DWord multiply.
1784 * We assume that the restriction applies to GLK as well.
1786 * We assume that the restriction does not apply to the null register.
1788 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1789 ERROR_IF(brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MAC
||
1790 brw_inst_acc_wr_control(devinfo
, inst
) ||
1791 (BRW_ARCHITECTURE_REGISTER_FILE
== file
&&
1792 reg
!= BRW_ARF_NULL
) ||
1793 (BRW_ARCHITECTURE_REGISTER_FILE
== dst_file
&&
1794 dst_reg
!= BRW_ARF_NULL
),
1795 "Architecture registers cannot be used when the execution "
1800 /* The PRMs say that for BDW, SKL:
1802 * If Align16 is required for an operation with QW destination and non-QW
1803 * source datatypes, the execution size cannot exceed 2.
1805 * We assume that the restriction applies to all Gen8+ parts.
1807 if (devinfo
->gen
>= 8) {
1808 enum brw_reg_type src0_type
= brw_inst_src0_type(devinfo
, inst
);
1809 enum brw_reg_type src1_type
=
1810 num_sources
> 1 ? brw_inst_src1_type(devinfo
, inst
) : src0_type
;
1811 unsigned src0_type_size
= brw_reg_type_to_size(src0_type
);
1812 unsigned src1_type_size
= brw_reg_type_to_size(src1_type
);
1814 ERROR_IF(brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
&&
1815 dst_type_size
== 8 &&
1816 (src0_type_size
!= 8 || src1_type_size
!= 8) &&
1817 brw_inst_exec_size(devinfo
, inst
) > BRW_EXECUTE_2
,
1818 "In Align16 exec size cannot exceed 2 with a QWord destination "
1819 "and a non-QWord source");
1822 /* The PRMs say that for CHV, BXT:
1824 * When source or destination datatype is 64b or operation is integer
1825 * DWord multiply, DepCtrl must not be used.
1827 * We assume that the restriction applies to GLK as well.
1829 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1830 ERROR_IF(brw_inst_no_dd_check(devinfo
, inst
) ||
1831 brw_inst_no_dd_clear(devinfo
, inst
),
1832 "DepCtrl is not allowed when the execution type is 64-bit");
1838 static struct string
1839 instruction_restrictions(const struct gen_device_info
*devinfo
,
1840 const brw_inst
*inst
)
1842 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1844 /* From GEN:BUG:1604601757:
1846 * "When multiplying a DW and any lower precision integer, source modifier
1847 * is not supported."
1849 if (devinfo
->gen
>= 12 &&
1850 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MUL
) {
1851 enum brw_reg_type exec_type
= execution_type(devinfo
, inst
);
1852 const bool src0_valid
= type_sz(brw_inst_src0_type(devinfo
, inst
)) == 4 ||
1853 brw_inst_src0_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
||
1854 !(brw_inst_src0_negate(devinfo
, inst
) ||
1855 brw_inst_src0_abs(devinfo
, inst
));
1856 const bool src1_valid
= type_sz(brw_inst_src1_type(devinfo
, inst
)) == 4 ||
1857 brw_inst_src1_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
||
1858 !(brw_inst_src1_negate(devinfo
, inst
) ||
1859 brw_inst_src1_abs(devinfo
, inst
));
1861 ERROR_IF(!brw_reg_type_is_floating_point(exec_type
) &&
1862 type_sz(exec_type
) == 4 && !(src0_valid
&& src1_valid
),
1863 "When multiplying a DW and any lower precision integer, source "
1864 "modifier is not supported.");
1871 brw_validate_instructions(const struct gen_device_info
*devinfo
,
1872 const void *assembly
, int start_offset
, int end_offset
,
1873 struct disasm_info
*disasm
)
1877 for (int src_offset
= start_offset
; src_offset
< end_offset
;) {
1878 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1879 const brw_inst
*inst
= assembly
+ src_offset
;
1880 bool is_compact
= brw_inst_cmpt_control(devinfo
, inst
);
1881 brw_inst uncompacted
;
1884 brw_compact_inst
*compacted
= (void *)inst
;
1885 brw_uncompact_instruction(devinfo
, &uncompacted
, compacted
);
1886 inst
= &uncompacted
;
1889 if (is_unsupported_inst(devinfo
, inst
)) {
1890 ERROR("Instruction not supported on this Gen");
1892 CHECK(sources_not_null
);
1893 CHECK(send_restrictions
);
1894 CHECK(alignment_supported
);
1895 CHECK(general_restrictions_based_on_operand_types
);
1896 CHECK(general_restrictions_on_region_parameters
);
1897 CHECK(special_restrictions_for_mixed_float_mode
);
1898 CHECK(region_alignment_rules
);
1899 CHECK(vector_immediate_restrictions
);
1900 CHECK(special_requirements_for_handling_double_precision_data_types
);
1901 CHECK(instruction_restrictions
);
1904 if (error_msg
.str
&& disasm
) {
1905 disasm_insert_error(disasm
, src_offset
, error_msg
.str
);
1907 valid
= valid
&& error_msg
.len
== 0;
1908 free(error_msg
.str
);
1911 src_offset
+= sizeof(brw_compact_inst
);
1913 src_offset
+= sizeof(brw_inst
);