2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
35 #include "brw_vec4_gs_visitor.h"
37 #include "brw_dead_control_flow.h"
38 #include "dev/gen_debug.h"
39 #include "compiler/glsl_types.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "program/prog_parameter.h"
42 #include "util/u_math.h"
46 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
50 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
51 const fs_reg
*src
, unsigned sources
)
53 memset((void*)this, 0, sizeof(*this));
55 this->src
= new fs_reg
[MAX2(sources
, 3)];
56 for (unsigned i
= 0; i
< sources
; i
++)
57 this->src
[i
] = src
[i
];
59 this->opcode
= opcode
;
61 this->sources
= sources
;
62 this->exec_size
= exec_size
;
65 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
67 assert(this->exec_size
!= 0);
69 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
71 /* This will be the case for almost all instructions. */
78 this->size_written
= dst
.component_size(exec_size
);
81 this->size_written
= 0;
85 unreachable("Invalid destination register file");
88 this->writes_accumulator
= false;
93 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
96 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
98 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
101 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
103 init(opcode
, exec_size
, dst
, NULL
, 0);
106 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
109 const fs_reg src
[1] = { src0
};
110 init(opcode
, exec_size
, dst
, src
, 1);
113 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
114 const fs_reg
&src0
, const fs_reg
&src1
)
116 const fs_reg src
[2] = { src0
, src1
};
117 init(opcode
, exec_size
, dst
, src
, 2);
120 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
121 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
123 const fs_reg src
[3] = { src0
, src1
, src2
};
124 init(opcode
, exec_size
, dst
, src
, 3);
127 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
128 const fs_reg src
[], unsigned sources
)
130 init(opcode
, exec_width
, dst
, src
, sources
);
133 fs_inst::fs_inst(const fs_inst
&that
)
135 memcpy((void*)this, &that
, sizeof(that
));
137 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
139 for (unsigned i
= 0; i
< that
.sources
; i
++)
140 this->src
[i
] = that
.src
[i
];
149 fs_inst::resize_sources(uint8_t num_sources
)
151 if (this->sources
!= num_sources
) {
152 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
154 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
155 src
[i
] = this->src
[i
];
159 this->sources
= num_sources
;
164 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
166 const fs_reg
&surf_index
,
167 const fs_reg
&varying_offset
,
168 uint32_t const_offset
)
170 /* We have our constant surface use a pitch of 4 bytes, so our index can
171 * be any component of a vector, and then we load 4 contiguous
172 * components starting from that.
174 * We break down the const_offset to a portion added to the variable offset
175 * and a portion done using fs_reg::offset, which means that if you have
176 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
177 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
178 * later notice that those loads are all the same and eliminate the
181 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
182 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
184 /* The pull load message will load a vec4 (16 bytes). If we are loading
185 * a double this means we are only loading 2 elements worth of data.
186 * We also want to use a 32-bit data type for the dst of the load operation
187 * so other parts of the driver don't get confused about the size of the
190 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
191 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
192 vec4_result
, surf_index
, vec4_offset
);
193 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
195 shuffle_from_32bit_read(bld
, dst
, vec4_result
,
196 (const_offset
& 0xf) / type_sz(dst
.type
), 1);
200 * A helper for MOV generation for fixing up broken hardware SEND dependency
204 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
206 /* The caller always wants uncompressed to emit the minimal extra
207 * dependencies, and to avoid having to deal with aligning its regs to 2.
209 const fs_builder ubld
= bld
.annotate("send dependency resolve")
212 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
216 fs_inst::is_send_from_grf() const
219 case SHADER_OPCODE_SEND
:
220 case SHADER_OPCODE_SHADER_TIME_ADD
:
221 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
222 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
223 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
224 case SHADER_OPCODE_URB_WRITE_SIMD8
:
225 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
226 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
227 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
228 case SHADER_OPCODE_URB_READ_SIMD8
:
229 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
231 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
232 return src
[1].file
== VGRF
;
233 case FS_OPCODE_FB_WRITE
:
234 case FS_OPCODE_FB_READ
:
235 return src
[0].file
== VGRF
;
238 return src
[0].file
== VGRF
;
245 fs_inst::is_control_source(unsigned arg
) const
248 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
249 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
250 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
253 case SHADER_OPCODE_BROADCAST
:
254 case SHADER_OPCODE_SHUFFLE
:
255 case SHADER_OPCODE_QUAD_SWIZZLE
:
256 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
257 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
258 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
259 case SHADER_OPCODE_GET_BUFFER_SIZE
:
262 case SHADER_OPCODE_MOV_INDIRECT
:
263 case SHADER_OPCODE_CLUSTER_BROADCAST
:
264 case SHADER_OPCODE_TEX
:
266 case SHADER_OPCODE_TXD
:
267 case SHADER_OPCODE_TXF
:
268 case SHADER_OPCODE_TXF_LZ
:
269 case SHADER_OPCODE_TXF_CMS
:
270 case SHADER_OPCODE_TXF_CMS_W
:
271 case SHADER_OPCODE_TXF_UMS
:
272 case SHADER_OPCODE_TXF_MCS
:
273 case SHADER_OPCODE_TXL
:
274 case SHADER_OPCODE_TXL_LZ
:
275 case SHADER_OPCODE_TXS
:
276 case SHADER_OPCODE_LOD
:
277 case SHADER_OPCODE_TG4
:
278 case SHADER_OPCODE_TG4_OFFSET
:
279 case SHADER_OPCODE_SAMPLEINFO
:
280 return arg
== 1 || arg
== 2;
282 case SHADER_OPCODE_SEND
:
283 return arg
== 0 || arg
== 1;
291 * Returns true if this instruction's sources and destinations cannot
292 * safely be the same register.
294 * In most cases, a register can be written over safely by the same
295 * instruction that is its last use. For a single instruction, the
296 * sources are dereferenced before writing of the destination starts
299 * However, there are a few cases where this can be problematic:
301 * - Virtual opcodes that translate to multiple instructions in the
302 * code generator: if src == dst and one instruction writes the
303 * destination before a later instruction reads the source, then
304 * src will have been clobbered.
306 * - SIMD16 compressed instructions with certain regioning (see below).
308 * The register allocator uses this information to set up conflicts between
309 * GRF sources and the destination.
312 fs_inst::has_source_and_destination_hazard() const
315 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
316 /* Multiple partial writes to the destination */
318 case SHADER_OPCODE_SHUFFLE
:
319 /* This instruction returns an arbitrary channel from the source and
320 * gets split into smaller instructions in the generator. It's possible
321 * that one of the instructions will read from a channel corresponding
322 * to an earlier instruction.
324 case SHADER_OPCODE_SEL_EXEC
:
325 /* This is implemented as
327 * mov(16) g4<1>D 0D { align1 WE_all 1H };
328 * mov(16) g4<1>D g5<8,8,1>D { align1 1H }
330 * Because the source is only read in the second instruction, the first
331 * may stomp all over it.
334 case SHADER_OPCODE_QUAD_SWIZZLE
:
336 case BRW_SWIZZLE_XXXX
:
337 case BRW_SWIZZLE_YYYY
:
338 case BRW_SWIZZLE_ZZZZ
:
339 case BRW_SWIZZLE_WWWW
:
340 case BRW_SWIZZLE_XXZZ
:
341 case BRW_SWIZZLE_YYWW
:
342 case BRW_SWIZZLE_XYXY
:
343 case BRW_SWIZZLE_ZWZW
:
344 /* These can be implemented as a single Align1 region on all
345 * platforms, so there's never a hazard between source and
346 * destination. C.f. fs_generator::generate_quad_swizzle().
350 return !is_uniform(src
[0]);
353 /* The SIMD16 compressed instruction
355 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
357 * is actually decoded in hardware as:
359 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
360 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
362 * Which is safe. However, if we have uniform accesses
363 * happening, we get into trouble:
365 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
366 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
368 * Now our destination for the first instruction overwrote the
369 * second instruction's src0, and we get garbage for those 8
370 * pixels. There's a similar issue for the pre-gen6
371 * pixel_x/pixel_y, which are registers of 16-bit values and thus
372 * would get stomped by the first decode as well.
374 if (exec_size
== 16) {
375 for (int i
= 0; i
< sources
; i
++) {
376 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
377 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
378 src
[i
].type
== BRW_REGISTER_TYPE_W
||
379 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
380 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
390 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
392 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
395 fs_reg reg
= this->src
[0];
396 if (reg
.file
!= VGRF
|| reg
.offset
!= 0 || reg
.stride
!= 1)
399 if (grf_alloc
.sizes
[reg
.nr
] * REG_SIZE
!= this->size_written
)
402 for (int i
= 0; i
< this->sources
; i
++) {
403 reg
.type
= this->src
[i
].type
;
404 if (!this->src
[i
].equals(reg
))
407 if (i
< this->header_size
) {
408 reg
.offset
+= REG_SIZE
;
410 reg
= horiz_offset(reg
, this->exec_size
);
418 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
) const
420 if (devinfo
->gen
== 6 && is_math())
423 if (is_send_from_grf())
426 if (!backend_instruction::can_do_source_mods())
433 fs_inst::can_do_cmod()
435 if (!backend_instruction::can_do_cmod())
438 /* The accumulator result appears to get used for the conditional modifier
439 * generation. When negating a UD value, there is a 33rd bit generated for
440 * the sign in the accumulator value, so now you can't check, for example,
441 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
443 for (unsigned i
= 0; i
< sources
; i
++) {
444 if (type_is_unsigned_int(src
[i
].type
) && src
[i
].negate
)
452 fs_inst::can_change_types() const
454 return dst
.type
== src
[0].type
&&
455 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
456 (opcode
== BRW_OPCODE_MOV
||
457 (opcode
== BRW_OPCODE_SEL
&&
458 dst
.type
== src
[1].type
&&
459 predicate
!= BRW_PREDICATE_NONE
&&
460 !src
[1].abs
&& !src
[1].negate
));
466 memset((void*)this, 0, sizeof(*this));
467 type
= BRW_REGISTER_TYPE_UD
;
471 /** Generic unset register constructor. */
475 this->file
= BAD_FILE
;
478 fs_reg::fs_reg(struct ::brw_reg reg
) :
483 if (this->file
== IMM
&&
484 (this->type
!= BRW_REGISTER_TYPE_V
&&
485 this->type
!= BRW_REGISTER_TYPE_UV
&&
486 this->type
!= BRW_REGISTER_TYPE_VF
)) {
492 fs_reg::equals(const fs_reg
&r
) const
494 return (this->backend_reg::equals(r
) &&
499 fs_reg::negative_equals(const fs_reg
&r
) const
501 return (this->backend_reg::negative_equals(r
) &&
506 fs_reg::is_contiguous() const
512 fs_reg::component_size(unsigned width
) const
514 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
517 return MAX2(width
* stride
, 1) * type_sz(type
);
521 type_size_scalar(const struct glsl_type
*type
, bool bindless
)
523 unsigned int size
, i
;
525 switch (type
->base_type
) {
528 case GLSL_TYPE_FLOAT
:
530 return type
->components();
531 case GLSL_TYPE_UINT16
:
532 case GLSL_TYPE_INT16
:
533 case GLSL_TYPE_FLOAT16
:
534 return DIV_ROUND_UP(type
->components(), 2);
535 case GLSL_TYPE_UINT8
:
537 return DIV_ROUND_UP(type
->components(), 4);
538 case GLSL_TYPE_DOUBLE
:
539 case GLSL_TYPE_UINT64
:
540 case GLSL_TYPE_INT64
:
541 return type
->components() * 2;
542 case GLSL_TYPE_ARRAY
:
543 return type_size_scalar(type
->fields
.array
, bindless
) * type
->length
;
544 case GLSL_TYPE_STRUCT
:
545 case GLSL_TYPE_INTERFACE
:
547 for (i
= 0; i
< type
->length
; i
++) {
548 size
+= type_size_scalar(type
->fields
.structure
[i
].type
, bindless
);
551 case GLSL_TYPE_SAMPLER
:
552 case GLSL_TYPE_IMAGE
:
554 return type
->components() * 2;
555 case GLSL_TYPE_ATOMIC_UINT
:
556 /* Samplers, atomics, and images take up no register space, since
557 * they're baked in at link time.
560 case GLSL_TYPE_SUBROUTINE
:
563 case GLSL_TYPE_ERROR
:
564 case GLSL_TYPE_FUNCTION
:
565 unreachable("not reached");
572 * Create a MOV to read the timestamp register.
574 * The caller is responsible for emitting the MOV. The return value is
575 * the destination of the MOV, with extra parameters set.
578 fs_visitor::get_timestamp(const fs_builder
&bld
)
580 assert(devinfo
->gen
>= 7);
582 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
585 BRW_REGISTER_TYPE_UD
));
587 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
589 /* We want to read the 3 fields we care about even if it's not enabled in
592 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
598 fs_visitor::emit_shader_time_begin()
600 /* We want only the low 32 bits of the timestamp. Since it's running
601 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
602 * which is plenty of time for our purposes. It is identical across the
603 * EUs, but since it's tracking GPU core speed it will increment at a
604 * varying rate as render P-states change.
606 shader_start_time
= component(
607 get_timestamp(bld
.annotate("shader time start")), 0);
611 fs_visitor::emit_shader_time_end()
613 /* Insert our code just before the final SEND with EOT. */
614 exec_node
*end
= this->instructions
.get_tail();
615 assert(end
&& ((fs_inst
*) end
)->eot
);
616 const fs_builder ibld
= bld
.annotate("shader time end")
617 .exec_all().at(NULL
, end
);
618 const fs_reg timestamp
= get_timestamp(ibld
);
620 /* We only use the low 32 bits of the timestamp - see
621 * emit_shader_time_begin()).
623 * We could also check if render P-states have changed (or anything
624 * else that might disrupt timing) by setting smear to 2 and checking if
625 * that field is != 0.
627 const fs_reg shader_end_time
= component(timestamp
, 0);
629 /* Check that there weren't any timestamp reset events (assuming these
630 * were the only two timestamp reads that happened).
632 const fs_reg reset
= component(timestamp
, 2);
633 set_condmod(BRW_CONDITIONAL_Z
,
634 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
635 ibld
.IF(BRW_PREDICATE_NORMAL
);
637 fs_reg start
= shader_start_time
;
639 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
640 BRW_REGISTER_TYPE_UD
),
642 const fs_builder cbld
= ibld
.group(1, 0);
643 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
645 /* If there were no instructions between the two timestamp gets, the diff
646 * is 2 cycles. Remove that overhead, so I can forget about that when
647 * trying to determine the time taken for single instructions.
649 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
650 SHADER_TIME_ADD(cbld
, 0, diff
);
651 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
652 ibld
.emit(BRW_OPCODE_ELSE
);
653 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
654 ibld
.emit(BRW_OPCODE_ENDIF
);
658 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
659 int shader_time_subindex
,
662 int index
= shader_time_index
* 3 + shader_time_subindex
;
663 struct brw_reg offset
= brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
);
666 if (dispatch_width
== 8)
667 payload
= vgrf(glsl_type::uvec2_type
);
669 payload
= vgrf(glsl_type::uint_type
);
671 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
675 fs_visitor::vfail(const char *format
, va_list va
)
684 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
685 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
687 this->fail_msg
= msg
;
690 fprintf(stderr
, "%s", msg
);
695 fs_visitor::fail(const char *format
, ...)
699 va_start(va
, format
);
705 * Mark this program as impossible to compile with dispatch width greater
708 * During the SIMD8 compile (which happens first), we can detect and flag
709 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
710 * SIMD16+ compile altogether.
712 * During a compile of dispatch width greater than n (if one happens anyway),
713 * this just calls fail().
716 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
718 if (dispatch_width
> n
) {
721 max_dispatch_width
= n
;
722 compiler
->shader_perf_log(log_data
,
723 "Shader dispatch width limited to SIMD%d: %s",
729 * Returns true if the instruction has a flag that means it won't
730 * update an entire destination register.
732 * For example, dead code elimination and live variable analysis want to know
733 * when a write to a variable screens off any preceding values that were in
737 fs_inst::is_partial_write() const
739 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
740 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
741 !this->dst
.is_contiguous() ||
742 this->dst
.offset
% REG_SIZE
!= 0);
746 fs_inst::components_read(unsigned i
) const
748 /* Return zero if the source is not present. */
749 if (src
[i
].file
== BAD_FILE
)
753 case FS_OPCODE_LINTERP
:
759 case FS_OPCODE_PIXEL_X
:
760 case FS_OPCODE_PIXEL_Y
:
764 case FS_OPCODE_FB_WRITE_LOGICAL
:
765 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
766 /* First/second FB write color. */
768 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
772 case SHADER_OPCODE_TEX_LOGICAL
:
773 case SHADER_OPCODE_TXD_LOGICAL
:
774 case SHADER_OPCODE_TXF_LOGICAL
:
775 case SHADER_OPCODE_TXL_LOGICAL
:
776 case SHADER_OPCODE_TXS_LOGICAL
:
777 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
778 case FS_OPCODE_TXB_LOGICAL
:
779 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
780 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
781 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
782 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
783 case SHADER_OPCODE_LOD_LOGICAL
:
784 case SHADER_OPCODE_TG4_LOGICAL
:
785 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
786 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
787 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
788 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
789 /* Texture coordinates. */
790 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
791 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
792 /* Texture derivatives. */
793 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
794 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
795 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
796 /* Texture offset. */
797 else if (i
== TEX_LOGICAL_SRC_TG4_OFFSET
)
800 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
805 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
806 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
807 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
);
808 /* Surface coordinates. */
809 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
810 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
811 /* Surface operation source (ignored for reads). */
812 else if (i
== SURFACE_LOGICAL_SRC_DATA
)
817 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
818 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
819 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
820 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
821 /* Surface coordinates. */
822 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
823 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
824 /* Surface operation source. */
825 else if (i
== SURFACE_LOGICAL_SRC_DATA
)
826 return src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
830 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
831 assert(src
[2].file
== IMM
);
834 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
835 assert(src
[2].file
== IMM
);
836 return i
== 1 ? src
[2].ud
: 1;
838 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
839 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
840 assert(src
[2].file
== IMM
);
843 const unsigned op
= src
[2].ud
;
858 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
859 assert(src
[2].file
== IMM
);
862 const unsigned op
= src
[2].ud
;
863 return op
== BRW_AOP_FCMPWR
? 2 : 1;
868 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
869 /* Scattered logical opcodes use the following params:
870 * src[0] Surface coordinates
871 * src[1] Surface operation source (ignored for reads)
873 * src[3] IMM with always 1 dimension.
874 * src[4] IMM with arg bitsize for scattered read/write 8, 16, 32
876 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
877 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
878 return i
== SURFACE_LOGICAL_SRC_DATA
? 0 : 1;
880 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
881 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
882 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
885 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
886 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
887 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
888 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
889 const unsigned op
= src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
890 /* Surface coordinates. */
891 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
892 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
893 /* Surface operation source. */
894 else if (i
== SURFACE_LOGICAL_SRC_DATA
&& op
== BRW_AOP_CMPWR
)
896 else if (i
== SURFACE_LOGICAL_SRC_DATA
&&
897 (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
|| op
== BRW_AOP_PREDEC
))
902 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
903 return (i
== 0 ? 2 : 1);
905 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
: {
906 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
907 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
908 const unsigned op
= src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
909 /* Surface coordinates. */
910 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
911 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
912 /* Surface operation source. */
913 else if (i
== SURFACE_LOGICAL_SRC_DATA
&& op
== BRW_AOP_FCMPWR
)
925 fs_inst::size_read(int arg
) const
928 case SHADER_OPCODE_SEND
:
930 return mlen
* REG_SIZE
;
931 } else if (arg
== 3) {
932 return ex_mlen
* REG_SIZE
;
936 case FS_OPCODE_FB_WRITE
:
937 case FS_OPCODE_REP_FB_WRITE
:
940 return src
[0].file
== BAD_FILE
? 0 : 2 * REG_SIZE
;
942 return mlen
* REG_SIZE
;
946 case FS_OPCODE_FB_READ
:
947 case SHADER_OPCODE_URB_WRITE_SIMD8
:
948 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
949 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
950 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
951 case SHADER_OPCODE_URB_READ_SIMD8
:
952 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
953 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
954 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
956 return mlen
* REG_SIZE
;
959 case FS_OPCODE_SET_SAMPLE_ID
:
964 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
965 /* The payload is actually stored in src1 */
967 return mlen
* REG_SIZE
;
970 case FS_OPCODE_LINTERP
:
975 case SHADER_OPCODE_LOAD_PAYLOAD
:
976 if (arg
< this->header_size
)
980 case CS_OPCODE_CS_TERMINATE
:
981 case SHADER_OPCODE_BARRIER
:
984 case SHADER_OPCODE_MOV_INDIRECT
:
986 assert(src
[2].file
== IMM
);
992 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
993 return mlen
* REG_SIZE
;
997 switch (src
[arg
].file
) {
1000 return components_read(arg
) * type_sz(src
[arg
].type
);
1006 return components_read(arg
) * src
[arg
].component_size(exec_size
);
1008 unreachable("MRF registers are not allowed as sources");
1014 /* Return the subset of flag registers that an instruction could
1015 * potentially read or write based on the execution controls and flag
1016 * subregister number of the instruction.
1019 flag_mask(const fs_inst
*inst
)
1021 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
1022 const unsigned end
= start
+ inst
->exec_size
;
1023 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
1027 bit_mask(unsigned n
)
1029 return (n
>= CHAR_BIT
* sizeof(bit_mask(n
)) ? ~0u : (1u << n
) - 1);
1033 flag_mask(const fs_reg
&r
, unsigned sz
)
1035 if (r
.file
== ARF
) {
1036 const unsigned start
= (r
.nr
- BRW_ARF_FLAG
) * 4 + r
.subnr
;
1037 const unsigned end
= start
+ sz
;
1038 return bit_mask(end
) & ~bit_mask(start
);
1046 fs_inst::flags_read(const gen_device_info
*devinfo
) const
1048 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
1049 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
1050 /* The vertical predication modes combine corresponding bits from
1051 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
1053 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
1054 return flag_mask(this) << shift
| flag_mask(this);
1055 } else if (predicate
) {
1056 return flag_mask(this);
1059 for (int i
= 0; i
< sources
; i
++) {
1060 mask
|= flag_mask(src
[i
], size_read(i
));
1067 fs_inst::flags_written() const
1069 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
1070 opcode
!= BRW_OPCODE_CSEL
&&
1071 opcode
!= BRW_OPCODE_IF
&&
1072 opcode
!= BRW_OPCODE_WHILE
)) ||
1073 opcode
== SHADER_OPCODE_FIND_LIVE_CHANNEL
||
1074 opcode
== FS_OPCODE_FB_WRITE
) {
1075 return flag_mask(this);
1077 return flag_mask(dst
, size_written
);
1082 * Returns how many MRFs an FS opcode will write over.
1084 * Note that this is not the 0 or 1 implied writes in an actual gen
1085 * instruction -- the FS opcodes often generate MOVs in addition.
1088 fs_visitor::implied_mrf_writes(fs_inst
*inst
) const
1090 if (inst
->mlen
== 0)
1093 if (inst
->base_mrf
== -1)
1096 switch (inst
->opcode
) {
1097 case SHADER_OPCODE_RCP
:
1098 case SHADER_OPCODE_RSQ
:
1099 case SHADER_OPCODE_SQRT
:
1100 case SHADER_OPCODE_EXP2
:
1101 case SHADER_OPCODE_LOG2
:
1102 case SHADER_OPCODE_SIN
:
1103 case SHADER_OPCODE_COS
:
1104 return 1 * dispatch_width
/ 8;
1105 case SHADER_OPCODE_POW
:
1106 case SHADER_OPCODE_INT_QUOTIENT
:
1107 case SHADER_OPCODE_INT_REMAINDER
:
1108 return 2 * dispatch_width
/ 8;
1109 case SHADER_OPCODE_TEX
:
1111 case SHADER_OPCODE_TXD
:
1112 case SHADER_OPCODE_TXF
:
1113 case SHADER_OPCODE_TXF_CMS
:
1114 case SHADER_OPCODE_TXF_MCS
:
1115 case SHADER_OPCODE_TG4
:
1116 case SHADER_OPCODE_TG4_OFFSET
:
1117 case SHADER_OPCODE_TXL
:
1118 case SHADER_OPCODE_TXS
:
1119 case SHADER_OPCODE_LOD
:
1120 case SHADER_OPCODE_SAMPLEINFO
:
1122 case FS_OPCODE_FB_WRITE
:
1123 case FS_OPCODE_REP_FB_WRITE
:
1124 return inst
->src
[0].file
== BAD_FILE
? 0 : 2;
1125 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1126 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1128 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
1130 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1133 unreachable("not reached");
1138 fs_visitor::vgrf(const glsl_type
*const type
)
1140 int reg_width
= dispatch_width
/ 8;
1142 alloc
.allocate(type_size_scalar(type
, false) * reg_width
),
1143 brw_type_for_base_type(type
));
1146 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1151 this->type
= BRW_REGISTER_TYPE_F
;
1152 this->stride
= (file
== UNIFORM
? 0 : 1);
1155 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1161 this->stride
= (file
== UNIFORM
? 0 : 1);
1164 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1165 * This brings in those uniform definitions
1168 fs_visitor::import_uniforms(fs_visitor
*v
)
1170 this->push_constant_loc
= v
->push_constant_loc
;
1171 this->pull_constant_loc
= v
->pull_constant_loc
;
1172 this->uniforms
= v
->uniforms
;
1173 this->subgroup_id
= v
->subgroup_id
;
1177 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1179 assert(stage
== MESA_SHADER_FRAGMENT
);
1181 /* gl_FragCoord.x */
1182 bld
.MOV(wpos
, this->pixel_x
);
1183 wpos
= offset(wpos
, bld
, 1);
1185 /* gl_FragCoord.y */
1186 bld
.MOV(wpos
, this->pixel_y
);
1187 wpos
= offset(wpos
, bld
, 1);
1189 /* gl_FragCoord.z */
1190 if (devinfo
->gen
>= 6) {
1191 bld
.MOV(wpos
, fetch_payload_reg(bld
, payload
.source_depth_reg
));
1193 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1194 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1195 interp_reg(VARYING_SLOT_POS
, 2));
1197 wpos
= offset(wpos
, bld
, 1);
1199 /* gl_FragCoord.w: Already set up in emit_interpolation */
1200 bld
.MOV(wpos
, this->wpos_w
);
1203 enum brw_barycentric_mode
1204 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1206 /* Barycentric modes don't make sense for flat inputs. */
1207 assert(mode
!= INTERP_MODE_FLAT
);
1211 case nir_intrinsic_load_barycentric_pixel
:
1212 case nir_intrinsic_load_barycentric_at_offset
:
1213 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1215 case nir_intrinsic_load_barycentric_centroid
:
1216 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1218 case nir_intrinsic_load_barycentric_sample
:
1219 case nir_intrinsic_load_barycentric_at_sample
:
1220 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1223 unreachable("invalid intrinsic");
1226 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1229 return (enum brw_barycentric_mode
) bary
;
1233 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1235 static enum brw_barycentric_mode
1236 centroid_to_pixel(enum brw_barycentric_mode bary
)
1238 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1239 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1240 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1244 fs_visitor::emit_frontfacing_interpolation()
1246 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1248 if (devinfo
->gen
>= 6) {
1249 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1250 * a boolean result from this (~0/true or 0/false).
1252 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1253 * this task in only one instruction:
1254 * - a negation source modifier will flip the bit; and
1255 * - a W -> D type conversion will sign extend the bit into the high
1256 * word of the destination.
1258 * An ASR 15 fills the low word of the destination.
1260 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1263 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1265 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1266 * a boolean result from this (1/true or 0/false).
1268 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1269 * the negation source modifier to flip it. Unfortunately the SHR
1270 * instruction only operates on UD (or D with an abs source modifier)
1271 * sources without negation.
1273 * Instead, use ASR (which will give ~0/true or 0/false).
1275 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1278 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1285 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1287 assert(stage
== MESA_SHADER_FRAGMENT
);
1288 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1289 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1291 if (wm_prog_data
->persample_dispatch
) {
1292 /* Convert int_sample_pos to floating point */
1293 bld
.MOV(dst
, int_sample_pos
);
1294 /* Scale to the range [0, 1] */
1295 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1298 /* From ARB_sample_shading specification:
1299 * "When rendering to a non-multisample buffer, or if multisample
1300 * rasterization is disabled, gl_SamplePosition will always be
1303 bld
.MOV(dst
, brw_imm_f(0.5f
));
1308 fs_visitor::emit_samplepos_setup()
1310 assert(devinfo
->gen
>= 6);
1312 const fs_builder abld
= bld
.annotate("compute sample position");
1313 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1315 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1316 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1318 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1319 * mode will be enabled.
1321 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1322 * R31.1:0 Position Offset X/Y for Slot[3:0]
1323 * R31.3:2 Position Offset X/Y for Slot[7:4]
1326 * The X, Y sample positions come in as bytes in thread payload. So, read
1327 * the positions using vstride=16, width=8, hstride=2.
1329 const fs_reg sample_pos_reg
=
1330 fetch_payload_reg(abld
, payload
.sample_pos_reg
, BRW_REGISTER_TYPE_W
);
1332 /* Compute gl_SamplePosition.x */
1333 abld
.MOV(int_sample_x
, subscript(sample_pos_reg
, BRW_REGISTER_TYPE_B
, 0));
1334 compute_sample_position(offset(pos
, abld
, 0), int_sample_x
);
1336 /* Compute gl_SamplePosition.y */
1337 abld
.MOV(int_sample_y
, subscript(sample_pos_reg
, BRW_REGISTER_TYPE_B
, 1));
1338 compute_sample_position(offset(pos
, abld
, 1), int_sample_y
);
1343 fs_visitor::emit_sampleid_setup()
1345 assert(stage
== MESA_SHADER_FRAGMENT
);
1346 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1347 assert(devinfo
->gen
>= 6);
1349 const fs_builder abld
= bld
.annotate("compute sample id");
1350 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uint_type
));
1352 if (!key
->multisample_fbo
) {
1353 /* As per GL_ARB_sample_shading specification:
1354 * "When rendering to a non-multisample buffer, or if multisample
1355 * rasterization is disabled, gl_SampleID will always be zero."
1357 abld
.MOV(*reg
, brw_imm_d(0));
1358 } else if (devinfo
->gen
>= 8) {
1359 /* Sample ID comes in as 4-bit numbers in g1.0:
1361 * 15:12 Slot 3 SampleID (only used in SIMD16)
1362 * 11:8 Slot 2 SampleID (only used in SIMD16)
1363 * 7:4 Slot 1 SampleID
1364 * 3:0 Slot 0 SampleID
1366 * Each slot corresponds to four channels, so we want to replicate each
1367 * half-byte value to 4 channels in a row:
1369 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1370 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1372 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1373 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1375 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1376 * channels to read the first byte (7:0), and the second group of 8
1377 * channels to read the second byte (15:8). Then, we shift right by
1378 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1379 * values into place. Finally, we AND with 0xf to keep the low nibble.
1381 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1382 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1384 * TODO: These payload bits exist on Gen7 too, but they appear to always
1385 * be zero, so this code fails to work. We should find out why.
1387 const fs_reg tmp
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
1389 for (unsigned i
= 0; i
< DIV_ROUND_UP(dispatch_width
, 16); i
++) {
1390 const fs_builder hbld
= abld
.group(MIN2(16, dispatch_width
), i
);
1391 hbld
.SHR(offset(tmp
, hbld
, i
),
1392 stride(retype(brw_vec1_grf(1 + i
, 0), BRW_REGISTER_TYPE_UB
),
1394 brw_imm_v(0x44440000));
1397 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1399 const fs_reg t1
= component(abld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
1400 const fs_reg t2
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
1402 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1403 * 8x multisampling, subspan 0 will represent sample N (where N
1404 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1405 * 7. We can find the value of N by looking at R0.0 bits 7:6
1406 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1407 * (since samples are always delivered in pairs). That is, we
1408 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1409 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1410 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1411 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1412 * populating a temporary variable with the sequence (0, 1, 2, 3),
1413 * and then reading from it using vstride=1, width=4, hstride=0.
1414 * These computations hold good for 4x multisampling as well.
1416 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1417 * the first four slots are sample 0 of subspan 0; the next four
1418 * are sample 1 of subspan 0; the third group is sample 0 of
1419 * subspan 1, and finally sample 1 of subspan 1.
1422 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1423 * accomodate 16x MSAA.
1425 abld
.exec_all().group(1, 0)
1426 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1428 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1430 /* This works for SIMD8-SIMD16. It also works for SIMD32 but only if we
1431 * can assume 4x MSAA. Disallow it on IVB+
1433 * FINISHME: One day, we could come up with a way to do this that
1434 * actually works on gen7.
1436 if (devinfo
->gen
>= 7)
1437 limit_dispatch_width(16, "gl_SampleId is unsupported in SIMD32 on gen7");
1438 abld
.exec_all().group(8, 0).MOV(t2
, brw_imm_v(0x32103210));
1440 /* This special instruction takes care of setting vstride=1,
1441 * width=4, hstride=0 of t2 during an ADD instruction.
1443 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1450 fs_visitor::emit_samplemaskin_setup()
1452 assert(stage
== MESA_SHADER_FRAGMENT
);
1453 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1454 assert(devinfo
->gen
>= 6);
1456 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1458 fs_reg coverage_mask
=
1459 fetch_payload_reg(bld
, payload
.sample_mask_in_reg
, BRW_REGISTER_TYPE_D
);
1461 if (wm_prog_data
->persample_dispatch
) {
1462 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1463 * and a mask representing which sample is being processed by the
1464 * current shader invocation.
1466 * From the OES_sample_variables specification:
1467 * "When per-sample shading is active due to the use of a fragment input
1468 * qualified by "sample" or due to the use of the gl_SampleID or
1469 * gl_SamplePosition variables, only the bit for the current sample is
1470 * set in gl_SampleMaskIn."
1472 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1474 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1475 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1477 fs_reg one
= vgrf(glsl_type::int_type
);
1478 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1479 abld
.MOV(one
, brw_imm_d(1));
1480 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1481 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1483 /* In per-pixel mode, the coverage mask is sufficient. */
1484 *reg
= coverage_mask
;
1490 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1492 if (!src
.abs
&& !src
.negate
)
1495 fs_reg temp
= bld
.vgrf(src
.type
);
1502 fs_visitor::emit_discard_jump()
1504 assert(brw_wm_prog_data(this->prog_data
)->uses_kill
);
1506 /* For performance, after a discard, jump to the end of the
1507 * shader if all relevant channels have been discarded.
1509 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1510 discard_jump
->flag_subreg
= 1;
1512 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1513 discard_jump
->predicate_inverse
= true;
1517 fs_visitor::emit_gs_thread_end()
1519 assert(stage
== MESA_SHADER_GEOMETRY
);
1521 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1523 if (gs_compile
->control_data_header_size_bits
> 0) {
1524 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1527 const fs_builder abld
= bld
.annotate("thread end");
1530 if (gs_prog_data
->static_vertex_count
!= -1) {
1531 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1532 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1533 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1534 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1535 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1538 /* Delete now dead instructions. */
1539 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1545 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1549 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1550 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1551 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1554 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1555 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1556 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1557 sources
[1] = this->final_gs_vertex_count
;
1558 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1559 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1567 fs_visitor::assign_curb_setup()
1569 unsigned uniform_push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
1571 unsigned ubo_push_length
= 0;
1572 unsigned ubo_push_start
[4];
1573 for (int i
= 0; i
< 4; i
++) {
1574 ubo_push_start
[i
] = 8 * (ubo_push_length
+ uniform_push_length
);
1575 ubo_push_length
+= stage_prog_data
->ubo_ranges
[i
].length
;
1578 prog_data
->curb_read_length
= uniform_push_length
+ ubo_push_length
;
1580 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1581 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1582 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1583 if (inst
->src
[i
].file
== UNIFORM
) {
1584 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1586 if (inst
->src
[i
].nr
>= UBO_START
) {
1587 /* constant_nr is in 32-bit units, the rest are in bytes */
1588 constant_nr
= ubo_push_start
[inst
->src
[i
].nr
- UBO_START
] +
1589 inst
->src
[i
].offset
/ 4;
1590 } else if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1591 constant_nr
= push_constant_loc
[uniform_nr
];
1593 /* Section 5.11 of the OpenGL 4.1 spec says:
1594 * "Out-of-bounds reads return undefined values, which include
1595 * values from other variables of the active program or zero."
1596 * Just return the first push constant.
1601 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1604 brw_reg
.abs
= inst
->src
[i
].abs
;
1605 brw_reg
.negate
= inst
->src
[i
].negate
;
1607 assert(inst
->src
[i
].stride
== 0);
1608 inst
->src
[i
] = byte_offset(
1609 retype(brw_reg
, inst
->src
[i
].type
),
1610 inst
->src
[i
].offset
% 4);
1615 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1616 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1620 calculate_urb_setup(const struct gen_device_info
*devinfo
,
1621 const struct brw_wm_prog_key
*key
,
1622 struct brw_wm_prog_data
*prog_data
,
1623 const nir_shader
*nir
)
1625 memset(prog_data
->urb_setup
, -1,
1626 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1629 /* Figure out where each of the incoming setup attributes lands. */
1630 if (devinfo
->gen
>= 6) {
1631 if (util_bitcount64(nir
->info
.inputs_read
&
1632 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1633 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1634 * first 16 varying inputs, so we can put them wherever we want.
1635 * Just put them in order.
1637 * This is useful because it means that (a) inputs not used by the
1638 * fragment shader won't take up valuable register space, and (b) we
1639 * won't have to recompile the fragment shader if it gets paired with
1640 * a different vertex (or geometry) shader.
1642 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1643 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1644 BITFIELD64_BIT(i
)) {
1645 prog_data
->urb_setup
[i
] = urb_next
++;
1649 /* We have enough input varyings that the SF/SBE pipeline stage can't
1650 * arbitrarily rearrange them to suit our whim; we have to put them
1651 * in an order that matches the output of the previous pipeline stage
1652 * (geometry or vertex shader).
1654 struct brw_vue_map prev_stage_vue_map
;
1655 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1656 key
->input_slots_valid
,
1657 nir
->info
.separate_shader
);
1660 brw_compute_first_urb_slot_required(nir
->info
.inputs_read
,
1661 &prev_stage_vue_map
);
1663 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1664 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1666 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1667 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1668 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1669 BITFIELD64_BIT(varying
))) {
1670 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1673 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1676 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1677 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1678 /* Point size is packed into the header, not as a general attribute */
1679 if (i
== VARYING_SLOT_PSIZ
)
1682 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1683 /* The back color slot is skipped when the front color is
1684 * also written to. In addition, some slots can be
1685 * written in the vertex shader and not read in the
1686 * fragment shader. So the register number must always be
1687 * incremented, mapped or not.
1689 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1690 prog_data
->urb_setup
[i
] = urb_next
;
1696 * It's a FS only attribute, and we did interpolation for this attribute
1697 * in SF thread. So, count it here, too.
1699 * See compile_sf_prog() for more info.
1701 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1702 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1705 prog_data
->num_varying_inputs
= urb_next
;
1709 fs_visitor::assign_urb_setup()
1711 assert(stage
== MESA_SHADER_FRAGMENT
);
1712 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1714 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1716 /* Offset all the urb_setup[] index by the actual position of the
1717 * setup regs, now that the location of the constants has been chosen.
1719 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1720 for (int i
= 0; i
< inst
->sources
; i
++) {
1721 if (inst
->src
[i
].file
== ATTR
) {
1722 /* ATTR regs in the FS are in units of logical scalar inputs each
1723 * of which consumes half of a GRF register.
1725 assert(inst
->src
[i
].offset
< REG_SIZE
/ 2);
1726 const unsigned grf
= urb_start
+ inst
->src
[i
].nr
/ 2;
1727 const unsigned offset
= (inst
->src
[i
].nr
% 2) * (REG_SIZE
/ 2) +
1728 inst
->src
[i
].offset
;
1729 const unsigned width
= inst
->src
[i
].stride
== 0 ?
1730 1 : MIN2(inst
->exec_size
, 8);
1731 struct brw_reg reg
= stride(
1732 byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1734 width
* inst
->src
[i
].stride
,
1735 width
, inst
->src
[i
].stride
);
1736 reg
.abs
= inst
->src
[i
].abs
;
1737 reg
.negate
= inst
->src
[i
].negate
;
1743 /* Each attribute is 4 setup channels, each of which is half a reg. */
1744 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1748 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1750 for (int i
= 0; i
< inst
->sources
; i
++) {
1751 if (inst
->src
[i
].file
== ATTR
) {
1752 int grf
= payload
.num_regs
+
1753 prog_data
->curb_read_length
+
1755 inst
->src
[i
].offset
/ REG_SIZE
;
1757 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1759 * VertStride must be used to cross GRF register boundaries. This
1760 * rule implies that elements within a 'Width' cannot cross GRF
1763 * So, for registers that are large enough, we have to split the exec
1764 * size in two and trust the compression state to sort it out.
1766 unsigned total_size
= inst
->exec_size
*
1767 inst
->src
[i
].stride
*
1768 type_sz(inst
->src
[i
].type
);
1770 assert(total_size
<= 2 * REG_SIZE
);
1771 const unsigned exec_size
=
1772 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1774 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1775 struct brw_reg reg
=
1776 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1777 inst
->src
[i
].offset
% REG_SIZE
),
1778 exec_size
* inst
->src
[i
].stride
,
1779 width
, inst
->src
[i
].stride
);
1780 reg
.abs
= inst
->src
[i
].abs
;
1781 reg
.negate
= inst
->src
[i
].negate
;
1789 fs_visitor::assign_vs_urb_setup()
1791 struct brw_vs_prog_data
*vs_prog_data
= brw_vs_prog_data(prog_data
);
1793 assert(stage
== MESA_SHADER_VERTEX
);
1795 /* Each attribute is 4 regs. */
1796 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1798 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1800 /* Rewrite all ATTR file references to the hw grf that they land in. */
1801 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1802 convert_attr_sources_to_hw_regs(inst
);
1807 fs_visitor::assign_tcs_urb_setup()
1809 assert(stage
== MESA_SHADER_TESS_CTRL
);
1811 /* Rewrite all ATTR file references to HW_REGs. */
1812 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1813 convert_attr_sources_to_hw_regs(inst
);
1818 fs_visitor::assign_tes_urb_setup()
1820 assert(stage
== MESA_SHADER_TESS_EVAL
);
1822 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1824 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1826 /* Rewrite all ATTR file references to HW_REGs. */
1827 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1828 convert_attr_sources_to_hw_regs(inst
);
1833 fs_visitor::assign_gs_urb_setup()
1835 assert(stage
== MESA_SHADER_GEOMETRY
);
1837 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1839 first_non_payload_grf
+=
1840 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1842 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1843 /* Rewrite all ATTR file references to GRFs. */
1844 convert_attr_sources_to_hw_regs(inst
);
1850 * Split large virtual GRFs into separate components if we can.
1852 * This is mostly duplicated with what brw_fs_vector_splitting does,
1853 * but that's really conservative because it's afraid of doing
1854 * splitting that doesn't result in real progress after the rest of
1855 * the optimization phases, which would cause infinite looping in
1856 * optimization. We can do it once here, safely. This also has the
1857 * opportunity to split interpolated values, or maybe even uniforms,
1858 * which we don't have at the IR level.
1860 * We want to split, because virtual GRFs are what we register
1861 * allocate and spill (due to contiguousness requirements for some
1862 * instructions), and they're what we naturally generate in the
1863 * codegen process, but most virtual GRFs don't actually need to be
1864 * contiguous sets of GRFs. If we split, we'll end up with reduced
1865 * live intervals and better dead code elimination and coalescing.
1868 fs_visitor::split_virtual_grfs()
1870 /* Compact the register file so we eliminate dead vgrfs. This
1871 * only defines split points for live registers, so if we have
1872 * too large dead registers they will hit assertions later.
1874 compact_virtual_grfs();
1876 int num_vars
= this->alloc
.count
;
1878 /* Count the total number of registers */
1880 int vgrf_to_reg
[num_vars
];
1881 for (int i
= 0; i
< num_vars
; i
++) {
1882 vgrf_to_reg
[i
] = reg_count
;
1883 reg_count
+= alloc
.sizes
[i
];
1886 /* An array of "split points". For each register slot, this indicates
1887 * if this slot can be separated from the previous slot. Every time an
1888 * instruction uses multiple elements of a register (as a source or
1889 * destination), we mark the used slots as inseparable. Then we go
1890 * through and split the registers into the smallest pieces we can.
1892 bool *split_points
= new bool[reg_count
];
1893 memset(split_points
, 0, reg_count
* sizeof(*split_points
));
1895 /* Mark all used registers as fully splittable */
1896 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1897 if (inst
->dst
.file
== VGRF
) {
1898 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1899 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1900 split_points
[reg
+ j
] = true;
1903 for (int i
= 0; i
< inst
->sources
; i
++) {
1904 if (inst
->src
[i
].file
== VGRF
) {
1905 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1906 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1907 split_points
[reg
+ j
] = true;
1912 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1913 if (inst
->dst
.file
== VGRF
) {
1914 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1915 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1916 split_points
[reg
+ j
] = false;
1918 for (int i
= 0; i
< inst
->sources
; i
++) {
1919 if (inst
->src
[i
].file
== VGRF
) {
1920 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1921 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1922 split_points
[reg
+ j
] = false;
1927 int *new_virtual_grf
= new int[reg_count
];
1928 int *new_reg_offset
= new int[reg_count
];
1931 for (int i
= 0; i
< num_vars
; i
++) {
1932 /* The first one should always be 0 as a quick sanity check. */
1933 assert(split_points
[reg
] == false);
1936 new_reg_offset
[reg
] = 0;
1941 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1942 /* If this is a split point, reset the offset to 0 and allocate a
1943 * new virtual GRF for the previous offset many registers
1945 if (split_points
[reg
]) {
1946 assert(offset
<= MAX_VGRF_SIZE
);
1947 int grf
= alloc
.allocate(offset
);
1948 for (int k
= reg
- offset
; k
< reg
; k
++)
1949 new_virtual_grf
[k
] = grf
;
1952 new_reg_offset
[reg
] = offset
;
1957 /* The last one gets the original register number */
1958 assert(offset
<= MAX_VGRF_SIZE
);
1959 alloc
.sizes
[i
] = offset
;
1960 for (int k
= reg
- offset
; k
< reg
; k
++)
1961 new_virtual_grf
[k
] = i
;
1963 assert(reg
== reg_count
);
1965 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1966 if (inst
->dst
.file
== VGRF
) {
1967 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1968 inst
->dst
.nr
= new_virtual_grf
[reg
];
1969 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
1970 inst
->dst
.offset
% REG_SIZE
;
1971 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1973 for (int i
= 0; i
< inst
->sources
; i
++) {
1974 if (inst
->src
[i
].file
== VGRF
) {
1975 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1976 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1977 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
1978 inst
->src
[i
].offset
% REG_SIZE
;
1979 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1983 invalidate_live_intervals();
1985 delete[] split_points
;
1986 delete[] new_virtual_grf
;
1987 delete[] new_reg_offset
;
1991 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1993 * During code generation, we create tons of temporary variables, many of
1994 * which get immediately killed and are never used again. Yet, in later
1995 * optimization and analysis passes, such as compute_live_intervals, we need
1996 * to loop over all the virtual GRFs. Compacting them can save a lot of
2000 fs_visitor::compact_virtual_grfs()
2002 bool progress
= false;
2003 int *remap_table
= new int[this->alloc
.count
];
2004 memset(remap_table
, -1, this->alloc
.count
* sizeof(int));
2006 /* Mark which virtual GRFs are used. */
2007 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
2008 if (inst
->dst
.file
== VGRF
)
2009 remap_table
[inst
->dst
.nr
] = 0;
2011 for (int i
= 0; i
< inst
->sources
; i
++) {
2012 if (inst
->src
[i
].file
== VGRF
)
2013 remap_table
[inst
->src
[i
].nr
] = 0;
2017 /* Compact the GRF arrays. */
2019 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
2020 if (remap_table
[i
] == -1) {
2021 /* We just found an unused register. This means that we are
2022 * actually going to compact something.
2026 remap_table
[i
] = new_index
;
2027 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
2028 invalidate_live_intervals();
2033 this->alloc
.count
= new_index
;
2035 /* Patch all the instructions to use the newly renumbered registers */
2036 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2037 if (inst
->dst
.file
== VGRF
)
2038 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
2040 for (int i
= 0; i
< inst
->sources
; i
++) {
2041 if (inst
->src
[i
].file
== VGRF
)
2042 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
2046 /* Patch all the references to delta_xy, since they're used in register
2047 * allocation. If they're unused, switch them to BAD_FILE so we don't
2048 * think some random VGRF is delta_xy.
2050 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2051 if (delta_xy
[i
].file
== VGRF
) {
2052 if (remap_table
[delta_xy
[i
].nr
] != -1) {
2053 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
2055 delta_xy
[i
].file
= BAD_FILE
;
2060 delete[] remap_table
;
2066 get_subgroup_id_param_index(const brw_stage_prog_data
*prog_data
)
2068 if (prog_data
->nr_params
== 0)
2071 /* The local thread id is always the last parameter in the list */
2072 uint32_t last_param
= prog_data
->param
[prog_data
->nr_params
- 1];
2073 if (last_param
== BRW_PARAM_BUILTIN_SUBGROUP_ID
)
2074 return prog_data
->nr_params
- 1;
2080 * Struct for handling complex alignments.
2082 * A complex alignment is stored as multiplier and an offset. A value is
2083 * considered to be aligned if it is {offset} larger than a multiple of {mul}.
2084 * For instance, with an alignment of {8, 2}, cplx_align_apply would do the
2087 * N | cplx_align_apply({8, 2}, N)
2088 * ----+-----------------------------
2102 #define CPLX_ALIGN_MAX_MUL 8
2105 cplx_align_assert_sane(struct cplx_align a
)
2107 assert(a
.mul
> 0 && util_is_power_of_two_nonzero(a
.mul
));
2108 assert(a
.offset
< a
.mul
);
2112 * Combines two alignments to produce a least multiple of sorts.
2114 * The returned alignment is the smallest (in terms of multiplier) such that
2115 * anything aligned to both a and b will be aligned to the new alignment.
2116 * This function will assert-fail if a and b are not compatible, i.e. if the
2117 * offset parameters are such that no common alignment is possible.
2119 static struct cplx_align
2120 cplx_align_combine(struct cplx_align a
, struct cplx_align b
)
2122 cplx_align_assert_sane(a
);
2123 cplx_align_assert_sane(b
);
2125 /* Assert that the alignments agree. */
2126 assert((a
.offset
& (b
.mul
- 1)) == (b
.offset
& (a
.mul
- 1)));
2128 return a
.mul
> b
.mul
? a
: b
;
2132 * Apply a complex alignment
2134 * This function will return the smallest number greater than or equal to
2135 * offset that is aligned to align.
2138 cplx_align_apply(struct cplx_align align
, unsigned offset
)
2140 return ALIGN(offset
- align
.offset
, align
.mul
) + align
.offset
;
2143 #define UNIFORM_SLOT_SIZE 4
2145 struct uniform_slot_info
{
2146 /** True if the given uniform slot is live */
2149 /** True if this slot and the next slot must remain contiguous */
2150 unsigned contiguous
:1;
2152 struct cplx_align align
;
2156 mark_uniform_slots_read(struct uniform_slot_info
*slots
,
2157 unsigned num_slots
, unsigned alignment
)
2159 assert(alignment
> 0 && util_is_power_of_two_nonzero(alignment
));
2160 assert(alignment
<= CPLX_ALIGN_MAX_MUL
);
2162 /* We can't align a slot to anything less than the slot size */
2163 alignment
= MAX2(alignment
, UNIFORM_SLOT_SIZE
);
2165 struct cplx_align align
= {alignment
, 0};
2166 cplx_align_assert_sane(align
);
2168 for (unsigned i
= 0; i
< num_slots
; i
++) {
2169 slots
[i
].is_live
= true;
2170 if (i
< num_slots
- 1)
2171 slots
[i
].contiguous
= true;
2173 align
.offset
= (i
* UNIFORM_SLOT_SIZE
) & (align
.mul
- 1);
2174 if (slots
[i
].align
.mul
== 0) {
2175 slots
[i
].align
= align
;
2177 slots
[i
].align
= cplx_align_combine(slots
[i
].align
, align
);
2183 * Assign UNIFORM file registers to either push constants or pull constants.
2185 * We allow a fragment shader to have more than the specified minimum
2186 * maximum number of fragment shader uniform components (64). If
2187 * there are too many of these, they'd fill up all of register space.
2188 * So, this will push some of them out to the pull constant buffer and
2189 * update the program to load them.
2192 fs_visitor::assign_constant_locations()
2194 /* Only the first compile gets to decide on locations. */
2195 if (push_constant_loc
) {
2196 assert(pull_constant_loc
);
2200 struct uniform_slot_info slots
[uniforms
];
2201 memset(slots
, 0, sizeof(slots
));
2203 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2204 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2205 if (inst
->src
[i
].file
!= UNIFORM
)
2208 /* NIR tightly packs things so the uniform number might not be
2209 * aligned (if we have a double right after a float, for instance).
2210 * This is fine because the process of re-arranging them will ensure
2211 * that things are properly aligned. The offset into that uniform,
2212 * however, must be aligned.
2214 * In Vulkan, we have explicit offsets but everything is crammed
2215 * into a single "variable" so inst->src[i].nr will always be 0.
2216 * Everything will be properly aligned relative to that one base.
2218 assert(inst
->src
[i
].offset
% type_sz(inst
->src
[i
].type
) == 0);
2220 unsigned u
= inst
->src
[i
].nr
+
2221 inst
->src
[i
].offset
/ UNIFORM_SLOT_SIZE
;
2226 unsigned slots_read
;
2227 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2228 slots_read
= DIV_ROUND_UP(inst
->src
[2].ud
, UNIFORM_SLOT_SIZE
);
2230 unsigned bytes_read
= inst
->components_read(i
) *
2231 type_sz(inst
->src
[i
].type
);
2232 slots_read
= DIV_ROUND_UP(bytes_read
, UNIFORM_SLOT_SIZE
);
2235 assert(u
+ slots_read
<= uniforms
);
2236 mark_uniform_slots_read(&slots
[u
], slots_read
,
2237 type_sz(inst
->src
[i
].type
));
2241 int subgroup_id_index
= get_subgroup_id_param_index(stage_prog_data
);
2243 /* Only allow 16 registers (128 uniform components) as push constants.
2245 * Just demote the end of the list. We could probably do better
2246 * here, demoting things that are rarely used in the program first.
2248 * If changing this value, note the limitation about total_regs in
2251 unsigned int max_push_components
= 16 * 8;
2252 if (subgroup_id_index
>= 0)
2253 max_push_components
--; /* Save a slot for the thread ID */
2255 /* We push small arrays, but no bigger than 16 floats. This is big enough
2256 * for a vec4 but hopefully not large enough to push out other stuff. We
2257 * should probably use a better heuristic at some point.
2259 const unsigned int max_chunk_size
= 16;
2261 unsigned int num_push_constants
= 0;
2262 unsigned int num_pull_constants
= 0;
2264 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2265 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2267 /* Default to -1 meaning no location */
2268 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2269 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2271 int chunk_start
= -1;
2272 struct cplx_align align
;
2273 for (unsigned u
= 0; u
< uniforms
; u
++) {
2274 if (!slots
[u
].is_live
) {
2275 assert(chunk_start
== -1);
2279 /* Skip subgroup_id_index to put it in the last push register. */
2280 if (subgroup_id_index
== (int)u
)
2283 if (chunk_start
== -1) {
2285 align
= slots
[u
].align
;
2287 /* Offset into the chunk */
2288 unsigned chunk_offset
= (u
- chunk_start
) * UNIFORM_SLOT_SIZE
;
2290 /* Shift the slot alignment down by the chunk offset so it is
2291 * comparable with the base chunk alignment.
2293 struct cplx_align slot_align
= slots
[u
].align
;
2295 (slot_align
.offset
- chunk_offset
) & (align
.mul
- 1);
2297 align
= cplx_align_combine(align
, slot_align
);
2300 /* Sanity check the alignment */
2301 cplx_align_assert_sane(align
);
2303 if (slots
[u
].contiguous
)
2306 /* Adjust the alignment to be in terms of slots, not bytes */
2307 assert((align
.mul
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2308 assert((align
.offset
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2309 align
.mul
/= UNIFORM_SLOT_SIZE
;
2310 align
.offset
/= UNIFORM_SLOT_SIZE
;
2312 unsigned push_start_align
= cplx_align_apply(align
, num_push_constants
);
2313 unsigned chunk_size
= u
- chunk_start
+ 1;
2314 if ((!compiler
->supports_pull_constants
&& u
< UBO_START
) ||
2315 (chunk_size
< max_chunk_size
&&
2316 push_start_align
+ chunk_size
<= max_push_components
)) {
2317 /* Align up the number of push constants */
2318 num_push_constants
= push_start_align
;
2319 for (unsigned i
= 0; i
< chunk_size
; i
++)
2320 push_constant_loc
[chunk_start
+ i
] = num_push_constants
++;
2322 /* We need to pull this one */
2323 num_pull_constants
= cplx_align_apply(align
, num_pull_constants
);
2324 for (unsigned i
= 0; i
< chunk_size
; i
++)
2325 pull_constant_loc
[chunk_start
+ i
] = num_pull_constants
++;
2328 /* Reset the chunk and start again */
2332 /* Add the CS local thread ID uniform at the end of the push constants */
2333 if (subgroup_id_index
>= 0)
2334 push_constant_loc
[subgroup_id_index
] = num_push_constants
++;
2336 /* As the uniforms are going to be reordered, stash the old array and
2337 * create two new arrays for push/pull params.
2339 uint32_t *param
= stage_prog_data
->param
;
2340 stage_prog_data
->nr_params
= num_push_constants
;
2341 if (num_push_constants
) {
2342 stage_prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t,
2343 num_push_constants
);
2345 stage_prog_data
->param
= NULL
;
2347 assert(stage_prog_data
->nr_pull_params
== 0);
2348 assert(stage_prog_data
->pull_param
== NULL
);
2349 if (num_pull_constants
> 0) {
2350 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2351 stage_prog_data
->pull_param
= rzalloc_array(mem_ctx
, uint32_t,
2352 num_pull_constants
);
2355 /* Now that we know how many regular uniforms we'll push, reduce the
2356 * UBO push ranges so we don't exceed the 3DSTATE_CONSTANT limits.
2358 unsigned push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
2359 for (int i
= 0; i
< 4; i
++) {
2360 struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2362 if (push_length
+ range
->length
> 64)
2363 range
->length
= 64 - push_length
;
2365 push_length
+= range
->length
;
2367 assert(push_length
<= 64);
2369 /* Up until now, the param[] array has been indexed by reg + offset
2370 * of UNIFORM registers. Move pull constants into pull_param[] and
2371 * condense param[] to only contain the uniforms we chose to push.
2373 * NOTE: Because we are condensing the params[] array, we know that
2374 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2375 * having to make a copy.
2377 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2378 uint32_t value
= param
[i
];
2379 if (pull_constant_loc
[i
] != -1) {
2380 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2381 } else if (push_constant_loc
[i
] != -1) {
2382 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2389 fs_visitor::get_pull_locs(const fs_reg
&src
,
2390 unsigned *out_surf_index
,
2391 unsigned *out_pull_index
)
2393 assert(src
.file
== UNIFORM
);
2395 if (src
.nr
>= UBO_START
) {
2396 const struct brw_ubo_range
*range
=
2397 &prog_data
->ubo_ranges
[src
.nr
- UBO_START
];
2399 /* If this access is in our (reduced) range, use the push data. */
2400 if (src
.offset
/ 32 < range
->length
)
2403 *out_surf_index
= prog_data
->binding_table
.ubo_start
+ range
->block
;
2404 *out_pull_index
= (32 * range
->start
+ src
.offset
) / 4;
2408 const unsigned location
= src
.nr
+ src
.offset
/ 4;
2410 if (location
< uniforms
&& pull_constant_loc
[location
] != -1) {
2411 /* A regular uniform push constant */
2412 *out_surf_index
= stage_prog_data
->binding_table
.pull_constants_start
;
2413 *out_pull_index
= pull_constant_loc
[location
];
2421 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2422 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2425 fs_visitor::lower_constant_loads()
2427 unsigned index
, pull_index
;
2429 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2430 /* Set up the annotation tracking for new generated instructions. */
2431 const fs_builder
ibld(this, block
, inst
);
2433 for (int i
= 0; i
< inst
->sources
; i
++) {
2434 if (inst
->src
[i
].file
!= UNIFORM
)
2437 /* We'll handle this case later */
2438 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2441 if (!get_pull_locs(inst
->src
[i
], &index
, &pull_index
))
2444 assert(inst
->src
[i
].stride
== 0);
2446 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
2447 const fs_builder ubld
= ibld
.exec_all().group(block_sz
/ 4, 0);
2448 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
2449 const unsigned base
= pull_index
* 4;
2451 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2452 dst
, brw_imm_ud(index
), brw_imm_ud(base
& ~(block_sz
- 1)));
2454 /* Rewrite the instruction to use the temporary VGRF. */
2455 inst
->src
[i
].file
= VGRF
;
2456 inst
->src
[i
].nr
= dst
.nr
;
2457 inst
->src
[i
].offset
= (base
& (block_sz
- 1)) +
2458 inst
->src
[i
].offset
% 4;
2461 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2462 inst
->src
[0].file
== UNIFORM
) {
2464 if (!get_pull_locs(inst
->src
[0], &index
, &pull_index
))
2467 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2471 inst
->remove(block
);
2474 invalidate_live_intervals();
2478 fs_visitor::opt_algebraic()
2480 bool progress
= false;
2482 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2483 switch (inst
->opcode
) {
2484 case BRW_OPCODE_MOV
:
2485 if (!devinfo
->has_64bit_types
&&
2486 (inst
->dst
.type
== BRW_REGISTER_TYPE_DF
||
2487 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
||
2488 inst
->dst
.type
== BRW_REGISTER_TYPE_Q
)) {
2489 assert(inst
->dst
.type
== inst
->src
[0].type
);
2490 assert(!inst
->saturate
);
2491 assert(!inst
->src
[0].abs
);
2492 assert(!inst
->src
[0].negate
);
2493 const brw::fs_builder
ibld(this, block
, inst
);
2495 if (inst
->src
[0].file
== IMM
) {
2496 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2497 brw_imm_ud(inst
->src
[0].u64
>> 32));
2498 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2499 brw_imm_ud(inst
->src
[0].u64
));
2501 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2502 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1));
2503 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2504 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0));
2507 inst
->remove(block
);
2511 if ((inst
->conditional_mod
== BRW_CONDITIONAL_Z
||
2512 inst
->conditional_mod
== BRW_CONDITIONAL_NZ
) &&
2513 inst
->dst
.is_null() &&
2514 (inst
->src
[0].abs
|| inst
->src
[0].negate
)) {
2515 inst
->src
[0].abs
= false;
2516 inst
->src
[0].negate
= false;
2521 if (inst
->src
[0].file
!= IMM
)
2524 if (inst
->saturate
) {
2525 /* Full mixed-type saturates don't happen. However, we can end up
2528 * mov.sat(8) g21<1>DF -1F
2530 * Other mixed-size-but-same-base-type cases may also be possible.
2532 if (inst
->dst
.type
!= inst
->src
[0].type
&&
2533 inst
->dst
.type
!= BRW_REGISTER_TYPE_DF
&&
2534 inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
)
2535 assert(!"unimplemented: saturate mixed types");
2537 if (brw_saturate_immediate(inst
->src
[0].type
,
2538 &inst
->src
[0].as_brw_reg())) {
2539 inst
->saturate
= false;
2545 case BRW_OPCODE_MUL
:
2546 if (inst
->src
[1].file
!= IMM
)
2550 if (inst
->src
[1].is_one()) {
2551 inst
->opcode
= BRW_OPCODE_MOV
;
2552 inst
->src
[1] = reg_undef
;
2558 if (inst
->src
[1].is_negative_one()) {
2559 inst
->opcode
= BRW_OPCODE_MOV
;
2560 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2561 inst
->src
[1] = reg_undef
;
2566 if (inst
->src
[0].file
== IMM
) {
2567 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2568 inst
->opcode
= BRW_OPCODE_MOV
;
2569 inst
->src
[0].f
*= inst
->src
[1].f
;
2570 inst
->src
[1] = reg_undef
;
2575 case BRW_OPCODE_ADD
:
2576 if (inst
->src
[1].file
!= IMM
)
2579 if (inst
->src
[0].file
== IMM
) {
2580 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2581 inst
->opcode
= BRW_OPCODE_MOV
;
2582 inst
->src
[0].f
+= inst
->src
[1].f
;
2583 inst
->src
[1] = reg_undef
;
2589 if (inst
->src
[0].equals(inst
->src
[1]) ||
2590 inst
->src
[1].is_zero()) {
2591 /* On Gen8+, the OR instruction can have a source modifier that
2592 * performs logical not on the operand. Cases of 'OR r0, ~r1, 0'
2593 * or 'OR r0, ~r1, ~r1' should become a NOT instead of a MOV.
2595 if (inst
->src
[0].negate
) {
2596 inst
->opcode
= BRW_OPCODE_NOT
;
2597 inst
->src
[0].negate
= false;
2599 inst
->opcode
= BRW_OPCODE_MOV
;
2601 inst
->src
[1] = reg_undef
;
2606 case BRW_OPCODE_CMP
:
2607 if ((inst
->conditional_mod
== BRW_CONDITIONAL_Z
||
2608 inst
->conditional_mod
== BRW_CONDITIONAL_NZ
) &&
2609 inst
->src
[1].is_zero() &&
2610 (inst
->src
[0].abs
|| inst
->src
[0].negate
)) {
2611 inst
->src
[0].abs
= false;
2612 inst
->src
[0].negate
= false;
2617 case BRW_OPCODE_SEL
:
2618 if (!devinfo
->has_64bit_types
&&
2619 (inst
->dst
.type
== BRW_REGISTER_TYPE_DF
||
2620 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
||
2621 inst
->dst
.type
== BRW_REGISTER_TYPE_Q
)) {
2622 assert(inst
->dst
.type
== inst
->src
[0].type
);
2623 assert(!inst
->saturate
);
2624 assert(!inst
->src
[0].abs
&& !inst
->src
[0].negate
);
2625 assert(!inst
->src
[1].abs
&& !inst
->src
[1].negate
);
2626 const brw::fs_builder
ibld(this, block
, inst
);
2628 set_predicate(inst
->predicate
,
2629 ibld
.SEL(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2630 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
2631 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0)));
2632 set_predicate(inst
->predicate
,
2633 ibld
.SEL(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2634 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1),
2635 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 1)));
2637 inst
->remove(block
);
2640 if (inst
->src
[0].equals(inst
->src
[1])) {
2641 inst
->opcode
= BRW_OPCODE_MOV
;
2642 inst
->src
[1] = reg_undef
;
2643 inst
->predicate
= BRW_PREDICATE_NONE
;
2644 inst
->predicate_inverse
= false;
2646 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2647 switch (inst
->conditional_mod
) {
2648 case BRW_CONDITIONAL_LE
:
2649 case BRW_CONDITIONAL_L
:
2650 switch (inst
->src
[1].type
) {
2651 case BRW_REGISTER_TYPE_F
:
2652 if (inst
->src
[1].f
>= 1.0f
) {
2653 inst
->opcode
= BRW_OPCODE_MOV
;
2654 inst
->src
[1] = reg_undef
;
2655 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2663 case BRW_CONDITIONAL_GE
:
2664 case BRW_CONDITIONAL_G
:
2665 switch (inst
->src
[1].type
) {
2666 case BRW_REGISTER_TYPE_F
:
2667 if (inst
->src
[1].f
<= 0.0f
) {
2668 inst
->opcode
= BRW_OPCODE_MOV
;
2669 inst
->src
[1] = reg_undef
;
2670 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2682 case BRW_OPCODE_MAD
:
2683 if (inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
||
2684 inst
->src
[1].type
!= BRW_REGISTER_TYPE_F
||
2685 inst
->src
[2].type
!= BRW_REGISTER_TYPE_F
)
2687 if (inst
->src
[1].is_one()) {
2688 inst
->opcode
= BRW_OPCODE_ADD
;
2689 inst
->src
[1] = inst
->src
[2];
2690 inst
->src
[2] = reg_undef
;
2692 } else if (inst
->src
[2].is_one()) {
2693 inst
->opcode
= BRW_OPCODE_ADD
;
2694 inst
->src
[2] = reg_undef
;
2698 case SHADER_OPCODE_BROADCAST
:
2699 if (is_uniform(inst
->src
[0])) {
2700 inst
->opcode
= BRW_OPCODE_MOV
;
2702 inst
->force_writemask_all
= true;
2704 } else if (inst
->src
[1].file
== IMM
) {
2705 inst
->opcode
= BRW_OPCODE_MOV
;
2706 /* It's possible that the selected component will be too large and
2707 * overflow the register. This can happen if someone does a
2708 * readInvocation() from GLSL or SPIR-V and provides an OOB
2709 * invocationIndex. If this happens and we some how manage
2710 * to constant fold it in and get here, then component() may cause
2711 * us to start reading outside of the VGRF which will lead to an
2712 * assert later. Instead, just let it wrap around if it goes over
2715 const unsigned comp
= inst
->src
[1].ud
& (inst
->exec_size
- 1);
2716 inst
->src
[0] = component(inst
->src
[0], comp
);
2718 inst
->force_writemask_all
= true;
2723 case SHADER_OPCODE_SHUFFLE
:
2724 if (is_uniform(inst
->src
[0])) {
2725 inst
->opcode
= BRW_OPCODE_MOV
;
2728 } else if (inst
->src
[1].file
== IMM
) {
2729 inst
->opcode
= BRW_OPCODE_MOV
;
2730 inst
->src
[0] = component(inst
->src
[0],
2741 /* Swap if src[0] is immediate. */
2742 if (progress
&& inst
->is_commutative()) {
2743 if (inst
->src
[0].file
== IMM
) {
2744 fs_reg tmp
= inst
->src
[1];
2745 inst
->src
[1] = inst
->src
[0];
2754 * Optimize sample messages that have constant zero values for the trailing
2755 * texture coordinates. We can just reduce the message length for these
2756 * instructions instead of reserving a register for it. Trailing parameters
2757 * that aren't sent default to zero anyway. This will cause the dead code
2758 * eliminator to remove the MOV instruction that would otherwise be emitted to
2759 * set up the zero value.
2762 fs_visitor::opt_zero_samples()
2764 /* Gen4 infers the texturing opcode based on the message length so we can't
2767 if (devinfo
->gen
< 5)
2770 bool progress
= false;
2772 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2773 if (!inst
->is_tex())
2776 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2778 if (load_payload
->is_head_sentinel() ||
2779 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2782 /* We don't want to remove the message header or the first parameter.
2783 * Removing the first parameter is not allowed, see the Haswell PRM
2784 * volume 7, page 149:
2786 * "Parameter 0 is required except for the sampleinfo message, which
2787 * has no parameter 0"
2789 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2790 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2791 (inst
->exec_size
/ 8) +
2792 inst
->header_size
- 1].is_zero()) {
2793 inst
->mlen
-= inst
->exec_size
/ 8;
2799 invalidate_live_intervals();
2805 * Optimize sample messages which are followed by the final RT write.
2807 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2808 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2809 * final texturing results copied to the framebuffer write payload and modify
2810 * them to write to the framebuffer directly.
2813 fs_visitor::opt_sampler_eot()
2815 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2817 if (stage
!= MESA_SHADER_FRAGMENT
|| dispatch_width
> 16)
2820 if (devinfo
->gen
!= 9 && !devinfo
->is_cherryview
)
2823 /* FINISHME: It should be possible to implement this optimization when there
2824 * are multiple drawbuffers.
2826 if (key
->nr_color_regions
!= 1)
2829 /* Requires emitting a bunch of saturating MOV instructions during logical
2830 * send lowering to clamp the color payload, which the sampler unit isn't
2831 * going to do for us.
2833 if (key
->clamp_fragment_color
)
2836 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2837 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2838 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2839 assert(fb_write
->eot
);
2840 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2842 /* There wasn't one; nothing to do. */
2843 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2846 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2848 /* 3D Sampler » Messages » Message Format
2850 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2851 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2853 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2854 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2855 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2856 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2857 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2858 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2859 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2860 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2863 /* XXX - This shouldn't be necessary. */
2864 if (tex_inst
->prev
->is_head_sentinel())
2867 /* Check that the FB write sources are fully initialized by the single
2868 * texturing instruction.
2870 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2871 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2872 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2873 fb_write
->size_read(i
) != tex_inst
->size_written
)
2875 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2876 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2881 assert(!tex_inst
->eot
); /* We can't get here twice */
2882 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2884 const fs_builder
ibld(this, block
, tex_inst
);
2886 tex_inst
->offset
|= fb_write
->target
<< 24;
2887 tex_inst
->eot
= true;
2888 tex_inst
->dst
= ibld
.null_reg_ud();
2889 tex_inst
->size_written
= 0;
2890 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2892 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2893 * flag and submit a header together with the sampler message as required
2896 invalidate_live_intervals();
2901 fs_visitor::opt_register_renaming()
2903 bool progress
= false;
2906 unsigned remap
[alloc
.count
];
2907 memset(remap
, ~0u, sizeof(unsigned) * alloc
.count
);
2909 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2910 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2912 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2913 inst
->opcode
== BRW_OPCODE_WHILE
) {
2917 /* Rewrite instruction sources. */
2918 for (int i
= 0; i
< inst
->sources
; i
++) {
2919 if (inst
->src
[i
].file
== VGRF
&&
2920 remap
[inst
->src
[i
].nr
] != ~0u &&
2921 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2922 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2927 const unsigned dst
= inst
->dst
.nr
;
2930 inst
->dst
.file
== VGRF
&&
2931 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
2932 !inst
->is_partial_write()) {
2933 if (remap
[dst
] == ~0u) {
2936 remap
[dst
] = alloc
.allocate(regs_written(inst
));
2937 inst
->dst
.nr
= remap
[dst
];
2940 } else if (inst
->dst
.file
== VGRF
&&
2941 remap
[dst
] != ~0u &&
2942 remap
[dst
] != dst
) {
2943 inst
->dst
.nr
= remap
[dst
];
2949 invalidate_live_intervals();
2951 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2952 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != ~0u) {
2953 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2962 * Remove redundant or useless discard jumps.
2964 * For example, we can eliminate jumps in the following sequence:
2966 * discard-jump (redundant with the next jump)
2967 * discard-jump (useless; jumps to the next instruction)
2971 fs_visitor::opt_redundant_discard_jumps()
2973 bool progress
= false;
2975 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2977 fs_inst
*placeholder_halt
= NULL
;
2978 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2979 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2980 placeholder_halt
= inst
;
2985 if (!placeholder_halt
)
2988 /* Delete any HALTs immediately before the placeholder halt. */
2989 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2990 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2991 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2992 prev
->remove(last_bblock
);
2997 invalidate_live_intervals();
3003 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
3004 * from \p r.offset which overlaps the region starting at \p s.offset and
3005 * spanning \p ds bytes.
3007 static inline unsigned
3008 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
3010 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
3011 const int shift
= rel_offset
/ REG_SIZE
;
3012 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
3013 assert(reg_space(r
) == reg_space(s
) &&
3014 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
3015 return ((1 << n
) - 1) << shift
;
3019 fs_visitor::opt_peephole_csel()
3021 if (devinfo
->gen
< 8)
3024 bool progress
= false;
3026 foreach_block_reverse(block
, cfg
) {
3027 int ip
= block
->end_ip
+ 1;
3029 foreach_inst_in_block_reverse_safe(fs_inst
, inst
, block
) {
3032 if (inst
->opcode
!= BRW_OPCODE_SEL
||
3033 inst
->predicate
!= BRW_PREDICATE_NORMAL
||
3034 (inst
->dst
.type
!= BRW_REGISTER_TYPE_F
&&
3035 inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3036 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3039 /* Because it is a 3-src instruction, CSEL cannot have an immediate
3040 * value as a source, but we can sometimes handle zero.
3042 if ((inst
->src
[0].file
!= VGRF
&& inst
->src
[0].file
!= ATTR
&&
3043 inst
->src
[0].file
!= UNIFORM
) ||
3044 (inst
->src
[1].file
!= VGRF
&& inst
->src
[1].file
!= ATTR
&&
3045 inst
->src
[1].file
!= UNIFORM
&& !inst
->src
[1].is_zero()))
3048 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3049 if (!scan_inst
->flags_written())
3052 if ((scan_inst
->opcode
!= BRW_OPCODE_CMP
&&
3053 scan_inst
->opcode
!= BRW_OPCODE_MOV
) ||
3054 scan_inst
->predicate
!= BRW_PREDICATE_NONE
||
3055 (scan_inst
->src
[0].file
!= VGRF
&&
3056 scan_inst
->src
[0].file
!= ATTR
&&
3057 scan_inst
->src
[0].file
!= UNIFORM
) ||
3058 scan_inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
)
3061 if (scan_inst
->opcode
== BRW_OPCODE_CMP
&& !scan_inst
->src
[1].is_zero())
3064 const brw::fs_builder
ibld(this, block
, inst
);
3066 const enum brw_conditional_mod cond
=
3067 inst
->predicate_inverse
3068 ? brw_negate_cmod(scan_inst
->conditional_mod
)
3069 : scan_inst
->conditional_mod
;
3071 fs_inst
*csel_inst
= NULL
;
3073 if (inst
->src
[1].file
!= IMM
) {
3074 csel_inst
= ibld
.CSEL(inst
->dst
,
3079 } else if (cond
== BRW_CONDITIONAL_NZ
) {
3080 /* Consider the sequence
3082 * cmp.nz.f0 null<1>F g3<8,8,1>F 0F
3083 * (+f0) sel g124<1>UD g2<8,8,1>UD 0x00000000UD
3085 * The sel will pick the immediate value 0 if r0 is ±0.0.
3086 * Therefore, this sequence is equivalent:
3088 * cmp.nz.f0 null<1>F g3<8,8,1>F 0F
3089 * (+f0) sel g124<1>F g2<8,8,1>F (abs)g3<8,8,1>F
3091 * The abs is ensures that the result is 0UD when g3 is -0.0F.
3092 * By normal cmp-sel merging, this is also equivalent:
3094 * csel.nz g124<1>F g2<4,4,1>F (abs)g3<4,4,1>F g3<4,4,1>F
3096 csel_inst
= ibld
.CSEL(inst
->dst
,
3102 csel_inst
->src
[1].abs
= true;
3105 if (csel_inst
!= NULL
) {
3107 csel_inst
->saturate
= inst
->saturate
;
3108 inst
->remove(block
);
3120 fs_visitor::compute_to_mrf()
3122 bool progress
= false;
3125 /* No MRFs on Gen >= 7. */
3126 if (devinfo
->gen
>= 7)
3129 calculate_live_intervals();
3131 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3135 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3136 inst
->is_partial_write() ||
3137 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
3138 inst
->dst
.type
!= inst
->src
[0].type
||
3139 inst
->src
[0].abs
|| inst
->src
[0].negate
||
3140 !inst
->src
[0].is_contiguous() ||
3141 inst
->src
[0].offset
% REG_SIZE
!= 0)
3144 /* Can't compute-to-MRF this GRF if someone else was going to
3147 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
3150 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
3151 * things that computed the value of all GRFs of the source region. The
3152 * regs_left bitset keeps track of the registers we haven't yet found a
3153 * generating instruction for.
3155 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
3157 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3158 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3159 inst
->src
[0], inst
->size_read(0))) {
3160 /* Found the last thing to write our reg we want to turn
3161 * into a compute-to-MRF.
3164 /* If this one instruction didn't populate all the
3165 * channels, bail. We might be able to rewrite everything
3166 * that writes that reg, but it would require smarter
3169 if (scan_inst
->is_partial_write())
3172 /* Handling things not fully contained in the source of the copy
3173 * would need us to understand coalescing out more than one MOV at
3176 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
3177 inst
->src
[0], inst
->size_read(0)))
3180 /* SEND instructions can't have MRF as a destination. */
3181 if (scan_inst
->mlen
)
3184 if (devinfo
->gen
== 6) {
3185 /* gen6 math instructions must have the destination be
3186 * GRF, so no compute-to-MRF for them.
3188 if (scan_inst
->is_math()) {
3193 /* Clear the bits for any registers this instruction overwrites. */
3194 regs_left
&= ~mask_relative_to(
3195 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3200 /* We don't handle control flow here. Most computation of
3201 * values that end up in MRFs are shortly before the MRF
3204 if (block
->start() == scan_inst
)
3207 /* You can't read from an MRF, so if someone else reads our
3208 * MRF's source GRF that we wanted to rewrite, that stops us.
3210 bool interfered
= false;
3211 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
3212 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
3213 inst
->src
[0], inst
->size_read(0))) {
3220 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3221 inst
->dst
, inst
->size_written
)) {
3222 /* If somebody else writes our MRF here, we can't
3223 * compute-to-MRF before that.
3228 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
3229 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
3230 inst
->dst
, inst
->size_written
)) {
3231 /* Found a SEND instruction, which means that there are
3232 * live values in MRFs from base_mrf to base_mrf +
3233 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3243 /* Found all generating instructions of our MRF's source value, so it
3244 * should be safe to rewrite them to point to the MRF directly.
3246 regs_left
= (1 << regs_read(inst
, 0)) - 1;
3248 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3249 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3250 inst
->src
[0], inst
->size_read(0))) {
3251 /* Clear the bits for any registers this instruction overwrites. */
3252 regs_left
&= ~mask_relative_to(
3253 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3255 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
3256 reg_offset(inst
->src
[0]);
3258 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
3259 /* Apply the same address transformation done by the hardware
3260 * for COMPR4 MRF writes.
3262 assert(rel_offset
< 2 * REG_SIZE
);
3263 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
3265 /* Clear the COMPR4 bit if the generating instruction is not
3268 if (scan_inst
->size_written
< 2 * REG_SIZE
)
3269 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
3272 /* Calculate the MRF number the result of this instruction is
3273 * ultimately written to.
3275 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
3278 scan_inst
->dst
.file
= MRF
;
3279 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
3280 scan_inst
->saturate
|= inst
->saturate
;
3287 inst
->remove(block
);
3292 invalidate_live_intervals();
3298 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
3299 * flow. We could probably do better here with some form of divergence
3303 fs_visitor::eliminate_find_live_channel()
3305 bool progress
= false;
3308 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
3309 /* The optimization below assumes that channel zero is live on thread
3310 * dispatch, which may not be the case if the fixed function dispatches
3316 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3317 switch (inst
->opcode
) {
3323 case BRW_OPCODE_ENDIF
:
3324 case BRW_OPCODE_WHILE
:
3328 case FS_OPCODE_DISCARD_JUMP
:
3329 /* This can potentially make control flow non-uniform until the end
3334 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
3336 inst
->opcode
= BRW_OPCODE_MOV
;
3337 inst
->src
[0] = brw_imm_ud(0u);
3339 inst
->force_writemask_all
= true;
3353 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
3354 * instructions to FS_OPCODE_REP_FB_WRITE.
3357 fs_visitor::emit_repclear_shader()
3359 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3361 int color_mrf
= base_mrf
+ 2;
3365 mov
= bld
.exec_all().group(4, 0)
3366 .MOV(brw_message_reg(color_mrf
),
3367 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
3369 struct brw_reg reg
=
3370 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
3371 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
3372 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
3374 mov
= bld
.exec_all().group(4, 0)
3375 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
3378 fs_inst
*write
= NULL
;
3379 if (key
->nr_color_regions
== 1) {
3380 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3381 write
->saturate
= key
->clamp_fragment_color
;
3382 write
->base_mrf
= color_mrf
;
3384 write
->header_size
= 0;
3387 assume(key
->nr_color_regions
> 0);
3389 struct brw_reg header
=
3390 retype(brw_message_reg(base_mrf
), BRW_REGISTER_TYPE_UD
);
3391 bld
.exec_all().group(16, 0)
3392 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3394 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
3396 bld
.exec_all().group(1, 0)
3397 .MOV(component(header
, 2), brw_imm_ud(i
));
3400 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3401 write
->saturate
= key
->clamp_fragment_color
;
3402 write
->base_mrf
= base_mrf
;
3404 write
->header_size
= 2;
3409 write
->last_rt
= true;
3413 assign_constant_locations();
3414 assign_curb_setup();
3416 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3418 assert(mov
->src
[0].file
== FIXED_GRF
);
3419 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3424 * Walks through basic blocks, looking for repeated MRF writes and
3425 * removing the later ones.
3428 fs_visitor::remove_duplicate_mrf_writes()
3430 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3431 bool progress
= false;
3433 /* Need to update the MRF tracking for compressed instructions. */
3434 if (dispatch_width
>= 16)
3437 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3439 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3440 if (inst
->is_control_flow()) {
3441 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3444 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3445 inst
->dst
.file
== MRF
) {
3446 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3447 if (prev_inst
&& prev_inst
->opcode
== BRW_OPCODE_MOV
&&
3448 inst
->dst
.equals(prev_inst
->dst
) &&
3449 inst
->src
[0].equals(prev_inst
->src
[0]) &&
3450 inst
->saturate
== prev_inst
->saturate
&&
3451 inst
->predicate
== prev_inst
->predicate
&&
3452 inst
->conditional_mod
== prev_inst
->conditional_mod
&&
3453 inst
->exec_size
== prev_inst
->exec_size
) {
3454 inst
->remove(block
);
3460 /* Clear out the last-write records for MRFs that were overwritten. */
3461 if (inst
->dst
.file
== MRF
) {
3462 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3465 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3466 /* Found a SEND instruction, which will include two or fewer
3467 * implied MRF writes. We could do better here.
3469 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3470 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3474 /* Clear out any MRF move records whose sources got overwritten. */
3475 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3476 if (last_mrf_move
[i
] &&
3477 regions_overlap(inst
->dst
, inst
->size_written
,
3478 last_mrf_move
[i
]->src
[0],
3479 last_mrf_move
[i
]->size_read(0))) {
3480 last_mrf_move
[i
] = NULL
;
3484 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3485 inst
->dst
.file
== MRF
&&
3486 inst
->src
[0].file
!= ARF
&&
3487 !inst
->is_partial_write()) {
3488 last_mrf_move
[inst
->dst
.nr
] = inst
;
3493 invalidate_live_intervals();
3499 * Rounding modes for conversion instructions are included for each
3500 * conversion, but right now it is a state. So once it is set,
3501 * we don't need to call it again for subsequent calls.
3503 * This is useful for vector/matrices conversions, as setting the
3504 * mode once is enough for the full vector/matrix
3507 fs_visitor::remove_extra_rounding_modes()
3509 bool progress
= false;
3511 foreach_block (block
, cfg
) {
3512 brw_rnd_mode prev_mode
= BRW_RND_MODE_UNSPECIFIED
;
3514 foreach_inst_in_block_safe (fs_inst
, inst
, block
) {
3515 if (inst
->opcode
== SHADER_OPCODE_RND_MODE
) {
3516 assert(inst
->src
[0].file
== BRW_IMMEDIATE_VALUE
);
3517 const brw_rnd_mode mode
= (brw_rnd_mode
) inst
->src
[0].d
;
3518 if (mode
== prev_mode
) {
3519 inst
->remove(block
);
3529 invalidate_live_intervals();
3535 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3537 /* Clear the flag for registers that actually got read (as expected). */
3538 for (int i
= 0; i
< inst
->sources
; i
++) {
3540 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3541 grf
= inst
->src
[i
].nr
;
3546 if (grf
>= first_grf
&&
3547 grf
< first_grf
+ grf_len
) {
3548 deps
[grf
- first_grf
] = false;
3549 if (inst
->exec_size
== 16)
3550 deps
[grf
- first_grf
+ 1] = false;
3556 * Implements this workaround for the original 965:
3558 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3559 * check for post destination dependencies on this instruction, software
3560 * must ensure that there is no destination hazard for the case of ‘write
3561 * followed by a posted write’ shown in the following example.
3564 * 2. send r3.xy <rest of send instruction>
3567 * Due to no post-destination dependency check on the ‘send’, the above
3568 * code sequence could have two instructions (1 and 2) in flight at the
3569 * same time that both consider ‘r3’ as the target of their final writes.
3572 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3575 int write_len
= regs_written(inst
);
3576 int first_write_grf
= inst
->dst
.nr
;
3577 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3578 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3580 memset(needs_dep
, false, sizeof(needs_dep
));
3581 memset(needs_dep
, true, write_len
);
3583 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3585 /* Walk backwards looking for writes to registers we're writing which
3586 * aren't read since being written. If we hit the start of the program,
3587 * we assume that there are no outstanding dependencies on entry to the
3590 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3591 /* If we hit control flow, assume that there *are* outstanding
3592 * dependencies, and force their cleanup before our instruction.
3594 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3595 for (int i
= 0; i
< write_len
; i
++) {
3597 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3598 first_write_grf
+ i
);
3603 /* We insert our reads as late as possible on the assumption that any
3604 * instruction but a MOV that might have left us an outstanding
3605 * dependency has more latency than a MOV.
3607 if (scan_inst
->dst
.file
== VGRF
) {
3608 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3609 int reg
= scan_inst
->dst
.nr
+ i
;
3611 if (reg
>= first_write_grf
&&
3612 reg
< first_write_grf
+ write_len
&&
3613 needs_dep
[reg
- first_write_grf
]) {
3614 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3615 needs_dep
[reg
- first_write_grf
] = false;
3616 if (scan_inst
->exec_size
== 16)
3617 needs_dep
[reg
- first_write_grf
+ 1] = false;
3622 /* Clear the flag for registers that actually got read (as expected). */
3623 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3625 /* Continue the loop only if we haven't resolved all the dependencies */
3627 for (i
= 0; i
< write_len
; i
++) {
3637 * Implements this workaround for the original 965:
3639 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3640 * used as a destination register until after it has been sourced by an
3641 * instruction with a different destination register.
3644 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3646 int write_len
= regs_written(inst
);
3647 unsigned first_write_grf
= inst
->dst
.nr
;
3648 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3649 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3651 memset(needs_dep
, false, sizeof(needs_dep
));
3652 memset(needs_dep
, true, write_len
);
3653 /* Walk forwards looking for writes to registers we're writing which aren't
3654 * read before being written.
3656 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3657 /* If we hit control flow, force resolve all remaining dependencies. */
3658 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3659 for (int i
= 0; i
< write_len
; i
++) {
3661 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3662 first_write_grf
+ i
);
3667 /* Clear the flag for registers that actually got read (as expected). */
3668 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3670 /* We insert our reads as late as possible since they're reading the
3671 * result of a SEND, which has massive latency.
3673 if (scan_inst
->dst
.file
== VGRF
&&
3674 scan_inst
->dst
.nr
>= first_write_grf
&&
3675 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3676 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3677 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3679 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3682 /* Continue the loop only if we haven't resolved all the dependencies */
3684 for (i
= 0; i
< write_len
; i
++) {
3694 fs_visitor::insert_gen4_send_dependency_workarounds()
3696 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3699 bool progress
= false;
3701 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3702 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3703 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3704 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3710 invalidate_live_intervals();
3714 * Turns the generic expression-style uniform pull constant load instruction
3715 * into a hardware-specific series of instructions for loading a pull
3718 * The expression style allows the CSE pass before this to optimize out
3719 * repeated loads from the same offset, and gives the pre-register-allocation
3720 * scheduling full flexibility, while the conversion to native instructions
3721 * allows the post-register-allocation scheduler the best information
3724 * Note that execution masking for setting up pull constant loads is special:
3725 * the channels that need to be written are unrelated to the current execution
3726 * mask, since a later instruction will use one of the result channels as a
3727 * source operand for all 8 or 16 of its channels.
3730 fs_visitor::lower_uniform_pull_constant_loads()
3732 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3733 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3736 if (devinfo
->gen
>= 7) {
3737 const fs_builder ubld
= fs_builder(this, block
, inst
).exec_all();
3738 const fs_reg payload
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
);
3740 ubld
.group(8, 0).MOV(payload
,
3741 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3742 ubld
.group(1, 0).MOV(component(payload
, 2),
3743 brw_imm_ud(inst
->src
[1].ud
/ 16));
3745 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3746 inst
->src
[1] = payload
;
3747 inst
->header_size
= 1;
3750 invalidate_live_intervals();
3752 /* Before register allocation, we didn't tell the scheduler about the
3753 * MRF we use. We know it's safe to use this MRF because nothing
3754 * else does except for register spill/unspill, which generates and
3755 * uses its MRF within a single IR instruction.
3757 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3764 fs_visitor::lower_load_payload()
3766 bool progress
= false;
3768 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3769 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3772 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3773 assert(inst
->saturate
== false);
3774 fs_reg dst
= inst
->dst
;
3776 /* Get rid of COMPR4. We'll add it back in if we need it */
3777 if (dst
.file
== MRF
)
3778 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3780 const fs_builder
ibld(this, block
, inst
);
3781 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3783 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3784 if (inst
->src
[i
].file
!= BAD_FILE
) {
3785 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3786 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3787 hbld
.MOV(mov_dst
, mov_src
);
3789 dst
= offset(dst
, hbld
, 1);
3792 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3793 inst
->exec_size
> 8) {
3794 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3795 * a straightforward copy. Instead, the result of the
3796 * LOAD_PAYLOAD is treated as interleaved and the first four
3797 * non-header sources are unpacked as:
3808 * This is used for gen <= 5 fb writes.
3810 assert(inst
->exec_size
== 16);
3811 assert(inst
->header_size
+ 4 <= inst
->sources
);
3812 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3813 if (inst
->src
[i
].file
!= BAD_FILE
) {
3814 if (devinfo
->has_compr4
) {
3815 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3816 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3817 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3819 /* Platform doesn't have COMPR4. We have to fake it */
3820 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3821 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3823 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3830 /* The loop above only ever incremented us through the first set
3831 * of 4 registers. However, thanks to the magic of COMPR4, we
3832 * actually wrote to the first 8 registers, so we need to take
3833 * that into account now.
3837 /* The COMPR4 code took care of the first 4 sources. We'll let
3838 * the regular path handle any remaining sources. Yes, we are
3839 * modifying the instruction but we're about to delete it so
3840 * this really doesn't hurt anything.
3842 inst
->header_size
+= 4;
3845 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3846 if (inst
->src
[i
].file
!= BAD_FILE
) {
3847 dst
.type
= inst
->src
[i
].type
;
3848 ibld
.MOV(dst
, inst
->src
[i
]);
3850 dst
.type
= BRW_REGISTER_TYPE_UD
;
3852 dst
= offset(dst
, ibld
, 1);
3855 inst
->remove(block
);
3860 invalidate_live_intervals();
3866 fs_visitor::lower_mul_dword_inst(fs_inst
*inst
, bblock_t
*block
)
3868 const fs_builder
ibld(this, block
, inst
);
3870 if (inst
->src
[1].file
== IMM
&& inst
->src
[1].ud
< (1 << 16)) {
3871 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3872 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3875 * If multiplying by an immediate value that fits in 16-bits, do a
3876 * single MUL instruction with that value in the proper location.
3878 if (devinfo
->gen
< 7) {
3879 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8), inst
->dst
.type
);
3880 ibld
.MOV(imm
, inst
->src
[1]);
3881 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3883 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3884 ibld
.MUL(inst
->dst
, inst
->src
[0],
3885 ud
? brw_imm_uw(inst
->src
[1].ud
)
3886 : brw_imm_w(inst
->src
[1].d
));
3889 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3890 * do 32-bit integer multiplication in one instruction, but instead
3891 * must do a sequence (which actually calculates a 64-bit result):
3893 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3894 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3895 * mov(8) g2<1>D acc0<8,8,1>D
3897 * But on Gen > 6, the ability to use second accumulator register
3898 * (acc1) for non-float data types was removed, preventing a simple
3899 * implementation in SIMD16. A 16-channel result can be calculated by
3900 * executing the three instructions twice in SIMD8, once with quarter
3901 * control of 1Q for the first eight channels and again with 2Q for
3902 * the second eight channels.
3904 * Which accumulator register is implicitly accessed (by AccWrEnable
3905 * for instance) is determined by the quarter control. Unfortunately
3906 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3907 * implicit accumulator access by an instruction with 2Q will access
3908 * acc1 regardless of whether the data type is usable in acc1.
3910 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3911 * integer data types.
3913 * Since we only want the low 32-bits of the result, we can do two
3914 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3915 * adjust the high result and add them (like the mach is doing):
3917 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3918 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3919 * shl(8) g9<1>D g8<8,8,1>D 16D
3920 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3922 * We avoid the shl instruction by realizing that we only want to add
3923 * the low 16-bits of the "high" result to the high 16-bits of the
3924 * "low" result and using proper regioning on the add:
3926 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3927 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3928 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3930 * Since it does not use the (single) accumulator register, we can
3931 * schedule multi-component multiplications much better.
3934 bool needs_mov
= false;
3935 fs_reg orig_dst
= inst
->dst
;
3937 /* Get a new VGRF for the "low" 32x16-bit multiplication result if
3938 * reusing the original destination is impossible due to hardware
3939 * restrictions, source/destination overlap, or it being the null
3942 fs_reg low
= inst
->dst
;
3943 if (orig_dst
.is_null() || orig_dst
.file
== MRF
||
3944 regions_overlap(inst
->dst
, inst
->size_written
,
3945 inst
->src
[0], inst
->size_read(0)) ||
3946 regions_overlap(inst
->dst
, inst
->size_written
,
3947 inst
->src
[1], inst
->size_read(1)) ||
3948 inst
->dst
.stride
>= 4) {
3950 low
= fs_reg(VGRF
, alloc
.allocate(regs_written(inst
)),
3954 /* Get a new VGRF but keep the same stride as inst->dst */
3955 fs_reg
high(VGRF
, alloc
.allocate(regs_written(inst
)), inst
->dst
.type
);
3956 high
.stride
= inst
->dst
.stride
;
3957 high
.offset
= inst
->dst
.offset
% REG_SIZE
;
3959 if (devinfo
->gen
>= 7) {
3960 if (inst
->src
[1].abs
)
3961 lower_src_modifiers(this, block
, inst
, 1);
3963 if (inst
->src
[1].file
== IMM
) {
3964 ibld
.MUL(low
, inst
->src
[0],
3965 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
3966 ibld
.MUL(high
, inst
->src
[0],
3967 brw_imm_uw(inst
->src
[1].ud
>> 16));
3969 ibld
.MUL(low
, inst
->src
[0],
3970 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
3971 ibld
.MUL(high
, inst
->src
[0],
3972 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
3975 if (inst
->src
[0].abs
)
3976 lower_src_modifiers(this, block
, inst
, 0);
3978 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
3980 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
3984 ibld
.ADD(subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3985 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3986 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
3988 if (needs_mov
|| inst
->conditional_mod
)
3989 set_condmod(inst
->conditional_mod
, ibld
.MOV(orig_dst
, low
));
3994 fs_visitor::lower_mul_qword_inst(fs_inst
*inst
, bblock_t
*block
)
3996 const fs_builder
ibld(this, block
, inst
);
3998 /* Considering two 64-bit integers ab and cd where each letter ab
3999 * corresponds to 32 bits, we get a 128-bit result WXYZ. We * cd
4000 * only need to provide the YZ part of the result. -------
4002 * Only BD needs to be 64 bits. For AD and BC we only care + AD
4003 * about the lower 32 bits (since they are part of the upper + BC
4004 * 32 bits of our result). AC is not needed since it starts + AC
4005 * on the 65th bit of the result. -------
4008 unsigned int q_regs
= regs_written(inst
);
4009 unsigned int d_regs
= (q_regs
+ 1) / 2;
4011 fs_reg
bd(VGRF
, alloc
.allocate(q_regs
), BRW_REGISTER_TYPE_UQ
);
4012 fs_reg
ad(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4013 fs_reg
bc(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4015 /* Here we need the full 64 bit result for 32b * 32b. */
4016 if (devinfo
->has_integer_dword_mul
) {
4017 ibld
.MUL(bd
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4018 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4020 fs_reg
bd_high(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4021 fs_reg
bd_low(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4022 fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
), BRW_REGISTER_TYPE_UD
);
4024 fs_inst
*mul
= ibld
.MUL(acc
,
4025 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4026 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
4027 mul
->writes_accumulator
= true;
4029 ibld
.MACH(bd_high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4030 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4031 ibld
.MOV(bd_low
, acc
);
4033 ibld
.MOV(subscript(bd
, BRW_REGISTER_TYPE_UD
, 0), bd_low
);
4034 ibld
.MOV(subscript(bd
, BRW_REGISTER_TYPE_UD
, 1), bd_high
);
4037 ibld
.MUL(ad
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1),
4038 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4039 ibld
.MUL(bc
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4040 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 1));
4042 ibld
.ADD(ad
, ad
, bc
);
4043 ibld
.ADD(subscript(bd
, BRW_REGISTER_TYPE_UD
, 1),
4044 subscript(bd
, BRW_REGISTER_TYPE_UD
, 1), ad
);
4046 ibld
.MOV(inst
->dst
, bd
);
4050 fs_visitor::lower_mulh_inst(fs_inst
*inst
, bblock_t
*block
)
4052 const fs_builder
ibld(this, block
, inst
);
4054 /* According to the BDW+ BSpec page for the "Multiply Accumulate
4055 * High" instruction:
4057 * "An added preliminary mov is required for source modification on
4059 * mov (8) r3.0<1>:d -r3<8;8,1>:d
4060 * mul (8) acc0:d r2.0<8;8,1>:d r3.0<16;8,2>:uw
4061 * mach (8) r5.0<1>:d r2.0<8;8,1>:d r3.0<8;8,1>:d"
4063 if (devinfo
->gen
>= 8 && (inst
->src
[1].negate
|| inst
->src
[1].abs
))
4064 lower_src_modifiers(this, block
, inst
, 1);
4066 /* Should have been lowered to 8-wide. */
4067 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
4068 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
), inst
->dst
.type
);
4069 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
4070 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
4072 if (devinfo
->gen
>= 8) {
4073 /* Until Gen8, integer multiplies read 32-bits from one source,
4074 * and 16-bits from the other, and relying on the MACH instruction
4075 * to generate the high bits of the result.
4077 * On Gen8, the multiply instruction does a full 32x32-bit
4078 * multiply, but in order to do a 64-bit multiply we can simulate
4079 * the previous behavior and then use a MACH instruction.
4081 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
4082 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
4083 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
4084 mul
->src
[1].stride
*= 2;
4086 if (mul
->src
[1].file
== IMM
) {
4087 mul
->src
[1] = brw_imm_uw(mul
->src
[1].ud
);
4089 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4091 /* Among other things the quarter control bits influence which
4092 * accumulator register is used by the hardware for instructions
4093 * that access the accumulator implicitly (e.g. MACH). A
4094 * second-half instruction would normally map to acc1, which
4095 * doesn't exist on Gen7 and up (the hardware does emulate it for
4096 * floating-point instructions *only* by taking advantage of the
4097 * extra precision of acc0 not normally used for floating point
4100 * HSW and up are careful enough not to try to access an
4101 * accumulator register that doesn't exist, but on earlier Gen7
4102 * hardware we need to make sure that the quarter control bits are
4103 * zero to avoid non-deterministic behaviour and emit an extra MOV
4104 * to get the result masked correctly according to the current
4108 mach
->force_writemask_all
= true;
4109 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
4110 ibld
.MOV(inst
->dst
, mach
->dst
);
4115 fs_visitor::lower_integer_multiplication()
4117 bool progress
= false;
4119 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4120 if (inst
->opcode
== BRW_OPCODE_MUL
) {
4121 if ((inst
->dst
.type
== BRW_REGISTER_TYPE_Q
||
4122 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
) &&
4123 (inst
->src
[0].type
== BRW_REGISTER_TYPE_Q
||
4124 inst
->src
[0].type
== BRW_REGISTER_TYPE_UQ
) &&
4125 (inst
->src
[1].type
== BRW_REGISTER_TYPE_Q
||
4126 inst
->src
[1].type
== BRW_REGISTER_TYPE_UQ
)) {
4127 lower_mul_qword_inst(inst
, block
);
4128 inst
->remove(block
);
4130 } else if (!inst
->dst
.is_accumulator() &&
4131 (inst
->dst
.type
== BRW_REGISTER_TYPE_D
||
4132 inst
->dst
.type
== BRW_REGISTER_TYPE_UD
) &&
4133 !devinfo
->has_integer_dword_mul
) {
4134 lower_mul_dword_inst(inst
, block
);
4135 inst
->remove(block
);
4138 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
4139 lower_mulh_inst(inst
, block
);
4140 inst
->remove(block
);
4147 invalidate_live_intervals();
4153 fs_visitor::lower_minmax()
4155 assert(devinfo
->gen
< 6);
4157 bool progress
= false;
4159 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4160 const fs_builder
ibld(this, block
, inst
);
4162 if (inst
->opcode
== BRW_OPCODE_SEL
&&
4163 inst
->predicate
== BRW_PREDICATE_NONE
) {
4164 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
4165 * the original SEL.L/GE instruction
4167 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
4168 inst
->conditional_mod
);
4169 inst
->predicate
= BRW_PREDICATE_NORMAL
;
4170 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
4177 invalidate_live_intervals();
4183 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
4184 fs_reg
*dst
, fs_reg color
, unsigned components
)
4186 if (key
->clamp_fragment_color
) {
4187 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
4188 assert(color
.type
== BRW_REGISTER_TYPE_F
);
4190 for (unsigned i
= 0; i
< components
; i
++)
4192 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
4197 for (unsigned i
= 0; i
< components
; i
++)
4198 dst
[i
] = offset(color
, bld
, i
);
4202 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
4203 const struct brw_wm_prog_data
*prog_data
,
4204 const brw_wm_prog_key
*key
,
4205 const fs_visitor::thread_payload
&payload
)
4207 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
4208 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4209 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
4210 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
4211 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
4212 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
4213 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
4214 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
4215 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
4216 const unsigned components
=
4217 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
4219 /* We can potentially have a message length of up to 15, so we have to set
4220 * base_mrf to either 0 or 1 in order to fit in m0..m15.
4223 int header_size
= 2, payload_header_size
;
4224 unsigned length
= 0;
4226 if (devinfo
->gen
< 6) {
4227 /* TODO: Support SIMD32 on gen4-5 */
4228 assert(bld
.group() < 16);
4230 /* For gen4-5, we always have a header consisting of g0 and g1. We have
4231 * an implied MOV from g0,g1 to the start of the message. The MOV from
4232 * g0 is handled by the hardware and the MOV from g1 is provided by the
4233 * generator. This is required because, on gen4-5, the generator may
4234 * generate two write messages with different message lengths in order
4235 * to handle AA data properly.
4237 * Also, since the pixel mask goes in the g0 portion of the message and
4238 * since render target writes are the last thing in the shader, we write
4239 * the pixel mask directly into g0 and it will get copied as part of the
4242 if (prog_data
->uses_kill
) {
4243 bld
.exec_all().group(1, 0)
4244 .MOV(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
),
4245 brw_flag_reg(0, 1));
4248 assert(length
== 0);
4250 } else if ((devinfo
->gen
<= 7 && !devinfo
->is_haswell
&&
4251 prog_data
->uses_kill
) ||
4252 color1
.file
!= BAD_FILE
||
4253 key
->nr_color_regions
> 1) {
4254 /* From the Sandy Bridge PRM, volume 4, page 198:
4256 * "Dispatched Pixel Enables. One bit per pixel indicating
4257 * which pixels were originally enabled when the thread was
4258 * dispatched. This field is only required for the end-of-
4259 * thread message and on all dual-source messages."
4261 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4263 fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4264 if (bld
.group() < 16) {
4265 /* The header starts off as g0 and g1 for the first half */
4266 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4267 BRW_REGISTER_TYPE_UD
));
4269 /* The header starts off as g0 and g2 for the second half */
4270 assert(bld
.group() < 32);
4271 const fs_reg header_sources
[2] = {
4272 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4273 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
),
4275 ubld
.LOAD_PAYLOAD(header
, header_sources
, 2, 0);
4278 uint32_t g00_bits
= 0;
4280 /* Set "Source0 Alpha Present to RenderTarget" bit in message
4283 if (inst
->target
> 0 && prog_data
->replicate_alpha
)
4284 g00_bits
|= 1 << 11;
4286 /* Set computes stencil to render target */
4287 if (prog_data
->computed_stencil
)
4288 g00_bits
|= 1 << 14;
4291 /* OR extra bits into g0.0 */
4292 ubld
.group(1, 0).OR(component(header
, 0),
4293 retype(brw_vec1_grf(0, 0),
4294 BRW_REGISTER_TYPE_UD
),
4295 brw_imm_ud(g00_bits
));
4298 /* Set the render target index for choosing BLEND_STATE. */
4299 if (inst
->target
> 0) {
4300 ubld
.group(1, 0).MOV(component(header
, 2), brw_imm_ud(inst
->target
));
4303 if (prog_data
->uses_kill
) {
4304 assert(bld
.group() < 16);
4305 ubld
.group(1, 0).MOV(retype(component(header
, 15),
4306 BRW_REGISTER_TYPE_UW
),
4307 brw_flag_reg(0, 1));
4310 assert(length
== 0);
4311 sources
[0] = header
;
4312 sources
[1] = horiz_offset(header
, 8);
4315 assert(length
== 0 || length
== 2);
4316 header_size
= length
;
4318 if (payload
.aa_dest_stencil_reg
[0]) {
4319 assert(inst
->group
< 16);
4320 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
4321 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
4322 .MOV(sources
[length
],
4323 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
[0], 0)));
4327 if (src0_alpha
.file
!= BAD_FILE
) {
4328 for (unsigned i
= 0; i
< bld
.dispatch_width() / 8; i
++) {
4329 const fs_builder
&ubld
= bld
.exec_all().group(8, i
)
4330 .annotate("FB write src0 alpha");
4331 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_F
);
4332 ubld
.MOV(tmp
, horiz_offset(src0_alpha
, i
* 8));
4333 setup_color_payload(ubld
, key
, &sources
[length
], tmp
, 1);
4336 } else if (prog_data
->replicate_alpha
&& inst
->target
!= 0) {
4337 /* Handle the case when fragment shader doesn't write to draw buffer
4338 * zero. No need to call setup_color_payload() for src0_alpha because
4339 * alpha value will be undefined.
4341 length
+= bld
.dispatch_width() / 8;
4344 if (sample_mask
.file
!= BAD_FILE
) {
4345 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
4346 BRW_REGISTER_TYPE_UD
);
4348 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
4349 * relevant. Since it's unsigned single words one vgrf is always
4350 * 16-wide, but only the lower or higher 8 channels will be used by the
4351 * hardware when doing a SIMD8 write depending on whether we have
4352 * selected the subspans for the first or second half respectively.
4354 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
4355 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
4356 sample_mask
.stride
*= 2;
4358 bld
.exec_all().annotate("FB write oMask")
4359 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
4365 payload_header_size
= length
;
4367 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
4370 if (color1
.file
!= BAD_FILE
) {
4371 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
4375 if (src_depth
.file
!= BAD_FILE
) {
4376 sources
[length
] = src_depth
;
4380 if (dst_depth
.file
!= BAD_FILE
) {
4381 sources
[length
] = dst_depth
;
4385 if (src_stencil
.file
!= BAD_FILE
) {
4386 assert(devinfo
->gen
>= 9);
4387 assert(bld
.dispatch_width() == 8);
4389 /* XXX: src_stencil is only available on gen9+. dst_depth is never
4390 * available on gen9+. As such it's impossible to have both enabled at the
4391 * same time and therefore length cannot overrun the array.
4393 assert(length
< 15);
4395 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4396 bld
.exec_all().annotate("FB write OS")
4397 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
4398 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
4403 if (devinfo
->gen
>= 7) {
4404 /* Send from the GRF */
4405 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
4406 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
4407 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
4408 load
->dst
= payload
;
4410 inst
->src
[0] = payload
;
4411 inst
->resize_sources(1);
4413 /* Send from the MRF */
4414 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
4415 sources
, length
, payload_header_size
);
4417 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
4418 * will do this for us if we just give it a COMPR4 destination.
4420 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
4421 load
->dst
.nr
|= BRW_MRF_COMPR4
;
4423 if (devinfo
->gen
< 6) {
4424 /* Set up src[0] for the implied MOV from grf0-1 */
4425 inst
->resize_sources(1);
4426 inst
->src
[0] = brw_vec8_grf(0, 0);
4428 inst
->resize_sources(0);
4433 inst
->opcode
= FS_OPCODE_FB_WRITE
;
4434 inst
->mlen
= regs_written(load
);
4435 inst
->header_size
= header_size
;
4439 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4441 const fs_builder
&ubld
= bld
.exec_all().group(8, 0);
4442 const unsigned length
= 2;
4443 const fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, length
);
4445 if (bld
.group() < 16) {
4446 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4447 BRW_REGISTER_TYPE_UD
));
4449 assert(bld
.group() < 32);
4450 const fs_reg header_sources
[] = {
4451 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4452 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
)
4454 ubld
.LOAD_PAYLOAD(header
, header_sources
, ARRAY_SIZE(header_sources
), 0);
4457 inst
->resize_sources(1);
4458 inst
->src
[0] = header
;
4459 inst
->opcode
= FS_OPCODE_FB_READ
;
4460 inst
->mlen
= length
;
4461 inst
->header_size
= length
;
4465 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4466 const fs_reg
&coordinate
,
4467 const fs_reg
&shadow_c
,
4468 const fs_reg
&lod
, const fs_reg
&lod2
,
4469 const fs_reg
&surface
,
4470 const fs_reg
&sampler
,
4471 unsigned coord_components
,
4472 unsigned grad_components
)
4474 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
4475 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
4476 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
4477 fs_reg msg_end
= msg_begin
;
4480 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
4482 for (unsigned i
= 0; i
< coord_components
; i
++)
4483 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
4484 offset(coordinate
, bld
, i
));
4486 msg_end
= offset(msg_end
, bld
, coord_components
);
4488 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
4489 * require all three components to be present and zero if they are unused.
4491 if (coord_components
> 0 &&
4492 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
4493 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
4494 for (unsigned i
= coord_components
; i
< 3; i
++)
4495 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
4497 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
4500 if (op
== SHADER_OPCODE_TXD
) {
4501 /* TXD unsupported in SIMD16 mode. */
4502 assert(bld
.dispatch_width() == 8);
4504 /* the slots for u and v are always present, but r is optional */
4505 if (coord_components
< 2)
4506 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
4509 * dPdx = dudx, dvdx, drdx
4510 * dPdy = dudy, dvdy, drdy
4512 * 1-arg: Does not exist.
4514 * 2-arg: dudx dvdx dudy dvdy
4515 * dPdx.x dPdx.y dPdy.x dPdy.y
4518 * 3-arg: dudx dvdx drdx dudy dvdy drdy
4519 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
4520 * m5 m6 m7 m8 m9 m10
4522 for (unsigned i
= 0; i
< grad_components
; i
++)
4523 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
4525 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4527 for (unsigned i
= 0; i
< grad_components
; i
++)
4528 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
4530 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4534 /* Bias/LOD with shadow comparator is unsupported in SIMD16 -- *Without*
4535 * shadow comparator (including RESINFO) it's unsupported in SIMD8 mode.
4537 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
4538 bld
.dispatch_width() == 16);
4540 const brw_reg_type type
=
4541 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
4542 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
4543 bld
.MOV(retype(msg_end
, type
), lod
);
4544 msg_end
= offset(msg_end
, bld
, 1);
4547 if (shadow_c
.file
!= BAD_FILE
) {
4548 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
4549 /* There's no plain shadow compare message, so we use shadow
4550 * compare with a bias of 0.0.
4552 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
4553 msg_end
= offset(msg_end
, bld
, 1);
4556 bld
.MOV(msg_end
, shadow_c
);
4557 msg_end
= offset(msg_end
, bld
, 1);
4561 inst
->src
[0] = reg_undef
;
4562 inst
->src
[1] = surface
;
4563 inst
->src
[2] = sampler
;
4564 inst
->resize_sources(3);
4565 inst
->base_mrf
= msg_begin
.nr
;
4566 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
4567 inst
->header_size
= 1;
4571 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4572 const fs_reg
&coordinate
,
4573 const fs_reg
&shadow_c
,
4574 const fs_reg
&lod
, const fs_reg
&lod2
,
4575 const fs_reg
&sample_index
,
4576 const fs_reg
&surface
,
4577 const fs_reg
&sampler
,
4578 unsigned coord_components
,
4579 unsigned grad_components
)
4581 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
4582 fs_reg msg_coords
= message
;
4583 unsigned header_size
= 0;
4585 if (inst
->offset
!= 0) {
4586 /* The offsets set up by the visitor are in the m1 header, so we can't
4593 for (unsigned i
= 0; i
< coord_components
; i
++)
4594 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
4595 offset(coordinate
, bld
, i
));
4597 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
4598 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
4600 if (shadow_c
.file
!= BAD_FILE
) {
4601 fs_reg msg_shadow
= msg_lod
;
4602 bld
.MOV(msg_shadow
, shadow_c
);
4603 msg_lod
= offset(msg_shadow
, bld
, 1);
4608 case SHADER_OPCODE_TXL
:
4610 bld
.MOV(msg_lod
, lod
);
4611 msg_end
= offset(msg_lod
, bld
, 1);
4613 case SHADER_OPCODE_TXD
:
4616 * dPdx = dudx, dvdx, drdx
4617 * dPdy = dudy, dvdy, drdy
4619 * Load up these values:
4620 * - dudx dudy dvdx dvdy drdx drdy
4621 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
4624 for (unsigned i
= 0; i
< grad_components
; i
++) {
4625 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
4626 msg_end
= offset(msg_end
, bld
, 1);
4628 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
4629 msg_end
= offset(msg_end
, bld
, 1);
4632 case SHADER_OPCODE_TXS
:
4633 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4634 bld
.MOV(msg_lod
, lod
);
4635 msg_end
= offset(msg_lod
, bld
, 1);
4637 case SHADER_OPCODE_TXF
:
4638 msg_lod
= offset(msg_coords
, bld
, 3);
4639 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4640 msg_end
= offset(msg_lod
, bld
, 1);
4642 case SHADER_OPCODE_TXF_CMS
:
4643 msg_lod
= offset(msg_coords
, bld
, 3);
4645 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4647 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4648 msg_end
= offset(msg_lod
, bld
, 2);
4655 inst
->src
[0] = reg_undef
;
4656 inst
->src
[1] = surface
;
4657 inst
->src
[2] = sampler
;
4658 inst
->resize_sources(3);
4659 inst
->base_mrf
= message
.nr
;
4660 inst
->mlen
= msg_end
.nr
- message
.nr
;
4661 inst
->header_size
= header_size
;
4663 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4664 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4668 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
4670 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4673 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4677 sampler_msg_type(const gen_device_info
*devinfo
,
4678 opcode opcode
, bool shadow_compare
)
4680 assert(devinfo
->gen
>= 5);
4682 case SHADER_OPCODE_TEX
:
4683 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
:
4684 GEN5_SAMPLER_MESSAGE_SAMPLE
;
4686 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
:
4687 GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
4688 case SHADER_OPCODE_TXL
:
4689 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
:
4690 GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
4691 case SHADER_OPCODE_TXL_LZ
:
4692 return shadow_compare
? GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ
:
4693 GEN9_SAMPLER_MESSAGE_SAMPLE_LZ
;
4694 case SHADER_OPCODE_TXS
:
4695 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
4696 return GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
4697 case SHADER_OPCODE_TXD
:
4698 assert(!shadow_compare
|| devinfo
->gen
>= 8 || devinfo
->is_haswell
);
4699 return shadow_compare
? HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
:
4700 GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
4701 case SHADER_OPCODE_TXF
:
4702 return GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
4703 case SHADER_OPCODE_TXF_LZ
:
4704 assert(devinfo
->gen
>= 9);
4705 return GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ
;
4706 case SHADER_OPCODE_TXF_CMS_W
:
4707 assert(devinfo
->gen
>= 9);
4708 return GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
4709 case SHADER_OPCODE_TXF_CMS
:
4710 return devinfo
->gen
>= 7 ? GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
:
4711 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
4712 case SHADER_OPCODE_TXF_UMS
:
4713 assert(devinfo
->gen
>= 7);
4714 return GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
4715 case SHADER_OPCODE_TXF_MCS
:
4716 assert(devinfo
->gen
>= 7);
4717 return GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
4718 case SHADER_OPCODE_LOD
:
4719 return GEN5_SAMPLER_MESSAGE_LOD
;
4720 case SHADER_OPCODE_TG4
:
4721 assert(devinfo
->gen
>= 7);
4722 return shadow_compare
? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
:
4723 GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
4725 case SHADER_OPCODE_TG4_OFFSET
:
4726 assert(devinfo
->gen
>= 7);
4727 return shadow_compare
? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
:
4728 GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
4729 case SHADER_OPCODE_SAMPLEINFO
:
4730 return GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
4732 unreachable("not reached");
4737 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4738 const fs_reg
&coordinate
,
4739 const fs_reg
&shadow_c
,
4740 fs_reg lod
, const fs_reg
&lod2
,
4741 const fs_reg
&min_lod
,
4742 const fs_reg
&sample_index
,
4744 const fs_reg
&surface
,
4745 const fs_reg
&sampler
,
4746 const fs_reg
&surface_handle
,
4747 const fs_reg
&sampler_handle
,
4748 const fs_reg
&tg4_offset
,
4749 unsigned coord_components
,
4750 unsigned grad_components
)
4752 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4753 const brw_stage_prog_data
*prog_data
= bld
.shader
->stage_prog_data
;
4754 unsigned reg_width
= bld
.dispatch_width() / 8;
4755 unsigned header_size
= 0, length
= 0;
4756 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4757 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4758 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4760 /* We must have exactly one of surface/sampler and surface/sampler_handle */
4761 assert((surface
.file
== BAD_FILE
) != (surface_handle
.file
== BAD_FILE
));
4762 assert((sampler
.file
== BAD_FILE
) != (sampler_handle
.file
== BAD_FILE
));
4764 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4765 inst
->offset
!= 0 || inst
->eot
||
4766 op
== SHADER_OPCODE_SAMPLEINFO
||
4767 sampler_handle
.file
!= BAD_FILE
||
4768 is_high_sampler(devinfo
, sampler
)) {
4769 /* For general texture offsets (no txf workaround), we need a header to
4772 * TG4 needs to place its channel select in the header, for interaction
4773 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4774 * larger sampler numbers we need to offset the Sampler State Pointer in
4777 fs_reg header
= retype(sources
[0], BRW_REGISTER_TYPE_UD
);
4781 /* If we're requesting fewer than four channels worth of response,
4782 * and we have an explicit header, we need to set up the sampler
4783 * writemask. It's reversed from normal: 1 means "don't write".
4785 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4786 assert(regs_written(inst
) % reg_width
== 0);
4787 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4788 inst
->offset
|= mask
<< 12;
4791 /* Build the actual header */
4792 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4793 const fs_builder ubld1
= ubld
.group(1, 0);
4794 ubld
.MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
4796 ubld1
.MOV(component(header
, 2), brw_imm_ud(inst
->offset
));
4797 } else if (bld
.shader
->stage
!= MESA_SHADER_VERTEX
&&
4798 bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
) {
4799 /* The vertex and fragment stages have g0.2 set to 0, so
4800 * header0.2 is 0 when g0 is copied. Other stages may not, so we
4801 * must set it to 0 to avoid setting undesirable bits in the
4804 ubld1
.MOV(component(header
, 2), brw_imm_ud(0));
4807 if (sampler_handle
.file
!= BAD_FILE
) {
4808 /* Bindless sampler handles aren't relative to the sampler state
4809 * pointer passed into the shader through SAMPLER_STATE_POINTERS_*.
4810 * Instead, it's an absolute pointer relative to dynamic state base
4813 * Sampler states are 16 bytes each and the pointer we give here has
4814 * to be 32-byte aligned. In order to avoid more indirect messages
4815 * than required, we assume that all bindless sampler states are
4816 * 32-byte aligned. This sacrifices a bit of general state base
4817 * address space but means we can do something more efficient in the
4820 ubld1
.MOV(component(header
, 3), sampler_handle
);
4821 } else if (is_high_sampler(devinfo
, sampler
)) {
4822 if (sampler
.file
== BRW_IMMEDIATE_VALUE
) {
4823 assert(sampler
.ud
>= 16);
4824 const int sampler_state_size
= 16; /* 16 bytes */
4826 ubld1
.ADD(component(header
, 3),
4827 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
4828 brw_imm_ud(16 * (sampler
.ud
/ 16) * sampler_state_size
));
4830 fs_reg tmp
= ubld1
.vgrf(BRW_REGISTER_TYPE_UD
);
4831 ubld1
.AND(tmp
, sampler
, brw_imm_ud(0x0f0));
4832 ubld1
.SHL(tmp
, tmp
, brw_imm_ud(4));
4833 ubld1
.ADD(component(header
, 3),
4834 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
4840 if (shadow_c
.file
!= BAD_FILE
) {
4841 bld
.MOV(sources
[length
], shadow_c
);
4845 bool coordinate_done
= false;
4847 /* Set up the LOD info */
4850 case SHADER_OPCODE_TXL
:
4851 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4852 op
= SHADER_OPCODE_TXL_LZ
;
4855 bld
.MOV(sources
[length
], lod
);
4858 case SHADER_OPCODE_TXD
:
4859 /* TXD should have been lowered in SIMD16 mode. */
4860 assert(bld
.dispatch_width() == 8);
4862 /* Load dPdx and the coordinate together:
4863 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4865 for (unsigned i
= 0; i
< coord_components
; i
++) {
4866 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4868 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4869 * only derivatives for (u, v, r).
4871 if (i
< grad_components
) {
4872 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4873 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4877 coordinate_done
= true;
4879 case SHADER_OPCODE_TXS
:
4880 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4883 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
4884 /* We need an LOD; just use 0 */
4885 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), brw_imm_ud(0));
4888 case SHADER_OPCODE_TXF
:
4889 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4890 * On Gen9 they are u, v, lod, r
4892 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4894 if (devinfo
->gen
>= 9) {
4895 if (coord_components
>= 2) {
4896 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4897 offset(coordinate
, bld
, 1));
4899 sources
[length
] = brw_imm_d(0);
4904 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4905 op
= SHADER_OPCODE_TXF_LZ
;
4907 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4911 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4912 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4913 offset(coordinate
, bld
, i
));
4915 coordinate_done
= true;
4918 case SHADER_OPCODE_TXF_CMS
:
4919 case SHADER_OPCODE_TXF_CMS_W
:
4920 case SHADER_OPCODE_TXF_UMS
:
4921 case SHADER_OPCODE_TXF_MCS
:
4922 if (op
== SHADER_OPCODE_TXF_UMS
||
4923 op
== SHADER_OPCODE_TXF_CMS
||
4924 op
== SHADER_OPCODE_TXF_CMS_W
) {
4925 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4929 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4930 /* Data from the multisample control surface. */
4931 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4934 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4937 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4938 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4941 offset(mcs
, bld
, 1));
4946 /* There is no offsetting for this message; just copy in the integer
4947 * texture coordinates.
4949 for (unsigned i
= 0; i
< coord_components
; i
++)
4950 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4951 offset(coordinate
, bld
, i
));
4953 coordinate_done
= true;
4955 case SHADER_OPCODE_TG4_OFFSET
:
4956 /* More crazy intermixing */
4957 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4958 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4960 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4961 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4962 offset(tg4_offset
, bld
, i
));
4964 if (coord_components
== 3) /* r if present */
4965 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4967 coordinate_done
= true;
4973 /* Set up the coordinate (except for cases where it was done above) */
4974 if (!coordinate_done
) {
4975 for (unsigned i
= 0; i
< coord_components
; i
++)
4976 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4979 if (min_lod
.file
!= BAD_FILE
) {
4980 /* Account for all of the missing coordinate sources */
4981 length
+= 4 - coord_components
;
4982 if (op
== SHADER_OPCODE_TXD
)
4983 length
+= (3 - grad_components
) * 2;
4985 bld
.MOV(sources
[length
++], min_lod
);
4990 mlen
= length
* reg_width
- header_size
;
4992 mlen
= length
* reg_width
;
4994 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4995 BRW_REGISTER_TYPE_F
);
4996 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4998 /* Generate the SEND. */
4999 inst
->opcode
= SHADER_OPCODE_SEND
;
5001 inst
->header_size
= header_size
;
5003 const unsigned msg_type
=
5004 sampler_msg_type(devinfo
, op
, inst
->shadow_compare
);
5005 const unsigned simd_mode
=
5006 inst
->exec_size
<= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8
:
5007 BRW_SAMPLER_SIMD_MODE_SIMD16
;
5009 uint32_t base_binding_table_index
;
5011 case SHADER_OPCODE_TG4
:
5012 case SHADER_OPCODE_TG4_OFFSET
:
5013 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
5015 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5016 base_binding_table_index
= prog_data
->binding_table
.image_start
;
5019 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
5023 inst
->sfid
= BRW_SFID_SAMPLER
;
5024 if (surface
.file
== IMM
&&
5025 (sampler
.file
== IMM
|| sampler_handle
.file
!= BAD_FILE
)) {
5026 inst
->desc
= brw_sampler_desc(devinfo
,
5027 surface
.ud
+ base_binding_table_index
,
5028 sampler
.file
== IMM
? sampler
.ud
% 16 : 0,
5031 0 /* return_format unused on gen7+ */);
5032 inst
->src
[0] = brw_imm_ud(0);
5033 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5034 } else if (surface_handle
.file
!= BAD_FILE
) {
5035 /* Bindless surface */
5036 assert(devinfo
->gen
>= 9);
5037 inst
->desc
= brw_sampler_desc(devinfo
,
5039 sampler
.file
== IMM
? sampler
.ud
% 16 : 0,
5042 0 /* return_format unused on gen7+ */);
5044 /* For bindless samplers, the entire address is included in the message
5045 * header so we can leave the portion in the message descriptor 0.
5047 if (sampler_handle
.file
!= BAD_FILE
|| sampler
.file
== IMM
) {
5048 inst
->src
[0] = brw_imm_ud(0);
5050 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5051 fs_reg desc
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5052 ubld
.SHL(desc
, sampler
, brw_imm_ud(8));
5053 inst
->src
[0] = desc
;
5056 /* We assume that the driver provided the handle in the top 20 bits so
5057 * we can use the surface handle directly as the extended descriptor.
5059 inst
->src
[1] = retype(surface_handle
, BRW_REGISTER_TYPE_UD
);
5061 /* Immediate portion of the descriptor */
5062 inst
->desc
= brw_sampler_desc(devinfo
,
5067 0 /* return_format unused on gen7+ */);
5068 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5069 fs_reg desc
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5070 if (surface
.equals(sampler
)) {
5071 /* This case is common in GL */
5072 ubld
.MUL(desc
, surface
, brw_imm_ud(0x101));
5074 if (sampler_handle
.file
!= BAD_FILE
) {
5075 ubld
.MOV(desc
, surface
);
5076 } else if (sampler
.file
== IMM
) {
5077 ubld
.OR(desc
, surface
, brw_imm_ud(sampler
.ud
<< 8));
5079 ubld
.SHL(desc
, sampler
, brw_imm_ud(8));
5080 ubld
.OR(desc
, desc
, surface
);
5083 if (base_binding_table_index
)
5084 ubld
.ADD(desc
, desc
, brw_imm_ud(base_binding_table_index
));
5085 ubld
.AND(desc
, desc
, brw_imm_ud(0xfff));
5087 inst
->src
[0] = component(desc
, 0);
5088 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5091 inst
->src
[2] = src_payload
;
5092 inst
->resize_sources(3);
5095 /* EOT sampler messages don't make sense to split because it would
5096 * involve ending half of the thread early.
5098 assert(inst
->group
== 0);
5099 /* We need to use SENDC for EOT sampler messages */
5100 inst
->check_tdr
= true;
5101 inst
->send_has_side_effects
= true;
5104 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
5105 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
5109 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
5111 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5112 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
5113 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
5114 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
5115 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
5116 const fs_reg
&min_lod
= inst
->src
[TEX_LOGICAL_SRC_MIN_LOD
];
5117 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
5118 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
5119 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
5120 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
5121 const fs_reg
&surface_handle
= inst
->src
[TEX_LOGICAL_SRC_SURFACE_HANDLE
];
5122 const fs_reg
&sampler_handle
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
];
5123 const fs_reg
&tg4_offset
= inst
->src
[TEX_LOGICAL_SRC_TG4_OFFSET
];
5124 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
5125 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
5126 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
5127 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
5129 if (devinfo
->gen
>= 7) {
5130 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
5131 shadow_c
, lod
, lod2
, min_lod
,
5133 mcs
, surface
, sampler
,
5134 surface_handle
, sampler_handle
,
5136 coord_components
, grad_components
);
5137 } else if (devinfo
->gen
>= 5) {
5138 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
5139 shadow_c
, lod
, lod2
, sample_index
,
5141 coord_components
, grad_components
);
5143 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
5144 shadow_c
, lod
, lod2
,
5146 coord_components
, grad_components
);
5151 * Initialize the header present in some typed and untyped surface
5155 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
5157 fs_builder ubld
= bld
.exec_all().group(8, 0);
5158 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5159 ubld
.MOV(dst
, brw_imm_d(0));
5160 ubld
.group(1, 0).MOV(component(dst
, 7), sample_mask
);
5165 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5167 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5169 /* Get the logical send arguments. */
5170 const fs_reg
&addr
= inst
->src
[SURFACE_LOGICAL_SRC_ADDRESS
];
5171 const fs_reg
&src
= inst
->src
[SURFACE_LOGICAL_SRC_DATA
];
5172 const fs_reg
&surface
= inst
->src
[SURFACE_LOGICAL_SRC_SURFACE
];
5173 const fs_reg
&surface_handle
= inst
->src
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
];
5174 const UNUSED fs_reg
&dims
= inst
->src
[SURFACE_LOGICAL_SRC_IMM_DIMS
];
5175 const fs_reg
&arg
= inst
->src
[SURFACE_LOGICAL_SRC_IMM_ARG
];
5176 assert(arg
.file
== IMM
);
5178 /* We must have exactly one of surface and surface_handle */
5179 assert((surface
.file
== BAD_FILE
) != (surface_handle
.file
== BAD_FILE
));
5181 /* Calculate the total number of components of the payload. */
5182 const unsigned addr_sz
= inst
->components_read(SURFACE_LOGICAL_SRC_ADDRESS
);
5183 const unsigned src_sz
= inst
->components_read(SURFACE_LOGICAL_SRC_DATA
);
5185 const bool is_typed_access
=
5186 inst
->opcode
== SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
||
5187 inst
->opcode
== SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
||
5188 inst
->opcode
== SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
;
5190 /* From the BDW PRM Volume 7, page 147:
5192 * "For the Data Cache Data Port*, the header must be present for the
5193 * following message types: [...] Typed read/write/atomics"
5195 * Earlier generations have a similar wording. Because of this restriction
5196 * we don't attempt to implement sample masks via predication for such
5197 * messages prior to Gen9, since we have to provide a header anyway. On
5198 * Gen11+ the header has been removed so we can only use predication.
5200 const unsigned header_sz
= devinfo
->gen
< 9 && is_typed_access
? 1 : 0;
5202 const bool has_side_effects
= inst
->has_side_effects();
5203 fs_reg sample_mask
= has_side_effects
? bld
.sample_mask_reg() :
5204 fs_reg(brw_imm_d(0xffff));
5206 fs_reg payload
, payload2
;
5207 unsigned mlen
, ex_mlen
= 0;
5208 if (devinfo
->gen
>= 9) {
5209 /* We have split sends on gen9 and above */
5210 assert(header_sz
== 0);
5211 payload
= bld
.move_to_vgrf(addr
, addr_sz
);
5212 payload2
= bld
.move_to_vgrf(src
, src_sz
);
5213 mlen
= addr_sz
* (inst
->exec_size
/ 8);
5214 ex_mlen
= src_sz
* (inst
->exec_size
/ 8);
5216 /* Allocate space for the payload. */
5217 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
5218 payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
5219 fs_reg
*const components
= new fs_reg
[sz
];
5222 /* Construct the payload. */
5224 components
[n
++] = emit_surface_header(bld
, sample_mask
);
5226 for (unsigned i
= 0; i
< addr_sz
; i
++)
5227 components
[n
++] = offset(addr
, bld
, i
);
5229 for (unsigned i
= 0; i
< src_sz
; i
++)
5230 components
[n
++] = offset(src
, bld
, i
);
5232 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
5233 mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
5235 delete[] components
;
5238 /* Predicate the instruction on the sample mask if no header is
5241 if (!header_sz
&& sample_mask
.file
!= BAD_FILE
&&
5242 sample_mask
.file
!= IMM
) {
5243 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5244 if (inst
->predicate
) {
5245 assert(inst
->predicate
== BRW_PREDICATE_NORMAL
);
5246 assert(!inst
->predicate_inverse
);
5247 assert(inst
->flag_subreg
< 2);
5248 /* Combine the sample mask with the existing predicate by using a
5249 * vertical predication mode.
5251 inst
->predicate
= BRW_PREDICATE_ALIGN1_ALLV
;
5252 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
+ 2),
5256 inst
->flag_subreg
= 2;
5257 inst
->predicate
= BRW_PREDICATE_NORMAL
;
5258 inst
->predicate_inverse
= false;
5259 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
), sample_mask
.type
),
5265 switch (inst
->opcode
) {
5266 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5267 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5268 /* Byte scattered opcodes go through the normal data cache */
5269 sfid
= GEN7_SFID_DATAPORT_DATA_CACHE
;
5272 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5273 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5274 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5275 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5276 /* Untyped Surface messages go through the data cache but the SFID value
5277 * changed on Haswell.
5279 sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
5280 HSW_SFID_DATAPORT_DATA_CACHE_1
:
5281 GEN7_SFID_DATAPORT_DATA_CACHE
);
5284 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5285 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5286 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5287 /* Typed surface messages go through the render cache on IVB and the
5288 * data cache on HSW+.
5290 sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
5291 HSW_SFID_DATAPORT_DATA_CACHE_1
:
5292 GEN6_SFID_DATAPORT_RENDER_CACHE
);
5296 unreachable("Unsupported surface opcode");
5300 switch (inst
->opcode
) {
5301 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5302 desc
= brw_dp_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5303 arg
.ud
, /* num_channels */
5307 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5308 desc
= brw_dp_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5309 arg
.ud
, /* num_channels */
5313 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5314 desc
= brw_dp_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5315 arg
.ud
, /* bit_size */
5319 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5320 desc
= brw_dp_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5321 arg
.ud
, /* bit_size */
5325 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5326 desc
= brw_dp_untyped_atomic_desc(devinfo
, inst
->exec_size
,
5327 arg
.ud
, /* atomic_op */
5328 !inst
->dst
.is_null());
5331 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5332 desc
= brw_dp_untyped_atomic_float_desc(devinfo
, inst
->exec_size
,
5333 arg
.ud
, /* atomic_op */
5334 !inst
->dst
.is_null());
5337 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5338 desc
= brw_dp_typed_surface_rw_desc(devinfo
, inst
->exec_size
, inst
->group
,
5339 arg
.ud
, /* num_channels */
5343 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5344 desc
= brw_dp_typed_surface_rw_desc(devinfo
, inst
->exec_size
, inst
->group
,
5345 arg
.ud
, /* num_channels */
5349 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5350 desc
= brw_dp_typed_atomic_desc(devinfo
, inst
->exec_size
, inst
->group
,
5351 arg
.ud
, /* atomic_op */
5352 !inst
->dst
.is_null());
5356 unreachable("Unknown surface logical instruction");
5359 /* Update the original instruction. */
5360 inst
->opcode
= SHADER_OPCODE_SEND
;
5362 inst
->ex_mlen
= ex_mlen
;
5363 inst
->header_size
= header_sz
;
5364 inst
->send_has_side_effects
= has_side_effects
;
5365 inst
->send_is_volatile
= !has_side_effects
;
5367 /* Set up SFID and descriptors */
5370 if (surface
.file
== IMM
) {
5371 inst
->desc
|= surface
.ud
& 0xff;
5372 inst
->src
[0] = brw_imm_ud(0);
5373 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5374 } else if (surface_handle
.file
!= BAD_FILE
) {
5375 /* Bindless surface */
5376 assert(devinfo
->gen
>= 9);
5377 inst
->desc
|= GEN9_BTI_BINDLESS
;
5378 inst
->src
[0] = brw_imm_ud(0);
5380 /* We assume that the driver provided the handle in the top 20 bits so
5381 * we can use the surface handle directly as the extended descriptor.
5383 inst
->src
[1] = retype(surface_handle
, BRW_REGISTER_TYPE_UD
);
5385 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5386 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5387 ubld
.AND(tmp
, surface
, brw_imm_ud(0xff));
5388 inst
->src
[0] = component(tmp
, 0);
5389 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5392 /* Finally, the payload */
5393 inst
->src
[2] = payload
;
5394 inst
->src
[3] = payload2
;
5396 inst
->resize_sources(4);
5400 lower_a64_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5402 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5404 const fs_reg
&addr
= inst
->src
[0];
5405 const fs_reg
&src
= inst
->src
[1];
5406 const unsigned src_comps
= inst
->components_read(1);
5407 assert(inst
->src
[2].file
== IMM
);
5408 const unsigned arg
= inst
->src
[2].ud
;
5409 const bool has_side_effects
= inst
->has_side_effects();
5411 /* If the surface message has side effects and we're a fragment shader, we
5412 * have to predicate with the sample mask to avoid helper invocations.
5414 if (has_side_effects
&& bld
.shader
->stage
== MESA_SHADER_FRAGMENT
) {
5415 inst
->flag_subreg
= 2;
5416 inst
->predicate
= BRW_PREDICATE_NORMAL
;
5417 inst
->predicate_inverse
= false;
5419 fs_reg sample_mask
= bld
.sample_mask_reg();
5420 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5421 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
), sample_mask
.type
),
5425 fs_reg payload
, payload2
;
5426 unsigned mlen
, ex_mlen
= 0;
5427 if (devinfo
->gen
>= 9) {
5428 /* On Skylake and above, we have SENDS */
5429 mlen
= 2 * (inst
->exec_size
/ 8);
5430 ex_mlen
= src_comps
* type_sz(src
.type
) * inst
->exec_size
/ REG_SIZE
;
5431 payload
= retype(bld
.move_to_vgrf(addr
, 1), BRW_REGISTER_TYPE_UD
);
5432 payload2
= retype(bld
.move_to_vgrf(src
, src_comps
),
5433 BRW_REGISTER_TYPE_UD
);
5435 /* Add two because the address is 64-bit */
5436 const unsigned dwords
= 2 + src_comps
;
5437 mlen
= dwords
* (inst
->exec_size
/ 8);
5443 for (unsigned i
= 0; i
< src_comps
; i
++)
5444 sources
[1 + i
] = offset(src
, bld
, i
);
5446 payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, dwords
);
5447 bld
.LOAD_PAYLOAD(payload
, sources
, 1 + src_comps
, 0);
5451 switch (inst
->opcode
) {
5452 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
5453 desc
= brw_dp_a64_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5454 arg
, /* num_channels */
5458 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
5459 desc
= brw_dp_a64_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5460 arg
, /* num_channels */
5464 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
5465 desc
= brw_dp_a64_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5470 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
5471 desc
= brw_dp_a64_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5476 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
5477 desc
= brw_dp_a64_untyped_atomic_desc(devinfo
, inst
->exec_size
, 32,
5478 arg
, /* atomic_op */
5479 !inst
->dst
.is_null());
5482 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
5483 desc
= brw_dp_a64_untyped_atomic_desc(devinfo
, inst
->exec_size
, 64,
5484 arg
, /* atomic_op */
5485 !inst
->dst
.is_null());
5489 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5490 desc
= brw_dp_a64_untyped_atomic_float_desc(devinfo
, inst
->exec_size
,
5491 arg
, /* atomic_op */
5492 !inst
->dst
.is_null());
5496 unreachable("Unknown A64 logical instruction");
5499 /* Update the original instruction. */
5500 inst
->opcode
= SHADER_OPCODE_SEND
;
5502 inst
->ex_mlen
= ex_mlen
;
5503 inst
->header_size
= 0;
5504 inst
->send_has_side_effects
= has_side_effects
;
5505 inst
->send_is_volatile
= !has_side_effects
;
5507 /* Set up SFID and descriptors */
5508 inst
->sfid
= HSW_SFID_DATAPORT_DATA_CACHE_1
;
5510 inst
->resize_sources(4);
5511 inst
->src
[0] = brw_imm_ud(0); /* desc */
5512 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5513 inst
->src
[2] = payload
;
5514 inst
->src
[3] = payload2
;
5518 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5520 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5522 if (devinfo
->gen
>= 7) {
5523 fs_reg index
= inst
->src
[0];
5524 /* We are switching the instruction from an ALU-like instruction to a
5525 * send-from-grf instruction. Since sends can't handle strides or
5526 * source modifiers, we have to make a copy of the offset source.
5528 fs_reg offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5529 bld
.MOV(offset
, inst
->src
[1]);
5531 const unsigned simd_mode
=
5532 inst
->exec_size
<= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8
:
5533 BRW_SAMPLER_SIMD_MODE_SIMD16
;
5535 inst
->opcode
= SHADER_OPCODE_SEND
;
5536 inst
->mlen
= inst
->exec_size
/ 8;
5537 inst
->resize_sources(3);
5539 inst
->sfid
= BRW_SFID_SAMPLER
;
5540 inst
->desc
= brw_sampler_desc(devinfo
, 0, 0,
5541 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
5543 if (index
.file
== IMM
) {
5544 inst
->desc
|= index
.ud
& 0xff;
5545 inst
->src
[0] = brw_imm_ud(0);
5547 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5548 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5549 ubld
.AND(tmp
, index
, brw_imm_ud(0xff));
5550 inst
->src
[0] = component(tmp
, 0);
5552 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5553 inst
->src
[2] = offset
; /* payload */
5555 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
5556 BRW_REGISTER_TYPE_UD
);
5558 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
5560 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
5561 inst
->resize_sources(1);
5562 inst
->base_mrf
= payload
.nr
;
5563 inst
->header_size
= 1;
5564 inst
->mlen
= 1 + inst
->exec_size
/ 8;
5569 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5571 assert(bld
.shader
->devinfo
->gen
< 6);
5574 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
5576 if (inst
->sources
> 1) {
5577 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
5578 * "Message Payload":
5580 * "Operand0[7]. For the INT DIV functions, this operand is the
5583 * "Operand1[7]. For the INT DIV functions, this operand is the
5586 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
5587 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
5588 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
5590 inst
->resize_sources(1);
5591 inst
->src
[0] = src0
;
5593 assert(inst
->exec_size
== 8);
5594 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
5599 fs_visitor::lower_logical_sends()
5601 bool progress
= false;
5603 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5604 const fs_builder
ibld(this, block
, inst
);
5606 switch (inst
->opcode
) {
5607 case FS_OPCODE_FB_WRITE_LOGICAL
:
5608 assert(stage
== MESA_SHADER_FRAGMENT
);
5609 lower_fb_write_logical_send(ibld
, inst
,
5610 brw_wm_prog_data(prog_data
),
5611 (const brw_wm_prog_key
*)key
,
5615 case FS_OPCODE_FB_READ_LOGICAL
:
5616 lower_fb_read_logical_send(ibld
, inst
);
5619 case SHADER_OPCODE_TEX_LOGICAL
:
5620 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
5623 case SHADER_OPCODE_TXD_LOGICAL
:
5624 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
5627 case SHADER_OPCODE_TXF_LOGICAL
:
5628 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
5631 case SHADER_OPCODE_TXL_LOGICAL
:
5632 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
5635 case SHADER_OPCODE_TXS_LOGICAL
:
5636 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
5639 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5640 lower_sampler_logical_send(ibld
, inst
,
5641 SHADER_OPCODE_IMAGE_SIZE_LOGICAL
);
5644 case FS_OPCODE_TXB_LOGICAL
:
5645 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
5648 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
5649 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
5652 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
5653 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
5656 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
5657 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
5660 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
5661 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
5664 case SHADER_OPCODE_LOD_LOGICAL
:
5665 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
5668 case SHADER_OPCODE_TG4_LOGICAL
:
5669 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
5672 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
5673 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
5676 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
5677 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
5680 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5681 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5682 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5683 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5684 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5685 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5686 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5687 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5688 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5689 lower_surface_logical_send(ibld
, inst
);
5692 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
5693 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
5694 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
5695 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
5696 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
5697 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
5698 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5699 lower_a64_logical_send(ibld
, inst
);
5702 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
5703 lower_varying_pull_constant_logical_send(ibld
, inst
);
5706 case SHADER_OPCODE_RCP
:
5707 case SHADER_OPCODE_RSQ
:
5708 case SHADER_OPCODE_SQRT
:
5709 case SHADER_OPCODE_EXP2
:
5710 case SHADER_OPCODE_LOG2
:
5711 case SHADER_OPCODE_SIN
:
5712 case SHADER_OPCODE_COS
:
5713 case SHADER_OPCODE_POW
:
5714 case SHADER_OPCODE_INT_QUOTIENT
:
5715 case SHADER_OPCODE_INT_REMAINDER
:
5716 /* The math opcodes are overloaded for the send-like and
5717 * expression-like instructions which seems kind of icky. Gen6+ has
5718 * a native (but rather quirky) MATH instruction so we don't need to
5719 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
5720 * logical instructions (which we can easily recognize because they
5721 * have mlen = 0) into send-like virtual instructions.
5723 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
5724 lower_math_logical_send(ibld
, inst
);
5739 invalidate_live_intervals();
5745 is_mixed_float_with_fp32_dst(const fs_inst
*inst
)
5747 /* This opcode sometimes uses :W type on the source even if the operand is
5748 * a :HF, because in gen7 there is no support for :HF, and thus it uses :W.
5750 if (inst
->opcode
== BRW_OPCODE_F16TO32
)
5753 if (inst
->dst
.type
!= BRW_REGISTER_TYPE_F
)
5756 for (int i
= 0; i
< inst
->sources
; i
++) {
5757 if (inst
->src
[i
].type
== BRW_REGISTER_TYPE_HF
)
5765 is_mixed_float_with_packed_fp16_dst(const fs_inst
*inst
)
5767 /* This opcode sometimes uses :W type on the destination even if the
5768 * destination is a :HF, because in gen7 there is no support for :HF, and
5771 if (inst
->opcode
== BRW_OPCODE_F32TO16
&&
5772 inst
->dst
.stride
== 1)
5775 if (inst
->dst
.type
!= BRW_REGISTER_TYPE_HF
||
5776 inst
->dst
.stride
!= 1)
5779 for (int i
= 0; i
< inst
->sources
; i
++) {
5780 if (inst
->src
[i
].type
== BRW_REGISTER_TYPE_F
)
5788 * Get the closest allowed SIMD width for instruction \p inst accounting for
5789 * some common regioning and execution control restrictions that apply to FPU
5790 * instructions. These restrictions don't necessarily have any relevance to
5791 * instructions not executed by the FPU pipeline like extended math, control
5792 * flow or send message instructions.
5794 * For virtual opcodes it's really up to the instruction -- In some cases
5795 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
5796 * instructions) it may simplify virtual instruction lowering if we can
5797 * enforce FPU-like regioning restrictions already on the virtual instruction,
5798 * in other cases (e.g. virtual send-like instructions) this may be
5799 * excessively restrictive.
5802 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
5803 const fs_inst
*inst
)
5805 /* Maximum execution size representable in the instruction controls. */
5806 unsigned max_width
= MIN2(32, inst
->exec_size
);
5808 /* According to the PRMs:
5809 * "A. In Direct Addressing mode, a source cannot span more than 2
5810 * adjacent GRF registers.
5811 * B. A destination cannot span more than 2 adjacent GRF registers."
5813 * Look for the source or destination with the largest register region
5814 * which is the one that is going to limit the overall execution size of
5815 * the instruction due to this rule.
5817 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
5819 for (unsigned i
= 0; i
< inst
->sources
; i
++)
5820 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
5822 /* Calculate the maximum execution size of the instruction based on the
5823 * factor by which it goes over the hardware limit of 2 GRFs.
5826 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
5828 /* According to the IVB PRMs:
5829 * "When destination spans two registers, the source MUST span two
5830 * registers. The exception to the above rule:
5832 * - When source is scalar, the source registers are not incremented.
5833 * - When source is packed integer Word and destination is packed
5834 * integer DWord, the source register is not incremented but the
5835 * source sub register is incremented."
5837 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
5838 * restrictions. The code below intentionally doesn't check whether the
5839 * destination type is integer because empirically the hardware doesn't
5840 * seem to care what the actual type is as long as it's dword-aligned.
5842 if (devinfo
->gen
< 8) {
5843 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5844 /* IVB implements DF scalars as <0;2,1> regions. */
5845 const bool is_scalar_exception
= is_uniform(inst
->src
[i
]) &&
5846 (devinfo
->is_haswell
|| type_sz(inst
->src
[i
].type
) != 8);
5847 const bool is_packed_word_exception
=
5848 type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
5849 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1;
5851 /* We check size_read(i) against size_written instead of REG_SIZE
5852 * because we want to properly handle SIMD32. In SIMD32, you can end
5853 * up with writes to 4 registers and a source that reads 2 registers
5854 * and we may still need to lower all the way to SIMD8 in that case.
5856 if (inst
->size_written
> REG_SIZE
&&
5857 inst
->size_read(i
) != 0 &&
5858 inst
->size_read(i
) < inst
->size_written
&&
5859 !is_scalar_exception
&& !is_packed_word_exception
) {
5860 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
5861 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
5866 if (devinfo
->gen
< 6) {
5867 /* From the G45 PRM, Volume 4 Page 361:
5869 * "Operand Alignment Rule: With the exceptions listed below, a
5870 * source/destination operand in general should be aligned to even
5871 * 256-bit physical register with a region size equal to two 256-bit
5872 * physical registers."
5874 * Normally we enforce this by allocating virtual registers to the
5875 * even-aligned class. But we need to handle payload registers.
5877 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5878 if (inst
->src
[i
].file
== FIXED_GRF
&& (inst
->src
[i
].nr
& 1) &&
5879 inst
->size_read(i
) > REG_SIZE
) {
5880 max_width
= MIN2(max_width
, 8);
5885 /* From the IVB PRMs:
5886 * "When an instruction is SIMD32, the low 16 bits of the execution mask
5887 * are applied for both halves of the SIMD32 instruction. If different
5888 * execution mask channels are required, split the instruction into two
5889 * SIMD16 instructions."
5891 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
5892 * 32-wide control flow support in hardware and will behave similarly.
5894 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
5895 max_width
= MIN2(max_width
, 16);
5897 /* From the IVB PRMs (applies to HSW too):
5898 * "Instructions with condition modifiers must not use SIMD32."
5900 * From the BDW PRMs (applies to later hardware too):
5901 * "Ternary instruction with condition modifiers must not use SIMD32."
5903 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
5904 max_width
= MIN2(max_width
, 16);
5906 /* From the IVB PRMs (applies to other devices that don't have the
5907 * gen_device_info::supports_simd16_3src flag set):
5908 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
5909 * SIMD8 is not allowed for DF operations."
5911 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
5912 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
5914 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
5915 * the 8-bit quarter of the execution mask signals specified in the
5916 * instruction control fields) for the second compressed half of any
5917 * single-precision instruction (for double-precision instructions
5918 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
5919 * the EU will apply the wrong execution controls for the second
5920 * sequential GRF write if the number of channels per GRF is not exactly
5921 * eight in single-precision mode (or four in double-float mode).
5923 * In this situation we calculate the maximum size of the split
5924 * instructions so they only ever write to a single register.
5926 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
5927 !inst
->force_writemask_all
) {
5928 const unsigned channels_per_grf
= inst
->exec_size
/
5929 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
5930 const unsigned exec_type_size
= get_exec_type_size(inst
);
5931 assert(exec_type_size
);
5933 /* The hardware shifts exactly 8 channels per compressed half of the
5934 * instruction in single-precision mode and exactly 4 in double-precision.
5936 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
5937 max_width
= MIN2(max_width
, channels_per_grf
);
5939 /* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
5940 * because HW applies the same channel enable signals to both halves of
5941 * the compressed instruction which will be just wrong under
5942 * non-uniform control flow.
5944 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
5945 (exec_type_size
== 8 || type_sz(inst
->dst
.type
) == 8))
5946 max_width
= MIN2(max_width
, 4);
5949 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
5952 * "No SIMD16 in mixed mode when destination is f32. Instruction
5953 * execution size must be no more than 8."
5955 * FIXME: the simulator doesn't seem to complain if we don't do this and
5956 * empirical testing with existing CTS tests show that they pass just fine
5957 * without implementing this, however, since our interpretation of the PRM
5958 * is that conversion MOVs between HF and F are still mixed-float
5959 * instructions (and therefore subject to this restriction) we decided to
5960 * split them to be safe. Might be useful to do additional investigation to
5961 * lift the restriction if we can ensure that it is safe though, since these
5962 * conversions are common when half-float types are involved since many
5963 * instructions do not support HF types and conversions from/to F are
5966 if (is_mixed_float_with_fp32_dst(inst
))
5967 max_width
= MIN2(max_width
, 8);
5969 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
5972 * "No SIMD16 in mixed mode when destination is packed f16 for both
5973 * Align1 and Align16."
5975 if (is_mixed_float_with_packed_fp16_dst(inst
))
5976 max_width
= MIN2(max_width
, 8);
5978 /* Only power-of-two execution sizes are representable in the instruction
5981 return 1 << _mesa_logbase2(max_width
);
5985 * Get the maximum allowed SIMD width for instruction \p inst accounting for
5986 * various payload size restrictions that apply to sampler message
5989 * This is only intended to provide a maximum theoretical bound for the
5990 * execution size of the message based on the number of argument components
5991 * alone, which in most cases will determine whether the SIMD8 or SIMD16
5992 * variant of the message can be used, though some messages may have
5993 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
5994 * the message length to determine the exact SIMD width and argument count,
5995 * which makes a number of sampler message combinations impossible to
5999 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
6000 const fs_inst
*inst
)
6002 /* If we have a min_lod parameter on anything other than a simple sample
6003 * message, it will push it over 5 arguments and we have to fall back to
6006 if (inst
->opcode
!= SHADER_OPCODE_TEX
&&
6007 inst
->components_read(TEX_LOGICAL_SRC_MIN_LOD
))
6010 /* Calculate the number of coordinate components that have to be present
6011 * assuming that additional arguments follow the texel coordinates in the
6012 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
6013 * need to pad to four or three components depending on the message,
6014 * pre-ILK we need to pad to at most three components.
6016 const unsigned req_coord_components
=
6017 (devinfo
->gen
>= 7 ||
6018 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
6019 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
6020 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
6023 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
6024 * variant of the TXL or TXF message.
6026 const bool implicit_lod
= devinfo
->gen
>= 9 &&
6027 (inst
->opcode
== SHADER_OPCODE_TXL
||
6028 inst
->opcode
== SHADER_OPCODE_TXF
) &&
6029 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
6031 /* Calculate the total number of argument components that need to be passed
6032 * to the sampler unit.
6034 const unsigned num_payload_components
=
6035 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
6036 req_coord_components
) +
6037 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
6038 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
6039 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
6040 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
6041 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
6042 inst
->components_read(TEX_LOGICAL_SRC_TG4_OFFSET
) : 0) +
6043 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
6045 /* SIMD16 messages with more than five arguments exceed the maximum message
6046 * size supported by the sampler, regardless of whether a header is
6049 return MIN2(inst
->exec_size
,
6050 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
6054 * Get the closest native SIMD width supported by the hardware for instruction
6055 * \p inst. The instruction will be left untouched by
6056 * fs_visitor::lower_simd_width() if the returned value is equal to the
6057 * original execution size.
6060 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
6061 const fs_inst
*inst
)
6063 switch (inst
->opcode
) {
6064 case BRW_OPCODE_MOV
:
6065 case BRW_OPCODE_SEL
:
6066 case BRW_OPCODE_NOT
:
6067 case BRW_OPCODE_AND
:
6069 case BRW_OPCODE_XOR
:
6070 case BRW_OPCODE_SHR
:
6071 case BRW_OPCODE_SHL
:
6072 case BRW_OPCODE_ASR
:
6073 case BRW_OPCODE_CMPN
:
6074 case BRW_OPCODE_CSEL
:
6075 case BRW_OPCODE_F32TO16
:
6076 case BRW_OPCODE_F16TO32
:
6077 case BRW_OPCODE_BFREV
:
6078 case BRW_OPCODE_BFE
:
6079 case BRW_OPCODE_ADD
:
6080 case BRW_OPCODE_MUL
:
6081 case BRW_OPCODE_AVG
:
6082 case BRW_OPCODE_FRC
:
6083 case BRW_OPCODE_RNDU
:
6084 case BRW_OPCODE_RNDD
:
6085 case BRW_OPCODE_RNDE
:
6086 case BRW_OPCODE_RNDZ
:
6087 case BRW_OPCODE_LZD
:
6088 case BRW_OPCODE_FBH
:
6089 case BRW_OPCODE_FBL
:
6090 case BRW_OPCODE_CBIT
:
6091 case BRW_OPCODE_SAD2
:
6092 case BRW_OPCODE_MAD
:
6093 case BRW_OPCODE_LRP
:
6094 case FS_OPCODE_PACK
:
6095 case SHADER_OPCODE_SEL_EXEC
:
6096 case SHADER_OPCODE_CLUSTER_BROADCAST
:
6097 return get_fpu_lowered_simd_width(devinfo
, inst
);
6099 case BRW_OPCODE_CMP
: {
6100 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
6101 * when the destination is a GRF the dependency-clear bit on the flag
6102 * register is cleared early.
6104 * Suggested workarounds are to disable coissuing CMP instructions
6105 * or to split CMP(16) instructions into two CMP(8) instructions.
6107 * We choose to split into CMP(8) instructions since disabling
6108 * coissuing would affect CMP instructions not otherwise affected by
6111 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
6112 !inst
->dst
.is_null() ? 8 : ~0);
6113 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
6115 case BRW_OPCODE_BFI1
:
6116 case BRW_OPCODE_BFI2
:
6117 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
6119 * "Force BFI instructions to be executed always in SIMD8."
6121 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
6122 get_fpu_lowered_simd_width(devinfo
, inst
));
6125 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
6126 return inst
->exec_size
;
6128 case SHADER_OPCODE_RCP
:
6129 case SHADER_OPCODE_RSQ
:
6130 case SHADER_OPCODE_SQRT
:
6131 case SHADER_OPCODE_EXP2
:
6132 case SHADER_OPCODE_LOG2
:
6133 case SHADER_OPCODE_SIN
:
6134 case SHADER_OPCODE_COS
: {
6135 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
6136 * Gen6. Extended Math Function is limited to SIMD8 with half-float.
6138 if (devinfo
->gen
== 6 || (devinfo
->gen
== 4 && !devinfo
->is_g4x
))
6139 return MIN2(8, inst
->exec_size
);
6140 if (inst
->dst
.type
== BRW_REGISTER_TYPE_HF
)
6141 return MIN2(8, inst
->exec_size
);
6142 return MIN2(16, inst
->exec_size
);
6145 case SHADER_OPCODE_POW
: {
6146 /* SIMD16 is only allowed on Gen7+. Extended Math Function is limited
6147 * to SIMD8 with half-float
6149 if (devinfo
->gen
< 7)
6150 return MIN2(8, inst
->exec_size
);
6151 if (inst
->dst
.type
== BRW_REGISTER_TYPE_HF
)
6152 return MIN2(8, inst
->exec_size
);
6153 return MIN2(16, inst
->exec_size
);
6156 case SHADER_OPCODE_INT_QUOTIENT
:
6157 case SHADER_OPCODE_INT_REMAINDER
:
6158 /* Integer division is limited to SIMD8 on all generations. */
6159 return MIN2(8, inst
->exec_size
);
6161 case FS_OPCODE_LINTERP
:
6162 case SHADER_OPCODE_GET_BUFFER_SIZE
:
6163 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
6164 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
6165 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
6166 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
6167 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
6168 return MIN2(16, inst
->exec_size
);
6170 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
6171 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
6172 * message used to implement varying pull constant loads, so expand it
6173 * to SIMD16. An alternative with longer message payload length but
6174 * shorter return payload would be to use the SIMD8 sampler message that
6175 * takes (header, u, v, r) as parameters instead of (header, u).
6177 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
6179 case FS_OPCODE_DDX_COARSE
:
6180 case FS_OPCODE_DDX_FINE
:
6181 case FS_OPCODE_DDY_COARSE
:
6182 case FS_OPCODE_DDY_FINE
:
6183 /* The implementation of this virtual opcode may require emitting
6184 * compressed Align16 instructions, which are severely limited on some
6187 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
6188 * Region Restrictions):
6190 * "In Align16 access mode, SIMD16 is not allowed for DW operations
6191 * and SIMD8 is not allowed for DF operations."
6193 * In this context, "DW operations" means "operations acting on 32-bit
6194 * values", so it includes operations on floats.
6196 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
6197 * (Instruction Compression -> Rules and Restrictions):
6199 * "A compressed instruction must be in Align1 access mode. Align16
6200 * mode instructions cannot be compressed."
6202 * Similar text exists in the g45 PRM.
6204 * Empirically, compressed align16 instructions using odd register
6205 * numbers don't appear to work on Sandybridge either.
6207 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
6208 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
6209 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
6211 case SHADER_OPCODE_MULH
:
6212 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
6213 * is 8-wide on Gen7+.
6215 return (devinfo
->gen
>= 7 ? 8 :
6216 get_fpu_lowered_simd_width(devinfo
, inst
));
6218 case FS_OPCODE_FB_WRITE_LOGICAL
:
6219 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
6222 assert(devinfo
->gen
!= 6 ||
6223 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
6224 inst
->exec_size
== 8);
6225 /* Dual-source FB writes are unsupported in SIMD16 mode. */
6226 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
6227 8 : MIN2(16, inst
->exec_size
));
6229 case FS_OPCODE_FB_READ_LOGICAL
:
6230 return MIN2(16, inst
->exec_size
);
6232 case SHADER_OPCODE_TEX_LOGICAL
:
6233 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
6234 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
6235 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
6236 case SHADER_OPCODE_LOD_LOGICAL
:
6237 case SHADER_OPCODE_TG4_LOGICAL
:
6238 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
6239 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
6240 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
6241 return get_sampler_lowered_simd_width(devinfo
, inst
);
6243 case SHADER_OPCODE_TXD_LOGICAL
:
6244 /* TXD is unsupported in SIMD16 mode. */
6247 case SHADER_OPCODE_TXL_LOGICAL
:
6248 case FS_OPCODE_TXB_LOGICAL
:
6249 /* Only one execution size is representable pre-ILK depending on whether
6250 * the shadow reference argument is present.
6252 if (devinfo
->gen
== 4)
6253 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
6255 return get_sampler_lowered_simd_width(devinfo
, inst
);
6257 case SHADER_OPCODE_TXF_LOGICAL
:
6258 case SHADER_OPCODE_TXS_LOGICAL
:
6259 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
6260 * messages. Use SIMD16 instead.
6262 if (devinfo
->gen
== 4)
6265 return get_sampler_lowered_simd_width(devinfo
, inst
);
6267 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
6268 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
6269 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
6272 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
6273 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
6274 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
6275 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
6276 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
6277 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
6278 return MIN2(16, inst
->exec_size
);
6280 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
6281 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
6282 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
6283 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
6284 return devinfo
->gen
<= 8 ? 8 : MIN2(16, inst
->exec_size
);
6286 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
6287 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
6288 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
6291 case SHADER_OPCODE_URB_READ_SIMD8
:
6292 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
6293 case SHADER_OPCODE_URB_WRITE_SIMD8
:
6294 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
6295 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
6296 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
6297 return MIN2(8, inst
->exec_size
);
6299 case SHADER_OPCODE_QUAD_SWIZZLE
: {
6300 const unsigned swiz
= inst
->src
[1].ud
;
6301 return (is_uniform(inst
->src
[0]) ?
6302 get_fpu_lowered_simd_width(devinfo
, inst
) :
6303 devinfo
->gen
< 11 && type_sz(inst
->src
[0].type
) == 4 ? 8 :
6304 swiz
== BRW_SWIZZLE_XYXY
|| swiz
== BRW_SWIZZLE_ZWZW
? 4 :
6305 get_fpu_lowered_simd_width(devinfo
, inst
));
6307 case SHADER_OPCODE_MOV_INDIRECT
: {
6308 /* From IVB and HSW PRMs:
6310 * "2.When the destination requires two registers and the sources are
6311 * indirect, the sources must use 1x1 regioning mode.
6313 * In case of DF instructions in HSW/IVB, the exec_size is limited by
6314 * the EU decompression logic not handling VxH indirect addressing
6317 const unsigned max_size
= (devinfo
->gen
>= 8 ? 2 : 1) * REG_SIZE
;
6318 /* Prior to Broadwell, we only have 8 address subregisters. */
6319 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
6320 max_size
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
6324 case SHADER_OPCODE_LOAD_PAYLOAD
: {
6325 const unsigned reg_count
=
6326 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
6328 if (reg_count
> 2) {
6329 /* Only LOAD_PAYLOAD instructions with per-channel destination region
6330 * can be easily lowered (which excludes headers and heterogeneous
6333 assert(!inst
->header_size
);
6334 for (unsigned i
= 0; i
< inst
->sources
; i
++)
6335 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
6336 inst
->src
[i
].file
== BAD_FILE
);
6338 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
6340 return inst
->exec_size
;
6344 return inst
->exec_size
;
6349 * Return true if splitting out the group of channels of instruction \p inst
6350 * given by lbld.group() requires allocating a temporary for the i-th source
6351 * of the lowered instruction.
6354 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
6356 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
6357 (inst
->components_read(i
) == 1 &&
6358 lbld
.dispatch_width() <= inst
->exec_size
)) ||
6359 (inst
->flags_written() &
6360 flag_mask(inst
->src
[i
], type_sz(inst
->src
[i
].type
)));
6364 * Extract the data that would be consumed by the channel group given by
6365 * lbld.group() from the i-th source region of instruction \p inst and return
6366 * it as result in packed form.
6369 emit_unzip(const fs_builder
&lbld
, fs_inst
*inst
, unsigned i
)
6371 assert(lbld
.group() >= inst
->group
);
6373 /* Specified channel group from the source region. */
6374 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group() - inst
->group
);
6376 if (needs_src_copy(lbld
, inst
, i
)) {
6377 /* Builder of the right width to perform the copy avoiding uninitialized
6378 * data if the lowered execution size is greater than the original
6379 * execution size of the instruction.
6381 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
6382 inst
->exec_size
), 0);
6383 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
6385 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
6386 cbld
.MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
6390 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
6391 /* The source is invariant for all dispatch_width-wide groups of the
6394 return inst
->src
[i
];
6397 /* We can just point the lowered instruction at the right channel group
6398 * from the original region.
6405 * Return true if splitting out the group of channels of instruction \p inst
6406 * given by lbld.group() requires allocating a temporary for the destination
6407 * of the lowered instruction and copying the data back to the original
6408 * destination region.
6411 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
6413 /* If the instruction writes more than one component we'll have to shuffle
6414 * the results of multiple lowered instructions in order to make sure that
6415 * they end up arranged correctly in the original destination region.
6417 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
6420 /* If the lowered execution size is larger than the original the result of
6421 * the instruction won't fit in the original destination, so we'll have to
6422 * allocate a temporary in any case.
6424 if (lbld
.dispatch_width() > inst
->exec_size
)
6427 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6428 /* If we already made a copy of the source for other reasons there won't
6429 * be any overlap with the destination.
6431 if (needs_src_copy(lbld
, inst
, i
))
6434 /* In order to keep the logic simple we emit a copy whenever the
6435 * destination region doesn't exactly match an overlapping source, which
6436 * may point at the source and destination not being aligned group by
6437 * group which could cause one of the lowered instructions to overwrite
6438 * the data read from the same source by other lowered instructions.
6440 if (regions_overlap(inst
->dst
, inst
->size_written
,
6441 inst
->src
[i
], inst
->size_read(i
)) &&
6442 !inst
->dst
.equals(inst
->src
[i
]))
6450 * Insert data from a packed temporary into the channel group given by
6451 * lbld.group() of the destination region of instruction \p inst and return
6452 * the temporary as result. Any copy instructions that are required for
6453 * unzipping the previous value (in the case of partial writes) will be
6454 * inserted using \p lbld_before and any copy instructions required for
6455 * zipping up the destination of \p inst will be inserted using \p lbld_after.
6458 emit_zip(const fs_builder
&lbld_before
, const fs_builder
&lbld_after
,
6461 assert(lbld_before
.dispatch_width() == lbld_after
.dispatch_width());
6462 assert(lbld_before
.group() == lbld_after
.group());
6463 assert(lbld_after
.group() >= inst
->group
);
6465 /* Specified channel group from the destination region. */
6466 const fs_reg dst
= horiz_offset(inst
->dst
, lbld_after
.group() - inst
->group
);
6467 const unsigned dst_size
= inst
->size_written
/
6468 inst
->dst
.component_size(inst
->exec_size
);
6470 if (needs_dst_copy(lbld_after
, inst
)) {
6471 const fs_reg tmp
= lbld_after
.vgrf(inst
->dst
.type
, dst_size
);
6473 if (inst
->predicate
) {
6474 /* Handle predication by copying the original contents of
6475 * the destination into the temporary before emitting the
6476 * lowered instruction.
6478 const fs_builder gbld_before
=
6479 lbld_before
.group(MIN2(lbld_before
.dispatch_width(),
6480 inst
->exec_size
), 0);
6481 for (unsigned k
= 0; k
< dst_size
; ++k
) {
6482 gbld_before
.MOV(offset(tmp
, lbld_before
, k
),
6483 offset(dst
, inst
->exec_size
, k
));
6487 const fs_builder gbld_after
=
6488 lbld_after
.group(MIN2(lbld_after
.dispatch_width(),
6489 inst
->exec_size
), 0);
6490 for (unsigned k
= 0; k
< dst_size
; ++k
) {
6491 /* Use a builder of the right width to perform the copy avoiding
6492 * uninitialized data if the lowered execution size is greater than
6493 * the original execution size of the instruction.
6495 gbld_after
.MOV(offset(dst
, inst
->exec_size
, k
),
6496 offset(tmp
, lbld_after
, k
));
6502 /* No need to allocate a temporary for the lowered instruction, just
6503 * take the right group of channels from the original region.
6510 fs_visitor::lower_simd_width()
6512 bool progress
= false;
6514 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
6515 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
6517 if (lower_width
!= inst
->exec_size
) {
6518 /* Builder matching the original instruction. We may also need to
6519 * emit an instruction of width larger than the original, set the
6520 * execution size of the builder to the highest of both for now so
6521 * we're sure that both cases can be handled.
6523 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
6524 const fs_builder ibld
= bld
.at(block
, inst
)
6525 .exec_all(inst
->force_writemask_all
)
6526 .group(max_width
, inst
->group
/ max_width
);
6528 /* Split the copies in chunks of the execution width of either the
6529 * original or the lowered instruction, whichever is lower.
6531 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
6532 const unsigned dst_size
= inst
->size_written
/
6533 inst
->dst
.component_size(inst
->exec_size
);
6535 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
6537 /* Inserting the zip, unzip, and duplicated instructions in all of
6538 * the right spots is somewhat tricky. All of the unzip and any
6539 * instructions from the zip which unzip the destination prior to
6540 * writing need to happen before all of the per-group instructions
6541 * and the zip instructions need to happen after. In order to sort
6542 * this all out, we insert the unzip instructions before \p inst,
6543 * insert the per-group instructions after \p inst (i.e. before
6544 * inst->next), and insert the zip instructions before the
6545 * instruction after \p inst. Since we are inserting instructions
6546 * after \p inst, inst->next is a moving target and we need to save
6547 * it off here so that we insert the zip instructions in the right
6550 * Since we're inserting split instructions after after_inst, the
6551 * instructions will end up in the reverse order that we insert them.
6552 * However, certain render target writes require that the low group
6553 * instructions come before the high group. From the Ivy Bridge PRM
6554 * Vol. 4, Pt. 1, Section 3.9.11:
6556 * "If multiple SIMD8 Dual Source messages are delivered by the
6557 * pixel shader thread, each SIMD8_DUALSRC_LO message must be
6558 * issued before the SIMD8_DUALSRC_HI message with the same Slot
6559 * Group Select setting."
6561 * And, from Section 3.9.11.1 of the same PRM:
6563 * "When SIMD32 or SIMD16 PS threads send render target writes
6564 * with multiple SIMD8 and SIMD16 messages, the following must
6567 * All the slots (as described above) must have a corresponding
6568 * render target write irrespective of the slot's validity. A slot
6569 * is considered valid when at least one sample is enabled. For
6570 * example, a SIMD16 PS thread must send two SIMD8 render target
6571 * writes to cover all the slots.
6573 * PS thread must send SIMD render target write messages with
6574 * increasing slot numbers. For example, SIMD16 thread has
6575 * Slot[15:0] and if two SIMD8 render target writes are used, the
6576 * first SIMD8 render target write must send Slot[7:0] and the
6577 * next one must send Slot[15:8]."
6579 * In order to make low group instructions come before high group
6580 * instructions (this is required for some render target writes), we
6581 * split from the highest group to lowest.
6583 exec_node
*const after_inst
= inst
->next
;
6584 for (int i
= n
- 1; i
>= 0; i
--) {
6585 /* Emit a copy of the original instruction with the lowered width.
6586 * If the EOT flag was set throw it away except for the last
6587 * instruction to avoid killing the thread prematurely.
6589 fs_inst split_inst
= *inst
;
6590 split_inst
.exec_size
= lower_width
;
6591 split_inst
.eot
= inst
->eot
&& i
== int(n
- 1);
6593 /* Select the correct channel enables for the i-th group, then
6594 * transform the sources and destination and emit the lowered
6597 const fs_builder lbld
= ibld
.group(lower_width
, i
);
6599 for (unsigned j
= 0; j
< inst
->sources
; j
++)
6600 split_inst
.src
[j
] = emit_unzip(lbld
.at(block
, inst
), inst
, j
);
6602 split_inst
.dst
= emit_zip(lbld
.at(block
, inst
),
6603 lbld
.at(block
, after_inst
), inst
);
6604 split_inst
.size_written
=
6605 split_inst
.dst
.component_size(lower_width
) * dst_size
;
6607 lbld
.at(block
, inst
->next
).emit(split_inst
);
6610 inst
->remove(block
);
6616 invalidate_live_intervals();
6622 fs_visitor::dump_instructions()
6624 dump_instructions(NULL
);
6628 fs_visitor::dump_instructions(const char *name
)
6630 FILE *file
= stderr
;
6631 if (name
&& geteuid() != 0) {
6632 file
= fopen(name
, "w");
6638 calculate_register_pressure();
6639 int ip
= 0, max_pressure
= 0;
6640 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
6641 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
6642 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
6643 dump_instruction(inst
, file
);
6646 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
6649 foreach_in_list(backend_instruction
, inst
, &instructions
) {
6650 fprintf(file
, "%4d: ", ip
++);
6651 dump_instruction(inst
, file
);
6655 if (file
!= stderr
) {
6661 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
6663 dump_instruction(be_inst
, stderr
);
6667 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
6669 fs_inst
*inst
= (fs_inst
*)be_inst
;
6671 if (inst
->predicate
) {
6672 fprintf(file
, "(%cf%d.%d) ",
6673 inst
->predicate_inverse
? '-' : '+',
6674 inst
->flag_subreg
/ 2,
6675 inst
->flag_subreg
% 2);
6678 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
6680 fprintf(file
, ".sat");
6681 if (inst
->conditional_mod
) {
6682 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
6683 if (!inst
->predicate
&&
6684 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
6685 inst
->opcode
!= BRW_OPCODE_CSEL
&&
6686 inst
->opcode
!= BRW_OPCODE_IF
&&
6687 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
6688 fprintf(file
, ".f%d.%d", inst
->flag_subreg
/ 2,
6689 inst
->flag_subreg
% 2);
6692 fprintf(file
, "(%d) ", inst
->exec_size
);
6695 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
6698 if (inst
->ex_mlen
) {
6699 fprintf(file
, "(ex_mlen: %d) ", inst
->ex_mlen
);
6703 fprintf(file
, "(EOT) ");
6706 switch (inst
->dst
.file
) {
6708 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
6711 fprintf(file
, "g%d", inst
->dst
.nr
);
6714 fprintf(file
, "m%d", inst
->dst
.nr
);
6717 fprintf(file
, "(null)");
6720 fprintf(file
, "***u%d***", inst
->dst
.nr
);
6723 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
6726 switch (inst
->dst
.nr
) {
6728 fprintf(file
, "null");
6730 case BRW_ARF_ADDRESS
:
6731 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
6733 case BRW_ARF_ACCUMULATOR
:
6734 fprintf(file
, "acc%d", inst
->dst
.subnr
);
6737 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
6740 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
6745 unreachable("not reached");
6748 if (inst
->dst
.offset
||
6749 (inst
->dst
.file
== VGRF
&&
6750 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
6751 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
6752 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
6753 inst
->dst
.offset
% reg_size
);
6756 if (inst
->dst
.stride
!= 1)
6757 fprintf(file
, "<%u>", inst
->dst
.stride
);
6758 fprintf(file
, ":%s, ", brw_reg_type_to_letters(inst
->dst
.type
));
6760 for (int i
= 0; i
< inst
->sources
; i
++) {
6761 if (inst
->src
[i
].negate
)
6763 if (inst
->src
[i
].abs
)
6765 switch (inst
->src
[i
].file
) {
6767 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
6770 fprintf(file
, "g%d", inst
->src
[i
].nr
);
6773 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
6776 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
6779 fprintf(file
, "u%d", inst
->src
[i
].nr
);
6782 fprintf(file
, "(null)");
6785 switch (inst
->src
[i
].type
) {
6786 case BRW_REGISTER_TYPE_F
:
6787 fprintf(file
, "%-gf", inst
->src
[i
].f
);
6789 case BRW_REGISTER_TYPE_DF
:
6790 fprintf(file
, "%fdf", inst
->src
[i
].df
);
6792 case BRW_REGISTER_TYPE_W
:
6793 case BRW_REGISTER_TYPE_D
:
6794 fprintf(file
, "%dd", inst
->src
[i
].d
);
6796 case BRW_REGISTER_TYPE_UW
:
6797 case BRW_REGISTER_TYPE_UD
:
6798 fprintf(file
, "%uu", inst
->src
[i
].ud
);
6800 case BRW_REGISTER_TYPE_Q
:
6801 fprintf(file
, "%" PRId64
"q", inst
->src
[i
].d64
);
6803 case BRW_REGISTER_TYPE_UQ
:
6804 fprintf(file
, "%" PRIu64
"uq", inst
->src
[i
].u64
);
6806 case BRW_REGISTER_TYPE_VF
:
6807 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
6808 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
6809 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
6810 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
6811 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
6813 case BRW_REGISTER_TYPE_V
:
6814 case BRW_REGISTER_TYPE_UV
:
6815 fprintf(file
, "%08x%s", inst
->src
[i
].ud
,
6816 inst
->src
[i
].type
== BRW_REGISTER_TYPE_V
? "V" : "UV");
6819 fprintf(file
, "???");
6824 switch (inst
->src
[i
].nr
) {
6826 fprintf(file
, "null");
6828 case BRW_ARF_ADDRESS
:
6829 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
6831 case BRW_ARF_ACCUMULATOR
:
6832 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
6835 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
6838 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
6844 if (inst
->src
[i
].offset
||
6845 (inst
->src
[i
].file
== VGRF
&&
6846 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
6847 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
6848 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
6849 inst
->src
[i
].offset
% reg_size
);
6852 if (inst
->src
[i
].abs
)
6855 if (inst
->src
[i
].file
!= IMM
) {
6857 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
6858 unsigned hstride
= inst
->src
[i
].hstride
;
6859 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
6861 stride
= inst
->src
[i
].stride
;
6864 fprintf(file
, "<%u>", stride
);
6866 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
6869 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
6870 fprintf(file
, ", ");
6875 if (inst
->force_writemask_all
)
6876 fprintf(file
, "NoMask ");
6878 if (inst
->exec_size
!= dispatch_width
)
6879 fprintf(file
, "group%d ", inst
->group
);
6881 fprintf(file
, "\n");
6885 fs_visitor::setup_fs_payload_gen6()
6887 assert(stage
== MESA_SHADER_FRAGMENT
);
6888 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
6889 const unsigned payload_width
= MIN2(16, dispatch_width
);
6890 assert(dispatch_width
% payload_width
== 0);
6891 assert(devinfo
->gen
>= 6);
6893 prog_data
->uses_src_depth
= prog_data
->uses_src_w
=
6894 (nir
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
)) != 0;
6896 prog_data
->uses_sample_mask
=
6897 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
6899 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
6901 * "MSDISPMODE_PERSAMPLE is required in order to select
6904 * So we can only really get sample positions if we are doing real
6905 * per-sample dispatch. If we need gl_SamplePosition and we don't have
6906 * persample dispatch, we hard-code it to 0.5.
6908 prog_data
->uses_pos_offset
= prog_data
->persample_dispatch
&&
6909 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
6911 /* R0: PS thread payload header. */
6914 for (unsigned j
= 0; j
< dispatch_width
/ payload_width
; j
++) {
6915 /* R1: masks, pixel X/Y coordinates. */
6916 payload
.subspan_coord_reg
[j
] = payload
.num_regs
++;
6919 for (unsigned j
= 0; j
< dispatch_width
/ payload_width
; j
++) {
6920 /* R3-26: barycentric interpolation coordinates. These appear in the
6921 * same order that they appear in the brw_barycentric_mode enum. Each
6922 * set of coordinates occupies 2 registers if dispatch width == 8 and 4
6923 * registers if dispatch width == 16. Coordinates only appear if they
6924 * were enabled using the "Barycentric Interpolation Mode" bits in
6927 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
6928 if (prog_data
->barycentric_interp_modes
& (1 << i
)) {
6929 payload
.barycentric_coord_reg
[i
][j
] = payload
.num_regs
;
6930 payload
.num_regs
+= payload_width
/ 4;
6934 /* R27-28: interpolated depth if uses source depth */
6935 if (prog_data
->uses_src_depth
) {
6936 payload
.source_depth_reg
[j
] = payload
.num_regs
;
6937 payload
.num_regs
+= payload_width
/ 8;
6940 /* R29-30: interpolated W set if GEN6_WM_USES_SOURCE_W. */
6941 if (prog_data
->uses_src_w
) {
6942 payload
.source_w_reg
[j
] = payload
.num_regs
;
6943 payload
.num_regs
+= payload_width
/ 8;
6946 /* R31: MSAA position offsets. */
6947 if (prog_data
->uses_pos_offset
) {
6948 payload
.sample_pos_reg
[j
] = payload
.num_regs
;
6952 /* R32-33: MSAA input coverage mask */
6953 if (prog_data
->uses_sample_mask
) {
6954 assert(devinfo
->gen
>= 7);
6955 payload
.sample_mask_in_reg
[j
] = payload
.num_regs
;
6956 payload
.num_regs
+= payload_width
/ 8;
6960 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6961 source_depth_to_render_target
= true;
6966 fs_visitor::setup_vs_payload()
6968 /* R0: thread header, R1: urb handles */
6969 payload
.num_regs
= 2;
6973 fs_visitor::setup_gs_payload()
6975 assert(stage
== MESA_SHADER_GEOMETRY
);
6977 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
6978 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
6980 /* R0: thread header, R1: output URB handles */
6981 payload
.num_regs
= 2;
6983 if (gs_prog_data
->include_primitive_id
) {
6984 /* R2: Primitive ID 0..7 */
6988 /* Always enable VUE handles so we can safely use pull model if needed.
6990 * The push model for a GS uses a ton of register space even for trivial
6991 * scenarios with just a few inputs, so just make things easier and a bit
6992 * safer by always having pull model available.
6994 gs_prog_data
->base
.include_vue_handles
= true;
6996 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
6997 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
6999 /* Use a maximum of 24 registers for push-model inputs. */
7000 const unsigned max_push_components
= 24;
7002 /* If pushing our inputs would take too many registers, reduce the URB read
7003 * length (which is in HWords, or 8 registers), and resort to pulling.
7005 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
7006 * have to multiply by VerticesIn to obtain the total storage requirement.
7008 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
7009 max_push_components
) {
7010 vue_prog_data
->urb_read_length
=
7011 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
7016 fs_visitor::setup_cs_payload()
7018 assert(devinfo
->gen
>= 7);
7019 payload
.num_regs
= 1;
7023 fs_visitor::calculate_register_pressure()
7025 invalidate_live_intervals();
7026 calculate_live_intervals();
7028 unsigned num_instructions
= 0;
7029 foreach_block(block
, cfg
)
7030 num_instructions
+= block
->instructions
.length();
7032 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
7034 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
7035 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
7036 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
7041 fs_visitor::optimize()
7043 /* Start by validating the shader we currently have. */
7046 /* bld is the common builder object pointing at the end of the program we
7047 * used to translate it into i965 IR. For the optimization and lowering
7048 * passes coming next, any code added after the end of the program without
7049 * having explicitly called fs_builder::at() clearly points at a mistake.
7050 * Ideally optimization passes wouldn't be part of the visitor so they
7051 * wouldn't have access to bld at all, but they do, so just in case some
7052 * pass forgets to ask for a location explicitly set it to NULL here to
7053 * make it trip. The dispatch width is initialized to a bogus value to
7054 * make sure that optimizations set the execution controls explicitly to
7055 * match the code they are manipulating instead of relying on the defaults.
7057 bld
= fs_builder(this, 64);
7059 assign_constant_locations();
7060 lower_constant_loads();
7064 split_virtual_grfs();
7067 #define OPT(pass, args...) ({ \
7069 bool this_progress = pass(args); \
7071 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
7072 char filename[64]; \
7073 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
7074 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
7076 backend_shader::dump_instructions(filename); \
7081 progress = progress || this_progress; \
7085 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
7087 snprintf(filename
, 64, "%s%d-%s-00-00-start",
7088 stage_abbrev
, dispatch_width
, nir
->info
.name
);
7090 backend_shader::dump_instructions(filename
);
7093 bool progress
= false;
7097 /* Before anything else, eliminate dead code. The results of some NIR
7098 * instructions may effectively be calculated twice. Once when the
7099 * instruction is encountered, and again when the user of that result is
7100 * encountered. Wipe those away before algebraic optimizations and
7101 * especially copy propagation can mix things up.
7103 OPT(dead_code_eliminate
);
7105 OPT(remove_extra_rounding_modes
);
7112 OPT(remove_duplicate_mrf_writes
);
7116 OPT(opt_copy_propagation
);
7117 OPT(opt_predicated_break
, this);
7118 OPT(opt_cmod_propagation
);
7119 OPT(dead_code_eliminate
);
7120 OPT(opt_peephole_sel
);
7121 OPT(dead_control_flow_eliminate
, this);
7122 OPT(opt_register_renaming
);
7123 OPT(opt_saturate_propagation
);
7124 OPT(register_coalesce
);
7125 OPT(compute_to_mrf
);
7126 OPT(eliminate_find_live_channel
);
7128 OPT(compact_virtual_grfs
);
7131 /* Do this after cmod propagation has had every possible opportunity to
7132 * propagate results into SEL instructions.
7134 if (OPT(opt_peephole_csel
))
7135 OPT(dead_code_eliminate
);
7140 if (OPT(lower_pack
)) {
7141 OPT(register_coalesce
);
7142 OPT(dead_code_eliminate
);
7145 OPT(lower_simd_width
);
7147 /* After SIMD lowering just in case we had to unroll the EOT send. */
7148 OPT(opt_sampler_eot
);
7150 OPT(lower_logical_sends
);
7153 OPT(opt_copy_propagation
);
7154 /* Only run after logical send lowering because it's easier to implement
7155 * in terms of physical sends.
7157 if (OPT(opt_zero_samples
))
7158 OPT(opt_copy_propagation
);
7159 /* Run after logical send lowering to give it a chance to CSE the
7160 * LOAD_PAYLOAD instructions created to construct the payloads of
7161 * e.g. texturing messages in cases where it wasn't possible to CSE the
7162 * whole logical instruction.
7165 OPT(register_coalesce
);
7166 OPT(compute_to_mrf
);
7167 OPT(dead_code_eliminate
);
7168 OPT(remove_duplicate_mrf_writes
);
7169 OPT(opt_peephole_sel
);
7172 OPT(opt_redundant_discard_jumps
);
7174 if (OPT(lower_load_payload
)) {
7175 split_virtual_grfs();
7176 OPT(register_coalesce
);
7177 OPT(lower_simd_width
);
7178 OPT(compute_to_mrf
);
7179 OPT(dead_code_eliminate
);
7182 OPT(opt_combine_constants
);
7183 OPT(lower_integer_multiplication
);
7185 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
7186 OPT(opt_cmod_propagation
);
7188 OPT(opt_copy_propagation
);
7189 OPT(dead_code_eliminate
);
7192 if (OPT(lower_regioning
)) {
7193 OPT(opt_copy_propagation
);
7194 OPT(dead_code_eliminate
);
7195 OPT(lower_simd_width
);
7198 OPT(fixup_sends_duplicate_payload
);
7200 lower_uniform_pull_constant_loads();
7206 * From the Skylake PRM Vol. 2a docs for sends:
7208 * "It is required that the second block of GRFs does not overlap with the
7211 * There are plenty of cases where we may accidentally violate this due to
7212 * having, for instance, both sources be the constant 0. This little pass
7213 * just adds a new vgrf for the second payload and copies it over.
7216 fs_visitor::fixup_sends_duplicate_payload()
7218 bool progress
= false;
7220 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
7221 if (inst
->opcode
== SHADER_OPCODE_SEND
&& inst
->ex_mlen
> 0 &&
7222 regions_overlap(inst
->src
[2], inst
->mlen
* REG_SIZE
,
7223 inst
->src
[3], inst
->ex_mlen
* REG_SIZE
)) {
7224 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(inst
->ex_mlen
),
7225 BRW_REGISTER_TYPE_UD
);
7226 /* Sadly, we've lost all notion of channels and bit sizes at this
7227 * point. Just WE_all it.
7229 const fs_builder ibld
= bld
.at(block
, inst
).exec_all().group(16, 0);
7230 fs_reg copy_src
= retype(inst
->src
[3], BRW_REGISTER_TYPE_UD
);
7231 fs_reg copy_dst
= tmp
;
7232 for (unsigned i
= 0; i
< inst
->ex_mlen
; i
+= 2) {
7233 if (inst
->ex_mlen
== i
+ 1) {
7234 /* Only one register left; do SIMD8 */
7235 ibld
.group(8, 0).MOV(copy_dst
, copy_src
);
7237 ibld
.MOV(copy_dst
, copy_src
);
7239 copy_src
= offset(copy_src
, ibld
, 1);
7240 copy_dst
= offset(copy_dst
, ibld
, 1);
7248 invalidate_live_intervals();
7254 * Three source instruction must have a GRF/MRF destination register.
7255 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
7258 fs_visitor::fixup_3src_null_dest()
7260 bool progress
= false;
7262 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
7263 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
7264 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
7271 invalidate_live_intervals();
7275 fs_visitor::allocate_registers(unsigned min_dispatch_width
, bool allow_spilling
)
7279 static const enum instruction_scheduler_mode pre_modes
[] = {
7281 SCHEDULE_PRE_NON_LIFO
,
7285 static const char *scheduler_mode_name
[] = {
7291 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
7293 /* Try each scheduling heuristic to see if it can successfully register
7294 * allocate without spilling. They should be ordered by decreasing
7295 * performance but increasing likelihood of allocating.
7297 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
7298 schedule_instructions(pre_modes
[i
]);
7299 this->shader_stats
.scheduler_mode
= scheduler_mode_name
[i
];
7302 assign_regs_trivial();
7307 /* We only allow spilling for the last schedule mode and only if the
7308 * allow_spilling parameter and dispatch width work out ok.
7310 bool can_spill
= allow_spilling
&&
7311 (i
== ARRAY_SIZE(pre_modes
) - 1) &&
7312 dispatch_width
== min_dispatch_width
;
7314 /* We should only spill registers on the last scheduling. */
7315 assert(!spilled_any_registers
);
7317 allocated
= assign_regs(can_spill
, spill_all
);
7323 if (!allow_spilling
)
7324 fail("Failure to register allocate and spilling is not allowed.");
7326 /* We assume that any spilling is worse than just dropping back to
7327 * SIMD8. There's probably actually some intermediate point where
7328 * SIMD16 with a couple of spills is still better.
7330 if (dispatch_width
> min_dispatch_width
) {
7331 fail("Failure to register allocate. Reduce number of "
7332 "live scalar values to avoid this.");
7335 /* If we failed to allocate, we must have a reason */
7337 } else if (spilled_any_registers
) {
7338 compiler
->shader_perf_log(log_data
,
7339 "%s shader triggered register spilling. "
7340 "Try reducing the number of live scalar "
7341 "values to improve performance.\n",
7345 /* This must come after all optimization and register allocation, since
7346 * it inserts dead code that happens to have side effects, and it does
7347 * so based on the actual physical registers in use.
7349 insert_gen4_send_dependency_workarounds();
7354 opt_bank_conflicts();
7356 schedule_instructions(SCHEDULE_POST
);
7358 if (last_scratch
> 0) {
7359 ASSERTED
unsigned max_scratch_size
= 2 * 1024 * 1024;
7361 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
7363 if (stage
== MESA_SHADER_COMPUTE
) {
7364 if (devinfo
->is_haswell
) {
7365 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
7366 * field documentation, Haswell supports a minimum of 2kB of
7367 * scratch space for compute shaders, unlike every other stage
7370 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
7371 } else if (devinfo
->gen
<= 7) {
7372 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
7373 * field documentation, platforms prior to Haswell measure scratch
7374 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
7376 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
7377 max_scratch_size
= 12 * 1024;
7381 /* We currently only support up to 2MB of scratch space. If we
7382 * need to support more eventually, the documentation suggests
7383 * that we could allocate a larger buffer, and partition it out
7384 * ourselves. We'd just have to undo the hardware's address
7385 * calculation by subtracting (FFTID * Per Thread Scratch Space)
7386 * and then add FFTID * (Larger Per Thread Scratch Space).
7388 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
7389 * Thread Group Tracking > Local Memory/Scratch Space.
7391 assert(prog_data
->total_scratch
< max_scratch_size
);
7396 fs_visitor::run_vs()
7398 assert(stage
== MESA_SHADER_VERTEX
);
7402 if (shader_time_index
>= 0)
7403 emit_shader_time_begin();
7412 if (shader_time_index
>= 0)
7413 emit_shader_time_end();
7419 assign_curb_setup();
7420 assign_vs_urb_setup();
7422 fixup_3src_null_dest();
7423 allocate_registers(8, true);
7429 fs_visitor::set_tcs_invocation_id()
7431 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
7432 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
7434 const unsigned instance_id_mask
=
7435 devinfo
->gen
>= 11 ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
7436 const unsigned instance_id_shift
=
7437 devinfo
->gen
>= 11 ? 16 : 17;
7439 /* Get instance number from g0.2 bits 22:16 or 23:17 */
7440 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7441 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
7442 brw_imm_ud(instance_id_mask
));
7444 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7446 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
) {
7447 /* gl_InvocationID is just the thread number */
7448 bld
.SHR(invocation_id
, t
, brw_imm_ud(instance_id_shift
));
7452 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
);
7454 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
7455 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7456 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
7457 bld
.MOV(channels_ud
, channels_uw
);
7459 if (tcs_prog_data
->instances
== 1) {
7460 invocation_id
= channels_ud
;
7462 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7463 bld
.SHR(instance_times_8
, t
, brw_imm_ud(instance_id_shift
- 3));
7464 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
7469 fs_visitor::run_tcs()
7471 assert(stage
== MESA_SHADER_TESS_CTRL
);
7473 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
7474 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
7475 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
7477 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
||
7478 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
7480 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
7481 /* r1-r4 contain the ICP handles. */
7482 payload
.num_regs
= 5;
7484 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
7485 assert(tcs_key
->input_vertices
> 0);
7486 /* r1 contains output handles, r2 may contain primitive ID, then the
7487 * ICP handles occupy the next 1-32 registers.
7489 payload
.num_regs
= 2 + tcs_prog_data
->include_primitive_id
+
7490 tcs_key
->input_vertices
;
7493 if (shader_time_index
>= 0)
7494 emit_shader_time_begin();
7496 /* Initialize gl_InvocationID */
7497 set_tcs_invocation_id();
7499 const bool fix_dispatch_mask
=
7500 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
&&
7501 (nir
->info
.tess
.tcs_vertices_out
% 8) != 0;
7503 /* Fix the disptach mask */
7504 if (fix_dispatch_mask
) {
7505 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
7506 brw_imm_ud(nir
->info
.tess
.tcs_vertices_out
), BRW_CONDITIONAL_L
);
7507 bld
.IF(BRW_PREDICATE_NORMAL
);
7512 if (fix_dispatch_mask
) {
7513 bld
.emit(BRW_OPCODE_ENDIF
);
7516 /* Emit EOT write; set TR DS Cache bit */
7518 fs_reg(get_tcs_output_urb_handle()),
7519 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
7520 fs_reg(brw_imm_ud(0)),
7522 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
7523 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
7525 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
7526 bld
.null_reg_ud(), payload
);
7530 if (shader_time_index
>= 0)
7531 emit_shader_time_end();
7540 assign_curb_setup();
7541 assign_tcs_urb_setup();
7543 fixup_3src_null_dest();
7544 allocate_registers(8, true);
7550 fs_visitor::run_tes()
7552 assert(stage
== MESA_SHADER_TESS_EVAL
);
7554 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
7555 payload
.num_regs
= 5;
7557 if (shader_time_index
>= 0)
7558 emit_shader_time_begin();
7567 if (shader_time_index
>= 0)
7568 emit_shader_time_end();
7574 assign_curb_setup();
7575 assign_tes_urb_setup();
7577 fixup_3src_null_dest();
7578 allocate_registers(8, true);
7584 fs_visitor::run_gs()
7586 assert(stage
== MESA_SHADER_GEOMETRY
);
7590 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
7592 if (gs_compile
->control_data_header_size_bits
> 0) {
7593 /* Create a VGRF to store accumulated control data bits. */
7594 this->control_data_bits
= vgrf(glsl_type::uint_type
);
7596 /* If we're outputting more than 32 control data bits, then EmitVertex()
7597 * will set control_data_bits to 0 after emitting the first vertex.
7598 * Otherwise, we need to initialize it to 0 here.
7600 if (gs_compile
->control_data_header_size_bits
<= 32) {
7601 const fs_builder abld
= bld
.annotate("initialize control data bits");
7602 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
7606 if (shader_time_index
>= 0)
7607 emit_shader_time_begin();
7611 emit_gs_thread_end();
7613 if (shader_time_index
>= 0)
7614 emit_shader_time_end();
7623 assign_curb_setup();
7624 assign_gs_urb_setup();
7626 fixup_3src_null_dest();
7627 allocate_registers(8, true);
7632 /* From the SKL PRM, Volume 16, Workarounds:
7634 * 0877 3D Pixel Shader Hang possible when pixel shader dispatched with
7635 * only header phases (R0-R2)
7637 * WA: Enable a non-header phase (e.g. push constant) when dispatch would
7638 * have been header only.
7640 * Instead of enabling push constants one can alternatively enable one of the
7641 * inputs. Here one simply chooses "layer" which shouldn't impose much
7645 gen9_ps_header_only_workaround(struct brw_wm_prog_data
*wm_prog_data
)
7647 if (wm_prog_data
->num_varying_inputs
)
7650 if (wm_prog_data
->base
.curb_read_length
)
7653 wm_prog_data
->urb_setup
[VARYING_SLOT_LAYER
] = 0;
7654 wm_prog_data
->num_varying_inputs
= 1;
7658 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
7660 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
7661 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
7663 assert(stage
== MESA_SHADER_FRAGMENT
);
7665 if (devinfo
->gen
>= 6)
7666 setup_fs_payload_gen6();
7668 setup_fs_payload_gen4();
7672 } else if (do_rep_send
) {
7673 assert(dispatch_width
== 16);
7674 emit_repclear_shader();
7676 if (shader_time_index
>= 0)
7677 emit_shader_time_begin();
7679 if (nir
->info
.inputs_read
> 0 ||
7680 (nir
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
)) ||
7681 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
7682 if (devinfo
->gen
< 6)
7683 emit_interpolation_setup_gen4();
7685 emit_interpolation_setup_gen6();
7688 /* We handle discards by keeping track of the still-live pixels in f0.1.
7689 * Initialize it with the dispatched pixels.
7691 if (wm_prog_data
->uses_kill
) {
7692 const fs_reg dispatch_mask
=
7693 devinfo
->gen
>= 6 ? brw_vec1_grf(1, 7) : brw_vec1_grf(0, 0);
7694 bld
.exec_all().group(1, 0)
7695 .MOV(retype(brw_flag_reg(0, 1), BRW_REGISTER_TYPE_UW
),
7696 retype(dispatch_mask
, BRW_REGISTER_TYPE_UW
));
7704 if (wm_prog_data
->uses_kill
)
7705 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
7707 if (wm_key
->alpha_test_func
)
7712 if (shader_time_index
>= 0)
7713 emit_shader_time_end();
7719 assign_curb_setup();
7721 if (devinfo
->gen
>= 9)
7722 gen9_ps_header_only_workaround(wm_prog_data
);
7726 fixup_3src_null_dest();
7727 allocate_registers(8, allow_spilling
);
7737 fs_visitor::run_cs(unsigned min_dispatch_width
)
7739 assert(stage
== MESA_SHADER_COMPUTE
);
7740 assert(dispatch_width
>= min_dispatch_width
);
7744 if (shader_time_index
>= 0)
7745 emit_shader_time_begin();
7747 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
7748 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
7749 const fs_builder abld
= bld
.exec_all().group(1, 0);
7750 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
7751 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
7759 emit_cs_terminate();
7761 if (shader_time_index
>= 0)
7762 emit_shader_time_end();
7768 assign_curb_setup();
7770 fixup_3src_null_dest();
7771 allocate_registers(min_dispatch_width
, true);
7780 is_used_in_not_interp_frag_coord(nir_ssa_def
*def
)
7782 nir_foreach_use(src
, def
) {
7783 if (src
->parent_instr
->type
!= nir_instr_type_intrinsic
)
7786 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(src
->parent_instr
);
7787 if (intrin
->intrinsic
!= nir_intrinsic_load_frag_coord
)
7791 nir_foreach_if_use(src
, def
)
7798 * Return a bitfield where bit n is set if barycentric interpolation mode n
7799 * (see enum brw_barycentric_mode) is needed by the fragment shader.
7801 * We examine the load_barycentric intrinsics rather than looking at input
7802 * variables so that we catch interpolateAtCentroid() messages too, which
7803 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
7806 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
7807 const nir_shader
*shader
)
7809 unsigned barycentric_interp_modes
= 0;
7811 nir_foreach_function(f
, shader
) {
7815 nir_foreach_block(block
, f
->impl
) {
7816 nir_foreach_instr(instr
, block
) {
7817 if (instr
->type
!= nir_instr_type_intrinsic
)
7820 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
7821 switch (intrin
->intrinsic
) {
7822 case nir_intrinsic_load_barycentric_pixel
:
7823 case nir_intrinsic_load_barycentric_centroid
:
7824 case nir_intrinsic_load_barycentric_sample
:
7830 /* Ignore WPOS; it doesn't require interpolation. */
7831 assert(intrin
->dest
.is_ssa
);
7832 if (!is_used_in_not_interp_frag_coord(&intrin
->dest
.ssa
))
7835 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
7836 nir_intrinsic_interp_mode(intrin
);
7837 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
7838 enum brw_barycentric_mode bary
=
7839 brw_barycentric_mode(interp
, bary_op
);
7841 barycentric_interp_modes
|= 1 << bary
;
7843 if (devinfo
->needs_unlit_centroid_workaround
&&
7844 bary_op
== nir_intrinsic_load_barycentric_centroid
)
7845 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
7850 return barycentric_interp_modes
;
7854 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
7855 const nir_shader
*shader
)
7857 prog_data
->flat_inputs
= 0;
7859 nir_foreach_variable(var
, &shader
->inputs
) {
7860 unsigned slots
= glsl_count_attribute_slots(var
->type
, false);
7861 for (unsigned s
= 0; s
< slots
; s
++) {
7862 int input_index
= prog_data
->urb_setup
[var
->data
.location
+ s
];
7864 if (input_index
< 0)
7868 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
7869 prog_data
->flat_inputs
|= 1 << input_index
;
7875 computed_depth_mode(const nir_shader
*shader
)
7877 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
7878 switch (shader
->info
.fs
.depth_layout
) {
7879 case FRAG_DEPTH_LAYOUT_NONE
:
7880 case FRAG_DEPTH_LAYOUT_ANY
:
7881 return BRW_PSCDEPTH_ON
;
7882 case FRAG_DEPTH_LAYOUT_GREATER
:
7883 return BRW_PSCDEPTH_ON_GE
;
7884 case FRAG_DEPTH_LAYOUT_LESS
:
7885 return BRW_PSCDEPTH_ON_LE
;
7886 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
7887 return BRW_PSCDEPTH_OFF
;
7890 return BRW_PSCDEPTH_OFF
;
7894 * Move load_interpolated_input with simple (payload-based) barycentric modes
7895 * to the top of the program so we don't emit multiple PLNs for the same input.
7897 * This works around CSE not being able to handle non-dominating cases
7903 * interpolate the same exact input
7906 * This should be replaced by global value numbering someday.
7909 move_interpolation_to_top(nir_shader
*nir
)
7911 bool progress
= false;
7913 nir_foreach_function(f
, nir
) {
7917 nir_block
*top
= nir_start_block(f
->impl
);
7918 exec_node
*cursor_node
= NULL
;
7920 nir_foreach_block(block
, f
->impl
) {
7924 nir_foreach_instr_safe(instr
, block
) {
7925 if (instr
->type
!= nir_instr_type_intrinsic
)
7928 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
7929 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
7931 nir_intrinsic_instr
*bary_intrinsic
=
7932 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
7933 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
7935 /* Leave interpolateAtSample/Offset() where they are. */
7936 if (op
== nir_intrinsic_load_barycentric_at_sample
||
7937 op
== nir_intrinsic_load_barycentric_at_offset
)
7940 nir_instr
*move
[3] = {
7941 &bary_intrinsic
->instr
,
7942 intrin
->src
[1].ssa
->parent_instr
,
7946 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
7947 if (move
[i
]->block
!= top
) {
7948 move
[i
]->block
= top
;
7949 exec_node_remove(&move
[i
]->node
);
7951 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
7953 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
7955 cursor_node
= &move
[i
]->node
;
7961 nir_metadata_preserve(f
->impl
, (nir_metadata
)
7962 ((unsigned) nir_metadata_block_index
|
7963 (unsigned) nir_metadata_dominance
));
7970 * Demote per-sample barycentric intrinsics to centroid.
7972 * Useful when rendering to a non-multisampled buffer.
7975 demote_sample_qualifiers(nir_shader
*nir
)
7977 bool progress
= true;
7979 nir_foreach_function(f
, nir
) {
7984 nir_builder_init(&b
, f
->impl
);
7986 nir_foreach_block(block
, f
->impl
) {
7987 nir_foreach_instr_safe(instr
, block
) {
7988 if (instr
->type
!= nir_instr_type_intrinsic
)
7991 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
7992 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
7993 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
7996 b
.cursor
= nir_before_instr(instr
);
7997 nir_ssa_def
*centroid
=
7998 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
7999 nir_intrinsic_interp_mode(intrin
));
8000 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
8001 nir_src_for_ssa(centroid
));
8002 nir_instr_remove(instr
);
8007 nir_metadata_preserve(f
->impl
, (nir_metadata
)
8008 ((unsigned) nir_metadata_block_index
|
8009 (unsigned) nir_metadata_dominance
));
8016 * Pre-gen6, the register file of the EUs was shared between threads,
8017 * and each thread used some subset allocated on a 16-register block
8018 * granularity. The unit states wanted these block counts.
8021 brw_register_blocks(int reg_count
)
8023 return ALIGN(reg_count
, 16) / 16 - 1;
8027 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
8029 const struct brw_wm_prog_key
*key
,
8030 struct brw_wm_prog_data
*prog_data
,
8032 struct gl_program
*prog
,
8033 int shader_time_index8
, int shader_time_index16
,
8034 int shader_time_index32
, bool allow_spilling
,
8035 bool use_rep_send
, struct brw_vue_map
*vue_map
,
8038 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
8040 unsigned max_subgroup_size
= unlikely(INTEL_DEBUG
& DEBUG_DO32
) ? 32 : 16;
8042 brw_nir_apply_key(shader
, compiler
, &key
->base
, max_subgroup_size
, true);
8043 brw_nir_lower_fs_inputs(shader
, devinfo
, key
);
8044 brw_nir_lower_fs_outputs(shader
);
8046 if (devinfo
->gen
< 6)
8047 brw_setup_vue_interpolation(vue_map
, shader
, prog_data
);
8049 if (!key
->multisample_fbo
)
8050 NIR_PASS_V(shader
, demote_sample_qualifiers
);
8051 NIR_PASS_V(shader
, move_interpolation_to_top
);
8052 brw_postprocess_nir(shader
, compiler
, true);
8054 /* key->alpha_test_func means simulating alpha testing via discards,
8055 * so the shader definitely kills pixels.
8057 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
||
8058 key
->alpha_test_func
;
8059 prog_data
->uses_omask
= key
->multisample_fbo
&&
8060 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
8061 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
8062 prog_data
->computed_stencil
=
8063 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
8065 prog_data
->persample_dispatch
=
8066 key
->multisample_fbo
&&
8067 (key
->persample_interp
||
8068 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
8069 SYSTEM_BIT_SAMPLE_POS
)) ||
8070 shader
->info
.fs
.uses_sample_qualifier
||
8071 shader
->info
.outputs_read
);
8073 prog_data
->has_render_target_reads
= shader
->info
.outputs_read
!= 0ull;
8075 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
8076 prog_data
->post_depth_coverage
= shader
->info
.fs
.post_depth_coverage
;
8077 prog_data
->inner_coverage
= shader
->info
.fs
.inner_coverage
;
8079 prog_data
->barycentric_interp_modes
=
8080 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
8082 calculate_urb_setup(devinfo
, key
, prog_data
, shader
);
8083 brw_compute_flat_inputs(prog_data
, shader
);
8085 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
, *simd32_cfg
= NULL
;
8087 fs_visitor
v8(compiler
, log_data
, mem_ctx
, &key
->base
,
8088 &prog_data
->base
, prog
, shader
, 8,
8089 shader_time_index8
);
8090 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
8092 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
8095 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
8097 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
8098 prog_data
->reg_blocks_8
= brw_register_blocks(v8
.grf_used
);
8101 if (v8
.max_dispatch_width
>= 16 &&
8102 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
8103 /* Try a SIMD16 compile */
8104 fs_visitor
v16(compiler
, log_data
, mem_ctx
, &key
->base
,
8105 &prog_data
->base
, prog
, shader
, 16,
8106 shader_time_index16
);
8107 v16
.import_uniforms(&v8
);
8108 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
8109 compiler
->shader_perf_log(log_data
,
8110 "SIMD16 shader failed to compile: %s",
8113 simd16_cfg
= v16
.cfg
;
8114 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
8115 prog_data
->reg_blocks_16
= brw_register_blocks(v16
.grf_used
);
8119 /* Currently, the compiler only supports SIMD32 on SNB+ */
8120 if (v8
.max_dispatch_width
>= 32 && !use_rep_send
&&
8121 compiler
->devinfo
->gen
>= 6 &&
8122 unlikely(INTEL_DEBUG
& DEBUG_DO32
)) {
8123 /* Try a SIMD32 compile */
8124 fs_visitor
v32(compiler
, log_data
, mem_ctx
, &key
->base
,
8125 &prog_data
->base
, prog
, shader
, 32,
8126 shader_time_index32
);
8127 v32
.import_uniforms(&v8
);
8128 if (!v32
.run_fs(allow_spilling
, false)) {
8129 compiler
->shader_perf_log(log_data
,
8130 "SIMD32 shader failed to compile: %s",
8133 simd32_cfg
= v32
.cfg
;
8134 prog_data
->dispatch_grf_start_reg_32
= v32
.payload
.num_regs
;
8135 prog_data
->reg_blocks_32
= brw_register_blocks(v32
.grf_used
);
8139 /* When the caller requests a repclear shader, they want SIMD16-only */
8143 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
8144 * at the top to select the shader. We've never implemented that.
8145 * Instead, we just give them exactly one shader and we pick the widest one
8148 if (compiler
->devinfo
->gen
< 5) {
8149 if (simd32_cfg
|| simd16_cfg
)
8155 /* If computed depth is enabled SNB only allows SIMD8. */
8156 if (compiler
->devinfo
->gen
== 6 &&
8157 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
)
8158 assert(simd16_cfg
== NULL
&& simd32_cfg
== NULL
);
8160 if (compiler
->devinfo
->gen
<= 5 && !simd8_cfg
) {
8161 /* Iron lake and earlier only have one Dispatch GRF start field. Make
8162 * the data available in the base prog data struct for convenience.
8165 prog_data
->base
.dispatch_grf_start_reg
=
8166 prog_data
->dispatch_grf_start_reg_16
;
8167 } else if (simd32_cfg
) {
8168 prog_data
->base
.dispatch_grf_start_reg
=
8169 prog_data
->dispatch_grf_start_reg_32
;
8173 if (prog_data
->persample_dispatch
) {
8174 /* Starting with SandyBridge (where we first get MSAA), the different
8175 * pixel dispatch combinations are grouped into classifications A
8176 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
8177 * generations, the only configurations supporting persample dispatch
8178 * are are this in which only one dispatch width is enabled.
8180 if (simd32_cfg
|| simd16_cfg
)
8186 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
8187 v8
.shader_stats
, v8
.runtime_check_aads_emit
,
8188 MESA_SHADER_FRAGMENT
);
8190 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
8191 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
8192 shader
->info
.label
?
8193 shader
->info
.label
: "unnamed",
8194 shader
->info
.name
));
8198 prog_data
->dispatch_8
= true;
8199 g
.generate_code(simd8_cfg
, 8);
8203 prog_data
->dispatch_16
= true;
8204 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
8208 prog_data
->dispatch_32
= true;
8209 prog_data
->prog_offset_32
= g
.generate_code(simd32_cfg
, 32);
8212 return g
.get_assembly();
8216 fs_visitor::emit_cs_work_group_id_setup()
8218 assert(stage
== MESA_SHADER_COMPUTE
);
8220 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
8222 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
8223 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
8224 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
8226 bld
.MOV(*reg
, r0_1
);
8227 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
8228 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
8234 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
8236 block
->dwords
= dwords
;
8237 block
->regs
= DIV_ROUND_UP(dwords
, 8);
8238 block
->size
= block
->regs
* 32;
8242 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
8243 struct brw_cs_prog_data
*cs_prog_data
)
8245 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
8246 int subgroup_id_index
= get_subgroup_id_param_index(prog_data
);
8247 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
8249 /* The thread ID should be stored in the last param dword */
8250 assert(subgroup_id_index
== -1 ||
8251 subgroup_id_index
== (int)prog_data
->nr_params
- 1);
8253 unsigned cross_thread_dwords
, per_thread_dwords
;
8254 if (!cross_thread_supported
) {
8255 cross_thread_dwords
= 0u;
8256 per_thread_dwords
= prog_data
->nr_params
;
8257 } else if (subgroup_id_index
>= 0) {
8258 /* Fill all but the last register with cross-thread payload */
8259 cross_thread_dwords
= 8 * (subgroup_id_index
/ 8);
8260 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
8261 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
8263 /* Fill all data using cross-thread payload */
8264 cross_thread_dwords
= prog_data
->nr_params
;
8265 per_thread_dwords
= 0u;
8268 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
8269 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
8271 unsigned total_dwords
=
8272 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
8273 cs_prog_data
->push
.cross_thread
.size
) / 4;
8274 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
8276 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
8277 cs_prog_data
->push
.per_thread
.size
== 0);
8278 assert(cs_prog_data
->push
.cross_thread
.dwords
+
8279 cs_prog_data
->push
.per_thread
.dwords
==
8280 prog_data
->nr_params
);
8284 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
8286 cs_prog_data
->simd_size
= size
;
8287 unsigned group_size
= cs_prog_data
->local_size
[0] *
8288 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
8289 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
8293 compile_cs_to_nir(const struct brw_compiler
*compiler
,
8295 const struct brw_cs_prog_key
*key
,
8296 const nir_shader
*src_shader
,
8297 unsigned dispatch_width
)
8299 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
8300 brw_nir_apply_key(shader
, compiler
, &key
->base
, dispatch_width
, true);
8302 NIR_PASS_V(shader
, brw_nir_lower_cs_intrinsics
, dispatch_width
);
8304 /* Clean up after the local index and ID calculations. */
8305 NIR_PASS_V(shader
, nir_opt_constant_folding
);
8306 NIR_PASS_V(shader
, nir_opt_dce
);
8308 brw_postprocess_nir(shader
, compiler
, true);
8314 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
8316 const struct brw_cs_prog_key
*key
,
8317 struct brw_cs_prog_data
*prog_data
,
8318 const nir_shader
*src_shader
,
8319 int shader_time_index
,
8322 prog_data
->base
.total_shared
= src_shader
->info
.cs
.shared_size
;
8323 prog_data
->local_size
[0] = src_shader
->info
.cs
.local_size
[0];
8324 prog_data
->local_size
[1] = src_shader
->info
.cs
.local_size
[1];
8325 prog_data
->local_size
[2] = src_shader
->info
.cs
.local_size
[2];
8326 unsigned local_workgroup_size
=
8327 src_shader
->info
.cs
.local_size
[0] * src_shader
->info
.cs
.local_size
[1] *
8328 src_shader
->info
.cs
.local_size
[2];
8330 unsigned min_dispatch_width
=
8331 DIV_ROUND_UP(local_workgroup_size
, compiler
->devinfo
->max_cs_threads
);
8332 min_dispatch_width
= MAX2(8, min_dispatch_width
);
8333 min_dispatch_width
= util_next_power_of_two(min_dispatch_width
);
8334 assert(min_dispatch_width
<= 32);
8335 unsigned max_dispatch_width
= 32;
8337 fs_visitor
*v8
= NULL
, *v16
= NULL
, *v32
= NULL
;
8338 fs_visitor
*v
= NULL
;
8339 const char *fail_msg
= NULL
;
8341 if ((int)key
->base
.subgroup_size_type
>= (int)BRW_SUBGROUP_SIZE_REQUIRE_8
) {
8342 /* These enum values are expressly chosen to be equal to the subgroup
8343 * size that they require.
8345 const unsigned required_dispatch_width
=
8346 (unsigned)key
->base
.subgroup_size_type
;
8347 assert(required_dispatch_width
== 8 ||
8348 required_dispatch_width
== 16 ||
8349 required_dispatch_width
== 32);
8350 if (required_dispatch_width
< min_dispatch_width
||
8351 required_dispatch_width
> max_dispatch_width
) {
8352 fail_msg
= "Cannot satisfy explicit subgroup size";
8354 min_dispatch_width
= max_dispatch_width
= required_dispatch_width
;
8358 /* Now the main event: Visit the shader IR and generate our CS IR for it.
8360 if (!fail_msg
&& min_dispatch_width
<= 8 && max_dispatch_width
>= 8) {
8361 nir_shader
*nir8
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8363 v8
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8365 NULL
, /* Never used in core profile */
8366 nir8
, 8, shader_time_index
);
8367 if (!v8
->run_cs(min_dispatch_width
)) {
8368 fail_msg
= v8
->fail_msg
;
8370 /* We should always be able to do SIMD32 for compute shaders */
8371 assert(v8
->max_dispatch_width
>= 32);
8374 cs_set_simd_size(prog_data
, 8);
8375 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
8379 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
8380 !fail_msg
&& min_dispatch_width
<= 16 && max_dispatch_width
>= 16) {
8381 /* Try a SIMD16 compile */
8382 nir_shader
*nir16
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8384 v16
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8386 NULL
, /* Never used in core profile */
8387 nir16
, 16, shader_time_index
);
8389 v16
->import_uniforms(v8
);
8391 if (!v16
->run_cs(min_dispatch_width
)) {
8392 compiler
->shader_perf_log(log_data
,
8393 "SIMD16 shader failed to compile: %s",
8397 "Couldn't generate SIMD16 program and not "
8398 "enough threads for SIMD8";
8401 /* We should always be able to do SIMD32 for compute shaders */
8402 assert(v16
->max_dispatch_width
>= 32);
8405 cs_set_simd_size(prog_data
, 16);
8406 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
8410 /* We should always be able to do SIMD32 for compute shaders */
8411 assert(!v16
|| v16
->max_dispatch_width
>= 32);
8413 if (!fail_msg
&& (min_dispatch_width
> 16 || (INTEL_DEBUG
& DEBUG_DO32
)) &&
8414 max_dispatch_width
>= 32) {
8415 /* Try a SIMD32 compile */
8416 nir_shader
*nir32
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8418 v32
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8420 NULL
, /* Never used in core profile */
8421 nir32
, 32, shader_time_index
);
8423 v32
->import_uniforms(v8
);
8425 v32
->import_uniforms(v16
);
8427 if (!v32
->run_cs(min_dispatch_width
)) {
8428 compiler
->shader_perf_log(log_data
,
8429 "SIMD32 shader failed to compile: %s",
8433 "Couldn't generate SIMD32 program and not "
8434 "enough threads for SIMD16";
8438 cs_set_simd_size(prog_data
, 32);
8439 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
8443 const unsigned *ret
= NULL
;
8444 if (unlikely(v
== NULL
)) {
8447 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
8449 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
8450 v
->shader_stats
, v
->runtime_check_aads_emit
,
8451 MESA_SHADER_COMPUTE
);
8452 if (INTEL_DEBUG
& DEBUG_CS
) {
8453 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
8454 src_shader
->info
.label
?
8455 src_shader
->info
.label
: "unnamed",
8456 src_shader
->info
.name
);
8457 g
.enable_debug(name
);
8460 g
.generate_code(v
->cfg
, prog_data
->simd_size
);
8462 ret
= g
.get_assembly();
8473 * Test the dispatch mask packing assumptions of
8474 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
8475 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
8476 * executed with an unexpected dispatch mask.
8479 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
8481 const gl_shader_stage stage
= bld
.shader
->stage
;
8483 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
8484 bld
.shader
->stage_prog_data
)) {
8485 const fs_builder ubld
= bld
.exec_all().group(1, 0);
8486 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
8487 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
8490 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
8491 ubld
.AND(tmp
, mask
, tmp
);
8493 /* This will loop forever if the dispatch mask doesn't have the expected
8494 * form '2^n-1', in which case tmp will be non-zero.
8496 bld
.emit(BRW_OPCODE_DO
);
8497 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
8498 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));