2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
35 #include "brw_vec4_gs_visitor.h"
37 #include "brw_dead_control_flow.h"
38 #include "common/gen_debug.h"
39 #include "compiler/glsl_types.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "program/prog_parameter.h"
45 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
49 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
50 const fs_reg
*src
, unsigned sources
)
52 memset(this, 0, sizeof(*this));
54 this->src
= new fs_reg
[MAX2(sources
, 3)];
55 for (unsigned i
= 0; i
< sources
; i
++)
56 this->src
[i
] = src
[i
];
58 this->opcode
= opcode
;
60 this->sources
= sources
;
61 this->exec_size
= exec_size
;
64 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
66 assert(this->exec_size
!= 0);
68 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
70 /* This will be the case for almost all instructions. */
77 this->size_written
= dst
.component_size(exec_size
);
80 this->size_written
= 0;
84 unreachable("Invalid destination register file");
87 this->writes_accumulator
= false;
92 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
95 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
97 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
100 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
102 init(opcode
, exec_size
, dst
, NULL
, 0);
105 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
108 const fs_reg src
[1] = { src0
};
109 init(opcode
, exec_size
, dst
, src
, 1);
112 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
113 const fs_reg
&src0
, const fs_reg
&src1
)
115 const fs_reg src
[2] = { src0
, src1
};
116 init(opcode
, exec_size
, dst
, src
, 2);
119 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
120 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
122 const fs_reg src
[3] = { src0
, src1
, src2
};
123 init(opcode
, exec_size
, dst
, src
, 3);
126 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
127 const fs_reg src
[], unsigned sources
)
129 init(opcode
, exec_width
, dst
, src
, sources
);
132 fs_inst::fs_inst(const fs_inst
&that
)
134 memcpy(this, &that
, sizeof(that
));
136 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
138 for (unsigned i
= 0; i
< that
.sources
; i
++)
139 this->src
[i
] = that
.src
[i
];
148 fs_inst::resize_sources(uint8_t num_sources
)
150 if (this->sources
!= num_sources
) {
151 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
153 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
154 src
[i
] = this->src
[i
];
158 this->sources
= num_sources
;
163 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
165 const fs_reg
&surf_index
,
166 const fs_reg
&varying_offset
,
167 uint32_t const_offset
)
169 /* We have our constant surface use a pitch of 4 bytes, so our index can
170 * be any component of a vector, and then we load 4 contiguous
171 * components starting from that.
173 * We break down the const_offset to a portion added to the variable offset
174 * and a portion done using fs_reg::offset, which means that if you have
175 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
176 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
177 * later notice that those loads are all the same and eliminate the
180 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
181 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
183 /* The pull load message will load a vec4 (16 bytes). If we are loading
184 * a double this means we are only loading 2 elements worth of data.
185 * We also want to use a 32-bit data type for the dst of the load operation
186 * so other parts of the driver don't get confused about the size of the
189 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
190 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
191 vec4_result
, surf_index
, vec4_offset
);
192 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
194 shuffle_from_32bit_read(bld
, dst
, vec4_result
,
195 (const_offset
& 0xf) / type_sz(dst
.type
), 1);
199 * A helper for MOV generation for fixing up broken hardware SEND dependency
203 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
205 /* The caller always wants uncompressed to emit the minimal extra
206 * dependencies, and to avoid having to deal with aligning its regs to 2.
208 const fs_builder ubld
= bld
.annotate("send dependency resolve")
211 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
215 fs_inst::equals(fs_inst
*inst
) const
217 return (opcode
== inst
->opcode
&&
218 dst
.equals(inst
->dst
) &&
219 src
[0].equals(inst
->src
[0]) &&
220 src
[1].equals(inst
->src
[1]) &&
221 src
[2].equals(inst
->src
[2]) &&
222 saturate
== inst
->saturate
&&
223 predicate
== inst
->predicate
&&
224 conditional_mod
== inst
->conditional_mod
&&
225 mlen
== inst
->mlen
&&
226 base_mrf
== inst
->base_mrf
&&
227 target
== inst
->target
&&
229 header_size
== inst
->header_size
&&
230 shadow_compare
== inst
->shadow_compare
&&
231 exec_size
== inst
->exec_size
&&
232 offset
== inst
->offset
);
236 fs_inst::is_send_from_grf() const
239 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
240 case SHADER_OPCODE_SHADER_TIME_ADD
:
241 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
242 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
243 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
244 case SHADER_OPCODE_UNTYPED_ATOMIC
:
245 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
246 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
247 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
248 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
249 case SHADER_OPCODE_TYPED_ATOMIC
:
250 case SHADER_OPCODE_TYPED_SURFACE_READ
:
251 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
252 case SHADER_OPCODE_URB_WRITE_SIMD8
:
253 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
254 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
255 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
256 case SHADER_OPCODE_URB_READ_SIMD8
:
257 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
259 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
260 return src
[1].file
== VGRF
;
261 case FS_OPCODE_FB_WRITE
:
262 case FS_OPCODE_FB_READ
:
263 return src
[0].file
== VGRF
;
266 return src
[0].file
== VGRF
;
273 * Returns true if this instruction's sources and destinations cannot
274 * safely be the same register.
276 * In most cases, a register can be written over safely by the same
277 * instruction that is its last use. For a single instruction, the
278 * sources are dereferenced before writing of the destination starts
281 * However, there are a few cases where this can be problematic:
283 * - Virtual opcodes that translate to multiple instructions in the
284 * code generator: if src == dst and one instruction writes the
285 * destination before a later instruction reads the source, then
286 * src will have been clobbered.
288 * - SIMD16 compressed instructions with certain regioning (see below).
290 * The register allocator uses this information to set up conflicts between
291 * GRF sources and the destination.
294 fs_inst::has_source_and_destination_hazard() const
297 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
298 /* Multiple partial writes to the destination */
300 case SHADER_OPCODE_SHUFFLE
:
301 /* This instruction returns an arbitrary channel from the source and
302 * gets split into smaller instructions in the generator. It's possible
303 * that one of the instructions will read from a channel corresponding
304 * to an earlier instruction.
306 case SHADER_OPCODE_SEL_EXEC
:
307 /* This is implemented as
309 * mov(16) g4<1>D 0D { align1 WE_all 1H };
310 * mov(16) g4<1>D g5<8,8,1>D { align1 1H }
312 * Because the source is only read in the second instruction, the first
313 * may stomp all over it.
317 /* The SIMD16 compressed instruction
319 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
321 * is actually decoded in hardware as:
323 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
324 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
326 * Which is safe. However, if we have uniform accesses
327 * happening, we get into trouble:
329 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
330 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
332 * Now our destination for the first instruction overwrote the
333 * second instruction's src0, and we get garbage for those 8
334 * pixels. There's a similar issue for the pre-gen6
335 * pixel_x/pixel_y, which are registers of 16-bit values and thus
336 * would get stomped by the first decode as well.
338 if (exec_size
== 16) {
339 for (int i
= 0; i
< sources
; i
++) {
340 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
341 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
342 src
[i
].type
== BRW_REGISTER_TYPE_W
||
343 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
344 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
354 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
356 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
359 fs_reg reg
= this->src
[0];
360 if (reg
.file
!= VGRF
|| reg
.offset
!= 0 || reg
.stride
!= 1)
363 if (grf_alloc
.sizes
[reg
.nr
] * REG_SIZE
!= this->size_written
)
366 for (int i
= 0; i
< this->sources
; i
++) {
367 reg
.type
= this->src
[i
].type
;
368 if (!this->src
[i
].equals(reg
))
371 if (i
< this->header_size
) {
372 reg
.offset
+= REG_SIZE
;
374 reg
= horiz_offset(reg
, this->exec_size
);
382 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
)
384 if (devinfo
->gen
== 6 && is_math())
387 if (is_send_from_grf())
390 if (!backend_instruction::can_do_source_mods())
397 fs_inst::can_change_types() const
399 return dst
.type
== src
[0].type
&&
400 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
401 (opcode
== BRW_OPCODE_MOV
||
402 (opcode
== BRW_OPCODE_SEL
&&
403 dst
.type
== src
[1].type
&&
404 predicate
!= BRW_PREDICATE_NONE
&&
405 !src
[1].abs
&& !src
[1].negate
));
411 memset(this, 0, sizeof(*this));
412 type
= BRW_REGISTER_TYPE_UD
;
416 /** Generic unset register constructor. */
420 this->file
= BAD_FILE
;
423 fs_reg::fs_reg(struct ::brw_reg reg
) :
428 if (this->file
== IMM
&&
429 (this->type
!= BRW_REGISTER_TYPE_V
&&
430 this->type
!= BRW_REGISTER_TYPE_UV
&&
431 this->type
!= BRW_REGISTER_TYPE_VF
)) {
437 fs_reg::equals(const fs_reg
&r
) const
439 return (this->backend_reg::equals(r
) &&
444 fs_reg::negative_equals(const fs_reg
&r
) const
446 return (this->backend_reg::negative_equals(r
) &&
451 fs_reg::is_contiguous() const
457 fs_reg::component_size(unsigned width
) const
459 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
462 return MAX2(width
* stride
, 1) * type_sz(type
);
466 type_size_scalar(const struct glsl_type
*type
)
468 unsigned int size
, i
;
470 switch (type
->base_type
) {
473 case GLSL_TYPE_FLOAT
:
475 return type
->components();
476 case GLSL_TYPE_UINT16
:
477 case GLSL_TYPE_INT16
:
478 case GLSL_TYPE_FLOAT16
:
479 return DIV_ROUND_UP(type
->components(), 2);
480 case GLSL_TYPE_UINT8
:
482 return DIV_ROUND_UP(type
->components(), 4);
483 case GLSL_TYPE_DOUBLE
:
484 case GLSL_TYPE_UINT64
:
485 case GLSL_TYPE_INT64
:
486 return type
->components() * 2;
487 case GLSL_TYPE_ARRAY
:
488 return type_size_scalar(type
->fields
.array
) * type
->length
;
489 case GLSL_TYPE_STRUCT
:
491 for (i
= 0; i
< type
->length
; i
++) {
492 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
495 case GLSL_TYPE_SAMPLER
:
496 /* Samplers take up no register space, since they're baked in at
500 case GLSL_TYPE_ATOMIC_UINT
:
502 case GLSL_TYPE_SUBROUTINE
:
504 case GLSL_TYPE_IMAGE
:
505 return BRW_IMAGE_PARAM_SIZE
;
507 case GLSL_TYPE_ERROR
:
508 case GLSL_TYPE_INTERFACE
:
509 case GLSL_TYPE_FUNCTION
:
510 unreachable("not reached");
517 * Create a MOV to read the timestamp register.
519 * The caller is responsible for emitting the MOV. The return value is
520 * the destination of the MOV, with extra parameters set.
523 fs_visitor::get_timestamp(const fs_builder
&bld
)
525 assert(devinfo
->gen
>= 7);
527 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
530 BRW_REGISTER_TYPE_UD
));
532 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
534 /* We want to read the 3 fields we care about even if it's not enabled in
537 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
543 fs_visitor::emit_shader_time_begin()
545 /* We want only the low 32 bits of the timestamp. Since it's running
546 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
547 * which is plenty of time for our purposes. It is identical across the
548 * EUs, but since it's tracking GPU core speed it will increment at a
549 * varying rate as render P-states change.
551 shader_start_time
= component(
552 get_timestamp(bld
.annotate("shader time start")), 0);
556 fs_visitor::emit_shader_time_end()
558 /* Insert our code just before the final SEND with EOT. */
559 exec_node
*end
= this->instructions
.get_tail();
560 assert(end
&& ((fs_inst
*) end
)->eot
);
561 const fs_builder ibld
= bld
.annotate("shader time end")
562 .exec_all().at(NULL
, end
);
563 const fs_reg timestamp
= get_timestamp(ibld
);
565 /* We only use the low 32 bits of the timestamp - see
566 * emit_shader_time_begin()).
568 * We could also check if render P-states have changed (or anything
569 * else that might disrupt timing) by setting smear to 2 and checking if
570 * that field is != 0.
572 const fs_reg shader_end_time
= component(timestamp
, 0);
574 /* Check that there weren't any timestamp reset events (assuming these
575 * were the only two timestamp reads that happened).
577 const fs_reg reset
= component(timestamp
, 2);
578 set_condmod(BRW_CONDITIONAL_Z
,
579 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
580 ibld
.IF(BRW_PREDICATE_NORMAL
);
582 fs_reg start
= shader_start_time
;
584 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
585 BRW_REGISTER_TYPE_UD
),
587 const fs_builder cbld
= ibld
.group(1, 0);
588 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
590 /* If there were no instructions between the two timestamp gets, the diff
591 * is 2 cycles. Remove that overhead, so I can forget about that when
592 * trying to determine the time taken for single instructions.
594 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
595 SHADER_TIME_ADD(cbld
, 0, diff
);
596 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
597 ibld
.emit(BRW_OPCODE_ELSE
);
598 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
599 ibld
.emit(BRW_OPCODE_ENDIF
);
603 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
604 int shader_time_subindex
,
607 int index
= shader_time_index
* 3 + shader_time_subindex
;
608 struct brw_reg offset
= brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
);
611 if (dispatch_width
== 8)
612 payload
= vgrf(glsl_type::uvec2_type
);
614 payload
= vgrf(glsl_type::uint_type
);
616 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
620 fs_visitor::vfail(const char *format
, va_list va
)
629 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
630 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
632 this->fail_msg
= msg
;
635 fprintf(stderr
, "%s", msg
);
640 fs_visitor::fail(const char *format
, ...)
644 va_start(va
, format
);
650 * Mark this program as impossible to compile with dispatch width greater
653 * During the SIMD8 compile (which happens first), we can detect and flag
654 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
655 * SIMD16+ compile altogether.
657 * During a compile of dispatch width greater than n (if one happens anyway),
658 * this just calls fail().
661 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
663 if (dispatch_width
> n
) {
666 max_dispatch_width
= n
;
667 compiler
->shader_perf_log(log_data
,
668 "Shader dispatch width limited to SIMD%d: %s",
674 * Returns true if the instruction has a flag that means it won't
675 * update an entire destination register.
677 * For example, dead code elimination and live variable analysis want to know
678 * when a write to a variable screens off any preceding values that were in
682 fs_inst::is_partial_write() const
684 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
685 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
686 !this->dst
.is_contiguous() ||
687 this->dst
.offset
% REG_SIZE
!= 0);
691 fs_inst::components_read(unsigned i
) const
693 /* Return zero if the source is not present. */
694 if (src
[i
].file
== BAD_FILE
)
698 case FS_OPCODE_LINTERP
:
704 case FS_OPCODE_PIXEL_X
:
705 case FS_OPCODE_PIXEL_Y
:
709 case FS_OPCODE_FB_WRITE_LOGICAL
:
710 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
711 /* First/second FB write color. */
713 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
717 case SHADER_OPCODE_TEX_LOGICAL
:
718 case SHADER_OPCODE_TXD_LOGICAL
:
719 case SHADER_OPCODE_TXF_LOGICAL
:
720 case SHADER_OPCODE_TXL_LOGICAL
:
721 case SHADER_OPCODE_TXS_LOGICAL
:
722 case FS_OPCODE_TXB_LOGICAL
:
723 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
724 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
725 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
726 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
727 case SHADER_OPCODE_LOD_LOGICAL
:
728 case SHADER_OPCODE_TG4_LOGICAL
:
729 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
730 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
731 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
732 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
733 /* Texture coordinates. */
734 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
735 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
736 /* Texture derivatives. */
737 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
738 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
739 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
740 /* Texture offset. */
741 else if (i
== TEX_LOGICAL_SRC_TG4_OFFSET
)
744 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
749 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
750 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
751 assert(src
[3].file
== IMM
);
752 /* Surface coordinates. */
755 /* Surface operation source (ignored for reads). */
761 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
762 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
763 assert(src
[3].file
== IMM
&&
765 /* Surface coordinates. */
768 /* Surface operation source. */
774 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
775 /* Scattered logical opcodes use the following params:
776 * src[0] Surface coordinates
777 * src[1] Surface operation source (ignored for reads)
779 * src[3] IMM with always 1 dimension.
780 * src[4] IMM with arg bitsize for scattered read/write 8, 16, 32
782 assert(src
[3].file
== IMM
&&
784 return i
== 1 ? 0 : 1;
786 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
787 assert(src
[3].file
== IMM
&&
791 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
792 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
793 assert(src
[3].file
== IMM
&&
795 const unsigned op
= src
[4].ud
;
796 /* Surface coordinates. */
799 /* Surface operation source. */
800 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
802 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
803 op
== BRW_AOP_PREDEC
))
815 fs_inst::size_read(int arg
) const
818 case FS_OPCODE_FB_WRITE
:
819 case FS_OPCODE_REP_FB_WRITE
:
822 return src
[0].file
== BAD_FILE
? 0 : 2 * REG_SIZE
;
824 return mlen
* REG_SIZE
;
828 case FS_OPCODE_FB_READ
:
829 case SHADER_OPCODE_URB_WRITE_SIMD8
:
830 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
831 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
832 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
833 case SHADER_OPCODE_URB_READ_SIMD8
:
834 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
835 case SHADER_OPCODE_UNTYPED_ATOMIC
:
836 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
837 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
838 case SHADER_OPCODE_TYPED_ATOMIC
:
839 case SHADER_OPCODE_TYPED_SURFACE_READ
:
840 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
841 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
842 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
843 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
844 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
845 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
847 return mlen
* REG_SIZE
;
850 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
851 /* The payload is actually stored in src1 */
853 return mlen
* REG_SIZE
;
856 case FS_OPCODE_LINTERP
:
861 case SHADER_OPCODE_LOAD_PAYLOAD
:
862 if (arg
< this->header_size
)
866 case CS_OPCODE_CS_TERMINATE
:
867 case SHADER_OPCODE_BARRIER
:
870 case SHADER_OPCODE_MOV_INDIRECT
:
872 assert(src
[2].file
== IMM
);
878 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
879 return mlen
* REG_SIZE
;
883 switch (src
[arg
].file
) {
886 return components_read(arg
) * type_sz(src
[arg
].type
);
892 return components_read(arg
) * src
[arg
].component_size(exec_size
);
894 unreachable("MRF registers are not allowed as sources");
900 /* Return the subset of flag registers that an instruction could
901 * potentially read or write based on the execution controls and flag
902 * subregister number of the instruction.
905 flag_mask(const fs_inst
*inst
)
907 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
908 const unsigned end
= start
+ inst
->exec_size
;
909 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
915 return (n
>= CHAR_BIT
* sizeof(bit_mask(n
)) ? ~0u : (1u << n
) - 1);
919 flag_mask(const fs_reg
&r
, unsigned sz
)
922 const unsigned start
= (r
.nr
- BRW_ARF_FLAG
) * 4 + r
.subnr
;
923 const unsigned end
= start
+ sz
;
924 return bit_mask(end
) & ~bit_mask(start
);
932 fs_inst::flags_read(const gen_device_info
*devinfo
) const
934 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
935 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
936 /* The vertical predication modes combine corresponding bits from
937 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
939 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
940 return flag_mask(this) << shift
| flag_mask(this);
941 } else if (predicate
) {
942 return flag_mask(this);
945 for (int i
= 0; i
< sources
; i
++) {
946 mask
|= flag_mask(src
[i
], size_read(i
));
953 fs_inst::flags_written() const
955 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
956 opcode
!= BRW_OPCODE_CSEL
&&
957 opcode
!= BRW_OPCODE_IF
&&
958 opcode
!= BRW_OPCODE_WHILE
)) ||
959 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
||
960 opcode
== SHADER_OPCODE_FIND_LIVE_CHANNEL
||
961 opcode
== FS_OPCODE_FB_WRITE
) {
962 return flag_mask(this);
964 return flag_mask(dst
, size_written
);
969 * Returns how many MRFs an FS opcode will write over.
971 * Note that this is not the 0 or 1 implied writes in an actual gen
972 * instruction -- the FS opcodes often generate MOVs in addition.
975 fs_visitor::implied_mrf_writes(fs_inst
*inst
) const
980 if (inst
->base_mrf
== -1)
983 switch (inst
->opcode
) {
984 case SHADER_OPCODE_RCP
:
985 case SHADER_OPCODE_RSQ
:
986 case SHADER_OPCODE_SQRT
:
987 case SHADER_OPCODE_EXP2
:
988 case SHADER_OPCODE_LOG2
:
989 case SHADER_OPCODE_SIN
:
990 case SHADER_OPCODE_COS
:
991 return 1 * dispatch_width
/ 8;
992 case SHADER_OPCODE_POW
:
993 case SHADER_OPCODE_INT_QUOTIENT
:
994 case SHADER_OPCODE_INT_REMAINDER
:
995 return 2 * dispatch_width
/ 8;
996 case SHADER_OPCODE_TEX
:
998 case SHADER_OPCODE_TXD
:
999 case SHADER_OPCODE_TXF
:
1000 case SHADER_OPCODE_TXF_CMS
:
1001 case SHADER_OPCODE_TXF_MCS
:
1002 case SHADER_OPCODE_TG4
:
1003 case SHADER_OPCODE_TG4_OFFSET
:
1004 case SHADER_OPCODE_TXL
:
1005 case SHADER_OPCODE_TXS
:
1006 case SHADER_OPCODE_LOD
:
1007 case SHADER_OPCODE_SAMPLEINFO
:
1009 case FS_OPCODE_FB_WRITE
:
1010 case FS_OPCODE_REP_FB_WRITE
:
1011 return inst
->src
[0].file
== BAD_FILE
? 0 : 2;
1012 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1013 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1015 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
1017 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1020 unreachable("not reached");
1025 fs_visitor::vgrf(const glsl_type
*const type
)
1027 int reg_width
= dispatch_width
/ 8;
1028 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
1029 brw_type_for_base_type(type
));
1032 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1037 this->type
= BRW_REGISTER_TYPE_F
;
1038 this->stride
= (file
== UNIFORM
? 0 : 1);
1041 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1047 this->stride
= (file
== UNIFORM
? 0 : 1);
1050 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1051 * This brings in those uniform definitions
1054 fs_visitor::import_uniforms(fs_visitor
*v
)
1056 this->push_constant_loc
= v
->push_constant_loc
;
1057 this->pull_constant_loc
= v
->pull_constant_loc
;
1058 this->uniforms
= v
->uniforms
;
1059 this->subgroup_id
= v
->subgroup_id
;
1063 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1065 assert(stage
== MESA_SHADER_FRAGMENT
);
1067 /* gl_FragCoord.x */
1068 bld
.MOV(wpos
, this->pixel_x
);
1069 wpos
= offset(wpos
, bld
, 1);
1071 /* gl_FragCoord.y */
1072 bld
.MOV(wpos
, this->pixel_y
);
1073 wpos
= offset(wpos
, bld
, 1);
1075 /* gl_FragCoord.z */
1076 if (devinfo
->gen
>= 6) {
1077 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1079 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1080 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1081 component(interp_reg(VARYING_SLOT_POS
, 2), 0));
1083 wpos
= offset(wpos
, bld
, 1);
1085 /* gl_FragCoord.w: Already set up in emit_interpolation */
1086 bld
.MOV(wpos
, this->wpos_w
);
1089 enum brw_barycentric_mode
1090 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1092 /* Barycentric modes don't make sense for flat inputs. */
1093 assert(mode
!= INTERP_MODE_FLAT
);
1097 case nir_intrinsic_load_barycentric_pixel
:
1098 case nir_intrinsic_load_barycentric_at_offset
:
1099 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1101 case nir_intrinsic_load_barycentric_centroid
:
1102 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1104 case nir_intrinsic_load_barycentric_sample
:
1105 case nir_intrinsic_load_barycentric_at_sample
:
1106 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1109 unreachable("invalid intrinsic");
1112 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1115 return (enum brw_barycentric_mode
) bary
;
1119 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1121 static enum brw_barycentric_mode
1122 centroid_to_pixel(enum brw_barycentric_mode bary
)
1124 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1125 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1126 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1130 fs_visitor::emit_frontfacing_interpolation()
1132 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1134 if (devinfo
->gen
>= 6) {
1135 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1136 * a boolean result from this (~0/true or 0/false).
1138 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1139 * this task in only one instruction:
1140 * - a negation source modifier will flip the bit; and
1141 * - a W -> D type conversion will sign extend the bit into the high
1142 * word of the destination.
1144 * An ASR 15 fills the low word of the destination.
1146 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1149 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1151 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1152 * a boolean result from this (1/true or 0/false).
1154 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1155 * the negation source modifier to flip it. Unfortunately the SHR
1156 * instruction only operates on UD (or D with an abs source modifier)
1157 * sources without negation.
1159 * Instead, use ASR (which will give ~0/true or 0/false).
1161 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1164 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1171 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1173 assert(stage
== MESA_SHADER_FRAGMENT
);
1174 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1175 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1177 if (wm_prog_data
->persample_dispatch
) {
1178 /* Convert int_sample_pos to floating point */
1179 bld
.MOV(dst
, int_sample_pos
);
1180 /* Scale to the range [0, 1] */
1181 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1184 /* From ARB_sample_shading specification:
1185 * "When rendering to a non-multisample buffer, or if multisample
1186 * rasterization is disabled, gl_SamplePosition will always be
1189 bld
.MOV(dst
, brw_imm_f(0.5f
));
1194 fs_visitor::emit_samplepos_setup()
1196 assert(devinfo
->gen
>= 6);
1198 const fs_builder abld
= bld
.annotate("compute sample position");
1199 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1201 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1202 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1204 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1205 * mode will be enabled.
1207 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1208 * R31.1:0 Position Offset X/Y for Slot[3:0]
1209 * R31.3:2 Position Offset X/Y for Slot[7:4]
1212 * The X, Y sample positions come in as bytes in thread payload. So, read
1213 * the positions using vstride=16, width=8, hstride=2.
1215 struct brw_reg sample_pos_reg
=
1216 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1217 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1219 if (dispatch_width
== 8) {
1220 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1222 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1223 abld
.half(1).MOV(half(int_sample_x
, 1),
1224 fs_reg(suboffset(sample_pos_reg
, 16)));
1226 /* Compute gl_SamplePosition.x */
1227 compute_sample_position(pos
, int_sample_x
);
1228 pos
= offset(pos
, abld
, 1);
1229 if (dispatch_width
== 8) {
1230 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1232 abld
.half(0).MOV(half(int_sample_y
, 0),
1233 fs_reg(suboffset(sample_pos_reg
, 1)));
1234 abld
.half(1).MOV(half(int_sample_y
, 1),
1235 fs_reg(suboffset(sample_pos_reg
, 17)));
1237 /* Compute gl_SamplePosition.y */
1238 compute_sample_position(pos
, int_sample_y
);
1243 fs_visitor::emit_sampleid_setup()
1245 assert(stage
== MESA_SHADER_FRAGMENT
);
1246 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1247 assert(devinfo
->gen
>= 6);
1249 const fs_builder abld
= bld
.annotate("compute sample id");
1250 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uint_type
));
1252 if (!key
->multisample_fbo
) {
1253 /* As per GL_ARB_sample_shading specification:
1254 * "When rendering to a non-multisample buffer, or if multisample
1255 * rasterization is disabled, gl_SampleID will always be zero."
1257 abld
.MOV(*reg
, brw_imm_d(0));
1258 } else if (devinfo
->gen
>= 8) {
1259 /* Sample ID comes in as 4-bit numbers in g1.0:
1261 * 15:12 Slot 3 SampleID (only used in SIMD16)
1262 * 11:8 Slot 2 SampleID (only used in SIMD16)
1263 * 7:4 Slot 1 SampleID
1264 * 3:0 Slot 0 SampleID
1266 * Each slot corresponds to four channels, so we want to replicate each
1267 * half-byte value to 4 channels in a row:
1269 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1270 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1272 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1273 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1275 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1276 * channels to read the first byte (7:0), and the second group of 8
1277 * channels to read the second byte (15:8). Then, we shift right by
1278 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1279 * values into place. Finally, we AND with 0xf to keep the low nibble.
1281 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1282 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1284 * TODO: These payload bits exist on Gen7 too, but they appear to always
1285 * be zero, so this code fails to work. We should find out why.
1287 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UW
);
1289 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1290 BRW_REGISTER_TYPE_UB
), 1, 8, 0)),
1291 brw_imm_v(0x44440000));
1292 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1294 const fs_reg t1
= component(fs_reg(VGRF
, alloc
.allocate(1),
1295 BRW_REGISTER_TYPE_UD
), 0);
1296 const fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UW
);
1298 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1299 * 8x multisampling, subspan 0 will represent sample N (where N
1300 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1301 * 7. We can find the value of N by looking at R0.0 bits 7:6
1302 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1303 * (since samples are always delivered in pairs). That is, we
1304 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1305 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1306 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1307 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1308 * populating a temporary variable with the sequence (0, 1, 2, 3),
1309 * and then reading from it using vstride=1, width=4, hstride=0.
1310 * These computations hold good for 4x multisampling as well.
1312 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1313 * the first four slots are sample 0 of subspan 0; the next four
1314 * are sample 1 of subspan 0; the third group is sample 0 of
1315 * subspan 1, and finally sample 1 of subspan 1.
1318 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1319 * accomodate 16x MSAA.
1321 abld
.exec_all().group(1, 0)
1322 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1324 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1326 /* This works for both SIMD8 and SIMD16 */
1327 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1329 /* This special instruction takes care of setting vstride=1,
1330 * width=4, hstride=0 of t2 during an ADD instruction.
1332 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1339 fs_visitor::emit_samplemaskin_setup()
1341 assert(stage
== MESA_SHADER_FRAGMENT
);
1342 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1343 assert(devinfo
->gen
>= 6);
1345 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1347 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1348 BRW_REGISTER_TYPE_D
));
1350 if (wm_prog_data
->persample_dispatch
) {
1351 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1352 * and a mask representing which sample is being processed by the
1353 * current shader invocation.
1355 * From the OES_sample_variables specification:
1356 * "When per-sample shading is active due to the use of a fragment input
1357 * qualified by "sample" or due to the use of the gl_SampleID or
1358 * gl_SamplePosition variables, only the bit for the current sample is
1359 * set in gl_SampleMaskIn."
1361 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1363 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1364 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1366 fs_reg one
= vgrf(glsl_type::int_type
);
1367 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1368 abld
.MOV(one
, brw_imm_d(1));
1369 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1370 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1372 /* In per-pixel mode, the coverage mask is sufficient. */
1373 *reg
= coverage_mask
;
1379 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1381 if (!src
.abs
&& !src
.negate
)
1384 fs_reg temp
= bld
.vgrf(src
.type
);
1391 fs_visitor::emit_discard_jump()
1393 assert(brw_wm_prog_data(this->prog_data
)->uses_kill
);
1395 /* For performance, after a discard, jump to the end of the
1396 * shader if all relevant channels have been discarded.
1398 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1399 discard_jump
->flag_subreg
= 1;
1401 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1402 discard_jump
->predicate_inverse
= true;
1406 fs_visitor::emit_gs_thread_end()
1408 assert(stage
== MESA_SHADER_GEOMETRY
);
1410 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1412 if (gs_compile
->control_data_header_size_bits
> 0) {
1413 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1416 const fs_builder abld
= bld
.annotate("thread end");
1419 if (gs_prog_data
->static_vertex_count
!= -1) {
1420 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1421 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1422 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1423 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1424 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1427 /* Delete now dead instructions. */
1428 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1434 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1438 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1439 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1440 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1443 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1444 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1445 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1446 sources
[1] = this->final_gs_vertex_count
;
1447 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1448 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1456 fs_visitor::assign_curb_setup()
1458 unsigned uniform_push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
1460 unsigned ubo_push_length
= 0;
1461 unsigned ubo_push_start
[4];
1462 for (int i
= 0; i
< 4; i
++) {
1463 ubo_push_start
[i
] = 8 * (ubo_push_length
+ uniform_push_length
);
1464 ubo_push_length
+= stage_prog_data
->ubo_ranges
[i
].length
;
1467 prog_data
->curb_read_length
= uniform_push_length
+ ubo_push_length
;
1469 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1470 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1471 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1472 if (inst
->src
[i
].file
== UNIFORM
) {
1473 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1475 if (inst
->src
[i
].nr
>= UBO_START
) {
1476 /* constant_nr is in 32-bit units, the rest are in bytes */
1477 constant_nr
= ubo_push_start
[inst
->src
[i
].nr
- UBO_START
] +
1478 inst
->src
[i
].offset
/ 4;
1479 } else if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1480 constant_nr
= push_constant_loc
[uniform_nr
];
1482 /* Section 5.11 of the OpenGL 4.1 spec says:
1483 * "Out-of-bounds reads return undefined values, which include
1484 * values from other variables of the active program or zero."
1485 * Just return the first push constant.
1490 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1493 brw_reg
.abs
= inst
->src
[i
].abs
;
1494 brw_reg
.negate
= inst
->src
[i
].negate
;
1496 assert(inst
->src
[i
].stride
== 0);
1497 inst
->src
[i
] = byte_offset(
1498 retype(brw_reg
, inst
->src
[i
].type
),
1499 inst
->src
[i
].offset
% 4);
1504 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1505 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1509 fs_visitor::calculate_urb_setup()
1511 assert(stage
== MESA_SHADER_FRAGMENT
);
1512 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1513 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1515 memset(prog_data
->urb_setup
, -1,
1516 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1519 /* Figure out where each of the incoming setup attributes lands. */
1520 if (devinfo
->gen
>= 6) {
1521 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1522 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1523 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1524 * first 16 varying inputs, so we can put them wherever we want.
1525 * Just put them in order.
1527 * This is useful because it means that (a) inputs not used by the
1528 * fragment shader won't take up valuable register space, and (b) we
1529 * won't have to recompile the fragment shader if it gets paired with
1530 * a different vertex (or geometry) shader.
1532 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1533 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1534 BITFIELD64_BIT(i
)) {
1535 prog_data
->urb_setup
[i
] = urb_next
++;
1539 /* We have enough input varyings that the SF/SBE pipeline stage can't
1540 * arbitrarily rearrange them to suit our whim; we have to put them
1541 * in an order that matches the output of the previous pipeline stage
1542 * (geometry or vertex shader).
1544 struct brw_vue_map prev_stage_vue_map
;
1545 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1546 key
->input_slots_valid
,
1547 nir
->info
.separate_shader
);
1550 brw_compute_first_urb_slot_required(nir
->info
.inputs_read
,
1551 &prev_stage_vue_map
);
1553 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1554 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1556 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1557 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1558 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1559 BITFIELD64_BIT(varying
))) {
1560 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1563 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1566 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1567 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1568 /* Point size is packed into the header, not as a general attribute */
1569 if (i
== VARYING_SLOT_PSIZ
)
1572 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1573 /* The back color slot is skipped when the front color is
1574 * also written to. In addition, some slots can be
1575 * written in the vertex shader and not read in the
1576 * fragment shader. So the register number must always be
1577 * incremented, mapped or not.
1579 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1580 prog_data
->urb_setup
[i
] = urb_next
;
1586 * It's a FS only attribute, and we did interpolation for this attribute
1587 * in SF thread. So, count it here, too.
1589 * See compile_sf_prog() for more info.
1591 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1592 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1595 prog_data
->num_varying_inputs
= urb_next
;
1599 fs_visitor::assign_urb_setup()
1601 assert(stage
== MESA_SHADER_FRAGMENT
);
1602 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1604 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1606 /* Offset all the urb_setup[] index by the actual position of the
1607 * setup regs, now that the location of the constants has been chosen.
1609 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1610 for (int i
= 0; i
< inst
->sources
; i
++) {
1611 if (inst
->src
[i
].file
== ATTR
) {
1612 /* ATTR regs in the FS are in units of logical scalar inputs each
1613 * of which consumes half of a GRF register.
1615 assert(inst
->src
[i
].offset
< REG_SIZE
/ 2);
1616 const unsigned grf
= urb_start
+ inst
->src
[i
].nr
/ 2;
1617 const unsigned offset
= (inst
->src
[i
].nr
% 2) * (REG_SIZE
/ 2) +
1618 inst
->src
[i
].offset
;
1619 const unsigned width
= inst
->src
[i
].stride
== 0 ?
1620 1 : MIN2(inst
->exec_size
, 8);
1621 struct brw_reg reg
= stride(
1622 byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1624 width
* inst
->src
[i
].stride
,
1625 width
, inst
->src
[i
].stride
);
1626 reg
.abs
= inst
->src
[i
].abs
;
1627 reg
.negate
= inst
->src
[i
].negate
;
1633 /* Each attribute is 4 setup channels, each of which is half a reg. */
1634 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1638 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1640 for (int i
= 0; i
< inst
->sources
; i
++) {
1641 if (inst
->src
[i
].file
== ATTR
) {
1642 int grf
= payload
.num_regs
+
1643 prog_data
->curb_read_length
+
1645 inst
->src
[i
].offset
/ REG_SIZE
;
1647 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1649 * VertStride must be used to cross GRF register boundaries. This
1650 * rule implies that elements within a 'Width' cannot cross GRF
1653 * So, for registers that are large enough, we have to split the exec
1654 * size in two and trust the compression state to sort it out.
1656 unsigned total_size
= inst
->exec_size
*
1657 inst
->src
[i
].stride
*
1658 type_sz(inst
->src
[i
].type
);
1660 assert(total_size
<= 2 * REG_SIZE
);
1661 const unsigned exec_size
=
1662 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1664 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1665 struct brw_reg reg
=
1666 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1667 inst
->src
[i
].offset
% REG_SIZE
),
1668 exec_size
* inst
->src
[i
].stride
,
1669 width
, inst
->src
[i
].stride
);
1670 reg
.abs
= inst
->src
[i
].abs
;
1671 reg
.negate
= inst
->src
[i
].negate
;
1679 fs_visitor::assign_vs_urb_setup()
1681 struct brw_vs_prog_data
*vs_prog_data
= brw_vs_prog_data(prog_data
);
1683 assert(stage
== MESA_SHADER_VERTEX
);
1685 /* Each attribute is 4 regs. */
1686 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1688 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1690 /* Rewrite all ATTR file references to the hw grf that they land in. */
1691 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1692 convert_attr_sources_to_hw_regs(inst
);
1697 fs_visitor::assign_tcs_single_patch_urb_setup()
1699 assert(stage
== MESA_SHADER_TESS_CTRL
);
1701 /* Rewrite all ATTR file references to HW_REGs. */
1702 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1703 convert_attr_sources_to_hw_regs(inst
);
1708 fs_visitor::assign_tes_urb_setup()
1710 assert(stage
== MESA_SHADER_TESS_EVAL
);
1712 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1714 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1716 /* Rewrite all ATTR file references to HW_REGs. */
1717 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1718 convert_attr_sources_to_hw_regs(inst
);
1723 fs_visitor::assign_gs_urb_setup()
1725 assert(stage
== MESA_SHADER_GEOMETRY
);
1727 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1729 first_non_payload_grf
+=
1730 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1732 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1733 /* Rewrite all ATTR file references to GRFs. */
1734 convert_attr_sources_to_hw_regs(inst
);
1740 * Split large virtual GRFs into separate components if we can.
1742 * This is mostly duplicated with what brw_fs_vector_splitting does,
1743 * but that's really conservative because it's afraid of doing
1744 * splitting that doesn't result in real progress after the rest of
1745 * the optimization phases, which would cause infinite looping in
1746 * optimization. We can do it once here, safely. This also has the
1747 * opportunity to split interpolated values, or maybe even uniforms,
1748 * which we don't have at the IR level.
1750 * We want to split, because virtual GRFs are what we register
1751 * allocate and spill (due to contiguousness requirements for some
1752 * instructions), and they're what we naturally generate in the
1753 * codegen process, but most virtual GRFs don't actually need to be
1754 * contiguous sets of GRFs. If we split, we'll end up with reduced
1755 * live intervals and better dead code elimination and coalescing.
1758 fs_visitor::split_virtual_grfs()
1760 /* Compact the register file so we eliminate dead vgrfs. This
1761 * only defines split points for live registers, so if we have
1762 * too large dead registers they will hit assertions later.
1764 compact_virtual_grfs();
1766 int num_vars
= this->alloc
.count
;
1768 /* Count the total number of registers */
1770 int vgrf_to_reg
[num_vars
];
1771 for (int i
= 0; i
< num_vars
; i
++) {
1772 vgrf_to_reg
[i
] = reg_count
;
1773 reg_count
+= alloc
.sizes
[i
];
1776 /* An array of "split points". For each register slot, this indicates
1777 * if this slot can be separated from the previous slot. Every time an
1778 * instruction uses multiple elements of a register (as a source or
1779 * destination), we mark the used slots as inseparable. Then we go
1780 * through and split the registers into the smallest pieces we can.
1782 bool split_points
[reg_count
];
1783 memset(split_points
, 0, sizeof(split_points
));
1785 /* Mark all used registers as fully splittable */
1786 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1787 if (inst
->dst
.file
== VGRF
) {
1788 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1789 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1790 split_points
[reg
+ j
] = true;
1793 for (int i
= 0; i
< inst
->sources
; i
++) {
1794 if (inst
->src
[i
].file
== VGRF
) {
1795 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1796 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1797 split_points
[reg
+ j
] = true;
1802 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1803 if (inst
->dst
.file
== VGRF
) {
1804 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1805 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1806 split_points
[reg
+ j
] = false;
1808 for (int i
= 0; i
< inst
->sources
; i
++) {
1809 if (inst
->src
[i
].file
== VGRF
) {
1810 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1811 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1812 split_points
[reg
+ j
] = false;
1817 int new_virtual_grf
[reg_count
];
1818 int new_reg_offset
[reg_count
];
1821 for (int i
= 0; i
< num_vars
; i
++) {
1822 /* The first one should always be 0 as a quick sanity check. */
1823 assert(split_points
[reg
] == false);
1826 new_reg_offset
[reg
] = 0;
1831 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1832 /* If this is a split point, reset the offset to 0 and allocate a
1833 * new virtual GRF for the previous offset many registers
1835 if (split_points
[reg
]) {
1836 assert(offset
<= MAX_VGRF_SIZE
);
1837 int grf
= alloc
.allocate(offset
);
1838 for (int k
= reg
- offset
; k
< reg
; k
++)
1839 new_virtual_grf
[k
] = grf
;
1842 new_reg_offset
[reg
] = offset
;
1847 /* The last one gets the original register number */
1848 assert(offset
<= MAX_VGRF_SIZE
);
1849 alloc
.sizes
[i
] = offset
;
1850 for (int k
= reg
- offset
; k
< reg
; k
++)
1851 new_virtual_grf
[k
] = i
;
1853 assert(reg
== reg_count
);
1855 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1856 if (inst
->dst
.file
== VGRF
) {
1857 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1858 inst
->dst
.nr
= new_virtual_grf
[reg
];
1859 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
1860 inst
->dst
.offset
% REG_SIZE
;
1861 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1863 for (int i
= 0; i
< inst
->sources
; i
++) {
1864 if (inst
->src
[i
].file
== VGRF
) {
1865 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1866 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1867 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
1868 inst
->src
[i
].offset
% REG_SIZE
;
1869 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1873 invalidate_live_intervals();
1877 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1879 * During code generation, we create tons of temporary variables, many of
1880 * which get immediately killed and are never used again. Yet, in later
1881 * optimization and analysis passes, such as compute_live_intervals, we need
1882 * to loop over all the virtual GRFs. Compacting them can save a lot of
1886 fs_visitor::compact_virtual_grfs()
1888 bool progress
= false;
1889 int remap_table
[this->alloc
.count
];
1890 memset(remap_table
, -1, sizeof(remap_table
));
1892 /* Mark which virtual GRFs are used. */
1893 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1894 if (inst
->dst
.file
== VGRF
)
1895 remap_table
[inst
->dst
.nr
] = 0;
1897 for (int i
= 0; i
< inst
->sources
; i
++) {
1898 if (inst
->src
[i
].file
== VGRF
)
1899 remap_table
[inst
->src
[i
].nr
] = 0;
1903 /* Compact the GRF arrays. */
1905 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1906 if (remap_table
[i
] == -1) {
1907 /* We just found an unused register. This means that we are
1908 * actually going to compact something.
1912 remap_table
[i
] = new_index
;
1913 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1914 invalidate_live_intervals();
1919 this->alloc
.count
= new_index
;
1921 /* Patch all the instructions to use the newly renumbered registers */
1922 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1923 if (inst
->dst
.file
== VGRF
)
1924 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1926 for (int i
= 0; i
< inst
->sources
; i
++) {
1927 if (inst
->src
[i
].file
== VGRF
)
1928 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1932 /* Patch all the references to delta_xy, since they're used in register
1933 * allocation. If they're unused, switch them to BAD_FILE so we don't
1934 * think some random VGRF is delta_xy.
1936 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1937 if (delta_xy
[i
].file
== VGRF
) {
1938 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1939 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1941 delta_xy
[i
].file
= BAD_FILE
;
1950 get_subgroup_id_param_index(const brw_stage_prog_data
*prog_data
)
1952 if (prog_data
->nr_params
== 0)
1955 /* The local thread id is always the last parameter in the list */
1956 uint32_t last_param
= prog_data
->param
[prog_data
->nr_params
- 1];
1957 if (last_param
== BRW_PARAM_BUILTIN_SUBGROUP_ID
)
1958 return prog_data
->nr_params
- 1;
1964 * Struct for handling complex alignments.
1966 * A complex alignment is stored as multiplier and an offset. A value is
1967 * considered to be aligned if it is {offset} larger than a multiple of {mul}.
1968 * For instance, with an alignment of {8, 2}, cplx_align_apply would do the
1971 * N | cplx_align_apply({8, 2}, N)
1972 * ----+-----------------------------
1986 #define CPLX_ALIGN_MAX_MUL 8
1989 cplx_align_assert_sane(struct cplx_align a
)
1991 assert(a
.mul
> 0 && util_is_power_of_two_nonzero(a
.mul
));
1992 assert(a
.offset
< a
.mul
);
1996 * Combines two alignments to produce a least multiple of sorts.
1998 * The returned alignment is the smallest (in terms of multiplier) such that
1999 * anything aligned to both a and b will be aligned to the new alignment.
2000 * This function will assert-fail if a and b are not compatible, i.e. if the
2001 * offset parameters are such that no common alignment is possible.
2003 static struct cplx_align
2004 cplx_align_combine(struct cplx_align a
, struct cplx_align b
)
2006 cplx_align_assert_sane(a
);
2007 cplx_align_assert_sane(b
);
2009 /* Assert that the alignments agree. */
2010 assert((a
.offset
& (b
.mul
- 1)) == (b
.offset
& (a
.mul
- 1)));
2012 return a
.mul
> b
.mul
? a
: b
;
2016 * Apply a complex alignment
2018 * This function will return the smallest number greater than or equal to
2019 * offset that is aligned to align.
2022 cplx_align_apply(struct cplx_align align
, unsigned offset
)
2024 return ALIGN(offset
- align
.offset
, align
.mul
) + align
.offset
;
2027 #define UNIFORM_SLOT_SIZE 4
2029 struct uniform_slot_info
{
2030 /** True if the given uniform slot is live */
2033 /** True if this slot and the next slot must remain contiguous */
2034 unsigned contiguous
:1;
2036 struct cplx_align align
;
2040 mark_uniform_slots_read(struct uniform_slot_info
*slots
,
2041 unsigned num_slots
, unsigned alignment
)
2043 assert(alignment
> 0 && util_is_power_of_two_nonzero(alignment
));
2044 assert(alignment
<= CPLX_ALIGN_MAX_MUL
);
2046 /* We can't align a slot to anything less than the slot size */
2047 alignment
= MAX2(alignment
, UNIFORM_SLOT_SIZE
);
2049 struct cplx_align align
= {alignment
, 0};
2050 cplx_align_assert_sane(align
);
2052 for (unsigned i
= 0; i
< num_slots
; i
++) {
2053 slots
[i
].is_live
= true;
2054 if (i
< num_slots
- 1)
2055 slots
[i
].contiguous
= true;
2057 align
.offset
= (i
* UNIFORM_SLOT_SIZE
) & (align
.mul
- 1);
2058 if (slots
[i
].align
.mul
== 0) {
2059 slots
[i
].align
= align
;
2061 slots
[i
].align
= cplx_align_combine(slots
[i
].align
, align
);
2067 * Assign UNIFORM file registers to either push constants or pull constants.
2069 * We allow a fragment shader to have more than the specified minimum
2070 * maximum number of fragment shader uniform components (64). If
2071 * there are too many of these, they'd fill up all of register space.
2072 * So, this will push some of them out to the pull constant buffer and
2073 * update the program to load them.
2076 fs_visitor::assign_constant_locations()
2078 /* Only the first compile gets to decide on locations. */
2079 if (push_constant_loc
) {
2080 assert(pull_constant_loc
);
2084 struct uniform_slot_info slots
[uniforms
];
2085 memset(slots
, 0, sizeof(slots
));
2087 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2088 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2089 if (inst
->src
[i
].file
!= UNIFORM
)
2092 /* NIR tightly packs things so the uniform number might not be
2093 * aligned (if we have a double right after a float, for instance).
2094 * This is fine because the process of re-arranging them will ensure
2095 * that things are properly aligned. The offset into that uniform,
2096 * however, must be aligned.
2098 * In Vulkan, we have explicit offsets but everything is crammed
2099 * into a single "variable" so inst->src[i].nr will always be 0.
2100 * Everything will be properly aligned relative to that one base.
2102 assert(inst
->src
[i
].offset
% type_sz(inst
->src
[i
].type
) == 0);
2104 unsigned u
= inst
->src
[i
].nr
+
2105 inst
->src
[i
].offset
/ UNIFORM_SLOT_SIZE
;
2110 unsigned slots_read
;
2111 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2112 slots_read
= DIV_ROUND_UP(inst
->src
[2].ud
, UNIFORM_SLOT_SIZE
);
2114 unsigned bytes_read
= inst
->components_read(i
) *
2115 type_sz(inst
->src
[i
].type
);
2116 slots_read
= DIV_ROUND_UP(bytes_read
, UNIFORM_SLOT_SIZE
);
2119 assert(u
+ slots_read
<= uniforms
);
2120 mark_uniform_slots_read(&slots
[u
], slots_read
,
2121 type_sz(inst
->src
[i
].type
));
2125 int subgroup_id_index
= get_subgroup_id_param_index(stage_prog_data
);
2127 /* Only allow 16 registers (128 uniform components) as push constants.
2129 * Just demote the end of the list. We could probably do better
2130 * here, demoting things that are rarely used in the program first.
2132 * If changing this value, note the limitation about total_regs in
2135 unsigned int max_push_components
= 16 * 8;
2136 if (subgroup_id_index
>= 0)
2137 max_push_components
--; /* Save a slot for the thread ID */
2139 /* We push small arrays, but no bigger than 16 floats. This is big enough
2140 * for a vec4 but hopefully not large enough to push out other stuff. We
2141 * should probably use a better heuristic at some point.
2143 const unsigned int max_chunk_size
= 16;
2145 unsigned int num_push_constants
= 0;
2146 unsigned int num_pull_constants
= 0;
2148 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2149 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2151 /* Default to -1 meaning no location */
2152 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2153 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2155 int chunk_start
= -1;
2156 struct cplx_align align
;
2157 for (unsigned u
= 0; u
< uniforms
; u
++) {
2158 if (!slots
[u
].is_live
) {
2159 assert(chunk_start
== -1);
2163 /* Skip subgroup_id_index to put it in the last push register. */
2164 if (subgroup_id_index
== (int)u
)
2167 if (chunk_start
== -1) {
2169 align
= slots
[u
].align
;
2171 /* Offset into the chunk */
2172 unsigned chunk_offset
= (u
- chunk_start
) * UNIFORM_SLOT_SIZE
;
2174 /* Shift the slot alignment down by the chunk offset so it is
2175 * comparable with the base chunk alignment.
2177 struct cplx_align slot_align
= slots
[u
].align
;
2179 (slot_align
.offset
- chunk_offset
) & (align
.mul
- 1);
2181 align
= cplx_align_combine(align
, slot_align
);
2184 /* Sanity check the alignment */
2185 cplx_align_assert_sane(align
);
2187 if (slots
[u
].contiguous
)
2190 /* Adjust the alignment to be in terms of slots, not bytes */
2191 assert((align
.mul
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2192 assert((align
.offset
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2193 align
.mul
/= UNIFORM_SLOT_SIZE
;
2194 align
.offset
/= UNIFORM_SLOT_SIZE
;
2196 unsigned push_start_align
= cplx_align_apply(align
, num_push_constants
);
2197 unsigned chunk_size
= u
- chunk_start
+ 1;
2198 if ((!compiler
->supports_pull_constants
&& u
< UBO_START
) ||
2199 (chunk_size
< max_chunk_size
&&
2200 push_start_align
+ chunk_size
<= max_push_components
)) {
2201 /* Align up the number of push constants */
2202 num_push_constants
= push_start_align
;
2203 for (unsigned i
= 0; i
< chunk_size
; i
++)
2204 push_constant_loc
[chunk_start
+ i
] = num_push_constants
++;
2206 /* We need to pull this one */
2207 num_pull_constants
= cplx_align_apply(align
, num_pull_constants
);
2208 for (unsigned i
= 0; i
< chunk_size
; i
++)
2209 pull_constant_loc
[chunk_start
+ i
] = num_pull_constants
++;
2212 /* Reset the chunk and start again */
2216 /* Add the CS local thread ID uniform at the end of the push constants */
2217 if (subgroup_id_index
>= 0)
2218 push_constant_loc
[subgroup_id_index
] = num_push_constants
++;
2220 /* As the uniforms are going to be reordered, stash the old array and
2221 * create two new arrays for push/pull params.
2223 uint32_t *param
= stage_prog_data
->param
;
2224 stage_prog_data
->nr_params
= num_push_constants
;
2225 if (num_push_constants
) {
2226 stage_prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t,
2227 num_push_constants
);
2229 stage_prog_data
->param
= NULL
;
2231 assert(stage_prog_data
->nr_pull_params
== 0);
2232 assert(stage_prog_data
->pull_param
== NULL
);
2233 if (num_pull_constants
> 0) {
2234 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2235 stage_prog_data
->pull_param
= rzalloc_array(mem_ctx
, uint32_t,
2236 num_pull_constants
);
2239 /* Now that we know how many regular uniforms we'll push, reduce the
2240 * UBO push ranges so we don't exceed the 3DSTATE_CONSTANT limits.
2242 unsigned push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
2243 for (int i
= 0; i
< 4; i
++) {
2244 struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2246 if (push_length
+ range
->length
> 64)
2247 range
->length
= 64 - push_length
;
2249 push_length
+= range
->length
;
2251 assert(push_length
<= 64);
2253 /* Up until now, the param[] array has been indexed by reg + offset
2254 * of UNIFORM registers. Move pull constants into pull_param[] and
2255 * condense param[] to only contain the uniforms we chose to push.
2257 * NOTE: Because we are condensing the params[] array, we know that
2258 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2259 * having to make a copy.
2261 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2262 uint32_t value
= param
[i
];
2263 if (pull_constant_loc
[i
] != -1) {
2264 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2265 } else if (push_constant_loc
[i
] != -1) {
2266 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2273 fs_visitor::get_pull_locs(const fs_reg
&src
,
2274 unsigned *out_surf_index
,
2275 unsigned *out_pull_index
)
2277 assert(src
.file
== UNIFORM
);
2279 if (src
.nr
>= UBO_START
) {
2280 const struct brw_ubo_range
*range
=
2281 &prog_data
->ubo_ranges
[src
.nr
- UBO_START
];
2283 /* If this access is in our (reduced) range, use the push data. */
2284 if (src
.offset
/ 32 < range
->length
)
2287 *out_surf_index
= prog_data
->binding_table
.ubo_start
+ range
->block
;
2288 *out_pull_index
= (32 * range
->start
+ src
.offset
) / 4;
2292 const unsigned location
= src
.nr
+ src
.offset
/ 4;
2294 if (location
< uniforms
&& pull_constant_loc
[location
] != -1) {
2295 /* A regular uniform push constant */
2296 *out_surf_index
= stage_prog_data
->binding_table
.pull_constants_start
;
2297 *out_pull_index
= pull_constant_loc
[location
];
2305 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2306 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2309 fs_visitor::lower_constant_loads()
2311 unsigned index
, pull_index
;
2313 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2314 /* Set up the annotation tracking for new generated instructions. */
2315 const fs_builder
ibld(this, block
, inst
);
2317 for (int i
= 0; i
< inst
->sources
; i
++) {
2318 if (inst
->src
[i
].file
!= UNIFORM
)
2321 /* We'll handle this case later */
2322 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2325 if (!get_pull_locs(inst
->src
[i
], &index
, &pull_index
))
2328 assert(inst
->src
[i
].stride
== 0);
2330 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
2331 const fs_builder ubld
= ibld
.exec_all().group(block_sz
/ 4, 0);
2332 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
2333 const unsigned base
= pull_index
* 4;
2335 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2336 dst
, brw_imm_ud(index
), brw_imm_ud(base
& ~(block_sz
- 1)));
2338 /* Rewrite the instruction to use the temporary VGRF. */
2339 inst
->src
[i
].file
= VGRF
;
2340 inst
->src
[i
].nr
= dst
.nr
;
2341 inst
->src
[i
].offset
= (base
& (block_sz
- 1)) +
2342 inst
->src
[i
].offset
% 4;
2344 brw_mark_surface_used(prog_data
, index
);
2347 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2348 inst
->src
[0].file
== UNIFORM
) {
2350 if (!get_pull_locs(inst
->src
[0], &index
, &pull_index
))
2353 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2357 inst
->remove(block
);
2359 brw_mark_surface_used(prog_data
, index
);
2362 invalidate_live_intervals();
2366 fs_visitor::opt_algebraic()
2368 bool progress
= false;
2370 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2371 switch (inst
->opcode
) {
2372 case BRW_OPCODE_MOV
:
2373 if (inst
->src
[0].file
!= IMM
)
2376 if (inst
->saturate
) {
2377 if (inst
->dst
.type
!= inst
->src
[0].type
)
2378 assert(!"unimplemented: saturate mixed types");
2380 if (brw_saturate_immediate(inst
->dst
.type
,
2381 &inst
->src
[0].as_brw_reg())) {
2382 inst
->saturate
= false;
2388 case BRW_OPCODE_MUL
:
2389 if (inst
->src
[1].file
!= IMM
)
2393 if (inst
->src
[1].is_one()) {
2394 inst
->opcode
= BRW_OPCODE_MOV
;
2395 inst
->src
[1] = reg_undef
;
2401 if (inst
->src
[1].is_negative_one()) {
2402 inst
->opcode
= BRW_OPCODE_MOV
;
2403 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2404 inst
->src
[1] = reg_undef
;
2410 if (inst
->src
[1].is_zero()) {
2411 inst
->opcode
= BRW_OPCODE_MOV
;
2412 inst
->src
[0] = inst
->src
[1];
2413 inst
->src
[1] = reg_undef
;
2418 if (inst
->src
[0].file
== IMM
) {
2419 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2420 inst
->opcode
= BRW_OPCODE_MOV
;
2421 inst
->src
[0].f
*= inst
->src
[1].f
;
2422 inst
->src
[1] = reg_undef
;
2427 case BRW_OPCODE_ADD
:
2428 if (inst
->src
[1].file
!= IMM
)
2432 if (inst
->src
[1].is_zero()) {
2433 inst
->opcode
= BRW_OPCODE_MOV
;
2434 inst
->src
[1] = reg_undef
;
2439 if (inst
->src
[0].file
== IMM
) {
2440 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2441 inst
->opcode
= BRW_OPCODE_MOV
;
2442 inst
->src
[0].f
+= inst
->src
[1].f
;
2443 inst
->src
[1] = reg_undef
;
2449 if (inst
->src
[0].equals(inst
->src
[1]) ||
2450 inst
->src
[1].is_zero()) {
2451 inst
->opcode
= BRW_OPCODE_MOV
;
2452 inst
->src
[1] = reg_undef
;
2457 case BRW_OPCODE_LRP
:
2458 if (inst
->src
[1].equals(inst
->src
[2])) {
2459 inst
->opcode
= BRW_OPCODE_MOV
;
2460 inst
->src
[0] = inst
->src
[1];
2461 inst
->src
[1] = reg_undef
;
2462 inst
->src
[2] = reg_undef
;
2467 case BRW_OPCODE_CMP
:
2468 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2470 inst
->src
[0].negate
&&
2471 inst
->src
[1].is_zero()) {
2472 inst
->src
[0].abs
= false;
2473 inst
->src
[0].negate
= false;
2474 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2479 case BRW_OPCODE_SEL
:
2480 if (inst
->src
[0].equals(inst
->src
[1])) {
2481 inst
->opcode
= BRW_OPCODE_MOV
;
2482 inst
->src
[1] = reg_undef
;
2483 inst
->predicate
= BRW_PREDICATE_NONE
;
2484 inst
->predicate_inverse
= false;
2486 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2487 switch (inst
->conditional_mod
) {
2488 case BRW_CONDITIONAL_LE
:
2489 case BRW_CONDITIONAL_L
:
2490 switch (inst
->src
[1].type
) {
2491 case BRW_REGISTER_TYPE_F
:
2492 if (inst
->src
[1].f
>= 1.0f
) {
2493 inst
->opcode
= BRW_OPCODE_MOV
;
2494 inst
->src
[1] = reg_undef
;
2495 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2503 case BRW_CONDITIONAL_GE
:
2504 case BRW_CONDITIONAL_G
:
2505 switch (inst
->src
[1].type
) {
2506 case BRW_REGISTER_TYPE_F
:
2507 if (inst
->src
[1].f
<= 0.0f
) {
2508 inst
->opcode
= BRW_OPCODE_MOV
;
2509 inst
->src
[1] = reg_undef
;
2510 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2522 case BRW_OPCODE_MAD
:
2523 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2524 inst
->opcode
= BRW_OPCODE_MOV
;
2525 inst
->src
[1] = reg_undef
;
2526 inst
->src
[2] = reg_undef
;
2528 } else if (inst
->src
[0].is_zero()) {
2529 inst
->opcode
= BRW_OPCODE_MUL
;
2530 inst
->src
[0] = inst
->src
[2];
2531 inst
->src
[2] = reg_undef
;
2533 } else if (inst
->src
[1].is_one()) {
2534 inst
->opcode
= BRW_OPCODE_ADD
;
2535 inst
->src
[1] = inst
->src
[2];
2536 inst
->src
[2] = reg_undef
;
2538 } else if (inst
->src
[2].is_one()) {
2539 inst
->opcode
= BRW_OPCODE_ADD
;
2540 inst
->src
[2] = reg_undef
;
2542 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2543 inst
->opcode
= BRW_OPCODE_ADD
;
2544 inst
->src
[1].f
*= inst
->src
[2].f
;
2545 inst
->src
[2] = reg_undef
;
2549 case SHADER_OPCODE_BROADCAST
:
2550 if (is_uniform(inst
->src
[0])) {
2551 inst
->opcode
= BRW_OPCODE_MOV
;
2553 inst
->force_writemask_all
= true;
2555 } else if (inst
->src
[1].file
== IMM
) {
2556 inst
->opcode
= BRW_OPCODE_MOV
;
2557 /* It's possible that the selected component will be too large and
2558 * overflow the register. This can happen if someone does a
2559 * readInvocation() from GLSL or SPIR-V and provides an OOB
2560 * invocationIndex. If this happens and we some how manage
2561 * to constant fold it in and get here, then component() may cause
2562 * us to start reading outside of the VGRF which will lead to an
2563 * assert later. Instead, just let it wrap around if it goes over
2566 const unsigned comp
= inst
->src
[1].ud
& (inst
->exec_size
- 1);
2567 inst
->src
[0] = component(inst
->src
[0], comp
);
2569 inst
->force_writemask_all
= true;
2574 case SHADER_OPCODE_SHUFFLE
:
2575 if (is_uniform(inst
->src
[0])) {
2576 inst
->opcode
= BRW_OPCODE_MOV
;
2579 } else if (inst
->src
[1].file
== IMM
) {
2580 inst
->opcode
= BRW_OPCODE_MOV
;
2581 inst
->src
[0] = component(inst
->src
[0],
2592 /* Swap if src[0] is immediate. */
2593 if (progress
&& inst
->is_commutative()) {
2594 if (inst
->src
[0].file
== IMM
) {
2595 fs_reg tmp
= inst
->src
[1];
2596 inst
->src
[1] = inst
->src
[0];
2605 * Optimize sample messages that have constant zero values for the trailing
2606 * texture coordinates. We can just reduce the message length for these
2607 * instructions instead of reserving a register for it. Trailing parameters
2608 * that aren't sent default to zero anyway. This will cause the dead code
2609 * eliminator to remove the MOV instruction that would otherwise be emitted to
2610 * set up the zero value.
2613 fs_visitor::opt_zero_samples()
2615 /* Gen4 infers the texturing opcode based on the message length so we can't
2618 if (devinfo
->gen
< 5)
2621 bool progress
= false;
2623 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2624 if (!inst
->is_tex())
2627 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2629 if (load_payload
->is_head_sentinel() ||
2630 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2633 /* We don't want to remove the message header or the first parameter.
2634 * Removing the first parameter is not allowed, see the Haswell PRM
2635 * volume 7, page 149:
2637 * "Parameter 0 is required except for the sampleinfo message, which
2638 * has no parameter 0"
2640 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2641 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2642 (inst
->exec_size
/ 8) +
2643 inst
->header_size
- 1].is_zero()) {
2644 inst
->mlen
-= inst
->exec_size
/ 8;
2650 invalidate_live_intervals();
2656 * Optimize sample messages which are followed by the final RT write.
2658 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2659 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2660 * final texturing results copied to the framebuffer write payload and modify
2661 * them to write to the framebuffer directly.
2664 fs_visitor::opt_sampler_eot()
2666 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2668 if (stage
!= MESA_SHADER_FRAGMENT
)
2671 if (devinfo
->gen
!= 9 && !devinfo
->is_cherryview
)
2674 /* FINISHME: It should be possible to implement this optimization when there
2675 * are multiple drawbuffers.
2677 if (key
->nr_color_regions
!= 1)
2680 /* Requires emitting a bunch of saturating MOV instructions during logical
2681 * send lowering to clamp the color payload, which the sampler unit isn't
2682 * going to do for us.
2684 if (key
->clamp_fragment_color
)
2687 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2688 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2689 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2690 assert(fb_write
->eot
);
2691 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2693 /* There wasn't one; nothing to do. */
2694 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2697 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2699 /* 3D Sampler » Messages » Message Format
2701 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2702 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2704 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2705 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2706 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2707 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2708 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2709 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2710 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2711 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2714 /* XXX - This shouldn't be necessary. */
2715 if (tex_inst
->prev
->is_head_sentinel())
2718 /* Check that the FB write sources are fully initialized by the single
2719 * texturing instruction.
2721 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2722 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2723 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2724 fb_write
->size_read(i
) != tex_inst
->size_written
)
2726 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2727 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2732 assert(!tex_inst
->eot
); /* We can't get here twice */
2733 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2735 const fs_builder
ibld(this, block
, tex_inst
);
2737 tex_inst
->offset
|= fb_write
->target
<< 24;
2738 tex_inst
->eot
= true;
2739 tex_inst
->dst
= ibld
.null_reg_ud();
2740 tex_inst
->size_written
= 0;
2741 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2743 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2744 * flag and submit a header together with the sampler message as required
2747 invalidate_live_intervals();
2752 fs_visitor::opt_register_renaming()
2754 bool progress
= false;
2757 int remap
[alloc
.count
];
2758 memset(remap
, -1, sizeof(int) * alloc
.count
);
2760 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2761 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2763 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2764 inst
->opcode
== BRW_OPCODE_WHILE
) {
2768 /* Rewrite instruction sources. */
2769 for (int i
= 0; i
< inst
->sources
; i
++) {
2770 if (inst
->src
[i
].file
== VGRF
&&
2771 remap
[inst
->src
[i
].nr
] != -1 &&
2772 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2773 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2778 const int dst
= inst
->dst
.nr
;
2781 inst
->dst
.file
== VGRF
&&
2782 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
2783 !inst
->is_partial_write()) {
2784 if (remap
[dst
] == -1) {
2787 remap
[dst
] = alloc
.allocate(regs_written(inst
));
2788 inst
->dst
.nr
= remap
[dst
];
2791 } else if (inst
->dst
.file
== VGRF
&&
2793 remap
[dst
] != dst
) {
2794 inst
->dst
.nr
= remap
[dst
];
2800 invalidate_live_intervals();
2802 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2803 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2804 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2813 * Remove redundant or useless discard jumps.
2815 * For example, we can eliminate jumps in the following sequence:
2817 * discard-jump (redundant with the next jump)
2818 * discard-jump (useless; jumps to the next instruction)
2822 fs_visitor::opt_redundant_discard_jumps()
2824 bool progress
= false;
2826 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2828 fs_inst
*placeholder_halt
= NULL
;
2829 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2830 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2831 placeholder_halt
= inst
;
2836 if (!placeholder_halt
)
2839 /* Delete any HALTs immediately before the placeholder halt. */
2840 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2841 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2842 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2843 prev
->remove(last_bblock
);
2848 invalidate_live_intervals();
2854 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2855 * from \p r.offset which overlaps the region starting at \p s.offset and
2856 * spanning \p ds bytes.
2858 static inline unsigned
2859 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
2861 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
2862 const int shift
= rel_offset
/ REG_SIZE
;
2863 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
2864 assert(reg_space(r
) == reg_space(s
) &&
2865 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
2866 return ((1 << n
) - 1) << shift
;
2870 fs_visitor::opt_peephole_csel()
2872 if (devinfo
->gen
< 8)
2875 bool progress
= false;
2877 foreach_block_reverse(block
, cfg
) {
2878 int ip
= block
->end_ip
+ 1;
2880 foreach_inst_in_block_reverse_safe(fs_inst
, inst
, block
) {
2883 if (inst
->opcode
!= BRW_OPCODE_SEL
||
2884 inst
->predicate
!= BRW_PREDICATE_NORMAL
||
2885 (inst
->dst
.type
!= BRW_REGISTER_TYPE_F
&&
2886 inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
2887 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
2890 /* Because it is a 3-src instruction, CSEL cannot have an immediate
2891 * value as a source, but we can sometimes handle zero.
2893 if ((inst
->src
[0].file
!= VGRF
&& inst
->src
[0].file
!= ATTR
&&
2894 inst
->src
[0].file
!= UNIFORM
) ||
2895 (inst
->src
[1].file
!= VGRF
&& inst
->src
[1].file
!= ATTR
&&
2896 inst
->src
[1].file
!= UNIFORM
&& !inst
->src
[1].is_zero()))
2899 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2900 if (!scan_inst
->flags_written())
2903 if ((scan_inst
->opcode
!= BRW_OPCODE_CMP
&&
2904 scan_inst
->opcode
!= BRW_OPCODE_MOV
) ||
2905 scan_inst
->predicate
!= BRW_PREDICATE_NONE
||
2906 (scan_inst
->src
[0].file
!= VGRF
&&
2907 scan_inst
->src
[0].file
!= ATTR
&&
2908 scan_inst
->src
[0].file
!= UNIFORM
) ||
2909 scan_inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
)
2912 if (scan_inst
->opcode
== BRW_OPCODE_CMP
&& !scan_inst
->src
[1].is_zero())
2915 const brw::fs_builder
ibld(this, block
, inst
);
2917 const enum brw_conditional_mod cond
=
2918 inst
->predicate_inverse
2919 ? brw_negate_cmod(scan_inst
->conditional_mod
)
2920 : scan_inst
->conditional_mod
;
2922 fs_inst
*csel_inst
= NULL
;
2924 if (inst
->src
[1].file
!= IMM
) {
2925 csel_inst
= ibld
.CSEL(inst
->dst
,
2930 } else if (cond
== BRW_CONDITIONAL_NZ
) {
2931 /* Consider the sequence
2933 * cmp.nz.f0 null<1>F g3<8,8,1>F 0F
2934 * (+f0) sel g124<1>UD g2<8,8,1>UD 0x00000000UD
2936 * The sel will pick the immediate value 0 if r0 is ±0.0.
2937 * Therefore, this sequence is equivalent:
2939 * cmp.nz.f0 null<1>F g3<8,8,1>F 0F
2940 * (+f0) sel g124<1>F g2<8,8,1>F (abs)g3<8,8,1>F
2942 * The abs is ensures that the result is 0UD when g3 is -0.0F.
2943 * By normal cmp-sel merging, this is also equivalent:
2945 * csel.nz g124<1>F g2<4,4,1>F (abs)g3<4,4,1>F g3<4,4,1>F
2947 csel_inst
= ibld
.CSEL(inst
->dst
,
2953 csel_inst
->src
[1].abs
= true;
2956 if (csel_inst
!= NULL
) {
2958 inst
->remove(block
);
2970 fs_visitor::compute_to_mrf()
2972 bool progress
= false;
2975 /* No MRFs on Gen >= 7. */
2976 if (devinfo
->gen
>= 7)
2979 calculate_live_intervals();
2981 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2985 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2986 inst
->is_partial_write() ||
2987 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2988 inst
->dst
.type
!= inst
->src
[0].type
||
2989 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2990 !inst
->src
[0].is_contiguous() ||
2991 inst
->src
[0].offset
% REG_SIZE
!= 0)
2994 /* Can't compute-to-MRF this GRF if someone else was going to
2997 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
3000 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
3001 * things that computed the value of all GRFs of the source region. The
3002 * regs_left bitset keeps track of the registers we haven't yet found a
3003 * generating instruction for.
3005 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
3007 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3008 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3009 inst
->src
[0], inst
->size_read(0))) {
3010 /* Found the last thing to write our reg we want to turn
3011 * into a compute-to-MRF.
3014 /* If this one instruction didn't populate all the
3015 * channels, bail. We might be able to rewrite everything
3016 * that writes that reg, but it would require smarter
3019 if (scan_inst
->is_partial_write())
3022 /* Handling things not fully contained in the source of the copy
3023 * would need us to understand coalescing out more than one MOV at
3026 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
3027 inst
->src
[0], inst
->size_read(0)))
3030 /* SEND instructions can't have MRF as a destination. */
3031 if (scan_inst
->mlen
)
3034 if (devinfo
->gen
== 6) {
3035 /* gen6 math instructions must have the destination be
3036 * GRF, so no compute-to-MRF for them.
3038 if (scan_inst
->is_math()) {
3043 /* Clear the bits for any registers this instruction overwrites. */
3044 regs_left
&= ~mask_relative_to(
3045 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3050 /* We don't handle control flow here. Most computation of
3051 * values that end up in MRFs are shortly before the MRF
3054 if (block
->start() == scan_inst
)
3057 /* You can't read from an MRF, so if someone else reads our
3058 * MRF's source GRF that we wanted to rewrite, that stops us.
3060 bool interfered
= false;
3061 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
3062 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
3063 inst
->src
[0], inst
->size_read(0))) {
3070 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3071 inst
->dst
, inst
->size_written
)) {
3072 /* If somebody else writes our MRF here, we can't
3073 * compute-to-MRF before that.
3078 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
3079 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
3080 inst
->dst
, inst
->size_written
)) {
3081 /* Found a SEND instruction, which means that there are
3082 * live values in MRFs from base_mrf to base_mrf +
3083 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3093 /* Found all generating instructions of our MRF's source value, so it
3094 * should be safe to rewrite them to point to the MRF directly.
3096 regs_left
= (1 << regs_read(inst
, 0)) - 1;
3098 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3099 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3100 inst
->src
[0], inst
->size_read(0))) {
3101 /* Clear the bits for any registers this instruction overwrites. */
3102 regs_left
&= ~mask_relative_to(
3103 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3105 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
3106 reg_offset(inst
->src
[0]);
3108 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
3109 /* Apply the same address transformation done by the hardware
3110 * for COMPR4 MRF writes.
3112 assert(rel_offset
< 2 * REG_SIZE
);
3113 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
3115 /* Clear the COMPR4 bit if the generating instruction is not
3118 if (scan_inst
->size_written
< 2 * REG_SIZE
)
3119 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
3122 /* Calculate the MRF number the result of this instruction is
3123 * ultimately written to.
3125 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
3128 scan_inst
->dst
.file
= MRF
;
3129 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
3130 scan_inst
->saturate
|= inst
->saturate
;
3137 inst
->remove(block
);
3142 invalidate_live_intervals();
3148 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
3149 * flow. We could probably do better here with some form of divergence
3153 fs_visitor::eliminate_find_live_channel()
3155 bool progress
= false;
3158 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
3159 /* The optimization below assumes that channel zero is live on thread
3160 * dispatch, which may not be the case if the fixed function dispatches
3166 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3167 switch (inst
->opcode
) {
3173 case BRW_OPCODE_ENDIF
:
3174 case BRW_OPCODE_WHILE
:
3178 case FS_OPCODE_DISCARD_JUMP
:
3179 /* This can potentially make control flow non-uniform until the end
3184 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
3186 inst
->opcode
= BRW_OPCODE_MOV
;
3187 inst
->src
[0] = brw_imm_ud(0u);
3189 inst
->force_writemask_all
= true;
3203 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
3204 * instructions to FS_OPCODE_REP_FB_WRITE.
3207 fs_visitor::emit_repclear_shader()
3209 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3211 int color_mrf
= base_mrf
+ 2;
3215 mov
= bld
.exec_all().group(4, 0)
3216 .MOV(brw_message_reg(color_mrf
),
3217 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
3219 struct brw_reg reg
=
3220 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
3221 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
3222 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
3224 mov
= bld
.exec_all().group(4, 0)
3225 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
3228 fs_inst
*write
= NULL
;
3229 if (key
->nr_color_regions
== 1) {
3230 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3231 write
->saturate
= key
->clamp_fragment_color
;
3232 write
->base_mrf
= color_mrf
;
3234 write
->header_size
= 0;
3237 assume(key
->nr_color_regions
> 0);
3239 struct brw_reg header
=
3240 retype(brw_message_reg(base_mrf
), BRW_REGISTER_TYPE_UD
);
3241 bld
.exec_all().group(16, 0)
3242 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3244 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
3246 bld
.exec_all().group(1, 0)
3247 .MOV(component(header
, 2), brw_imm_ud(i
));
3250 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3251 write
->saturate
= key
->clamp_fragment_color
;
3252 write
->base_mrf
= base_mrf
;
3254 write
->header_size
= 2;
3259 write
->last_rt
= true;
3263 assign_constant_locations();
3264 assign_curb_setup();
3266 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3268 assert(mov
->src
[0].file
== FIXED_GRF
);
3269 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3274 * Walks through basic blocks, looking for repeated MRF writes and
3275 * removing the later ones.
3278 fs_visitor::remove_duplicate_mrf_writes()
3280 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3281 bool progress
= false;
3283 /* Need to update the MRF tracking for compressed instructions. */
3284 if (dispatch_width
>= 16)
3287 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3289 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3290 if (inst
->is_control_flow()) {
3291 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3294 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3295 inst
->dst
.file
== MRF
) {
3296 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3297 if (prev_inst
&& inst
->equals(prev_inst
)) {
3298 inst
->remove(block
);
3304 /* Clear out the last-write records for MRFs that were overwritten. */
3305 if (inst
->dst
.file
== MRF
) {
3306 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3309 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3310 /* Found a SEND instruction, which will include two or fewer
3311 * implied MRF writes. We could do better here.
3313 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3314 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3318 /* Clear out any MRF move records whose sources got overwritten. */
3319 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3320 if (last_mrf_move
[i
] &&
3321 regions_overlap(inst
->dst
, inst
->size_written
,
3322 last_mrf_move
[i
]->src
[0],
3323 last_mrf_move
[i
]->size_read(0))) {
3324 last_mrf_move
[i
] = NULL
;
3328 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3329 inst
->dst
.file
== MRF
&&
3330 inst
->src
[0].file
!= ARF
&&
3331 !inst
->is_partial_write()) {
3332 last_mrf_move
[inst
->dst
.nr
] = inst
;
3337 invalidate_live_intervals();
3343 * Rounding modes for conversion instructions are included for each
3344 * conversion, but right now it is a state. So once it is set,
3345 * we don't need to call it again for subsequent calls.
3347 * This is useful for vector/matrices conversions, as setting the
3348 * mode once is enough for the full vector/matrix
3351 fs_visitor::remove_extra_rounding_modes()
3353 bool progress
= false;
3355 foreach_block (block
, cfg
) {
3356 brw_rnd_mode prev_mode
= BRW_RND_MODE_UNSPECIFIED
;
3358 foreach_inst_in_block_safe (fs_inst
, inst
, block
) {
3359 if (inst
->opcode
== SHADER_OPCODE_RND_MODE
) {
3360 assert(inst
->src
[0].file
== BRW_IMMEDIATE_VALUE
);
3361 const brw_rnd_mode mode
= (brw_rnd_mode
) inst
->src
[0].d
;
3362 if (mode
== prev_mode
) {
3363 inst
->remove(block
);
3373 invalidate_live_intervals();
3379 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3381 /* Clear the flag for registers that actually got read (as expected). */
3382 for (int i
= 0; i
< inst
->sources
; i
++) {
3384 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3385 grf
= inst
->src
[i
].nr
;
3390 if (grf
>= first_grf
&&
3391 grf
< first_grf
+ grf_len
) {
3392 deps
[grf
- first_grf
] = false;
3393 if (inst
->exec_size
== 16)
3394 deps
[grf
- first_grf
+ 1] = false;
3400 * Implements this workaround for the original 965:
3402 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3403 * check for post destination dependencies on this instruction, software
3404 * must ensure that there is no destination hazard for the case of ‘write
3405 * followed by a posted write’ shown in the following example.
3408 * 2. send r3.xy <rest of send instruction>
3411 * Due to no post-destination dependency check on the ‘send’, the above
3412 * code sequence could have two instructions (1 and 2) in flight at the
3413 * same time that both consider ‘r3’ as the target of their final writes.
3416 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3419 int write_len
= regs_written(inst
);
3420 int first_write_grf
= inst
->dst
.nr
;
3421 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3422 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3424 memset(needs_dep
, false, sizeof(needs_dep
));
3425 memset(needs_dep
, true, write_len
);
3427 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3429 /* Walk backwards looking for writes to registers we're writing which
3430 * aren't read since being written. If we hit the start of the program,
3431 * we assume that there are no outstanding dependencies on entry to the
3434 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3435 /* If we hit control flow, assume that there *are* outstanding
3436 * dependencies, and force their cleanup before our instruction.
3438 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3439 for (int i
= 0; i
< write_len
; i
++) {
3441 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3442 first_write_grf
+ i
);
3447 /* We insert our reads as late as possible on the assumption that any
3448 * instruction but a MOV that might have left us an outstanding
3449 * dependency has more latency than a MOV.
3451 if (scan_inst
->dst
.file
== VGRF
) {
3452 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3453 int reg
= scan_inst
->dst
.nr
+ i
;
3455 if (reg
>= first_write_grf
&&
3456 reg
< first_write_grf
+ write_len
&&
3457 needs_dep
[reg
- first_write_grf
]) {
3458 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3459 needs_dep
[reg
- first_write_grf
] = false;
3460 if (scan_inst
->exec_size
== 16)
3461 needs_dep
[reg
- first_write_grf
+ 1] = false;
3466 /* Clear the flag for registers that actually got read (as expected). */
3467 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3469 /* Continue the loop only if we haven't resolved all the dependencies */
3471 for (i
= 0; i
< write_len
; i
++) {
3481 * Implements this workaround for the original 965:
3483 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3484 * used as a destination register until after it has been sourced by an
3485 * instruction with a different destination register.
3488 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3490 int write_len
= regs_written(inst
);
3491 int first_write_grf
= inst
->dst
.nr
;
3492 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3493 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3495 memset(needs_dep
, false, sizeof(needs_dep
));
3496 memset(needs_dep
, true, write_len
);
3497 /* Walk forwards looking for writes to registers we're writing which aren't
3498 * read before being written.
3500 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3501 /* If we hit control flow, force resolve all remaining dependencies. */
3502 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3503 for (int i
= 0; i
< write_len
; i
++) {
3505 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3506 first_write_grf
+ i
);
3511 /* Clear the flag for registers that actually got read (as expected). */
3512 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3514 /* We insert our reads as late as possible since they're reading the
3515 * result of a SEND, which has massive latency.
3517 if (scan_inst
->dst
.file
== VGRF
&&
3518 scan_inst
->dst
.nr
>= first_write_grf
&&
3519 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3520 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3521 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3523 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3526 /* Continue the loop only if we haven't resolved all the dependencies */
3528 for (i
= 0; i
< write_len
; i
++) {
3538 fs_visitor::insert_gen4_send_dependency_workarounds()
3540 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3543 bool progress
= false;
3545 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3546 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3547 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3548 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3554 invalidate_live_intervals();
3558 * Turns the generic expression-style uniform pull constant load instruction
3559 * into a hardware-specific series of instructions for loading a pull
3562 * The expression style allows the CSE pass before this to optimize out
3563 * repeated loads from the same offset, and gives the pre-register-allocation
3564 * scheduling full flexibility, while the conversion to native instructions
3565 * allows the post-register-allocation scheduler the best information
3568 * Note that execution masking for setting up pull constant loads is special:
3569 * the channels that need to be written are unrelated to the current execution
3570 * mask, since a later instruction will use one of the result channels as a
3571 * source operand for all 8 or 16 of its channels.
3574 fs_visitor::lower_uniform_pull_constant_loads()
3576 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3577 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3580 if (devinfo
->gen
>= 7) {
3581 const fs_builder ubld
= fs_builder(this, block
, inst
).exec_all();
3582 const fs_reg payload
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
);
3584 ubld
.group(8, 0).MOV(payload
,
3585 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3586 ubld
.group(1, 0).MOV(component(payload
, 2),
3587 brw_imm_ud(inst
->src
[1].ud
/ 16));
3589 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3590 inst
->src
[1] = payload
;
3591 inst
->header_size
= 1;
3594 invalidate_live_intervals();
3596 /* Before register allocation, we didn't tell the scheduler about the
3597 * MRF we use. We know it's safe to use this MRF because nothing
3598 * else does except for register spill/unspill, which generates and
3599 * uses its MRF within a single IR instruction.
3601 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3608 fs_visitor::lower_load_payload()
3610 bool progress
= false;
3612 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3613 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3616 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3617 assert(inst
->saturate
== false);
3618 fs_reg dst
= inst
->dst
;
3620 /* Get rid of COMPR4. We'll add it back in if we need it */
3621 if (dst
.file
== MRF
)
3622 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3624 const fs_builder
ibld(this, block
, inst
);
3625 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3627 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3628 if (inst
->src
[i
].file
!= BAD_FILE
) {
3629 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3630 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3631 hbld
.MOV(mov_dst
, mov_src
);
3633 dst
= offset(dst
, hbld
, 1);
3636 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3637 inst
->exec_size
> 8) {
3638 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3639 * a straightforward copy. Instead, the result of the
3640 * LOAD_PAYLOAD is treated as interleaved and the first four
3641 * non-header sources are unpacked as:
3652 * This is used for gen <= 5 fb writes.
3654 assert(inst
->exec_size
== 16);
3655 assert(inst
->header_size
+ 4 <= inst
->sources
);
3656 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3657 if (inst
->src
[i
].file
!= BAD_FILE
) {
3658 if (devinfo
->has_compr4
) {
3659 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3660 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3661 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3663 /* Platform doesn't have COMPR4. We have to fake it */
3664 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3665 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3667 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3674 /* The loop above only ever incremented us through the first set
3675 * of 4 registers. However, thanks to the magic of COMPR4, we
3676 * actually wrote to the first 8 registers, so we need to take
3677 * that into account now.
3681 /* The COMPR4 code took care of the first 4 sources. We'll let
3682 * the regular path handle any remaining sources. Yes, we are
3683 * modifying the instruction but we're about to delete it so
3684 * this really doesn't hurt anything.
3686 inst
->header_size
+= 4;
3689 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3690 if (inst
->src
[i
].file
!= BAD_FILE
)
3691 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3692 dst
= offset(dst
, ibld
, 1);
3695 inst
->remove(block
);
3700 invalidate_live_intervals();
3706 fs_visitor::lower_integer_multiplication()
3708 bool progress
= false;
3710 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3711 const fs_builder
ibld(this, block
, inst
);
3713 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3714 if (inst
->dst
.is_accumulator() ||
3715 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3716 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3719 if (devinfo
->has_integer_dword_mul
)
3722 if (inst
->src
[1].file
== IMM
&&
3723 inst
->src
[1].ud
< (1 << 16)) {
3724 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3725 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3728 * If multiplying by an immediate value that fits in 16-bits, do a
3729 * single MUL instruction with that value in the proper location.
3731 if (devinfo
->gen
< 7) {
3732 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3734 ibld
.MOV(imm
, inst
->src
[1]);
3735 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3737 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3738 ibld
.MUL(inst
->dst
, inst
->src
[0],
3739 ud
? brw_imm_uw(inst
->src
[1].ud
)
3740 : brw_imm_w(inst
->src
[1].d
));
3743 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3744 * do 32-bit integer multiplication in one instruction, but instead
3745 * must do a sequence (which actually calculates a 64-bit result):
3747 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3748 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3749 * mov(8) g2<1>D acc0<8,8,1>D
3751 * But on Gen > 6, the ability to use second accumulator register
3752 * (acc1) for non-float data types was removed, preventing a simple
3753 * implementation in SIMD16. A 16-channel result can be calculated by
3754 * executing the three instructions twice in SIMD8, once with quarter
3755 * control of 1Q for the first eight channels and again with 2Q for
3756 * the second eight channels.
3758 * Which accumulator register is implicitly accessed (by AccWrEnable
3759 * for instance) is determined by the quarter control. Unfortunately
3760 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3761 * implicit accumulator access by an instruction with 2Q will access
3762 * acc1 regardless of whether the data type is usable in acc1.
3764 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3765 * integer data types.
3767 * Since we only want the low 32-bits of the result, we can do two
3768 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3769 * adjust the high result and add them (like the mach is doing):
3771 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3772 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3773 * shl(8) g9<1>D g8<8,8,1>D 16D
3774 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3776 * We avoid the shl instruction by realizing that we only want to add
3777 * the low 16-bits of the "high" result to the high 16-bits of the
3778 * "low" result and using proper regioning on the add:
3780 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3781 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3782 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3784 * Since it does not use the (single) accumulator register, we can
3785 * schedule multi-component multiplications much better.
3788 bool needs_mov
= false;
3789 fs_reg orig_dst
= inst
->dst
;
3790 fs_reg low
= inst
->dst
;
3791 if (orig_dst
.is_null() || orig_dst
.file
== MRF
||
3792 regions_overlap(inst
->dst
, inst
->size_written
,
3793 inst
->src
[0], inst
->size_read(0)) ||
3794 regions_overlap(inst
->dst
, inst
->size_written
,
3795 inst
->src
[1], inst
->size_read(1))) {
3797 /* Get a new VGRF but keep the same stride as inst->dst */
3798 low
= fs_reg(VGRF
, alloc
.allocate(regs_written(inst
)),
3800 low
.stride
= inst
->dst
.stride
;
3801 low
.offset
= inst
->dst
.offset
% REG_SIZE
;
3804 /* Get a new VGRF but keep the same stride as inst->dst */
3805 fs_reg
high(VGRF
, alloc
.allocate(regs_written(inst
)),
3807 high
.stride
= inst
->dst
.stride
;
3808 high
.offset
= inst
->dst
.offset
% REG_SIZE
;
3810 if (devinfo
->gen
>= 7) {
3811 if (inst
->src
[1].file
== IMM
) {
3812 ibld
.MUL(low
, inst
->src
[0],
3813 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
3814 ibld
.MUL(high
, inst
->src
[0],
3815 brw_imm_uw(inst
->src
[1].ud
>> 16));
3817 ibld
.MUL(low
, inst
->src
[0],
3818 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
3819 ibld
.MUL(high
, inst
->src
[0],
3820 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
3823 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
3825 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
3829 ibld
.ADD(subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3830 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3831 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
3833 if (needs_mov
|| inst
->conditional_mod
) {
3834 set_condmod(inst
->conditional_mod
,
3835 ibld
.MOV(orig_dst
, low
));
3839 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3840 /* Should have been lowered to 8-wide. */
3841 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
3842 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3844 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3845 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3847 if (devinfo
->gen
>= 8) {
3848 /* Until Gen8, integer multiplies read 32-bits from one source,
3849 * and 16-bits from the other, and relying on the MACH instruction
3850 * to generate the high bits of the result.
3852 * On Gen8, the multiply instruction does a full 32x32-bit
3853 * multiply, but in order to do a 64-bit multiply we can simulate
3854 * the previous behavior and then use a MACH instruction.
3856 * FINISHME: Don't use source modifiers on src1.
3858 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3859 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3860 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3861 mul
->src
[1].stride
*= 2;
3863 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3865 /* Among other things the quarter control bits influence which
3866 * accumulator register is used by the hardware for instructions
3867 * that access the accumulator implicitly (e.g. MACH). A
3868 * second-half instruction would normally map to acc1, which
3869 * doesn't exist on Gen7 and up (the hardware does emulate it for
3870 * floating-point instructions *only* by taking advantage of the
3871 * extra precision of acc0 not normally used for floating point
3874 * HSW and up are careful enough not to try to access an
3875 * accumulator register that doesn't exist, but on earlier Gen7
3876 * hardware we need to make sure that the quarter control bits are
3877 * zero to avoid non-deterministic behaviour and emit an extra MOV
3878 * to get the result masked correctly according to the current
3882 mach
->force_writemask_all
= true;
3883 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3884 ibld
.MOV(inst
->dst
, mach
->dst
);
3890 inst
->remove(block
);
3895 invalidate_live_intervals();
3901 fs_visitor::lower_minmax()
3903 assert(devinfo
->gen
< 6);
3905 bool progress
= false;
3907 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3908 const fs_builder
ibld(this, block
, inst
);
3910 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3911 inst
->predicate
== BRW_PREDICATE_NONE
) {
3912 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3913 * the original SEL.L/GE instruction
3915 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3916 inst
->conditional_mod
);
3917 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3918 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3925 invalidate_live_intervals();
3931 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3932 fs_reg
*dst
, fs_reg color
, unsigned components
)
3934 if (key
->clamp_fragment_color
) {
3935 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3936 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3938 for (unsigned i
= 0; i
< components
; i
++)
3940 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3945 for (unsigned i
= 0; i
< components
; i
++)
3946 dst
[i
] = offset(color
, bld
, i
);
3950 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3951 const struct brw_wm_prog_data
*prog_data
,
3952 const brw_wm_prog_key
*key
,
3953 const fs_visitor::thread_payload
&payload
)
3955 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3956 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3957 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3958 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3959 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3960 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3961 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3962 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3963 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3964 const unsigned components
=
3965 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3967 /* We can potentially have a message length of up to 15, so we have to set
3968 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3971 int header_size
= 2, payload_header_size
;
3972 unsigned length
= 0;
3974 if (devinfo
->gen
< 6) {
3975 /* TODO: Support SIMD32 on gen4-5 */
3976 assert(bld
.group() < 16);
3978 /* For gen4-5, we always have a header consisting of g0 and g1. We have
3979 * an implied MOV from g0,g1 to the start of the message. The MOV from
3980 * g0 is handled by the hardware and the MOV from g1 is provided by the
3981 * generator. This is required because, on gen4-5, the generator may
3982 * generate two write messages with different message lengths in order
3983 * to handle AA data properly.
3985 * Also, since the pixel mask goes in the g0 portion of the message and
3986 * since render target writes are the last thing in the shader, we write
3987 * the pixel mask directly into g0 and it will get copied as part of the
3990 if (prog_data
->uses_kill
) {
3991 bld
.exec_all().group(1, 0)
3992 .MOV(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
),
3993 brw_flag_reg(0, 1));
3996 assert(length
== 0);
3998 } else if ((devinfo
->gen
<= 7 && !devinfo
->is_haswell
&&
3999 prog_data
->uses_kill
) ||
4000 color1
.file
!= BAD_FILE
||
4001 key
->nr_color_regions
> 1) {
4002 /* From the Sandy Bridge PRM, volume 4, page 198:
4004 * "Dispatched Pixel Enables. One bit per pixel indicating
4005 * which pixels were originally enabled when the thread was
4006 * dispatched. This field is only required for the end-of-
4007 * thread message and on all dual-source messages."
4009 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4011 fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4012 if (bld
.group() < 16) {
4013 /* The header starts off as g0 and g1 for the first half */
4014 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4015 BRW_REGISTER_TYPE_UD
));
4017 /* The header starts off as g0 and g2 for the second half */
4018 assert(bld
.group() < 32);
4019 const fs_reg header_sources
[2] = {
4020 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4021 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
),
4023 ubld
.LOAD_PAYLOAD(header
, header_sources
, 2, 0);
4026 uint32_t g00_bits
= 0;
4028 /* Set "Source0 Alpha Present to RenderTarget" bit in message
4031 if (inst
->target
> 0 && key
->replicate_alpha
)
4032 g00_bits
|= 1 << 11;
4034 /* Set computes stencil to render target */
4035 if (prog_data
->computed_stencil
)
4036 g00_bits
|= 1 << 14;
4039 /* OR extra bits into g0.0 */
4040 ubld
.group(1, 0).OR(component(header
, 0),
4041 retype(brw_vec1_grf(0, 0),
4042 BRW_REGISTER_TYPE_UD
),
4043 brw_imm_ud(g00_bits
));
4046 /* Set the render target index for choosing BLEND_STATE. */
4047 if (inst
->target
> 0) {
4048 ubld
.group(1, 0).MOV(component(header
, 2), brw_imm_ud(inst
->target
));
4051 if (prog_data
->uses_kill
) {
4052 assert(bld
.group() < 16);
4053 ubld
.group(1, 0).MOV(retype(component(header
, 15),
4054 BRW_REGISTER_TYPE_UW
),
4055 brw_flag_reg(0, 1));
4058 assert(length
== 0);
4059 sources
[0] = header
;
4060 sources
[1] = horiz_offset(header
, 8);
4063 assert(length
== 0 || length
== 2);
4064 header_size
= length
;
4066 if (payload
.aa_dest_stencil_reg
) {
4067 assert(inst
->group
< 16);
4068 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
4069 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
4070 .MOV(sources
[length
],
4071 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
4075 if (sample_mask
.file
!= BAD_FILE
) {
4076 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
4077 BRW_REGISTER_TYPE_UD
);
4079 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
4080 * relevant. Since it's unsigned single words one vgrf is always
4081 * 16-wide, but only the lower or higher 8 channels will be used by the
4082 * hardware when doing a SIMD8 write depending on whether we have
4083 * selected the subspans for the first or second half respectively.
4085 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
4086 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
4087 sample_mask
.stride
*= 2;
4089 bld
.exec_all().annotate("FB write oMask")
4090 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
4096 payload_header_size
= length
;
4098 if (src0_alpha
.file
!= BAD_FILE
) {
4099 /* FIXME: This is being passed at the wrong location in the payload and
4100 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
4101 * It's supposed to be immediately before oMask but there seems to be no
4102 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
4103 * requires header sources to form a contiguous segment at the beginning
4104 * of the message and src0_alpha has per-channel semantics.
4106 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
4108 } else if (key
->replicate_alpha
&& inst
->target
!= 0) {
4109 /* Handle the case when fragment shader doesn't write to draw buffer
4110 * zero. No need to call setup_color_payload() for src0_alpha because
4111 * alpha value will be undefined.
4116 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
4119 if (color1
.file
!= BAD_FILE
) {
4120 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
4124 if (src_depth
.file
!= BAD_FILE
) {
4125 sources
[length
] = src_depth
;
4129 if (dst_depth
.file
!= BAD_FILE
) {
4130 sources
[length
] = dst_depth
;
4134 if (src_stencil
.file
!= BAD_FILE
) {
4135 assert(devinfo
->gen
>= 9);
4136 assert(bld
.dispatch_width() == 8);
4138 /* XXX: src_stencil is only available on gen9+. dst_depth is never
4139 * available on gen9+. As such it's impossible to have both enabled at the
4140 * same time and therefore length cannot overrun the array.
4142 assert(length
< 15);
4144 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4145 bld
.exec_all().annotate("FB write OS")
4146 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
4147 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
4152 if (devinfo
->gen
>= 7) {
4153 /* Send from the GRF */
4154 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
4155 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
4156 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
4157 load
->dst
= payload
;
4159 inst
->src
[0] = payload
;
4160 inst
->resize_sources(1);
4162 /* Send from the MRF */
4163 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
4164 sources
, length
, payload_header_size
);
4166 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
4167 * will do this for us if we just give it a COMPR4 destination.
4169 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
4170 load
->dst
.nr
|= BRW_MRF_COMPR4
;
4172 if (devinfo
->gen
< 6) {
4173 /* Set up src[0] for the implied MOV from grf0-1 */
4174 inst
->resize_sources(1);
4175 inst
->src
[0] = brw_vec8_grf(0, 0);
4177 inst
->resize_sources(0);
4182 inst
->opcode
= FS_OPCODE_FB_WRITE
;
4183 inst
->mlen
= regs_written(load
);
4184 inst
->header_size
= header_size
;
4188 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4190 const fs_builder
&ubld
= bld
.exec_all();
4191 const unsigned length
= 2;
4192 const fs_reg header
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
, length
);
4195 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
4197 inst
->resize_sources(1);
4198 inst
->src
[0] = header
;
4199 inst
->opcode
= FS_OPCODE_FB_READ
;
4200 inst
->mlen
= length
;
4201 inst
->header_size
= length
;
4205 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4206 const fs_reg
&coordinate
,
4207 const fs_reg
&shadow_c
,
4208 const fs_reg
&lod
, const fs_reg
&lod2
,
4209 const fs_reg
&surface
,
4210 const fs_reg
&sampler
,
4211 unsigned coord_components
,
4212 unsigned grad_components
)
4214 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
4215 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
4216 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
4217 fs_reg msg_end
= msg_begin
;
4220 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
4222 for (unsigned i
= 0; i
< coord_components
; i
++)
4223 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
4224 offset(coordinate
, bld
, i
));
4226 msg_end
= offset(msg_end
, bld
, coord_components
);
4228 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
4229 * require all three components to be present and zero if they are unused.
4231 if (coord_components
> 0 &&
4232 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
4233 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
4234 for (unsigned i
= coord_components
; i
< 3; i
++)
4235 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
4237 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
4240 if (op
== SHADER_OPCODE_TXD
) {
4241 /* TXD unsupported in SIMD16 mode. */
4242 assert(bld
.dispatch_width() == 8);
4244 /* the slots for u and v are always present, but r is optional */
4245 if (coord_components
< 2)
4246 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
4249 * dPdx = dudx, dvdx, drdx
4250 * dPdy = dudy, dvdy, drdy
4252 * 1-arg: Does not exist.
4254 * 2-arg: dudx dvdx dudy dvdy
4255 * dPdx.x dPdx.y dPdy.x dPdy.y
4258 * 3-arg: dudx dvdx drdx dudy dvdy drdy
4259 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
4260 * m5 m6 m7 m8 m9 m10
4262 for (unsigned i
= 0; i
< grad_components
; i
++)
4263 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
4265 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4267 for (unsigned i
= 0; i
< grad_components
; i
++)
4268 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
4270 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4274 /* Bias/LOD with shadow comparator is unsupported in SIMD16 -- *Without*
4275 * shadow comparator (including RESINFO) it's unsupported in SIMD8 mode.
4277 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
4278 bld
.dispatch_width() == 16);
4280 const brw_reg_type type
=
4281 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
4282 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
4283 bld
.MOV(retype(msg_end
, type
), lod
);
4284 msg_end
= offset(msg_end
, bld
, 1);
4287 if (shadow_c
.file
!= BAD_FILE
) {
4288 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
4289 /* There's no plain shadow compare message, so we use shadow
4290 * compare with a bias of 0.0.
4292 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
4293 msg_end
= offset(msg_end
, bld
, 1);
4296 bld
.MOV(msg_end
, shadow_c
);
4297 msg_end
= offset(msg_end
, bld
, 1);
4301 inst
->src
[0] = reg_undef
;
4302 inst
->src
[1] = surface
;
4303 inst
->src
[2] = sampler
;
4304 inst
->resize_sources(3);
4305 inst
->base_mrf
= msg_begin
.nr
;
4306 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
4307 inst
->header_size
= 1;
4311 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4312 const fs_reg
&coordinate
,
4313 const fs_reg
&shadow_c
,
4314 const fs_reg
&lod
, const fs_reg
&lod2
,
4315 const fs_reg
&sample_index
,
4316 const fs_reg
&surface
,
4317 const fs_reg
&sampler
,
4318 unsigned coord_components
,
4319 unsigned grad_components
)
4321 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
4322 fs_reg msg_coords
= message
;
4323 unsigned header_size
= 0;
4325 if (inst
->offset
!= 0) {
4326 /* The offsets set up by the visitor are in the m1 header, so we can't
4333 for (unsigned i
= 0; i
< coord_components
; i
++)
4334 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
4335 offset(coordinate
, bld
, i
));
4337 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
4338 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
4340 if (shadow_c
.file
!= BAD_FILE
) {
4341 fs_reg msg_shadow
= msg_lod
;
4342 bld
.MOV(msg_shadow
, shadow_c
);
4343 msg_lod
= offset(msg_shadow
, bld
, 1);
4348 case SHADER_OPCODE_TXL
:
4350 bld
.MOV(msg_lod
, lod
);
4351 msg_end
= offset(msg_lod
, bld
, 1);
4353 case SHADER_OPCODE_TXD
:
4356 * dPdx = dudx, dvdx, drdx
4357 * dPdy = dudy, dvdy, drdy
4359 * Load up these values:
4360 * - dudx dudy dvdx dvdy drdx drdy
4361 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
4364 for (unsigned i
= 0; i
< grad_components
; i
++) {
4365 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
4366 msg_end
= offset(msg_end
, bld
, 1);
4368 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
4369 msg_end
= offset(msg_end
, bld
, 1);
4372 case SHADER_OPCODE_TXS
:
4373 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4374 bld
.MOV(msg_lod
, lod
);
4375 msg_end
= offset(msg_lod
, bld
, 1);
4377 case SHADER_OPCODE_TXF
:
4378 msg_lod
= offset(msg_coords
, bld
, 3);
4379 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4380 msg_end
= offset(msg_lod
, bld
, 1);
4382 case SHADER_OPCODE_TXF_CMS
:
4383 msg_lod
= offset(msg_coords
, bld
, 3);
4385 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4387 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4388 msg_end
= offset(msg_lod
, bld
, 2);
4395 inst
->src
[0] = reg_undef
;
4396 inst
->src
[1] = surface
;
4397 inst
->src
[2] = sampler
;
4398 inst
->resize_sources(3);
4399 inst
->base_mrf
= message
.nr
;
4400 inst
->mlen
= msg_end
.nr
- message
.nr
;
4401 inst
->header_size
= header_size
;
4403 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4404 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4408 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
4410 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4413 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4417 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4418 const fs_reg
&coordinate
,
4419 const fs_reg
&shadow_c
,
4420 fs_reg lod
, const fs_reg
&lod2
,
4421 const fs_reg
&sample_index
,
4423 const fs_reg
&surface
,
4424 const fs_reg
&sampler
,
4425 const fs_reg
&tg4_offset
,
4426 unsigned coord_components
,
4427 unsigned grad_components
)
4429 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4430 unsigned reg_width
= bld
.dispatch_width() / 8;
4431 unsigned header_size
= 0, length
= 0;
4432 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4433 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4434 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4436 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4437 inst
->offset
!= 0 || inst
->eot
||
4438 op
== SHADER_OPCODE_SAMPLEINFO
||
4439 is_high_sampler(devinfo
, sampler
)) {
4440 /* For general texture offsets (no txf workaround), we need a header to
4443 * TG4 needs to place its channel select in the header, for interaction
4444 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4445 * larger sampler numbers we need to offset the Sampler State Pointer in
4448 fs_reg header
= retype(sources
[0], BRW_REGISTER_TYPE_UD
);
4452 /* If we're requesting fewer than four channels worth of response,
4453 * and we have an explicit header, we need to set up the sampler
4454 * writemask. It's reversed from normal: 1 means "don't write".
4456 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4457 assert(regs_written(inst
) % reg_width
== 0);
4458 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4459 inst
->offset
|= mask
<< 12;
4462 /* Build the actual header */
4463 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4464 const fs_builder ubld1
= ubld
.group(1, 0);
4465 ubld
.MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
4467 ubld1
.MOV(component(header
, 2), brw_imm_ud(inst
->offset
));
4468 } else if (bld
.shader
->stage
!= MESA_SHADER_VERTEX
&&
4469 bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
) {
4470 /* The vertex and fragment stages have g0.2 set to 0, so
4471 * header0.2 is 0 when g0 is copied. Other stages may not, so we
4472 * must set it to 0 to avoid setting undesirable bits in the
4475 ubld1
.MOV(component(header
, 2), brw_imm_ud(0));
4478 if (is_high_sampler(devinfo
, sampler
)) {
4479 if (sampler
.file
== BRW_IMMEDIATE_VALUE
) {
4480 assert(sampler
.ud
>= 16);
4481 const int sampler_state_size
= 16; /* 16 bytes */
4483 ubld1
.ADD(component(header
, 3),
4484 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
4485 brw_imm_ud(16 * (sampler
.ud
/ 16) * sampler_state_size
));
4487 fs_reg tmp
= ubld1
.vgrf(BRW_REGISTER_TYPE_UD
);
4488 ubld1
.AND(tmp
, sampler
, brw_imm_ud(0x0f0));
4489 ubld1
.SHL(tmp
, tmp
, brw_imm_ud(4));
4490 ubld1
.ADD(component(header
, 3),
4491 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
4497 if (shadow_c
.file
!= BAD_FILE
) {
4498 bld
.MOV(sources
[length
], shadow_c
);
4502 bool coordinate_done
= false;
4504 /* Set up the LOD info */
4507 case SHADER_OPCODE_TXL
:
4508 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4509 op
= SHADER_OPCODE_TXL_LZ
;
4512 bld
.MOV(sources
[length
], lod
);
4515 case SHADER_OPCODE_TXD
:
4516 /* TXD should have been lowered in SIMD16 mode. */
4517 assert(bld
.dispatch_width() == 8);
4519 /* Load dPdx and the coordinate together:
4520 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4522 for (unsigned i
= 0; i
< coord_components
; i
++) {
4523 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4525 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4526 * only derivatives for (u, v, r).
4528 if (i
< grad_components
) {
4529 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4530 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4534 coordinate_done
= true;
4536 case SHADER_OPCODE_TXS
:
4537 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4540 case SHADER_OPCODE_TXF
:
4541 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4542 * On Gen9 they are u, v, lod, r
4544 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4546 if (devinfo
->gen
>= 9) {
4547 if (coord_components
>= 2) {
4548 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4549 offset(coordinate
, bld
, 1));
4551 sources
[length
] = brw_imm_d(0);
4556 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4557 op
= SHADER_OPCODE_TXF_LZ
;
4559 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4563 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4564 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4565 offset(coordinate
, bld
, i
));
4567 coordinate_done
= true;
4570 case SHADER_OPCODE_TXF_CMS
:
4571 case SHADER_OPCODE_TXF_CMS_W
:
4572 case SHADER_OPCODE_TXF_UMS
:
4573 case SHADER_OPCODE_TXF_MCS
:
4574 if (op
== SHADER_OPCODE_TXF_UMS
||
4575 op
== SHADER_OPCODE_TXF_CMS
||
4576 op
== SHADER_OPCODE_TXF_CMS_W
) {
4577 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4581 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4582 /* Data from the multisample control surface. */
4583 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4586 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4589 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4590 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4593 offset(mcs
, bld
, 1));
4598 /* There is no offsetting for this message; just copy in the integer
4599 * texture coordinates.
4601 for (unsigned i
= 0; i
< coord_components
; i
++)
4602 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4603 offset(coordinate
, bld
, i
));
4605 coordinate_done
= true;
4607 case SHADER_OPCODE_TG4_OFFSET
:
4608 /* More crazy intermixing */
4609 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4610 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4612 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4613 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4614 offset(tg4_offset
, bld
, i
));
4616 if (coord_components
== 3) /* r if present */
4617 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4619 coordinate_done
= true;
4625 /* Set up the coordinate (except for cases where it was done above) */
4626 if (!coordinate_done
) {
4627 for (unsigned i
= 0; i
< coord_components
; i
++)
4628 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4633 mlen
= length
* reg_width
- header_size
;
4635 mlen
= length
* reg_width
;
4637 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4638 BRW_REGISTER_TYPE_F
);
4639 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4641 /* Generate the SEND. */
4643 inst
->src
[0] = src_payload
;
4644 inst
->src
[1] = surface
;
4645 inst
->src
[2] = sampler
;
4646 inst
->resize_sources(3);
4648 inst
->header_size
= header_size
;
4650 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4651 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4655 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4657 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4658 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4659 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4660 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4661 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4662 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4663 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4664 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4665 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4666 const fs_reg
&tg4_offset
= inst
->src
[TEX_LOGICAL_SRC_TG4_OFFSET
];
4667 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4668 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4669 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4670 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4672 if (devinfo
->gen
>= 7) {
4673 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4674 shadow_c
, lod
, lod2
, sample_index
,
4675 mcs
, surface
, sampler
, tg4_offset
,
4676 coord_components
, grad_components
);
4677 } else if (devinfo
->gen
>= 5) {
4678 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4679 shadow_c
, lod
, lod2
, sample_index
,
4681 coord_components
, grad_components
);
4683 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4684 shadow_c
, lod
, lod2
,
4686 coord_components
, grad_components
);
4691 * Initialize the header present in some typed and untyped surface
4695 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4697 fs_builder ubld
= bld
.exec_all().group(8, 0);
4698 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4699 ubld
.MOV(dst
, brw_imm_d(0));
4700 ubld
.group(1, 0).MOV(component(dst
, 7), sample_mask
);
4705 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4706 const fs_reg
&sample_mask
)
4708 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4710 /* Get the logical send arguments. */
4711 const fs_reg
&addr
= inst
->src
[0];
4712 const fs_reg
&src
= inst
->src
[1];
4713 const fs_reg
&surface
= inst
->src
[2];
4714 const UNUSED fs_reg
&dims
= inst
->src
[3];
4715 const fs_reg
&arg
= inst
->src
[4];
4717 /* Calculate the total number of components of the payload. */
4718 const unsigned addr_sz
= inst
->components_read(0);
4719 const unsigned src_sz
= inst
->components_read(1);
4720 /* From the BDW PRM Volume 7, page 147:
4722 * "For the Data Cache Data Port*, the header must be present for the
4723 * following message types: [...] Typed read/write/atomics"
4725 * Earlier generations have a similar wording. Because of this restriction
4726 * we don't attempt to implement sample masks via predication for such
4727 * messages prior to Gen9, since we have to provide a header anyway. On
4728 * Gen11+ the header has been removed so we can only use predication.
4730 const unsigned header_sz
= devinfo
->gen
< 9 &&
4731 (op
== SHADER_OPCODE_TYPED_SURFACE_READ
||
4732 op
== SHADER_OPCODE_TYPED_SURFACE_WRITE
||
4733 op
== SHADER_OPCODE_TYPED_ATOMIC
) ? 1 : 0;
4734 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4736 /* Allocate space for the payload. */
4737 fs_reg
*const components
= new fs_reg
[sz
];
4738 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4741 /* Construct the payload. */
4743 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4745 for (unsigned i
= 0; i
< addr_sz
; i
++)
4746 components
[n
++] = offset(addr
, bld
, i
);
4748 for (unsigned i
= 0; i
< src_sz
; i
++)
4749 components
[n
++] = offset(src
, bld
, i
);
4751 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4753 /* Predicate the instruction on the sample mask if no header is
4756 if (!header_sz
&& sample_mask
.file
!= BAD_FILE
&&
4757 sample_mask
.file
!= IMM
) {
4758 const fs_builder ubld
= bld
.group(1, 0).exec_all();
4759 if (inst
->predicate
) {
4760 assert(inst
->predicate
== BRW_PREDICATE_NORMAL
);
4761 assert(!inst
->predicate_inverse
);
4762 assert(inst
->flag_subreg
< 2);
4763 /* Combine the sample mask with the existing predicate by using a
4764 * vertical predication mode.
4766 inst
->predicate
= BRW_PREDICATE_ALIGN1_ALLV
;
4767 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
+ 2),
4771 inst
->flag_subreg
= 2;
4772 inst
->predicate
= BRW_PREDICATE_NORMAL
;
4773 inst
->predicate_inverse
= false;
4774 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
), sample_mask
.type
),
4779 /* Update the original instruction. */
4781 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4782 inst
->header_size
= header_sz
;
4784 inst
->src
[0] = payload
;
4785 inst
->src
[1] = surface
;
4787 inst
->resize_sources(3);
4789 delete[] components
;
4793 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4795 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4797 if (devinfo
->gen
>= 7) {
4798 /* We are switching the instruction from an ALU-like instruction to a
4799 * send-from-grf instruction. Since sends can't handle strides or
4800 * source modifiers, we have to make a copy of the offset source.
4802 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4803 bld
.MOV(tmp
, inst
->src
[1]);
4806 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4809 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4810 BRW_REGISTER_TYPE_UD
);
4812 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4814 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4815 inst
->resize_sources(1);
4816 inst
->base_mrf
= payload
.nr
;
4817 inst
->header_size
= 1;
4818 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4823 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4825 assert(bld
.shader
->devinfo
->gen
< 6);
4828 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4830 if (inst
->sources
> 1) {
4831 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4832 * "Message Payload":
4834 * "Operand0[7]. For the INT DIV functions, this operand is the
4837 * "Operand1[7]. For the INT DIV functions, this operand is the
4840 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4841 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4842 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4844 inst
->resize_sources(1);
4845 inst
->src
[0] = src0
;
4847 assert(inst
->exec_size
== 8);
4848 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4853 fs_visitor::lower_logical_sends()
4855 bool progress
= false;
4857 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4858 const fs_builder
ibld(this, block
, inst
);
4860 switch (inst
->opcode
) {
4861 case FS_OPCODE_FB_WRITE_LOGICAL
:
4862 assert(stage
== MESA_SHADER_FRAGMENT
);
4863 lower_fb_write_logical_send(ibld
, inst
,
4864 brw_wm_prog_data(prog_data
),
4865 (const brw_wm_prog_key
*)key
,
4869 case FS_OPCODE_FB_READ_LOGICAL
:
4870 lower_fb_read_logical_send(ibld
, inst
);
4873 case SHADER_OPCODE_TEX_LOGICAL
:
4874 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4877 case SHADER_OPCODE_TXD_LOGICAL
:
4878 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4881 case SHADER_OPCODE_TXF_LOGICAL
:
4882 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4885 case SHADER_OPCODE_TXL_LOGICAL
:
4886 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4889 case SHADER_OPCODE_TXS_LOGICAL
:
4890 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4893 case FS_OPCODE_TXB_LOGICAL
:
4894 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4897 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4898 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4901 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4902 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4905 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4906 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4909 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4910 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4913 case SHADER_OPCODE_LOD_LOGICAL
:
4914 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4917 case SHADER_OPCODE_TG4_LOGICAL
:
4918 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4921 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4922 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4925 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4926 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
4929 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4930 lower_surface_logical_send(ibld
, inst
,
4931 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4935 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4936 lower_surface_logical_send(ibld
, inst
,
4937 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4938 ibld
.sample_mask_reg());
4941 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
4942 lower_surface_logical_send(ibld
, inst
,
4943 SHADER_OPCODE_BYTE_SCATTERED_READ
,
4947 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
4948 lower_surface_logical_send(ibld
, inst
,
4949 SHADER_OPCODE_BYTE_SCATTERED_WRITE
,
4950 ibld
.sample_mask_reg());
4953 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4954 lower_surface_logical_send(ibld
, inst
,
4955 SHADER_OPCODE_UNTYPED_ATOMIC
,
4956 ibld
.sample_mask_reg());
4959 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4960 lower_surface_logical_send(ibld
, inst
,
4961 SHADER_OPCODE_TYPED_SURFACE_READ
,
4965 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4966 lower_surface_logical_send(ibld
, inst
,
4967 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4968 ibld
.sample_mask_reg());
4971 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4972 lower_surface_logical_send(ibld
, inst
,
4973 SHADER_OPCODE_TYPED_ATOMIC
,
4974 ibld
.sample_mask_reg());
4977 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4978 lower_varying_pull_constant_logical_send(ibld
, inst
);
4981 case SHADER_OPCODE_RCP
:
4982 case SHADER_OPCODE_RSQ
:
4983 case SHADER_OPCODE_SQRT
:
4984 case SHADER_OPCODE_EXP2
:
4985 case SHADER_OPCODE_LOG2
:
4986 case SHADER_OPCODE_SIN
:
4987 case SHADER_OPCODE_COS
:
4988 case SHADER_OPCODE_POW
:
4989 case SHADER_OPCODE_INT_QUOTIENT
:
4990 case SHADER_OPCODE_INT_REMAINDER
:
4991 /* The math opcodes are overloaded for the send-like and
4992 * expression-like instructions which seems kind of icky. Gen6+ has
4993 * a native (but rather quirky) MATH instruction so we don't need to
4994 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
4995 * logical instructions (which we can easily recognize because they
4996 * have mlen = 0) into send-like virtual instructions.
4998 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
4999 lower_math_logical_send(ibld
, inst
);
5014 invalidate_live_intervals();
5020 * Get the closest allowed SIMD width for instruction \p inst accounting for
5021 * some common regioning and execution control restrictions that apply to FPU
5022 * instructions. These restrictions don't necessarily have any relevance to
5023 * instructions not executed by the FPU pipeline like extended math, control
5024 * flow or send message instructions.
5026 * For virtual opcodes it's really up to the instruction -- In some cases
5027 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
5028 * instructions) it may simplify virtual instruction lowering if we can
5029 * enforce FPU-like regioning restrictions already on the virtual instruction,
5030 * in other cases (e.g. virtual send-like instructions) this may be
5031 * excessively restrictive.
5034 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
5035 const fs_inst
*inst
)
5037 /* Maximum execution size representable in the instruction controls. */
5038 unsigned max_width
= MIN2(32, inst
->exec_size
);
5040 /* According to the PRMs:
5041 * "A. In Direct Addressing mode, a source cannot span more than 2
5042 * adjacent GRF registers.
5043 * B. A destination cannot span more than 2 adjacent GRF registers."
5045 * Look for the source or destination with the largest register region
5046 * which is the one that is going to limit the overall execution size of
5047 * the instruction due to this rule.
5049 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
5051 for (unsigned i
= 0; i
< inst
->sources
; i
++)
5052 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
5054 /* Calculate the maximum execution size of the instruction based on the
5055 * factor by which it goes over the hardware limit of 2 GRFs.
5058 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
5060 /* According to the IVB PRMs:
5061 * "When destination spans two registers, the source MUST span two
5062 * registers. The exception to the above rule:
5064 * - When source is scalar, the source registers are not incremented.
5065 * - When source is packed integer Word and destination is packed
5066 * integer DWord, the source register is not incremented but the
5067 * source sub register is incremented."
5069 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
5070 * restrictions. The code below intentionally doesn't check whether the
5071 * destination type is integer because empirically the hardware doesn't
5072 * seem to care what the actual type is as long as it's dword-aligned.
5074 if (devinfo
->gen
< 8) {
5075 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5076 /* IVB implements DF scalars as <0;2,1> regions. */
5077 const bool is_scalar_exception
= is_uniform(inst
->src
[i
]) &&
5078 (devinfo
->is_haswell
|| type_sz(inst
->src
[i
].type
) != 8);
5079 const bool is_packed_word_exception
=
5080 type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
5081 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1;
5083 if (inst
->size_written
> REG_SIZE
&&
5084 inst
->size_read(i
) != 0 && inst
->size_read(i
) <= REG_SIZE
&&
5085 !is_scalar_exception
&& !is_packed_word_exception
) {
5086 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
5087 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
5092 /* From the IVB PRMs:
5093 * "When an instruction is SIMD32, the low 16 bits of the execution mask
5094 * are applied for both halves of the SIMD32 instruction. If different
5095 * execution mask channels are required, split the instruction into two
5096 * SIMD16 instructions."
5098 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
5099 * 32-wide control flow support in hardware and will behave similarly.
5101 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
5102 max_width
= MIN2(max_width
, 16);
5104 /* From the IVB PRMs (applies to HSW too):
5105 * "Instructions with condition modifiers must not use SIMD32."
5107 * From the BDW PRMs (applies to later hardware too):
5108 * "Ternary instruction with condition modifiers must not use SIMD32."
5110 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
5111 max_width
= MIN2(max_width
, 16);
5113 /* From the IVB PRMs (applies to other devices that don't have the
5114 * gen_device_info::supports_simd16_3src flag set):
5115 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
5116 * SIMD8 is not allowed for DF operations."
5118 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
5119 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
5121 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
5122 * the 8-bit quarter of the execution mask signals specified in the
5123 * instruction control fields) for the second compressed half of any
5124 * single-precision instruction (for double-precision instructions
5125 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
5126 * the EU will apply the wrong execution controls for the second
5127 * sequential GRF write if the number of channels per GRF is not exactly
5128 * eight in single-precision mode (or four in double-float mode).
5130 * In this situation we calculate the maximum size of the split
5131 * instructions so they only ever write to a single register.
5133 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
5134 !inst
->force_writemask_all
) {
5135 const unsigned channels_per_grf
= inst
->exec_size
/
5136 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
5137 const unsigned exec_type_size
= get_exec_type_size(inst
);
5138 assert(exec_type_size
);
5140 /* The hardware shifts exactly 8 channels per compressed half of the
5141 * instruction in single-precision mode and exactly 4 in double-precision.
5143 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
5144 max_width
= MIN2(max_width
, channels_per_grf
);
5146 /* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
5147 * because HW applies the same channel enable signals to both halves of
5148 * the compressed instruction which will be just wrong under
5149 * non-uniform control flow.
5151 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
5152 (exec_type_size
== 8 || type_sz(inst
->dst
.type
) == 8))
5153 max_width
= MIN2(max_width
, 4);
5156 /* Only power-of-two execution sizes are representable in the instruction
5159 return 1 << _mesa_logbase2(max_width
);
5163 * Get the maximum allowed SIMD width for instruction \p inst accounting for
5164 * various payload size restrictions that apply to sampler message
5167 * This is only intended to provide a maximum theoretical bound for the
5168 * execution size of the message based on the number of argument components
5169 * alone, which in most cases will determine whether the SIMD8 or SIMD16
5170 * variant of the message can be used, though some messages may have
5171 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
5172 * the message length to determine the exact SIMD width and argument count,
5173 * which makes a number of sampler message combinations impossible to
5177 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
5178 const fs_inst
*inst
)
5180 /* Calculate the number of coordinate components that have to be present
5181 * assuming that additional arguments follow the texel coordinates in the
5182 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
5183 * need to pad to four or three components depending on the message,
5184 * pre-ILK we need to pad to at most three components.
5186 const unsigned req_coord_components
=
5187 (devinfo
->gen
>= 7 ||
5188 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
5189 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
5190 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
5193 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
5194 * variant of the TXL or TXF message.
5196 const bool implicit_lod
= devinfo
->gen
>= 9 &&
5197 (inst
->opcode
== SHADER_OPCODE_TXL
||
5198 inst
->opcode
== SHADER_OPCODE_TXF
) &&
5199 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
5201 /* Calculate the total number of argument components that need to be passed
5202 * to the sampler unit.
5204 const unsigned num_payload_components
=
5205 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
5206 req_coord_components
) +
5207 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
5208 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
5209 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
5210 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
5211 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
5212 inst
->components_read(TEX_LOGICAL_SRC_TG4_OFFSET
) : 0) +
5213 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
5215 /* SIMD16 messages with more than five arguments exceed the maximum message
5216 * size supported by the sampler, regardless of whether a header is
5219 return MIN2(inst
->exec_size
,
5220 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
5224 * Get the closest native SIMD width supported by the hardware for instruction
5225 * \p inst. The instruction will be left untouched by
5226 * fs_visitor::lower_simd_width() if the returned value is equal to the
5227 * original execution size.
5230 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
5231 const fs_inst
*inst
)
5233 switch (inst
->opcode
) {
5234 case BRW_OPCODE_MOV
:
5235 case BRW_OPCODE_SEL
:
5236 case BRW_OPCODE_NOT
:
5237 case BRW_OPCODE_AND
:
5239 case BRW_OPCODE_XOR
:
5240 case BRW_OPCODE_SHR
:
5241 case BRW_OPCODE_SHL
:
5242 case BRW_OPCODE_ASR
:
5243 case BRW_OPCODE_CMPN
:
5244 case BRW_OPCODE_CSEL
:
5245 case BRW_OPCODE_F32TO16
:
5246 case BRW_OPCODE_F16TO32
:
5247 case BRW_OPCODE_BFREV
:
5248 case BRW_OPCODE_BFE
:
5249 case BRW_OPCODE_ADD
:
5250 case BRW_OPCODE_MUL
:
5251 case BRW_OPCODE_AVG
:
5252 case BRW_OPCODE_FRC
:
5253 case BRW_OPCODE_RNDU
:
5254 case BRW_OPCODE_RNDD
:
5255 case BRW_OPCODE_RNDE
:
5256 case BRW_OPCODE_RNDZ
:
5257 case BRW_OPCODE_LZD
:
5258 case BRW_OPCODE_FBH
:
5259 case BRW_OPCODE_FBL
:
5260 case BRW_OPCODE_CBIT
:
5261 case BRW_OPCODE_SAD2
:
5262 case BRW_OPCODE_MAD
:
5263 case BRW_OPCODE_LRP
:
5264 case FS_OPCODE_PACK
:
5265 case SHADER_OPCODE_SEL_EXEC
:
5266 case SHADER_OPCODE_CLUSTER_BROADCAST
:
5267 return get_fpu_lowered_simd_width(devinfo
, inst
);
5269 case BRW_OPCODE_CMP
: {
5270 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
5271 * when the destination is a GRF the dependency-clear bit on the flag
5272 * register is cleared early.
5274 * Suggested workarounds are to disable coissuing CMP instructions
5275 * or to split CMP(16) instructions into two CMP(8) instructions.
5277 * We choose to split into CMP(8) instructions since disabling
5278 * coissuing would affect CMP instructions not otherwise affected by
5281 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
5282 !inst
->dst
.is_null() ? 8 : ~0);
5283 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
5285 case BRW_OPCODE_BFI1
:
5286 case BRW_OPCODE_BFI2
:
5287 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
5289 * "Force BFI instructions to be executed always in SIMD8."
5291 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
5292 get_fpu_lowered_simd_width(devinfo
, inst
));
5295 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
5296 return inst
->exec_size
;
5298 case SHADER_OPCODE_RCP
:
5299 case SHADER_OPCODE_RSQ
:
5300 case SHADER_OPCODE_SQRT
:
5301 case SHADER_OPCODE_EXP2
:
5302 case SHADER_OPCODE_LOG2
:
5303 case SHADER_OPCODE_SIN
:
5304 case SHADER_OPCODE_COS
:
5305 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
5308 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
5309 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
5310 MIN2(8, inst
->exec_size
));
5312 case SHADER_OPCODE_POW
:
5313 /* SIMD16 is only allowed on Gen7+. */
5314 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
5315 MIN2(8, inst
->exec_size
));
5317 case SHADER_OPCODE_INT_QUOTIENT
:
5318 case SHADER_OPCODE_INT_REMAINDER
:
5319 /* Integer division is limited to SIMD8 on all generations. */
5320 return MIN2(8, inst
->exec_size
);
5322 case FS_OPCODE_LINTERP
:
5323 case SHADER_OPCODE_GET_BUFFER_SIZE
:
5324 case FS_OPCODE_DDX_COARSE
:
5325 case FS_OPCODE_DDX_FINE
:
5326 case FS_OPCODE_DDY_COARSE
:
5327 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
5328 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
5329 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
5330 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
5331 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
5332 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
5333 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
5334 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
5335 return MIN2(16, inst
->exec_size
);
5337 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
5338 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
5339 * message used to implement varying pull constant loads, so expand it
5340 * to SIMD16. An alternative with longer message payload length but
5341 * shorter return payload would be to use the SIMD8 sampler message that
5342 * takes (header, u, v, r) as parameters instead of (header, u).
5344 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
5346 case FS_OPCODE_DDY_FINE
:
5347 /* The implementation of this virtual opcode may require emitting
5348 * compressed Align16 instructions, which are severely limited on some
5351 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
5352 * Region Restrictions):
5354 * "In Align16 access mode, SIMD16 is not allowed for DW operations
5355 * and SIMD8 is not allowed for DF operations."
5357 * In this context, "DW operations" means "operations acting on 32-bit
5358 * values", so it includes operations on floats.
5360 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
5361 * (Instruction Compression -> Rules and Restrictions):
5363 * "A compressed instruction must be in Align1 access mode. Align16
5364 * mode instructions cannot be compressed."
5366 * Similar text exists in the g45 PRM.
5368 * Empirically, compressed align16 instructions using odd register
5369 * numbers don't appear to work on Sandybridge either.
5371 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
5372 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
5373 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
5375 case SHADER_OPCODE_MULH
:
5376 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
5377 * is 8-wide on Gen7+.
5379 return (devinfo
->gen
>= 7 ? 8 :
5380 get_fpu_lowered_simd_width(devinfo
, inst
));
5382 case FS_OPCODE_FB_WRITE_LOGICAL
:
5383 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
5386 assert(devinfo
->gen
!= 6 ||
5387 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
5388 inst
->exec_size
== 8);
5389 /* Dual-source FB writes are unsupported in SIMD16 mode. */
5390 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
5391 8 : MIN2(16, inst
->exec_size
));
5393 case FS_OPCODE_FB_READ_LOGICAL
:
5394 return MIN2(16, inst
->exec_size
);
5396 case SHADER_OPCODE_TEX_LOGICAL
:
5397 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
5398 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
5399 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
5400 case SHADER_OPCODE_LOD_LOGICAL
:
5401 case SHADER_OPCODE_TG4_LOGICAL
:
5402 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
5403 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
5404 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
5405 return get_sampler_lowered_simd_width(devinfo
, inst
);
5407 case SHADER_OPCODE_TXD_LOGICAL
:
5408 /* TXD is unsupported in SIMD16 mode. */
5411 case SHADER_OPCODE_TXL_LOGICAL
:
5412 case FS_OPCODE_TXB_LOGICAL
:
5413 /* Only one execution size is representable pre-ILK depending on whether
5414 * the shadow reference argument is present.
5416 if (devinfo
->gen
== 4)
5417 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
5419 return get_sampler_lowered_simd_width(devinfo
, inst
);
5421 case SHADER_OPCODE_TXF_LOGICAL
:
5422 case SHADER_OPCODE_TXS_LOGICAL
:
5423 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
5424 * messages. Use SIMD16 instead.
5426 if (devinfo
->gen
== 4)
5429 return get_sampler_lowered_simd_width(devinfo
, inst
);
5431 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5432 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5433 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5436 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5437 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5438 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5439 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5440 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5441 return MIN2(16, inst
->exec_size
);
5443 case SHADER_OPCODE_URB_READ_SIMD8
:
5444 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
5445 case SHADER_OPCODE_URB_WRITE_SIMD8
:
5446 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
5447 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
5448 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
5449 return MIN2(8, inst
->exec_size
);
5451 case SHADER_OPCODE_QUAD_SWIZZLE
:
5454 case SHADER_OPCODE_MOV_INDIRECT
: {
5455 /* From IVB and HSW PRMs:
5457 * "2.When the destination requires two registers and the sources are
5458 * indirect, the sources must use 1x1 regioning mode.
5460 * In case of DF instructions in HSW/IVB, the exec_size is limited by
5461 * the EU decompression logic not handling VxH indirect addressing
5464 const unsigned max_size
= (devinfo
->gen
>= 8 ? 2 : 1) * REG_SIZE
;
5465 /* Prior to Broadwell, we only have 8 address subregisters. */
5466 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
5467 max_size
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
5471 case SHADER_OPCODE_LOAD_PAYLOAD
: {
5472 const unsigned reg_count
=
5473 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
5475 if (reg_count
> 2) {
5476 /* Only LOAD_PAYLOAD instructions with per-channel destination region
5477 * can be easily lowered (which excludes headers and heterogeneous
5480 assert(!inst
->header_size
);
5481 for (unsigned i
= 0; i
< inst
->sources
; i
++)
5482 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
5483 inst
->src
[i
].file
== BAD_FILE
);
5485 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
5487 return inst
->exec_size
;
5491 return inst
->exec_size
;
5496 * Return true if splitting out the group of channels of instruction \p inst
5497 * given by lbld.group() requires allocating a temporary for the i-th source
5498 * of the lowered instruction.
5501 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
5503 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
5504 (inst
->components_read(i
) == 1 &&
5505 lbld
.dispatch_width() <= inst
->exec_size
)) ||
5506 (inst
->flags_written() &
5507 flag_mask(inst
->src
[i
], type_sz(inst
->src
[i
].type
)));
5511 * Extract the data that would be consumed by the channel group given by
5512 * lbld.group() from the i-th source region of instruction \p inst and return
5513 * it as result in packed form.
5516 emit_unzip(const fs_builder
&lbld
, fs_inst
*inst
, unsigned i
)
5518 /* Specified channel group from the source region. */
5519 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group());
5521 if (needs_src_copy(lbld
, inst
, i
)) {
5522 /* Builder of the right width to perform the copy avoiding uninitialized
5523 * data if the lowered execution size is greater than the original
5524 * execution size of the instruction.
5526 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5527 inst
->exec_size
), 0);
5528 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
5530 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
5531 cbld
.MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
5535 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
5536 /* The source is invariant for all dispatch_width-wide groups of the
5539 return inst
->src
[i
];
5542 /* We can just point the lowered instruction at the right channel group
5543 * from the original region.
5550 * Return true if splitting out the group of channels of instruction \p inst
5551 * given by lbld.group() requires allocating a temporary for the destination
5552 * of the lowered instruction and copying the data back to the original
5553 * destination region.
5556 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
5558 /* If the instruction writes more than one component we'll have to shuffle
5559 * the results of multiple lowered instructions in order to make sure that
5560 * they end up arranged correctly in the original destination region.
5562 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
5565 /* If the lowered execution size is larger than the original the result of
5566 * the instruction won't fit in the original destination, so we'll have to
5567 * allocate a temporary in any case.
5569 if (lbld
.dispatch_width() > inst
->exec_size
)
5572 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5573 /* If we already made a copy of the source for other reasons there won't
5574 * be any overlap with the destination.
5576 if (needs_src_copy(lbld
, inst
, i
))
5579 /* In order to keep the logic simple we emit a copy whenever the
5580 * destination region doesn't exactly match an overlapping source, which
5581 * may point at the source and destination not being aligned group by
5582 * group which could cause one of the lowered instructions to overwrite
5583 * the data read from the same source by other lowered instructions.
5585 if (regions_overlap(inst
->dst
, inst
->size_written
,
5586 inst
->src
[i
], inst
->size_read(i
)) &&
5587 !inst
->dst
.equals(inst
->src
[i
]))
5595 * Insert data from a packed temporary into the channel group given by
5596 * lbld.group() of the destination region of instruction \p inst and return
5597 * the temporary as result. Any copy instructions that are required for
5598 * unzipping the previous value (in the case of partial writes) will be
5599 * inserted using \p lbld_before and any copy instructions required for
5600 * zipping up the destination of \p inst will be inserted using \p lbld_after.
5603 emit_zip(const fs_builder
&lbld_before
, const fs_builder
&lbld_after
,
5606 assert(lbld_before
.dispatch_width() == lbld_after
.dispatch_width());
5607 assert(lbld_before
.group() == lbld_after
.group());
5609 /* Specified channel group from the destination region. */
5610 const fs_reg dst
= horiz_offset(inst
->dst
, lbld_after
.group());
5611 const unsigned dst_size
= inst
->size_written
/
5612 inst
->dst
.component_size(inst
->exec_size
);
5614 if (needs_dst_copy(lbld_after
, inst
)) {
5615 const fs_reg tmp
= lbld_after
.vgrf(inst
->dst
.type
, dst_size
);
5617 if (inst
->predicate
) {
5618 /* Handle predication by copying the original contents of
5619 * the destination into the temporary before emitting the
5620 * lowered instruction.
5622 const fs_builder gbld_before
=
5623 lbld_before
.group(MIN2(lbld_before
.dispatch_width(),
5624 inst
->exec_size
), 0);
5625 for (unsigned k
= 0; k
< dst_size
; ++k
) {
5626 gbld_before
.MOV(offset(tmp
, lbld_before
, k
),
5627 offset(dst
, inst
->exec_size
, k
));
5631 const fs_builder gbld_after
=
5632 lbld_after
.group(MIN2(lbld_after
.dispatch_width(),
5633 inst
->exec_size
), 0);
5634 for (unsigned k
= 0; k
< dst_size
; ++k
) {
5635 /* Use a builder of the right width to perform the copy avoiding
5636 * uninitialized data if the lowered execution size is greater than
5637 * the original execution size of the instruction.
5639 gbld_after
.MOV(offset(dst
, inst
->exec_size
, k
),
5640 offset(tmp
, lbld_after
, k
));
5646 /* No need to allocate a temporary for the lowered instruction, just
5647 * take the right group of channels from the original region.
5654 fs_visitor::lower_simd_width()
5656 bool progress
= false;
5658 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5659 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5661 if (lower_width
!= inst
->exec_size
) {
5662 /* Builder matching the original instruction. We may also need to
5663 * emit an instruction of width larger than the original, set the
5664 * execution size of the builder to the highest of both for now so
5665 * we're sure that both cases can be handled.
5667 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5668 const fs_builder ibld
= bld
.at(block
, inst
)
5669 .exec_all(inst
->force_writemask_all
)
5670 .group(max_width
, inst
->group
/ max_width
);
5672 /* Split the copies in chunks of the execution width of either the
5673 * original or the lowered instruction, whichever is lower.
5675 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5676 const unsigned dst_size
= inst
->size_written
/
5677 inst
->dst
.component_size(inst
->exec_size
);
5679 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5681 /* Inserting the zip, unzip, and duplicated instructions in all of
5682 * the right spots is somewhat tricky. All of the unzip and any
5683 * instructions from the zip which unzip the destination prior to
5684 * writing need to happen before all of the per-group instructions
5685 * and the zip instructions need to happen after. In order to sort
5686 * this all out, we insert the unzip instructions before \p inst,
5687 * insert the per-group instructions after \p inst (i.e. before
5688 * inst->next), and insert the zip instructions before the
5689 * instruction after \p inst. Since we are inserting instructions
5690 * after \p inst, inst->next is a moving target and we need to save
5691 * it off here so that we insert the zip instructions in the right
5694 * Since we're inserting split instructions after after_inst, the
5695 * instructions will end up in the reverse order that we insert them.
5696 * However, certain render target writes require that the low group
5697 * instructions come before the high group. From the Ivy Bridge PRM
5698 * Vol. 4, Pt. 1, Section 3.9.11:
5700 * "If multiple SIMD8 Dual Source messages are delivered by the
5701 * pixel shader thread, each SIMD8_DUALSRC_LO message must be
5702 * issued before the SIMD8_DUALSRC_HI message with the same Slot
5703 * Group Select setting."
5705 * And, from Section 3.9.11.1 of the same PRM:
5707 * "When SIMD32 or SIMD16 PS threads send render target writes
5708 * with multiple SIMD8 and SIMD16 messages, the following must
5711 * All the slots (as described above) must have a corresponding
5712 * render target write irrespective of the slot's validity. A slot
5713 * is considered valid when at least one sample is enabled. For
5714 * example, a SIMD16 PS thread must send two SIMD8 render target
5715 * writes to cover all the slots.
5717 * PS thread must send SIMD render target write messages with
5718 * increasing slot numbers. For example, SIMD16 thread has
5719 * Slot[15:0] and if two SIMD8 render target writes are used, the
5720 * first SIMD8 render target write must send Slot[7:0] and the
5721 * next one must send Slot[15:8]."
5723 * In order to make low group instructions come before high group
5724 * instructions (this is required for some render target writes), we
5725 * split from the highest group to lowest.
5727 exec_node
*const after_inst
= inst
->next
;
5728 for (int i
= n
- 1; i
>= 0; i
--) {
5729 /* Emit a copy of the original instruction with the lowered width.
5730 * If the EOT flag was set throw it away except for the last
5731 * instruction to avoid killing the thread prematurely.
5733 fs_inst split_inst
= *inst
;
5734 split_inst
.exec_size
= lower_width
;
5735 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
5737 /* Select the correct channel enables for the i-th group, then
5738 * transform the sources and destination and emit the lowered
5741 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5743 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5744 split_inst
.src
[j
] = emit_unzip(lbld
.at(block
, inst
), inst
, j
);
5746 split_inst
.dst
= emit_zip(lbld
.at(block
, inst
),
5747 lbld
.at(block
, after_inst
), inst
);
5748 split_inst
.size_written
=
5749 split_inst
.dst
.component_size(lower_width
) * dst_size
;
5751 lbld
.at(block
, inst
->next
).emit(split_inst
);
5754 inst
->remove(block
);
5760 invalidate_live_intervals();
5766 fs_visitor::dump_instructions()
5768 dump_instructions(NULL
);
5772 fs_visitor::dump_instructions(const char *name
)
5774 FILE *file
= stderr
;
5775 if (name
&& geteuid() != 0) {
5776 file
= fopen(name
, "w");
5782 calculate_register_pressure();
5783 int ip
= 0, max_pressure
= 0;
5784 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5785 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5786 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5787 dump_instruction(inst
, file
);
5790 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5793 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5794 fprintf(file
, "%4d: ", ip
++);
5795 dump_instruction(inst
, file
);
5799 if (file
!= stderr
) {
5805 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5807 dump_instruction(be_inst
, stderr
);
5811 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5813 fs_inst
*inst
= (fs_inst
*)be_inst
;
5815 if (inst
->predicate
) {
5816 fprintf(file
, "(%cf%d.%d) ",
5817 inst
->predicate_inverse
? '-' : '+',
5818 inst
->flag_subreg
/ 2,
5819 inst
->flag_subreg
% 2);
5822 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5824 fprintf(file
, ".sat");
5825 if (inst
->conditional_mod
) {
5826 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5827 if (!inst
->predicate
&&
5828 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5829 inst
->opcode
!= BRW_OPCODE_CSEL
&&
5830 inst
->opcode
!= BRW_OPCODE_IF
&&
5831 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5832 fprintf(file
, ".f%d.%d", inst
->flag_subreg
/ 2,
5833 inst
->flag_subreg
% 2);
5836 fprintf(file
, "(%d) ", inst
->exec_size
);
5839 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5843 fprintf(file
, "(EOT) ");
5846 switch (inst
->dst
.file
) {
5848 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
5851 fprintf(file
, "g%d", inst
->dst
.nr
);
5854 fprintf(file
, "m%d", inst
->dst
.nr
);
5857 fprintf(file
, "(null)");
5860 fprintf(file
, "***u%d***", inst
->dst
.nr
);
5863 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
5866 switch (inst
->dst
.nr
) {
5868 fprintf(file
, "null");
5870 case BRW_ARF_ADDRESS
:
5871 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
5873 case BRW_ARF_ACCUMULATOR
:
5874 fprintf(file
, "acc%d", inst
->dst
.subnr
);
5877 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5880 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5885 unreachable("not reached");
5888 if (inst
->dst
.offset
||
5889 (inst
->dst
.file
== VGRF
&&
5890 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
5891 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
5892 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
5893 inst
->dst
.offset
% reg_size
);
5896 if (inst
->dst
.stride
!= 1)
5897 fprintf(file
, "<%u>", inst
->dst
.stride
);
5898 fprintf(file
, ":%s, ", brw_reg_type_to_letters(inst
->dst
.type
));
5900 for (int i
= 0; i
< inst
->sources
; i
++) {
5901 if (inst
->src
[i
].negate
)
5903 if (inst
->src
[i
].abs
)
5905 switch (inst
->src
[i
].file
) {
5907 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
5910 fprintf(file
, "g%d", inst
->src
[i
].nr
);
5913 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
5916 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
5919 fprintf(file
, "u%d", inst
->src
[i
].nr
);
5922 fprintf(file
, "(null)");
5925 switch (inst
->src
[i
].type
) {
5926 case BRW_REGISTER_TYPE_F
:
5927 fprintf(file
, "%-gf", inst
->src
[i
].f
);
5929 case BRW_REGISTER_TYPE_DF
:
5930 fprintf(file
, "%fdf", inst
->src
[i
].df
);
5932 case BRW_REGISTER_TYPE_W
:
5933 case BRW_REGISTER_TYPE_D
:
5934 fprintf(file
, "%dd", inst
->src
[i
].d
);
5936 case BRW_REGISTER_TYPE_UW
:
5937 case BRW_REGISTER_TYPE_UD
:
5938 fprintf(file
, "%uu", inst
->src
[i
].ud
);
5940 case BRW_REGISTER_TYPE_VF
:
5941 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
5942 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
5943 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
5944 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
5945 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5948 fprintf(file
, "???");
5953 switch (inst
->src
[i
].nr
) {
5955 fprintf(file
, "null");
5957 case BRW_ARF_ADDRESS
:
5958 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5960 case BRW_ARF_ACCUMULATOR
:
5961 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5964 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5967 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5973 if (inst
->src
[i
].offset
||
5974 (inst
->src
[i
].file
== VGRF
&&
5975 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
5976 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
5977 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
5978 inst
->src
[i
].offset
% reg_size
);
5981 if (inst
->src
[i
].abs
)
5984 if (inst
->src
[i
].file
!= IMM
) {
5986 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5987 unsigned hstride
= inst
->src
[i
].hstride
;
5988 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5990 stride
= inst
->src
[i
].stride
;
5993 fprintf(file
, "<%u>", stride
);
5995 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
5998 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5999 fprintf(file
, ", ");
6004 if (inst
->force_writemask_all
)
6005 fprintf(file
, "NoMask ");
6007 if (inst
->exec_size
!= dispatch_width
)
6008 fprintf(file
, "group%d ", inst
->group
);
6010 fprintf(file
, "\n");
6014 * Possibly returns an instruction that set up @param reg.
6016 * Sometimes we want to take the result of some expression/variable
6017 * dereference tree and rewrite the instruction generating the result
6018 * of the tree. When processing the tree, we know that the
6019 * instructions generated are all writing temporaries that are dead
6020 * outside of this tree. So, if we have some instructions that write
6021 * a temporary, we're free to point that temp write somewhere else.
6023 * Note that this doesn't guarantee that the instruction generated
6024 * only reg -- it might be the size=4 destination of a texture instruction.
6027 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
6032 end
->is_partial_write() ||
6033 !reg
.equals(end
->dst
)) {
6041 fs_visitor::setup_fs_payload_gen6()
6043 assert(stage
== MESA_SHADER_FRAGMENT
);
6044 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
6046 assert(devinfo
->gen
>= 6);
6048 /* R0-1: masks, pixel X/Y coordinates. */
6049 payload
.num_regs
= 2;
6050 /* R2: only for 32-pixel dispatch.*/
6052 /* R3-26: barycentric interpolation coordinates. These appear in the
6053 * same order that they appear in the brw_barycentric_mode
6054 * enum. Each set of coordinates occupies 2 registers if dispatch width
6055 * == 8 and 4 registers if dispatch width == 16. Coordinates only
6056 * appear if they were enabled using the "Barycentric Interpolation
6057 * Mode" bits in WM_STATE.
6059 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
6060 if (prog_data
->barycentric_interp_modes
& (1 << i
)) {
6061 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
6062 payload
.num_regs
+= 2;
6063 if (dispatch_width
== 16) {
6064 payload
.num_regs
+= 2;
6069 /* R27: interpolated depth if uses source depth */
6070 prog_data
->uses_src_depth
=
6071 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
6072 if (prog_data
->uses_src_depth
) {
6073 payload
.source_depth_reg
= payload
.num_regs
;
6075 if (dispatch_width
== 16) {
6076 /* R28: interpolated depth if not SIMD8. */
6081 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
6082 prog_data
->uses_src_w
=
6083 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
6084 if (prog_data
->uses_src_w
) {
6085 payload
.source_w_reg
= payload
.num_regs
;
6087 if (dispatch_width
== 16) {
6088 /* R30: interpolated W if not SIMD8. */
6093 /* R31: MSAA position offsets. */
6094 if (prog_data
->persample_dispatch
&&
6095 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
)) {
6096 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
6098 * "MSDISPMODE_PERSAMPLE is required in order to select
6101 * So we can only really get sample positions if we are doing real
6102 * per-sample dispatch. If we need gl_SamplePosition and we don't have
6103 * persample dispatch, we hard-code it to 0.5.
6105 prog_data
->uses_pos_offset
= true;
6106 payload
.sample_pos_reg
= payload
.num_regs
;
6110 /* R32: MSAA input coverage mask */
6111 prog_data
->uses_sample_mask
=
6112 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
6113 if (prog_data
->uses_sample_mask
) {
6114 assert(devinfo
->gen
>= 7);
6115 payload
.sample_mask_in_reg
= payload
.num_regs
;
6117 if (dispatch_width
== 16) {
6118 /* R33: input coverage mask if not SIMD8. */
6123 /* R34-: bary for 32-pixel. */
6124 /* R58-59: interp W for 32-pixel. */
6126 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6127 source_depth_to_render_target
= true;
6132 fs_visitor::setup_vs_payload()
6134 /* R0: thread header, R1: urb handles */
6135 payload
.num_regs
= 2;
6139 fs_visitor::setup_gs_payload()
6141 assert(stage
== MESA_SHADER_GEOMETRY
);
6143 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
6144 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
6146 /* R0: thread header, R1: output URB handles */
6147 payload
.num_regs
= 2;
6149 if (gs_prog_data
->include_primitive_id
) {
6150 /* R2: Primitive ID 0..7 */
6154 /* Always enable VUE handles so we can safely use pull model if needed.
6156 * The push model for a GS uses a ton of register space even for trivial
6157 * scenarios with just a few inputs, so just make things easier and a bit
6158 * safer by always having pull model available.
6160 gs_prog_data
->base
.include_vue_handles
= true;
6162 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
6163 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
6165 /* Use a maximum of 24 registers for push-model inputs. */
6166 const unsigned max_push_components
= 24;
6168 /* If pushing our inputs would take too many registers, reduce the URB read
6169 * length (which is in HWords, or 8 registers), and resort to pulling.
6171 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
6172 * have to multiply by VerticesIn to obtain the total storage requirement.
6174 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
6175 max_push_components
) {
6176 vue_prog_data
->urb_read_length
=
6177 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
6182 fs_visitor::setup_cs_payload()
6184 assert(devinfo
->gen
>= 7);
6185 payload
.num_regs
= 1;
6189 fs_visitor::calculate_register_pressure()
6191 invalidate_live_intervals();
6192 calculate_live_intervals();
6194 unsigned num_instructions
= 0;
6195 foreach_block(block
, cfg
)
6196 num_instructions
+= block
->instructions
.length();
6198 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
6200 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
6201 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
6202 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
6207 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
6209 * The needs_unlit_centroid_workaround ends up producing one of these per
6210 * channel of centroid input, so it's good to clean them up.
6212 * An assumption here is that nothing ever modifies the dispatched pixels
6213 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
6214 * dictates that anyway.
6217 fs_visitor::opt_drop_redundant_mov_to_flags()
6219 bool flag_mov_found
[4] = {false};
6220 bool progress
= false;
6222 /* Instructions removed by this pass can only be added if this were true */
6223 if (!devinfo
->needs_unlit_centroid_workaround
)
6226 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
6227 if (inst
->is_control_flow()) {
6228 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
6229 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
6230 if (!flag_mov_found
[inst
->flag_subreg
]) {
6231 flag_mov_found
[inst
->flag_subreg
] = true;
6233 inst
->remove(block
);
6236 } else if (inst
->flags_written()) {
6237 flag_mov_found
[inst
->flag_subreg
] = false;
6245 fs_visitor::optimize()
6247 /* Start by validating the shader we currently have. */
6250 /* bld is the common builder object pointing at the end of the program we
6251 * used to translate it into i965 IR. For the optimization and lowering
6252 * passes coming next, any code added after the end of the program without
6253 * having explicitly called fs_builder::at() clearly points at a mistake.
6254 * Ideally optimization passes wouldn't be part of the visitor so they
6255 * wouldn't have access to bld at all, but they do, so just in case some
6256 * pass forgets to ask for a location explicitly set it to NULL here to
6257 * make it trip. The dispatch width is initialized to a bogus value to
6258 * make sure that optimizations set the execution controls explicitly to
6259 * match the code they are manipulating instead of relying on the defaults.
6261 bld
= fs_builder(this, 64);
6263 assign_constant_locations();
6264 lower_constant_loads();
6268 split_virtual_grfs();
6271 #define OPT(pass, args...) ({ \
6273 bool this_progress = pass(args); \
6275 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
6276 char filename[64]; \
6277 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
6278 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
6280 backend_shader::dump_instructions(filename); \
6285 progress = progress || this_progress; \
6289 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
6291 snprintf(filename
, 64, "%s%d-%s-00-00-start",
6292 stage_abbrev
, dispatch_width
, nir
->info
.name
);
6294 backend_shader::dump_instructions(filename
);
6297 bool progress
= false;
6301 OPT(opt_drop_redundant_mov_to_flags
);
6302 OPT(remove_extra_rounding_modes
);
6309 OPT(remove_duplicate_mrf_writes
);
6313 OPT(opt_copy_propagation
);
6314 OPT(opt_predicated_break
, this);
6315 OPT(opt_cmod_propagation
);
6316 OPT(dead_code_eliminate
);
6317 OPT(opt_peephole_sel
);
6318 OPT(dead_control_flow_eliminate
, this);
6319 OPT(opt_register_renaming
);
6320 OPT(opt_saturate_propagation
);
6321 OPT(register_coalesce
);
6322 OPT(compute_to_mrf
);
6323 OPT(eliminate_find_live_channel
);
6325 OPT(compact_virtual_grfs
);
6328 /* Do this after cmod propagation has had every possible opportunity to
6329 * propagate results into SEL instructions.
6331 if (OPT(opt_peephole_csel
))
6332 OPT(dead_code_eliminate
);
6337 if (OPT(lower_pack
)) {
6338 OPT(register_coalesce
);
6339 OPT(dead_code_eliminate
);
6342 OPT(lower_simd_width
);
6344 /* After SIMD lowering just in case we had to unroll the EOT send. */
6345 OPT(opt_sampler_eot
);
6347 OPT(lower_logical_sends
);
6350 OPT(opt_copy_propagation
);
6351 /* Only run after logical send lowering because it's easier to implement
6352 * in terms of physical sends.
6354 if (OPT(opt_zero_samples
))
6355 OPT(opt_copy_propagation
);
6356 /* Run after logical send lowering to give it a chance to CSE the
6357 * LOAD_PAYLOAD instructions created to construct the payloads of
6358 * e.g. texturing messages in cases where it wasn't possible to CSE the
6359 * whole logical instruction.
6362 OPT(register_coalesce
);
6363 OPT(compute_to_mrf
);
6364 OPT(dead_code_eliminate
);
6365 OPT(remove_duplicate_mrf_writes
);
6366 OPT(opt_peephole_sel
);
6369 OPT(opt_redundant_discard_jumps
);
6371 if (OPT(lower_load_payload
)) {
6372 split_virtual_grfs();
6373 OPT(register_coalesce
);
6374 OPT(compute_to_mrf
);
6375 OPT(dead_code_eliminate
);
6378 OPT(opt_combine_constants
);
6379 OPT(lower_integer_multiplication
);
6381 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
6382 OPT(opt_cmod_propagation
);
6384 OPT(opt_copy_propagation
);
6385 OPT(dead_code_eliminate
);
6388 if (OPT(lower_conversions
)) {
6389 OPT(opt_copy_propagation
);
6390 OPT(dead_code_eliminate
);
6391 OPT(lower_simd_width
);
6394 lower_uniform_pull_constant_loads();
6400 * Three source instruction must have a GRF/MRF destination register.
6401 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
6404 fs_visitor::fixup_3src_null_dest()
6406 bool progress
= false;
6408 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
6409 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
6410 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
6417 invalidate_live_intervals();
6421 fs_visitor::allocate_registers(unsigned min_dispatch_width
, bool allow_spilling
)
6423 bool allocated_without_spills
;
6425 static const enum instruction_scheduler_mode pre_modes
[] = {
6427 SCHEDULE_PRE_NON_LIFO
,
6431 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
6433 /* Try each scheduling heuristic to see if it can successfully register
6434 * allocate without spilling. They should be ordered by decreasing
6435 * performance but increasing likelihood of allocating.
6437 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
6438 schedule_instructions(pre_modes
[i
]);
6441 assign_regs_trivial();
6442 allocated_without_spills
= true;
6444 allocated_without_spills
= assign_regs(false, spill_all
);
6446 if (allocated_without_spills
)
6450 if (!allocated_without_spills
) {
6451 if (!allow_spilling
)
6452 fail("Failure to register allocate and spilling is not allowed.");
6454 /* We assume that any spilling is worse than just dropping back to
6455 * SIMD8. There's probably actually some intermediate point where
6456 * SIMD16 with a couple of spills is still better.
6458 if (dispatch_width
> min_dispatch_width
) {
6459 fail("Failure to register allocate. Reduce number of "
6460 "live scalar values to avoid this.");
6462 compiler
->shader_perf_log(log_data
,
6463 "%s shader triggered register spilling. "
6464 "Try reducing the number of live scalar "
6465 "values to improve performance.\n",
6469 /* Since we're out of heuristics, just go spill registers until we
6470 * get an allocation.
6472 while (!assign_regs(true, spill_all
)) {
6478 /* This must come after all optimization and register allocation, since
6479 * it inserts dead code that happens to have side effects, and it does
6480 * so based on the actual physical registers in use.
6482 insert_gen4_send_dependency_workarounds();
6487 opt_bank_conflicts();
6489 schedule_instructions(SCHEDULE_POST
);
6491 if (last_scratch
> 0) {
6492 MAYBE_UNUSED
unsigned max_scratch_size
= 2 * 1024 * 1024;
6494 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
6496 if (stage
== MESA_SHADER_COMPUTE
) {
6497 if (devinfo
->is_haswell
) {
6498 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
6499 * field documentation, Haswell supports a minimum of 2kB of
6500 * scratch space for compute shaders, unlike every other stage
6503 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
6504 } else if (devinfo
->gen
<= 7) {
6505 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
6506 * field documentation, platforms prior to Haswell measure scratch
6507 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
6509 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
6510 max_scratch_size
= 12 * 1024;
6514 /* We currently only support up to 2MB of scratch space. If we
6515 * need to support more eventually, the documentation suggests
6516 * that we could allocate a larger buffer, and partition it out
6517 * ourselves. We'd just have to undo the hardware's address
6518 * calculation by subtracting (FFTID * Per Thread Scratch Space)
6519 * and then add FFTID * (Larger Per Thread Scratch Space).
6521 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
6522 * Thread Group Tracking > Local Memory/Scratch Space.
6524 assert(prog_data
->total_scratch
< max_scratch_size
);
6529 fs_visitor::run_vs()
6531 assert(stage
== MESA_SHADER_VERTEX
);
6535 if (shader_time_index
>= 0)
6536 emit_shader_time_begin();
6543 compute_clip_distance();
6547 if (shader_time_index
>= 0)
6548 emit_shader_time_end();
6554 assign_curb_setup();
6555 assign_vs_urb_setup();
6557 fixup_3src_null_dest();
6558 allocate_registers(8, true);
6564 fs_visitor::run_tcs_single_patch()
6566 assert(stage
== MESA_SHADER_TESS_CTRL
);
6568 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
6570 /* r1-r4 contain the ICP handles. */
6571 payload
.num_regs
= 5;
6573 if (shader_time_index
>= 0)
6574 emit_shader_time_begin();
6576 /* Initialize gl_InvocationID */
6577 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
6578 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6579 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
6580 bld
.MOV(channels_ud
, channels_uw
);
6582 if (tcs_prog_data
->instances
== 1) {
6583 invocation_id
= channels_ud
;
6585 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6587 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
6588 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6589 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6590 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
6591 brw_imm_ud(INTEL_MASK(23, 17)));
6592 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
6594 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
6597 /* Fix the disptach mask */
6598 if (nir
->info
.tess
.tcs_vertices_out
% 8) {
6599 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
6600 brw_imm_ud(nir
->info
.tess
.tcs_vertices_out
), BRW_CONDITIONAL_L
);
6601 bld
.IF(BRW_PREDICATE_NORMAL
);
6606 if (nir
->info
.tess
.tcs_vertices_out
% 8) {
6607 bld
.emit(BRW_OPCODE_ENDIF
);
6610 /* Emit EOT write; set TR DS Cache bit */
6612 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
6613 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
6614 fs_reg(brw_imm_ud(0)),
6616 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
6617 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
6619 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
6620 bld
.null_reg_ud(), payload
);
6624 if (shader_time_index
>= 0)
6625 emit_shader_time_end();
6634 assign_curb_setup();
6635 assign_tcs_single_patch_urb_setup();
6637 fixup_3src_null_dest();
6638 allocate_registers(8, true);
6644 fs_visitor::run_tes()
6646 assert(stage
== MESA_SHADER_TESS_EVAL
);
6648 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6649 payload
.num_regs
= 5;
6651 if (shader_time_index
>= 0)
6652 emit_shader_time_begin();
6661 if (shader_time_index
>= 0)
6662 emit_shader_time_end();
6668 assign_curb_setup();
6669 assign_tes_urb_setup();
6671 fixup_3src_null_dest();
6672 allocate_registers(8, true);
6678 fs_visitor::run_gs()
6680 assert(stage
== MESA_SHADER_GEOMETRY
);
6684 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6686 if (gs_compile
->control_data_header_size_bits
> 0) {
6687 /* Create a VGRF to store accumulated control data bits. */
6688 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6690 /* If we're outputting more than 32 control data bits, then EmitVertex()
6691 * will set control_data_bits to 0 after emitting the first vertex.
6692 * Otherwise, we need to initialize it to 0 here.
6694 if (gs_compile
->control_data_header_size_bits
<= 32) {
6695 const fs_builder abld
= bld
.annotate("initialize control data bits");
6696 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6700 if (shader_time_index
>= 0)
6701 emit_shader_time_begin();
6705 emit_gs_thread_end();
6707 if (shader_time_index
>= 0)
6708 emit_shader_time_end();
6717 assign_curb_setup();
6718 assign_gs_urb_setup();
6720 fixup_3src_null_dest();
6721 allocate_registers(8, true);
6726 /* From the SKL PRM, Volume 16, Workarounds:
6728 * 0877 3D Pixel Shader Hang possible when pixel shader dispatched with
6729 * only header phases (R0-R2)
6731 * WA: Enable a non-header phase (e.g. push constant) when dispatch would
6732 * have been header only.
6734 * Instead of enabling push constants one can alternatively enable one of the
6735 * inputs. Here one simply chooses "layer" which shouldn't impose much
6739 gen9_ps_header_only_workaround(struct brw_wm_prog_data
*wm_prog_data
)
6741 if (wm_prog_data
->num_varying_inputs
)
6744 if (wm_prog_data
->base
.curb_read_length
)
6747 wm_prog_data
->urb_setup
[VARYING_SLOT_LAYER
] = 0;
6748 wm_prog_data
->num_varying_inputs
= 1;
6752 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6754 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
6755 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6757 assert(stage
== MESA_SHADER_FRAGMENT
);
6759 if (devinfo
->gen
>= 6)
6760 setup_fs_payload_gen6();
6762 setup_fs_payload_gen4();
6766 } else if (do_rep_send
) {
6767 assert(dispatch_width
== 16);
6768 emit_repclear_shader();
6770 if (shader_time_index
>= 0)
6771 emit_shader_time_begin();
6773 calculate_urb_setup();
6774 if (nir
->info
.inputs_read
> 0 ||
6775 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
6776 if (devinfo
->gen
< 6)
6777 emit_interpolation_setup_gen4();
6779 emit_interpolation_setup_gen6();
6782 /* We handle discards by keeping track of the still-live pixels in f0.1.
6783 * Initialize it with the dispatched pixels.
6785 if (wm_prog_data
->uses_kill
) {
6786 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
6787 discard_init
->flag_subreg
= 1;
6790 /* Generate FS IR for main(). (the visitor only descends into
6791 * functions called "main").
6798 if (wm_prog_data
->uses_kill
)
6799 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6801 if (wm_key
->alpha_test_func
)
6806 if (shader_time_index
>= 0)
6807 emit_shader_time_end();
6813 assign_curb_setup();
6815 if (devinfo
->gen
>= 9)
6816 gen9_ps_header_only_workaround(wm_prog_data
);
6820 fixup_3src_null_dest();
6821 allocate_registers(8, allow_spilling
);
6831 fs_visitor::run_cs(unsigned min_dispatch_width
)
6833 assert(stage
== MESA_SHADER_COMPUTE
);
6834 assert(dispatch_width
>= min_dispatch_width
);
6838 if (shader_time_index
>= 0)
6839 emit_shader_time_begin();
6841 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6842 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6843 const fs_builder abld
= bld
.exec_all().group(1, 0);
6844 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
6845 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6853 emit_cs_terminate();
6855 if (shader_time_index
>= 0)
6856 emit_shader_time_end();
6862 assign_curb_setup();
6864 fixup_3src_null_dest();
6865 allocate_registers(min_dispatch_width
, true);
6874 * Return a bitfield where bit n is set if barycentric interpolation mode n
6875 * (see enum brw_barycentric_mode) is needed by the fragment shader.
6877 * We examine the load_barycentric intrinsics rather than looking at input
6878 * variables so that we catch interpolateAtCentroid() messages too, which
6879 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
6882 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
6883 const nir_shader
*shader
)
6885 unsigned barycentric_interp_modes
= 0;
6887 nir_foreach_function(f
, shader
) {
6891 nir_foreach_block(block
, f
->impl
) {
6892 nir_foreach_instr(instr
, block
) {
6893 if (instr
->type
!= nir_instr_type_intrinsic
)
6896 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6897 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6900 /* Ignore WPOS; it doesn't require interpolation. */
6901 if (nir_intrinsic_base(intrin
) == VARYING_SLOT_POS
)
6904 intrin
= nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6905 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
6906 nir_intrinsic_interp_mode(intrin
);
6907 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
6908 enum brw_barycentric_mode bary
=
6909 brw_barycentric_mode(interp
, bary_op
);
6911 barycentric_interp_modes
|= 1 << bary
;
6913 if (devinfo
->needs_unlit_centroid_workaround
&&
6914 bary_op
== nir_intrinsic_load_barycentric_centroid
)
6915 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
6920 return barycentric_interp_modes
;
6924 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
6925 const nir_shader
*shader
)
6927 prog_data
->flat_inputs
= 0;
6929 nir_foreach_variable(var
, &shader
->inputs
) {
6930 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
6932 if (input_index
< 0)
6936 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6937 prog_data
->flat_inputs
|= (1 << input_index
);
6942 computed_depth_mode(const nir_shader
*shader
)
6944 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6945 switch (shader
->info
.fs
.depth_layout
) {
6946 case FRAG_DEPTH_LAYOUT_NONE
:
6947 case FRAG_DEPTH_LAYOUT_ANY
:
6948 return BRW_PSCDEPTH_ON
;
6949 case FRAG_DEPTH_LAYOUT_GREATER
:
6950 return BRW_PSCDEPTH_ON_GE
;
6951 case FRAG_DEPTH_LAYOUT_LESS
:
6952 return BRW_PSCDEPTH_ON_LE
;
6953 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
6954 return BRW_PSCDEPTH_OFF
;
6957 return BRW_PSCDEPTH_OFF
;
6961 * Move load_interpolated_input with simple (payload-based) barycentric modes
6962 * to the top of the program so we don't emit multiple PLNs for the same input.
6964 * This works around CSE not being able to handle non-dominating cases
6970 * interpolate the same exact input
6973 * This should be replaced by global value numbering someday.
6976 move_interpolation_to_top(nir_shader
*nir
)
6978 bool progress
= false;
6980 nir_foreach_function(f
, nir
) {
6984 nir_block
*top
= nir_start_block(f
->impl
);
6985 exec_node
*cursor_node
= NULL
;
6987 nir_foreach_block(block
, f
->impl
) {
6991 nir_foreach_instr_safe(instr
, block
) {
6992 if (instr
->type
!= nir_instr_type_intrinsic
)
6995 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6996 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6998 nir_intrinsic_instr
*bary_intrinsic
=
6999 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
7000 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
7002 /* Leave interpolateAtSample/Offset() where they are. */
7003 if (op
== nir_intrinsic_load_barycentric_at_sample
||
7004 op
== nir_intrinsic_load_barycentric_at_offset
)
7007 nir_instr
*move
[3] = {
7008 &bary_intrinsic
->instr
,
7009 intrin
->src
[1].ssa
->parent_instr
,
7013 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
7014 if (move
[i
]->block
!= top
) {
7015 move
[i
]->block
= top
;
7016 exec_node_remove(&move
[i
]->node
);
7018 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
7020 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
7022 cursor_node
= &move
[i
]->node
;
7028 nir_metadata_preserve(f
->impl
, (nir_metadata
)
7029 ((unsigned) nir_metadata_block_index
|
7030 (unsigned) nir_metadata_dominance
));
7037 * Demote per-sample barycentric intrinsics to centroid.
7039 * Useful when rendering to a non-multisampled buffer.
7042 demote_sample_qualifiers(nir_shader
*nir
)
7044 bool progress
= true;
7046 nir_foreach_function(f
, nir
) {
7051 nir_builder_init(&b
, f
->impl
);
7053 nir_foreach_block(block
, f
->impl
) {
7054 nir_foreach_instr_safe(instr
, block
) {
7055 if (instr
->type
!= nir_instr_type_intrinsic
)
7058 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
7059 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
7060 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
7063 b
.cursor
= nir_before_instr(instr
);
7064 nir_ssa_def
*centroid
=
7065 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
7066 nir_intrinsic_interp_mode(intrin
));
7067 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
7068 nir_src_for_ssa(centroid
));
7069 nir_instr_remove(instr
);
7074 nir_metadata_preserve(f
->impl
, (nir_metadata
)
7075 ((unsigned) nir_metadata_block_index
|
7076 (unsigned) nir_metadata_dominance
));
7083 * Pre-gen6, the register file of the EUs was shared between threads,
7084 * and each thread used some subset allocated on a 16-register block
7085 * granularity. The unit states wanted these block counts.
7088 brw_register_blocks(int reg_count
)
7090 return ALIGN(reg_count
, 16) / 16 - 1;
7094 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
7096 const struct brw_wm_prog_key
*key
,
7097 struct brw_wm_prog_data
*prog_data
,
7098 const nir_shader
*src_shader
,
7099 struct gl_program
*prog
,
7100 int shader_time_index8
, int shader_time_index16
,
7101 bool allow_spilling
,
7102 bool use_rep_send
, struct brw_vue_map
*vue_map
,
7105 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
7107 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
7108 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, true);
7109 brw_nir_lower_fs_inputs(shader
, devinfo
, key
);
7110 brw_nir_lower_fs_outputs(shader
);
7112 if (devinfo
->gen
< 6) {
7113 brw_setup_vue_interpolation(vue_map
, shader
, prog_data
, devinfo
);
7116 if (!key
->multisample_fbo
)
7117 NIR_PASS_V(shader
, demote_sample_qualifiers
);
7118 NIR_PASS_V(shader
, move_interpolation_to_top
);
7119 shader
= brw_postprocess_nir(shader
, compiler
, true);
7121 /* key->alpha_test_func means simulating alpha testing via discards,
7122 * so the shader definitely kills pixels.
7124 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
||
7125 key
->alpha_test_func
;
7126 prog_data
->uses_omask
= key
->multisample_fbo
&&
7127 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
7128 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
7129 prog_data
->computed_stencil
=
7130 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
7132 prog_data
->persample_dispatch
=
7133 key
->multisample_fbo
&&
7134 (key
->persample_interp
||
7135 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
7136 SYSTEM_BIT_SAMPLE_POS
)) ||
7137 shader
->info
.fs
.uses_sample_qualifier
||
7138 shader
->info
.outputs_read
);
7140 prog_data
->has_render_target_reads
= shader
->info
.outputs_read
!= 0ull;
7142 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
7143 prog_data
->post_depth_coverage
= shader
->info
.fs
.post_depth_coverage
;
7144 prog_data
->inner_coverage
= shader
->info
.fs
.inner_coverage
;
7146 prog_data
->barycentric_interp_modes
=
7147 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
7149 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
;
7151 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
7152 &prog_data
->base
, prog
, shader
, 8,
7153 shader_time_index8
);
7154 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
7156 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
7159 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
7161 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
7162 prog_data
->reg_blocks_8
= brw_register_blocks(v8
.grf_used
);
7165 if (v8
.max_dispatch_width
>= 16 &&
7166 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
7167 /* Try a SIMD16 compile */
7168 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
7169 &prog_data
->base
, prog
, shader
, 16,
7170 shader_time_index16
);
7171 v16
.import_uniforms(&v8
);
7172 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
7173 compiler
->shader_perf_log(log_data
,
7174 "SIMD16 shader failed to compile: %s",
7177 simd16_cfg
= v16
.cfg
;
7178 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
7179 prog_data
->reg_blocks_16
= brw_register_blocks(v16
.grf_used
);
7183 /* When the caller requests a repclear shader, they want SIMD16-only */
7187 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
7188 * at the top to select the shader. We've never implemented that.
7189 * Instead, we just give them exactly one shader and we pick the widest one
7192 if (compiler
->devinfo
->gen
< 5 && simd16_cfg
)
7195 if (compiler
->devinfo
->gen
<= 5 && !simd8_cfg
) {
7196 /* Iron lake and earlier only have one Dispatch GRF start field. Make
7197 * the data available in the base prog data struct for convenience.
7200 prog_data
->base
.dispatch_grf_start_reg
=
7201 prog_data
->dispatch_grf_start_reg_16
;
7205 if (prog_data
->persample_dispatch
) {
7206 /* Starting with SandyBridge (where we first get MSAA), the different
7207 * pixel dispatch combinations are grouped into classifications A
7208 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
7209 * generations, the only configurations supporting persample dispatch
7210 * are are this in which only one dispatch width is enabled.
7212 * If computed depth is enabled, SNB only allows SIMD8 while IVB+
7213 * allow SIMD8 or SIMD16 so we choose SIMD16 if available.
7215 if (compiler
->devinfo
->gen
== 6 &&
7216 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
) {
7218 } else if (simd16_cfg
) {
7223 /* We have to compute the flat inputs after the visitor is finished running
7224 * because it relies on prog_data->urb_setup which is computed in
7225 * fs_visitor::calculate_urb_setup().
7227 brw_compute_flat_inputs(prog_data
, shader
);
7229 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
7230 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
7231 MESA_SHADER_FRAGMENT
);
7233 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
7234 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
7235 shader
->info
.label
?
7236 shader
->info
.label
: "unnamed",
7237 shader
->info
.name
));
7241 prog_data
->dispatch_8
= true;
7242 g
.generate_code(simd8_cfg
, 8);
7246 prog_data
->dispatch_16
= true;
7247 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
7250 return g
.get_assembly();
7254 fs_visitor::emit_cs_work_group_id_setup()
7256 assert(stage
== MESA_SHADER_COMPUTE
);
7258 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
7260 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
7261 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
7262 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
7264 bld
.MOV(*reg
, r0_1
);
7265 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
7266 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
7272 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
7274 block
->dwords
= dwords
;
7275 block
->regs
= DIV_ROUND_UP(dwords
, 8);
7276 block
->size
= block
->regs
* 32;
7280 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
7281 struct brw_cs_prog_data
*cs_prog_data
)
7283 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
7284 int subgroup_id_index
= get_subgroup_id_param_index(prog_data
);
7285 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
7287 /* The thread ID should be stored in the last param dword */
7288 assert(subgroup_id_index
== -1 ||
7289 subgroup_id_index
== (int)prog_data
->nr_params
- 1);
7291 unsigned cross_thread_dwords
, per_thread_dwords
;
7292 if (!cross_thread_supported
) {
7293 cross_thread_dwords
= 0u;
7294 per_thread_dwords
= prog_data
->nr_params
;
7295 } else if (subgroup_id_index
>= 0) {
7296 /* Fill all but the last register with cross-thread payload */
7297 cross_thread_dwords
= 8 * (subgroup_id_index
/ 8);
7298 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
7299 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
7301 /* Fill all data using cross-thread payload */
7302 cross_thread_dwords
= prog_data
->nr_params
;
7303 per_thread_dwords
= 0u;
7306 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
7307 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
7309 unsigned total_dwords
=
7310 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
7311 cs_prog_data
->push
.cross_thread
.size
) / 4;
7312 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
7314 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
7315 cs_prog_data
->push
.per_thread
.size
== 0);
7316 assert(cs_prog_data
->push
.cross_thread
.dwords
+
7317 cs_prog_data
->push
.per_thread
.dwords
==
7318 prog_data
->nr_params
);
7322 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
7324 cs_prog_data
->simd_size
= size
;
7325 unsigned group_size
= cs_prog_data
->local_size
[0] *
7326 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
7327 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
7331 compile_cs_to_nir(const struct brw_compiler
*compiler
,
7333 const struct brw_cs_prog_key
*key
,
7334 const nir_shader
*src_shader
,
7335 unsigned dispatch_width
)
7337 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
7338 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, true);
7339 brw_nir_lower_cs_intrinsics(shader
, dispatch_width
);
7340 return brw_postprocess_nir(shader
, compiler
, true);
7344 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
7346 const struct brw_cs_prog_key
*key
,
7347 struct brw_cs_prog_data
*prog_data
,
7348 const nir_shader
*src_shader
,
7349 int shader_time_index
,
7352 prog_data
->local_size
[0] = src_shader
->info
.cs
.local_size
[0];
7353 prog_data
->local_size
[1] = src_shader
->info
.cs
.local_size
[1];
7354 prog_data
->local_size
[2] = src_shader
->info
.cs
.local_size
[2];
7355 unsigned local_workgroup_size
=
7356 src_shader
->info
.cs
.local_size
[0] * src_shader
->info
.cs
.local_size
[1] *
7357 src_shader
->info
.cs
.local_size
[2];
7359 unsigned min_dispatch_width
=
7360 DIV_ROUND_UP(local_workgroup_size
, compiler
->devinfo
->max_cs_threads
);
7361 min_dispatch_width
= MAX2(8, min_dispatch_width
);
7362 min_dispatch_width
= util_next_power_of_two(min_dispatch_width
);
7363 assert(min_dispatch_width
<= 32);
7365 fs_visitor
*v8
= NULL
, *v16
= NULL
, *v32
= NULL
;
7367 const char *fail_msg
= NULL
;
7368 unsigned promoted_constants
= 0;
7370 /* Now the main event: Visit the shader IR and generate our CS IR for it.
7372 if (min_dispatch_width
<= 8) {
7373 nir_shader
*nir8
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
7375 v8
= new fs_visitor(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
7376 NULL
, /* Never used in core profile */
7377 nir8
, 8, shader_time_index
);
7378 if (!v8
->run_cs(min_dispatch_width
)) {
7379 fail_msg
= v8
->fail_msg
;
7381 /* We should always be able to do SIMD32 for compute shaders */
7382 assert(v8
->max_dispatch_width
>= 32);
7385 cs_set_simd_size(prog_data
, 8);
7386 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
7387 promoted_constants
= v8
->promoted_constants
;
7391 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
7392 !fail_msg
&& min_dispatch_width
<= 16) {
7393 /* Try a SIMD16 compile */
7394 nir_shader
*nir16
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
7396 v16
= new fs_visitor(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
7397 NULL
, /* Never used in core profile */
7398 nir16
, 16, shader_time_index
);
7400 v16
->import_uniforms(v8
);
7402 if (!v16
->run_cs(min_dispatch_width
)) {
7403 compiler
->shader_perf_log(log_data
,
7404 "SIMD16 shader failed to compile: %s",
7408 "Couldn't generate SIMD16 program and not "
7409 "enough threads for SIMD8";
7412 /* We should always be able to do SIMD32 for compute shaders */
7413 assert(v16
->max_dispatch_width
>= 32);
7416 cs_set_simd_size(prog_data
, 16);
7417 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
7418 promoted_constants
= v16
->promoted_constants
;
7422 /* We should always be able to do SIMD32 for compute shaders */
7423 assert(!v16
|| v16
->max_dispatch_width
>= 32);
7425 if (!fail_msg
&& (min_dispatch_width
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
7426 /* Try a SIMD32 compile */
7427 nir_shader
*nir32
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
7429 v32
= new fs_visitor(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
7430 NULL
, /* Never used in core profile */
7431 nir32
, 32, shader_time_index
);
7433 v32
->import_uniforms(v8
);
7435 v32
->import_uniforms(v16
);
7437 if (!v32
->run_cs(min_dispatch_width
)) {
7438 compiler
->shader_perf_log(log_data
,
7439 "SIMD32 shader failed to compile: %s",
7443 "Couldn't generate SIMD32 program and not "
7444 "enough threads for SIMD16";
7448 cs_set_simd_size(prog_data
, 32);
7449 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
7450 promoted_constants
= v32
->promoted_constants
;
7454 const unsigned *ret
= NULL
;
7455 if (unlikely(cfg
== NULL
)) {
7458 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
7460 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
7461 promoted_constants
, false, MESA_SHADER_COMPUTE
);
7462 if (INTEL_DEBUG
& DEBUG_CS
) {
7463 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
7464 src_shader
->info
.label
?
7465 src_shader
->info
.label
: "unnamed",
7466 src_shader
->info
.name
);
7467 g
.enable_debug(name
);
7470 g
.generate_code(cfg
, prog_data
->simd_size
);
7472 ret
= g
.get_assembly();
7483 * Test the dispatch mask packing assumptions of
7484 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
7485 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
7486 * executed with an unexpected dispatch mask.
7489 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
7491 const gl_shader_stage stage
= bld
.shader
->stage
;
7493 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
7494 bld
.shader
->stage_prog_data
)) {
7495 const fs_builder ubld
= bld
.exec_all().group(1, 0);
7496 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
7497 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
7500 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
7501 ubld
.AND(tmp
, mask
, tmp
);
7503 /* This will loop forever if the dispatch mask doesn't have the expected
7504 * form '2^n-1', in which case tmp will be non-zero.
7506 bld
.emit(BRW_OPCODE_DO
);
7507 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
7508 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));