2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
35 #include "brw_vec4_gs_visitor.h"
37 #include "brw_dead_control_flow.h"
38 #include "common/gen_debug.h"
39 #include "compiler/glsl_types.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "program/prog_parameter.h"
45 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
49 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
50 const fs_reg
*src
, unsigned sources
)
52 memset(this, 0, sizeof(*this));
54 this->src
= new fs_reg
[MAX2(sources
, 3)];
55 for (unsigned i
= 0; i
< sources
; i
++)
56 this->src
[i
] = src
[i
];
58 this->opcode
= opcode
;
60 this->sources
= sources
;
61 this->exec_size
= exec_size
;
64 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
66 assert(this->exec_size
!= 0);
68 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
70 /* This will be the case for almost all instructions. */
77 this->size_written
= dst
.component_size(exec_size
);
80 this->size_written
= 0;
84 unreachable("Invalid destination register file");
87 this->writes_accumulator
= false;
92 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
95 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
97 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
100 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
102 init(opcode
, exec_size
, dst
, NULL
, 0);
105 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
108 const fs_reg src
[1] = { src0
};
109 init(opcode
, exec_size
, dst
, src
, 1);
112 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
113 const fs_reg
&src0
, const fs_reg
&src1
)
115 const fs_reg src
[2] = { src0
, src1
};
116 init(opcode
, exec_size
, dst
, src
, 2);
119 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
120 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
122 const fs_reg src
[3] = { src0
, src1
, src2
};
123 init(opcode
, exec_size
, dst
, src
, 3);
126 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
127 const fs_reg src
[], unsigned sources
)
129 init(opcode
, exec_width
, dst
, src
, sources
);
132 fs_inst::fs_inst(const fs_inst
&that
)
134 memcpy(this, &that
, sizeof(that
));
136 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
138 for (unsigned i
= 0; i
< that
.sources
; i
++)
139 this->src
[i
] = that
.src
[i
];
148 fs_inst::resize_sources(uint8_t num_sources
)
150 if (this->sources
!= num_sources
) {
151 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
153 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
154 src
[i
] = this->src
[i
];
158 this->sources
= num_sources
;
163 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
165 const fs_reg
&surf_index
,
166 const fs_reg
&varying_offset
,
167 uint32_t const_offset
)
169 /* We have our constant surface use a pitch of 4 bytes, so our index can
170 * be any component of a vector, and then we load 4 contiguous
171 * components starting from that.
173 * We break down the const_offset to a portion added to the variable offset
174 * and a portion done using fs_reg::offset, which means that if you have
175 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
176 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
177 * later notice that those loads are all the same and eliminate the
180 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
181 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
183 /* The pull load message will load a vec4 (16 bytes). If we are loading
184 * a double this means we are only loading 2 elements worth of data.
185 * We also want to use a 32-bit data type for the dst of the load operation
186 * so other parts of the driver don't get confused about the size of the
189 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
190 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
191 vec4_result
, surf_index
, vec4_offset
);
192 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
194 if (type_sz(dst
.type
) == 8) {
195 shuffle_32bit_load_result_to_64bit_data(
196 bld
, retype(vec4_result
, dst
.type
), vec4_result
, 2);
199 vec4_result
.type
= dst
.type
;
200 bld
.MOV(dst
, offset(vec4_result
, bld
,
201 (const_offset
& 0xf) / type_sz(vec4_result
.type
)));
205 * A helper for MOV generation for fixing up broken hardware SEND dependency
209 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
211 /* The caller always wants uncompressed to emit the minimal extra
212 * dependencies, and to avoid having to deal with aligning its regs to 2.
214 const fs_builder ubld
= bld
.annotate("send dependency resolve")
217 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
221 fs_inst::equals(fs_inst
*inst
) const
223 return (opcode
== inst
->opcode
&&
224 dst
.equals(inst
->dst
) &&
225 src
[0].equals(inst
->src
[0]) &&
226 src
[1].equals(inst
->src
[1]) &&
227 src
[2].equals(inst
->src
[2]) &&
228 saturate
== inst
->saturate
&&
229 predicate
== inst
->predicate
&&
230 conditional_mod
== inst
->conditional_mod
&&
231 mlen
== inst
->mlen
&&
232 base_mrf
== inst
->base_mrf
&&
233 target
== inst
->target
&&
235 header_size
== inst
->header_size
&&
236 shadow_compare
== inst
->shadow_compare
&&
237 exec_size
== inst
->exec_size
&&
238 offset
== inst
->offset
);
242 fs_inst::is_send_from_grf() const
245 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
246 case SHADER_OPCODE_SHADER_TIME_ADD
:
247 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
248 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
249 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
250 case SHADER_OPCODE_UNTYPED_ATOMIC
:
251 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
252 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
253 case SHADER_OPCODE_TYPED_ATOMIC
:
254 case SHADER_OPCODE_TYPED_SURFACE_READ
:
255 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
256 case SHADER_OPCODE_URB_WRITE_SIMD8
:
257 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
258 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
259 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
260 case SHADER_OPCODE_URB_READ_SIMD8
:
261 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
263 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
264 return src
[1].file
== VGRF
;
265 case FS_OPCODE_FB_WRITE
:
266 case FS_OPCODE_FB_READ
:
267 return src
[0].file
== VGRF
;
270 return src
[0].file
== VGRF
;
277 * Returns true if this instruction's sources and destinations cannot
278 * safely be the same register.
280 * In most cases, a register can be written over safely by the same
281 * instruction that is its last use. For a single instruction, the
282 * sources are dereferenced before writing of the destination starts
285 * However, there are a few cases where this can be problematic:
287 * - Virtual opcodes that translate to multiple instructions in the
288 * code generator: if src == dst and one instruction writes the
289 * destination before a later instruction reads the source, then
290 * src will have been clobbered.
292 * - SIMD16 compressed instructions with certain regioning (see below).
294 * The register allocator uses this information to set up conflicts between
295 * GRF sources and the destination.
298 fs_inst::has_source_and_destination_hazard() const
301 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
302 /* Multiple partial writes to the destination */
305 /* The SIMD16 compressed instruction
307 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
309 * is actually decoded in hardware as:
311 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
312 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
314 * Which is safe. However, if we have uniform accesses
315 * happening, we get into trouble:
317 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
318 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
320 * Now our destination for the first instruction overwrote the
321 * second instruction's src0, and we get garbage for those 8
322 * pixels. There's a similar issue for the pre-gen6
323 * pixel_x/pixel_y, which are registers of 16-bit values and thus
324 * would get stomped by the first decode as well.
326 if (exec_size
== 16) {
327 for (int i
= 0; i
< sources
; i
++) {
328 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
329 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
330 src
[i
].type
== BRW_REGISTER_TYPE_W
||
331 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
332 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
342 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
344 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
347 fs_reg reg
= this->src
[0];
348 if (reg
.file
!= VGRF
|| reg
.offset
!= 0 || reg
.stride
!= 1)
351 if (grf_alloc
.sizes
[reg
.nr
] * REG_SIZE
!= this->size_written
)
354 for (int i
= 0; i
< this->sources
; i
++) {
355 reg
.type
= this->src
[i
].type
;
356 if (!this->src
[i
].equals(reg
))
359 if (i
< this->header_size
) {
360 reg
.offset
+= REG_SIZE
;
362 reg
= horiz_offset(reg
, this->exec_size
);
370 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
)
372 if (devinfo
->gen
== 6 && is_math())
375 if (is_send_from_grf())
378 if (!backend_instruction::can_do_source_mods())
385 fs_inst::can_change_types() const
387 return dst
.type
== src
[0].type
&&
388 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
389 (opcode
== BRW_OPCODE_MOV
||
390 (opcode
== BRW_OPCODE_SEL
&&
391 dst
.type
== src
[1].type
&&
392 predicate
!= BRW_PREDICATE_NONE
&&
393 !src
[1].abs
&& !src
[1].negate
));
397 fs_inst::has_side_effects() const
399 return this->eot
|| backend_instruction::has_side_effects();
405 memset(this, 0, sizeof(*this));
409 /** Generic unset register constructor. */
413 this->file
= BAD_FILE
;
416 fs_reg::fs_reg(struct ::brw_reg reg
) :
421 if (this->file
== IMM
&&
422 (this->type
!= BRW_REGISTER_TYPE_V
&&
423 this->type
!= BRW_REGISTER_TYPE_UV
&&
424 this->type
!= BRW_REGISTER_TYPE_VF
)) {
430 fs_reg::equals(const fs_reg
&r
) const
432 return (this->backend_reg::equals(r
) &&
437 fs_reg::is_contiguous() const
443 fs_reg::component_size(unsigned width
) const
445 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
448 return MAX2(width
* stride
, 1) * type_sz(type
);
452 type_size_scalar(const struct glsl_type
*type
)
454 unsigned int size
, i
;
456 switch (type
->base_type
) {
459 case GLSL_TYPE_FLOAT
:
461 return type
->components();
462 case GLSL_TYPE_DOUBLE
:
463 case GLSL_TYPE_UINT64
:
464 case GLSL_TYPE_INT64
:
465 return type
->components() * 2;
466 case GLSL_TYPE_ARRAY
:
467 return type_size_scalar(type
->fields
.array
) * type
->length
;
468 case GLSL_TYPE_STRUCT
:
470 for (i
= 0; i
< type
->length
; i
++) {
471 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
474 case GLSL_TYPE_SAMPLER
:
475 /* Samplers take up no register space, since they're baked in at
479 case GLSL_TYPE_ATOMIC_UINT
:
481 case GLSL_TYPE_SUBROUTINE
:
483 case GLSL_TYPE_IMAGE
:
484 return BRW_IMAGE_PARAM_SIZE
;
486 case GLSL_TYPE_ERROR
:
487 case GLSL_TYPE_INTERFACE
:
488 case GLSL_TYPE_FUNCTION
:
489 unreachable("not reached");
496 * Create a MOV to read the timestamp register.
498 * The caller is responsible for emitting the MOV. The return value is
499 * the destination of the MOV, with extra parameters set.
502 fs_visitor::get_timestamp(const fs_builder
&bld
)
504 assert(devinfo
->gen
>= 7);
506 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
509 BRW_REGISTER_TYPE_UD
));
511 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
513 /* We want to read the 3 fields we care about even if it's not enabled in
516 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
522 fs_visitor::emit_shader_time_begin()
524 /* We want only the low 32 bits of the timestamp. Since it's running
525 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
526 * which is plenty of time for our purposes. It is identical across the
527 * EUs, but since it's tracking GPU core speed it will increment at a
528 * varying rate as render P-states change.
530 shader_start_time
= component(
531 get_timestamp(bld
.annotate("shader time start")), 0);
535 fs_visitor::emit_shader_time_end()
537 /* Insert our code just before the final SEND with EOT. */
538 exec_node
*end
= this->instructions
.get_tail();
539 assert(end
&& ((fs_inst
*) end
)->eot
);
540 const fs_builder ibld
= bld
.annotate("shader time end")
541 .exec_all().at(NULL
, end
);
542 const fs_reg timestamp
= get_timestamp(ibld
);
544 /* We only use the low 32 bits of the timestamp - see
545 * emit_shader_time_begin()).
547 * We could also check if render P-states have changed (or anything
548 * else that might disrupt timing) by setting smear to 2 and checking if
549 * that field is != 0.
551 const fs_reg shader_end_time
= component(timestamp
, 0);
553 /* Check that there weren't any timestamp reset events (assuming these
554 * were the only two timestamp reads that happened).
556 const fs_reg reset
= component(timestamp
, 2);
557 set_condmod(BRW_CONDITIONAL_Z
,
558 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
559 ibld
.IF(BRW_PREDICATE_NORMAL
);
561 fs_reg start
= shader_start_time
;
563 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
564 BRW_REGISTER_TYPE_UD
),
566 const fs_builder cbld
= ibld
.group(1, 0);
567 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
569 /* If there were no instructions between the two timestamp gets, the diff
570 * is 2 cycles. Remove that overhead, so I can forget about that when
571 * trying to determine the time taken for single instructions.
573 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
574 SHADER_TIME_ADD(cbld
, 0, diff
);
575 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
576 ibld
.emit(BRW_OPCODE_ELSE
);
577 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
578 ibld
.emit(BRW_OPCODE_ENDIF
);
582 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
583 int shader_time_subindex
,
586 int index
= shader_time_index
* 3 + shader_time_subindex
;
587 struct brw_reg offset
= brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
);
590 if (dispatch_width
== 8)
591 payload
= vgrf(glsl_type::uvec2_type
);
593 payload
= vgrf(glsl_type::uint_type
);
595 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
599 fs_visitor::vfail(const char *format
, va_list va
)
608 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
609 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
611 this->fail_msg
= msg
;
614 fprintf(stderr
, "%s", msg
);
619 fs_visitor::fail(const char *format
, ...)
623 va_start(va
, format
);
629 * Mark this program as impossible to compile with dispatch width greater
632 * During the SIMD8 compile (which happens first), we can detect and flag
633 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
634 * SIMD16+ compile altogether.
636 * During a compile of dispatch width greater than n (if one happens anyway),
637 * this just calls fail().
640 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
642 if (dispatch_width
> n
) {
645 max_dispatch_width
= n
;
646 compiler
->shader_perf_log(log_data
,
647 "Shader dispatch width limited to SIMD%d: %s",
653 * Returns true if the instruction has a flag that means it won't
654 * update an entire destination register.
656 * For example, dead code elimination and live variable analysis want to know
657 * when a write to a variable screens off any preceding values that were in
661 fs_inst::is_partial_write() const
663 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
664 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
665 !this->dst
.is_contiguous() ||
666 this->dst
.offset
% REG_SIZE
!= 0);
670 fs_inst::components_read(unsigned i
) const
672 /* Return zero if the source is not present. */
673 if (src
[i
].file
== BAD_FILE
)
677 case FS_OPCODE_LINTERP
:
683 case FS_OPCODE_PIXEL_X
:
684 case FS_OPCODE_PIXEL_Y
:
688 case FS_OPCODE_FB_WRITE_LOGICAL
:
689 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
690 /* First/second FB write color. */
692 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
696 case SHADER_OPCODE_TEX_LOGICAL
:
697 case SHADER_OPCODE_TXD_LOGICAL
:
698 case SHADER_OPCODE_TXF_LOGICAL
:
699 case SHADER_OPCODE_TXL_LOGICAL
:
700 case SHADER_OPCODE_TXS_LOGICAL
:
701 case FS_OPCODE_TXB_LOGICAL
:
702 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
703 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
704 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
705 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
706 case SHADER_OPCODE_LOD_LOGICAL
:
707 case SHADER_OPCODE_TG4_LOGICAL
:
708 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
709 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
710 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
711 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
712 /* Texture coordinates. */
713 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
714 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
715 /* Texture derivatives. */
716 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
717 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
718 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
719 /* Texture offset. */
720 else if (i
== TEX_LOGICAL_SRC_TG4_OFFSET
)
723 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
728 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
729 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
730 assert(src
[3].file
== IMM
);
731 /* Surface coordinates. */
734 /* Surface operation source (ignored for reads). */
740 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
741 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
742 assert(src
[3].file
== IMM
&&
744 /* Surface coordinates. */
747 /* Surface operation source. */
753 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
754 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
755 assert(src
[3].file
== IMM
&&
757 const unsigned op
= src
[4].ud
;
758 /* Surface coordinates. */
761 /* Surface operation source. */
762 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
764 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
765 op
== BRW_AOP_PREDEC
))
777 fs_inst::size_read(int arg
) const
780 case FS_OPCODE_FB_WRITE
:
781 case FS_OPCODE_FB_READ
:
782 case SHADER_OPCODE_URB_WRITE_SIMD8
:
783 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
784 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
785 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
786 case SHADER_OPCODE_URB_READ_SIMD8
:
787 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
788 case SHADER_OPCODE_UNTYPED_ATOMIC
:
789 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
790 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
791 case SHADER_OPCODE_TYPED_ATOMIC
:
792 case SHADER_OPCODE_TYPED_SURFACE_READ
:
793 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
794 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
796 return mlen
* REG_SIZE
;
799 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
800 /* The payload is actually stored in src1 */
802 return mlen
* REG_SIZE
;
805 case FS_OPCODE_LINTERP
:
810 case SHADER_OPCODE_LOAD_PAYLOAD
:
811 if (arg
< this->header_size
)
815 case CS_OPCODE_CS_TERMINATE
:
816 case SHADER_OPCODE_BARRIER
:
819 case SHADER_OPCODE_MOV_INDIRECT
:
821 assert(src
[2].file
== IMM
);
827 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
828 return mlen
* REG_SIZE
;
832 switch (src
[arg
].file
) {
835 return components_read(arg
) * type_sz(src
[arg
].type
);
841 return components_read(arg
) * src
[arg
].component_size(exec_size
);
843 unreachable("MRF registers are not allowed as sources");
849 /* Return the subset of flag registers that an instruction could
850 * potentially read or write based on the execution controls and flag
851 * subregister number of the instruction.
854 flag_mask(const fs_inst
*inst
)
856 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
857 const unsigned end
= start
+ inst
->exec_size
;
858 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
863 fs_inst::flags_read(const gen_device_info
*devinfo
) const
865 /* XXX - This doesn't consider explicit uses of the flag register as source
868 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
869 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
870 /* The vertical predication modes combine corresponding bits from
871 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
873 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
874 return flag_mask(this) << shift
| flag_mask(this);
875 } else if (predicate
) {
876 return flag_mask(this);
883 fs_inst::flags_written() const
885 /* XXX - This doesn't consider explicit uses of the flag register as
886 * destination region.
888 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
889 opcode
!= BRW_OPCODE_IF
&&
890 opcode
!= BRW_OPCODE_WHILE
)) ||
891 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
892 return flag_mask(this);
899 * Returns how many MRFs an FS opcode will write over.
901 * Note that this is not the 0 or 1 implied writes in an actual gen
902 * instruction -- the FS opcodes often generate MOVs in addition.
905 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
910 if (inst
->base_mrf
== -1)
913 switch (inst
->opcode
) {
914 case SHADER_OPCODE_RCP
:
915 case SHADER_OPCODE_RSQ
:
916 case SHADER_OPCODE_SQRT
:
917 case SHADER_OPCODE_EXP2
:
918 case SHADER_OPCODE_LOG2
:
919 case SHADER_OPCODE_SIN
:
920 case SHADER_OPCODE_COS
:
921 return 1 * dispatch_width
/ 8;
922 case SHADER_OPCODE_POW
:
923 case SHADER_OPCODE_INT_QUOTIENT
:
924 case SHADER_OPCODE_INT_REMAINDER
:
925 return 2 * dispatch_width
/ 8;
926 case SHADER_OPCODE_TEX
:
928 case SHADER_OPCODE_TXD
:
929 case SHADER_OPCODE_TXF
:
930 case SHADER_OPCODE_TXF_CMS
:
931 case SHADER_OPCODE_TXF_MCS
:
932 case SHADER_OPCODE_TG4
:
933 case SHADER_OPCODE_TG4_OFFSET
:
934 case SHADER_OPCODE_TXL
:
935 case SHADER_OPCODE_TXS
:
936 case SHADER_OPCODE_LOD
:
937 case SHADER_OPCODE_SAMPLEINFO
:
939 case FS_OPCODE_FB_WRITE
:
941 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
942 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
944 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
946 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
949 unreachable("not reached");
954 fs_visitor::vgrf(const glsl_type
*const type
)
956 int reg_width
= dispatch_width
/ 8;
957 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
958 brw_type_for_base_type(type
));
961 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
966 this->type
= BRW_REGISTER_TYPE_F
;
967 this->stride
= (file
== UNIFORM
? 0 : 1);
970 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
976 this->stride
= (file
== UNIFORM
? 0 : 1);
979 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
980 * This brings in those uniform definitions
983 fs_visitor::import_uniforms(fs_visitor
*v
)
985 this->push_constant_loc
= v
->push_constant_loc
;
986 this->pull_constant_loc
= v
->pull_constant_loc
;
987 this->uniforms
= v
->uniforms
;
991 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
993 assert(stage
== MESA_SHADER_FRAGMENT
);
996 bld
.MOV(wpos
, this->pixel_x
);
997 wpos
= offset(wpos
, bld
, 1);
1000 bld
.MOV(wpos
, this->pixel_y
);
1001 wpos
= offset(wpos
, bld
, 1);
1003 /* gl_FragCoord.z */
1004 if (devinfo
->gen
>= 6) {
1005 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1007 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1008 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1009 interp_reg(VARYING_SLOT_POS
, 2));
1011 wpos
= offset(wpos
, bld
, 1);
1013 /* gl_FragCoord.w: Already set up in emit_interpolation */
1014 bld
.MOV(wpos
, this->wpos_w
);
1017 enum brw_barycentric_mode
1018 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1020 /* Barycentric modes don't make sense for flat inputs. */
1021 assert(mode
!= INTERP_MODE_FLAT
);
1025 case nir_intrinsic_load_barycentric_pixel
:
1026 case nir_intrinsic_load_barycentric_at_offset
:
1027 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1029 case nir_intrinsic_load_barycentric_centroid
:
1030 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1032 case nir_intrinsic_load_barycentric_sample
:
1033 case nir_intrinsic_load_barycentric_at_sample
:
1034 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1037 unreachable("invalid intrinsic");
1040 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1043 return (enum brw_barycentric_mode
) bary
;
1047 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1049 static enum brw_barycentric_mode
1050 centroid_to_pixel(enum brw_barycentric_mode bary
)
1052 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1053 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1054 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1058 fs_visitor::emit_frontfacing_interpolation()
1060 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1062 if (devinfo
->gen
>= 6) {
1063 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1064 * a boolean result from this (~0/true or 0/false).
1066 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1067 * this task in only one instruction:
1068 * - a negation source modifier will flip the bit; and
1069 * - a W -> D type conversion will sign extend the bit into the high
1070 * word of the destination.
1072 * An ASR 15 fills the low word of the destination.
1074 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1077 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1079 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1080 * a boolean result from this (1/true or 0/false).
1082 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1083 * the negation source modifier to flip it. Unfortunately the SHR
1084 * instruction only operates on UD (or D with an abs source modifier)
1085 * sources without negation.
1087 * Instead, use ASR (which will give ~0/true or 0/false).
1089 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1092 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1099 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1101 assert(stage
== MESA_SHADER_FRAGMENT
);
1102 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1103 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1105 if (wm_prog_data
->persample_dispatch
) {
1106 /* Convert int_sample_pos to floating point */
1107 bld
.MOV(dst
, int_sample_pos
);
1108 /* Scale to the range [0, 1] */
1109 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1112 /* From ARB_sample_shading specification:
1113 * "When rendering to a non-multisample buffer, or if multisample
1114 * rasterization is disabled, gl_SamplePosition will always be
1117 bld
.MOV(dst
, brw_imm_f(0.5f
));
1122 fs_visitor::emit_samplepos_setup()
1124 assert(devinfo
->gen
>= 6);
1126 const fs_builder abld
= bld
.annotate("compute sample position");
1127 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1129 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1130 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1132 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1133 * mode will be enabled.
1135 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1136 * R31.1:0 Position Offset X/Y for Slot[3:0]
1137 * R31.3:2 Position Offset X/Y for Slot[7:4]
1140 * The X, Y sample positions come in as bytes in thread payload. So, read
1141 * the positions using vstride=16, width=8, hstride=2.
1143 struct brw_reg sample_pos_reg
=
1144 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1145 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1147 if (dispatch_width
== 8) {
1148 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1150 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1151 abld
.half(1).MOV(half(int_sample_x
, 1),
1152 fs_reg(suboffset(sample_pos_reg
, 16)));
1154 /* Compute gl_SamplePosition.x */
1155 compute_sample_position(pos
, int_sample_x
);
1156 pos
= offset(pos
, abld
, 1);
1157 if (dispatch_width
== 8) {
1158 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1160 abld
.half(0).MOV(half(int_sample_y
, 0),
1161 fs_reg(suboffset(sample_pos_reg
, 1)));
1162 abld
.half(1).MOV(half(int_sample_y
, 1),
1163 fs_reg(suboffset(sample_pos_reg
, 17)));
1165 /* Compute gl_SamplePosition.y */
1166 compute_sample_position(pos
, int_sample_y
);
1171 fs_visitor::emit_sampleid_setup()
1173 assert(stage
== MESA_SHADER_FRAGMENT
);
1174 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1175 assert(devinfo
->gen
>= 6);
1177 const fs_builder abld
= bld
.annotate("compute sample id");
1178 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1180 if (!key
->multisample_fbo
) {
1181 /* As per GL_ARB_sample_shading specification:
1182 * "When rendering to a non-multisample buffer, or if multisample
1183 * rasterization is disabled, gl_SampleID will always be zero."
1185 abld
.MOV(*reg
, brw_imm_d(0));
1186 } else if (devinfo
->gen
>= 8) {
1187 /* Sample ID comes in as 4-bit numbers in g1.0:
1189 * 15:12 Slot 3 SampleID (only used in SIMD16)
1190 * 11:8 Slot 2 SampleID (only used in SIMD16)
1191 * 7:4 Slot 1 SampleID
1192 * 3:0 Slot 0 SampleID
1194 * Each slot corresponds to four channels, so we want to replicate each
1195 * half-byte value to 4 channels in a row:
1197 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1198 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1200 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1201 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1203 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1204 * channels to read the first byte (7:0), and the second group of 8
1205 * channels to read the second byte (15:8). Then, we shift right by
1206 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1207 * values into place. Finally, we AND with 0xf to keep the low nibble.
1209 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1210 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1212 * TODO: These payload bits exist on Gen7 too, but they appear to always
1213 * be zero, so this code fails to work. We should find out why.
1215 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1217 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1218 BRW_REGISTER_TYPE_B
), 1, 8, 0)),
1219 brw_imm_v(0x44440000));
1220 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1222 const fs_reg t1
= component(fs_reg(VGRF
, alloc
.allocate(1),
1223 BRW_REGISTER_TYPE_D
), 0);
1224 const fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1226 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1227 * 8x multisampling, subspan 0 will represent sample N (where N
1228 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1229 * 7. We can find the value of N by looking at R0.0 bits 7:6
1230 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1231 * (since samples are always delivered in pairs). That is, we
1232 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1233 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1234 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1235 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1236 * populating a temporary variable with the sequence (0, 1, 2, 3),
1237 * and then reading from it using vstride=1, width=4, hstride=0.
1238 * These computations hold good for 4x multisampling as well.
1240 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1241 * the first four slots are sample 0 of subspan 0; the next four
1242 * are sample 1 of subspan 0; the third group is sample 0 of
1243 * subspan 1, and finally sample 1 of subspan 1.
1246 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1247 * accomodate 16x MSAA.
1249 abld
.exec_all().group(1, 0)
1250 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1252 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1254 /* This works for both SIMD8 and SIMD16 */
1255 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1257 /* This special instruction takes care of setting vstride=1,
1258 * width=4, hstride=0 of t2 during an ADD instruction.
1260 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1267 fs_visitor::emit_samplemaskin_setup()
1269 assert(stage
== MESA_SHADER_FRAGMENT
);
1270 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1271 assert(devinfo
->gen
>= 6);
1273 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1275 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1276 BRW_REGISTER_TYPE_D
));
1278 if (wm_prog_data
->persample_dispatch
) {
1279 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1280 * and a mask representing which sample is being processed by the
1281 * current shader invocation.
1283 * From the OES_sample_variables specification:
1284 * "When per-sample shading is active due to the use of a fragment input
1285 * qualified by "sample" or due to the use of the gl_SampleID or
1286 * gl_SamplePosition variables, only the bit for the current sample is
1287 * set in gl_SampleMaskIn."
1289 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1291 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1292 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1294 fs_reg one
= vgrf(glsl_type::int_type
);
1295 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1296 abld
.MOV(one
, brw_imm_d(1));
1297 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1298 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1300 /* In per-pixel mode, the coverage mask is sufficient. */
1301 *reg
= coverage_mask
;
1307 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1309 if (!src
.abs
&& !src
.negate
)
1312 fs_reg temp
= bld
.vgrf(src
.type
);
1319 fs_visitor::emit_discard_jump()
1321 assert(brw_wm_prog_data(this->prog_data
)->uses_kill
);
1323 /* For performance, after a discard, jump to the end of the
1324 * shader if all relevant channels have been discarded.
1326 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1327 discard_jump
->flag_subreg
= 1;
1329 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1330 discard_jump
->predicate_inverse
= true;
1334 fs_visitor::emit_gs_thread_end()
1336 assert(stage
== MESA_SHADER_GEOMETRY
);
1338 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1340 if (gs_compile
->control_data_header_size_bits
> 0) {
1341 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1344 const fs_builder abld
= bld
.annotate("thread end");
1347 if (gs_prog_data
->static_vertex_count
!= -1) {
1348 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1349 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1350 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1351 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1352 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1355 /* Delete now dead instructions. */
1356 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1362 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1366 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1367 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1368 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1371 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1372 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1373 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1374 sources
[1] = this->final_gs_vertex_count
;
1375 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1376 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1384 fs_visitor::assign_curb_setup()
1386 unsigned uniform_push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
1388 unsigned ubo_push_length
= 0;
1389 unsigned ubo_push_start
[4];
1390 for (int i
= 0; i
< 4; i
++) {
1391 ubo_push_start
[i
] = 8 * (ubo_push_length
+ uniform_push_length
);
1392 ubo_push_length
+= stage_prog_data
->ubo_ranges
[i
].length
;
1395 prog_data
->curb_read_length
= uniform_push_length
+ ubo_push_length
;
1397 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1398 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1399 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1400 if (inst
->src
[i
].file
== UNIFORM
) {
1401 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1403 if (inst
->src
[i
].nr
>= UBO_START
) {
1404 /* constant_nr is in 32-bit units, the rest are in bytes */
1405 constant_nr
= ubo_push_start
[inst
->src
[i
].nr
- UBO_START
] +
1406 inst
->src
[i
].offset
/ 4;
1407 } else if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1408 constant_nr
= push_constant_loc
[uniform_nr
];
1410 /* Section 5.11 of the OpenGL 4.1 spec says:
1411 * "Out-of-bounds reads return undefined values, which include
1412 * values from other variables of the active program or zero."
1413 * Just return the first push constant.
1418 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1421 brw_reg
.abs
= inst
->src
[i
].abs
;
1422 brw_reg
.negate
= inst
->src
[i
].negate
;
1424 assert(inst
->src
[i
].stride
== 0);
1425 inst
->src
[i
] = byte_offset(
1426 retype(brw_reg
, inst
->src
[i
].type
),
1427 inst
->src
[i
].offset
% 4);
1432 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1433 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1437 fs_visitor::calculate_urb_setup()
1439 assert(stage
== MESA_SHADER_FRAGMENT
);
1440 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1441 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1443 memset(prog_data
->urb_setup
, -1,
1444 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1447 /* Figure out where each of the incoming setup attributes lands. */
1448 if (devinfo
->gen
>= 6) {
1449 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1450 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1451 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1452 * first 16 varying inputs, so we can put them wherever we want.
1453 * Just put them in order.
1455 * This is useful because it means that (a) inputs not used by the
1456 * fragment shader won't take up valuable register space, and (b) we
1457 * won't have to recompile the fragment shader if it gets paired with
1458 * a different vertex (or geometry) shader.
1460 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1461 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1462 BITFIELD64_BIT(i
)) {
1463 prog_data
->urb_setup
[i
] = urb_next
++;
1467 bool include_vue_header
=
1468 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1470 /* We have enough input varyings that the SF/SBE pipeline stage can't
1471 * arbitrarily rearrange them to suit our whim; we have to put them
1472 * in an order that matches the output of the previous pipeline stage
1473 * (geometry or vertex shader).
1475 struct brw_vue_map prev_stage_vue_map
;
1476 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1477 key
->input_slots_valid
,
1478 nir
->info
.separate_shader
);
1480 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1482 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1483 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1485 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1486 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1487 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1488 BITFIELD64_BIT(varying
))) {
1489 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1492 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1495 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1496 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1497 /* Point size is packed into the header, not as a general attribute */
1498 if (i
== VARYING_SLOT_PSIZ
)
1501 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1502 /* The back color slot is skipped when the front color is
1503 * also written to. In addition, some slots can be
1504 * written in the vertex shader and not read in the
1505 * fragment shader. So the register number must always be
1506 * incremented, mapped or not.
1508 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1509 prog_data
->urb_setup
[i
] = urb_next
;
1515 * It's a FS only attribute, and we did interpolation for this attribute
1516 * in SF thread. So, count it here, too.
1518 * See compile_sf_prog() for more info.
1520 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1521 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1524 prog_data
->num_varying_inputs
= urb_next
;
1528 fs_visitor::assign_urb_setup()
1530 assert(stage
== MESA_SHADER_FRAGMENT
);
1531 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1533 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1535 /* Offset all the urb_setup[] index by the actual position of the
1536 * setup regs, now that the location of the constants has been chosen.
1538 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1539 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1540 assert(inst
->src
[1].file
== FIXED_GRF
);
1541 inst
->src
[1].nr
+= urb_start
;
1544 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1545 assert(inst
->src
[0].file
== FIXED_GRF
);
1546 inst
->src
[0].nr
+= urb_start
;
1550 /* Each attribute is 4 setup channels, each of which is half a reg. */
1551 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1555 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1557 for (int i
= 0; i
< inst
->sources
; i
++) {
1558 if (inst
->src
[i
].file
== ATTR
) {
1559 int grf
= payload
.num_regs
+
1560 prog_data
->curb_read_length
+
1562 inst
->src
[i
].offset
/ REG_SIZE
;
1564 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1566 * VertStride must be used to cross GRF register boundaries. This
1567 * rule implies that elements within a 'Width' cannot cross GRF
1570 * So, for registers that are large enough, we have to split the exec
1571 * size in two and trust the compression state to sort it out.
1573 unsigned total_size
= inst
->exec_size
*
1574 inst
->src
[i
].stride
*
1575 type_sz(inst
->src
[i
].type
);
1577 assert(total_size
<= 2 * REG_SIZE
);
1578 const unsigned exec_size
=
1579 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1581 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1582 struct brw_reg reg
=
1583 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1584 inst
->src
[i
].offset
% REG_SIZE
),
1585 exec_size
* inst
->src
[i
].stride
,
1586 width
, inst
->src
[i
].stride
);
1587 reg
.abs
= inst
->src
[i
].abs
;
1588 reg
.negate
= inst
->src
[i
].negate
;
1596 fs_visitor::assign_vs_urb_setup()
1598 struct brw_vs_prog_data
*vs_prog_data
= brw_vs_prog_data(prog_data
);
1600 assert(stage
== MESA_SHADER_VERTEX
);
1602 /* Each attribute is 4 regs. */
1603 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1605 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1607 /* Rewrite all ATTR file references to the hw grf that they land in. */
1608 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1609 convert_attr_sources_to_hw_regs(inst
);
1614 fs_visitor::assign_tcs_single_patch_urb_setup()
1616 assert(stage
== MESA_SHADER_TESS_CTRL
);
1618 /* Rewrite all ATTR file references to HW_REGs. */
1619 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1620 convert_attr_sources_to_hw_regs(inst
);
1625 fs_visitor::assign_tes_urb_setup()
1627 assert(stage
== MESA_SHADER_TESS_EVAL
);
1629 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1631 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1633 /* Rewrite all ATTR file references to HW_REGs. */
1634 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1635 convert_attr_sources_to_hw_regs(inst
);
1640 fs_visitor::assign_gs_urb_setup()
1642 assert(stage
== MESA_SHADER_GEOMETRY
);
1644 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1646 first_non_payload_grf
+=
1647 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1649 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1650 /* Rewrite all ATTR file references to GRFs. */
1651 convert_attr_sources_to_hw_regs(inst
);
1657 * Split large virtual GRFs into separate components if we can.
1659 * This is mostly duplicated with what brw_fs_vector_splitting does,
1660 * but that's really conservative because it's afraid of doing
1661 * splitting that doesn't result in real progress after the rest of
1662 * the optimization phases, which would cause infinite looping in
1663 * optimization. We can do it once here, safely. This also has the
1664 * opportunity to split interpolated values, or maybe even uniforms,
1665 * which we don't have at the IR level.
1667 * We want to split, because virtual GRFs are what we register
1668 * allocate and spill (due to contiguousness requirements for some
1669 * instructions), and they're what we naturally generate in the
1670 * codegen process, but most virtual GRFs don't actually need to be
1671 * contiguous sets of GRFs. If we split, we'll end up with reduced
1672 * live intervals and better dead code elimination and coalescing.
1675 fs_visitor::split_virtual_grfs()
1677 /* Compact the register file so we eliminate dead vgrfs. This
1678 * only defines split points for live registers, so if we have
1679 * too large dead registers they will hit assertions later.
1681 compact_virtual_grfs();
1683 int num_vars
= this->alloc
.count
;
1685 /* Count the total number of registers */
1687 int vgrf_to_reg
[num_vars
];
1688 for (int i
= 0; i
< num_vars
; i
++) {
1689 vgrf_to_reg
[i
] = reg_count
;
1690 reg_count
+= alloc
.sizes
[i
];
1693 /* An array of "split points". For each register slot, this indicates
1694 * if this slot can be separated from the previous slot. Every time an
1695 * instruction uses multiple elements of a register (as a source or
1696 * destination), we mark the used slots as inseparable. Then we go
1697 * through and split the registers into the smallest pieces we can.
1699 bool split_points
[reg_count
];
1700 memset(split_points
, 0, sizeof(split_points
));
1702 /* Mark all used registers as fully splittable */
1703 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1704 if (inst
->dst
.file
== VGRF
) {
1705 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1706 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1707 split_points
[reg
+ j
] = true;
1710 for (int i
= 0; i
< inst
->sources
; i
++) {
1711 if (inst
->src
[i
].file
== VGRF
) {
1712 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1713 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1714 split_points
[reg
+ j
] = true;
1719 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1720 if (inst
->dst
.file
== VGRF
) {
1721 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1722 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1723 split_points
[reg
+ j
] = false;
1725 for (int i
= 0; i
< inst
->sources
; i
++) {
1726 if (inst
->src
[i
].file
== VGRF
) {
1727 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1728 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1729 split_points
[reg
+ j
] = false;
1734 int new_virtual_grf
[reg_count
];
1735 int new_reg_offset
[reg_count
];
1738 for (int i
= 0; i
< num_vars
; i
++) {
1739 /* The first one should always be 0 as a quick sanity check. */
1740 assert(split_points
[reg
] == false);
1743 new_reg_offset
[reg
] = 0;
1748 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1749 /* If this is a split point, reset the offset to 0 and allocate a
1750 * new virtual GRF for the previous offset many registers
1752 if (split_points
[reg
]) {
1753 assert(offset
<= MAX_VGRF_SIZE
);
1754 int grf
= alloc
.allocate(offset
);
1755 for (int k
= reg
- offset
; k
< reg
; k
++)
1756 new_virtual_grf
[k
] = grf
;
1759 new_reg_offset
[reg
] = offset
;
1764 /* The last one gets the original register number */
1765 assert(offset
<= MAX_VGRF_SIZE
);
1766 alloc
.sizes
[i
] = offset
;
1767 for (int k
= reg
- offset
; k
< reg
; k
++)
1768 new_virtual_grf
[k
] = i
;
1770 assert(reg
== reg_count
);
1772 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1773 if (inst
->dst
.file
== VGRF
) {
1774 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1775 inst
->dst
.nr
= new_virtual_grf
[reg
];
1776 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
1777 inst
->dst
.offset
% REG_SIZE
;
1778 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1780 for (int i
= 0; i
< inst
->sources
; i
++) {
1781 if (inst
->src
[i
].file
== VGRF
) {
1782 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1783 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1784 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
1785 inst
->src
[i
].offset
% REG_SIZE
;
1786 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1790 invalidate_live_intervals();
1794 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1796 * During code generation, we create tons of temporary variables, many of
1797 * which get immediately killed and are never used again. Yet, in later
1798 * optimization and analysis passes, such as compute_live_intervals, we need
1799 * to loop over all the virtual GRFs. Compacting them can save a lot of
1803 fs_visitor::compact_virtual_grfs()
1805 bool progress
= false;
1806 int remap_table
[this->alloc
.count
];
1807 memset(remap_table
, -1, sizeof(remap_table
));
1809 /* Mark which virtual GRFs are used. */
1810 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1811 if (inst
->dst
.file
== VGRF
)
1812 remap_table
[inst
->dst
.nr
] = 0;
1814 for (int i
= 0; i
< inst
->sources
; i
++) {
1815 if (inst
->src
[i
].file
== VGRF
)
1816 remap_table
[inst
->src
[i
].nr
] = 0;
1820 /* Compact the GRF arrays. */
1822 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1823 if (remap_table
[i
] == -1) {
1824 /* We just found an unused register. This means that we are
1825 * actually going to compact something.
1829 remap_table
[i
] = new_index
;
1830 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1831 invalidate_live_intervals();
1836 this->alloc
.count
= new_index
;
1838 /* Patch all the instructions to use the newly renumbered registers */
1839 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1840 if (inst
->dst
.file
== VGRF
)
1841 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1843 for (int i
= 0; i
< inst
->sources
; i
++) {
1844 if (inst
->src
[i
].file
== VGRF
)
1845 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1849 /* Patch all the references to delta_xy, since they're used in register
1850 * allocation. If they're unused, switch them to BAD_FILE so we don't
1851 * think some random VGRF is delta_xy.
1853 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1854 if (delta_xy
[i
].file
== VGRF
) {
1855 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1856 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1858 delta_xy
[i
].file
= BAD_FILE
;
1867 set_push_pull_constant_loc(unsigned uniform
, int *chunk_start
,
1868 unsigned *max_chunk_bitsize
,
1869 bool contiguous
, unsigned bitsize
,
1870 const unsigned target_bitsize
,
1871 int *push_constant_loc
, int *pull_constant_loc
,
1872 unsigned *num_push_constants
,
1873 unsigned *num_pull_constants
,
1874 const unsigned max_push_components
,
1875 const unsigned max_chunk_size
,
1876 struct brw_stage_prog_data
*stage_prog_data
)
1878 /* This is the first live uniform in the chunk */
1879 if (*chunk_start
< 0)
1880 *chunk_start
= uniform
;
1882 /* Keep track of the maximum bit size access in contiguous uniforms */
1883 *max_chunk_bitsize
= MAX2(*max_chunk_bitsize
, bitsize
);
1885 /* If this element does not need to be contiguous with the next, we
1886 * split at this point and everything between chunk_start and u forms a
1890 /* If bitsize doesn't match the target one, skip it */
1891 if (*max_chunk_bitsize
!= target_bitsize
) {
1892 /* FIXME: right now we only support 32 and 64-bit accesses */
1893 assert(*max_chunk_bitsize
== 4 || *max_chunk_bitsize
== 8);
1894 *max_chunk_bitsize
= 0;
1899 unsigned chunk_size
= uniform
- *chunk_start
+ 1;
1901 /* Decide whether we should push or pull this parameter. In the
1902 * Vulkan driver, push constants are explicitly exposed via the API
1903 * so we push everything. In GL, we only push small arrays.
1905 if (stage_prog_data
->pull_param
== NULL
||
1906 (*num_push_constants
+ chunk_size
<= max_push_components
&&
1907 chunk_size
<= max_chunk_size
)) {
1908 assert(*num_push_constants
+ chunk_size
<= max_push_components
);
1909 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1910 push_constant_loc
[j
] = (*num_push_constants
)++;
1912 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1913 pull_constant_loc
[j
] = (*num_pull_constants
)++;
1916 *max_chunk_bitsize
= 0;
1922 * Assign UNIFORM file registers to either push constants or pull constants.
1924 * We allow a fragment shader to have more than the specified minimum
1925 * maximum number of fragment shader uniform components (64). If
1926 * there are too many of these, they'd fill up all of register space.
1927 * So, this will push some of them out to the pull constant buffer and
1928 * update the program to load them.
1931 fs_visitor::assign_constant_locations()
1933 /* Only the first compile gets to decide on locations. */
1934 if (dispatch_width
!= min_dispatch_width
)
1937 bool is_live
[uniforms
];
1938 memset(is_live
, 0, sizeof(is_live
));
1939 unsigned bitsize_access
[uniforms
];
1940 memset(bitsize_access
, 0, sizeof(bitsize_access
));
1942 /* For each uniform slot, a value of true indicates that the given slot and
1943 * the next slot must remain contiguous. This is used to keep us from
1944 * splitting arrays apart.
1946 bool contiguous
[uniforms
];
1947 memset(contiguous
, 0, sizeof(contiguous
));
1949 int thread_local_id_index
=
1950 (stage
== MESA_SHADER_COMPUTE
) ?
1951 brw_cs_prog_data(stage_prog_data
)->thread_local_id_index
: -1;
1953 /* First, we walk through the instructions and do two things:
1955 * 1) Figure out which uniforms are live.
1957 * 2) Mark any indirectly used ranges of registers as contiguous.
1959 * Note that we don't move constant-indexed accesses to arrays. No
1960 * testing has been done of the performance impact of this choice.
1962 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1963 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1964 if (inst
->src
[i
].file
!= UNIFORM
)
1967 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1969 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
1970 assert(inst
->src
[2].ud
% 4 == 0);
1971 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
1972 assert(last
< uniforms
);
1974 for (unsigned j
= constant_nr
; j
< last
; j
++) {
1976 contiguous
[j
] = true;
1977 bitsize_access
[j
] = MAX2(bitsize_access
[j
], type_sz(inst
->src
[i
].type
));
1979 is_live
[last
] = true;
1980 bitsize_access
[last
] = MAX2(bitsize_access
[last
], type_sz(inst
->src
[i
].type
));
1982 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
) {
1983 int regs_read
= inst
->components_read(i
) *
1984 type_sz(inst
->src
[i
].type
) / 4;
1985 for (int j
= 0; j
< regs_read
; j
++) {
1986 is_live
[constant_nr
+ j
] = true;
1987 bitsize_access
[constant_nr
+ j
] =
1988 MAX2(bitsize_access
[constant_nr
+ j
], type_sz(inst
->src
[i
].type
));
1995 if (thread_local_id_index
>= 0 && !is_live
[thread_local_id_index
])
1996 thread_local_id_index
= -1;
1998 /* Only allow 16 registers (128 uniform components) as push constants.
2000 * Just demote the end of the list. We could probably do better
2001 * here, demoting things that are rarely used in the program first.
2003 * If changing this value, note the limitation about total_regs in
2006 unsigned int max_push_components
= 16 * 8;
2007 if (thread_local_id_index
>= 0)
2008 max_push_components
--; /* Save a slot for the thread ID */
2010 /* We push small arrays, but no bigger than 16 floats. This is big enough
2011 * for a vec4 but hopefully not large enough to push out other stuff. We
2012 * should probably use a better heuristic at some point.
2014 const unsigned int max_chunk_size
= 16;
2016 unsigned int num_push_constants
= 0;
2017 unsigned int num_pull_constants
= 0;
2019 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2020 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2022 /* Default to -1 meaning no location */
2023 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2024 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2026 int chunk_start
= -1;
2027 unsigned max_chunk_bitsize
= 0;
2029 /* First push 64-bit uniforms to ensure they are properly aligned */
2030 const unsigned uniform_64_bit_size
= type_sz(BRW_REGISTER_TYPE_DF
);
2031 for (unsigned u
= 0; u
< uniforms
; u
++) {
2035 set_push_pull_constant_loc(u
, &chunk_start
, &max_chunk_bitsize
,
2036 contiguous
[u
], bitsize_access
[u
],
2037 uniform_64_bit_size
,
2038 push_constant_loc
, pull_constant_loc
,
2039 &num_push_constants
, &num_pull_constants
,
2040 max_push_components
, max_chunk_size
,
2045 /* Then push the rest of uniforms */
2046 const unsigned uniform_32_bit_size
= type_sz(BRW_REGISTER_TYPE_F
);
2047 for (unsigned u
= 0; u
< uniforms
; u
++) {
2051 /* Skip thread_local_id_index to put it in the last push register. */
2052 if (thread_local_id_index
== (int)u
)
2055 set_push_pull_constant_loc(u
, &chunk_start
, &max_chunk_bitsize
,
2056 contiguous
[u
], bitsize_access
[u
],
2057 uniform_32_bit_size
,
2058 push_constant_loc
, pull_constant_loc
,
2059 &num_push_constants
, &num_pull_constants
,
2060 max_push_components
, max_chunk_size
,
2064 /* Add the CS local thread ID uniform at the end of the push constants */
2065 if (thread_local_id_index
>= 0)
2066 push_constant_loc
[thread_local_id_index
] = num_push_constants
++;
2068 /* As the uniforms are going to be reordered, take the data from a temporary
2069 * copy of the original param[].
2071 gl_constant_value
**param
= ralloc_array(NULL
, gl_constant_value
*,
2072 stage_prog_data
->nr_params
);
2073 memcpy(param
, stage_prog_data
->param
,
2074 sizeof(gl_constant_value
*) * stage_prog_data
->nr_params
);
2075 stage_prog_data
->nr_params
= num_push_constants
;
2076 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2078 /* Now that we know how many regular uniforms we'll push, reduce the
2079 * UBO push ranges so we don't exceed the 3DSTATE_CONSTANT limits.
2081 unsigned push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
2082 for (int i
= 0; i
< 4; i
++) {
2083 struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2085 if (push_length
+ range
->length
> 64)
2086 range
->length
= 64 - push_length
;
2088 push_length
+= range
->length
;
2090 assert(push_length
<= 64);
2092 /* Up until now, the param[] array has been indexed by reg + offset
2093 * of UNIFORM registers. Move pull constants into pull_param[] and
2094 * condense param[] to only contain the uniforms we chose to push.
2096 * NOTE: Because we are condensing the params[] array, we know that
2097 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2098 * having to make a copy.
2100 int new_thread_local_id_index
= -1;
2101 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2102 const gl_constant_value
*value
= param
[i
];
2104 if (pull_constant_loc
[i
] != -1) {
2105 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2106 } else if (push_constant_loc
[i
] != -1) {
2107 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2108 if (thread_local_id_index
== (int)i
)
2109 new_thread_local_id_index
= push_constant_loc
[i
];
2114 if (stage
== MESA_SHADER_COMPUTE
)
2115 brw_cs_prog_data(stage_prog_data
)->thread_local_id_index
=
2116 new_thread_local_id_index
;
2120 fs_visitor::get_pull_locs(const fs_reg
&src
,
2121 unsigned *out_surf_index
,
2122 unsigned *out_pull_index
)
2124 assert(src
.file
== UNIFORM
);
2126 if (src
.nr
>= UBO_START
) {
2127 const struct brw_ubo_range
*range
=
2128 &prog_data
->ubo_ranges
[src
.nr
- UBO_START
];
2130 /* If this access is in our (reduced) range, use the push data. */
2131 if (src
.offset
/ 32 < range
->length
)
2134 *out_surf_index
= prog_data
->binding_table
.ubo_start
+ range
->block
;
2135 *out_pull_index
= (32 * range
->start
+ src
.offset
) / 4;
2139 const unsigned location
= src
.nr
+ src
.offset
/ 4;
2141 if (location
< uniforms
&& pull_constant_loc
[location
] != -1) {
2142 /* A regular uniform push constant */
2143 *out_surf_index
= stage_prog_data
->binding_table
.pull_constants_start
;
2144 *out_pull_index
= pull_constant_loc
[location
];
2152 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2153 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2156 fs_visitor::lower_constant_loads()
2158 unsigned index
, pull_index
;
2160 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2161 /* Set up the annotation tracking for new generated instructions. */
2162 const fs_builder
ibld(this, block
, inst
);
2164 for (int i
= 0; i
< inst
->sources
; i
++) {
2165 if (inst
->src
[i
].file
!= UNIFORM
)
2168 /* We'll handle this case later */
2169 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2172 if (!get_pull_locs(inst
->src
[i
], &index
, &pull_index
))
2175 assert(inst
->src
[i
].stride
== 0);
2177 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
2178 const fs_builder ubld
= ibld
.exec_all().group(block_sz
/ 4, 0);
2179 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
2180 const unsigned base
= pull_index
* 4;
2182 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2183 dst
, brw_imm_ud(index
), brw_imm_ud(base
& ~(block_sz
- 1)));
2185 /* Rewrite the instruction to use the temporary VGRF. */
2186 inst
->src
[i
].file
= VGRF
;
2187 inst
->src
[i
].nr
= dst
.nr
;
2188 inst
->src
[i
].offset
= (base
& (block_sz
- 1)) +
2189 inst
->src
[i
].offset
% 4;
2191 brw_mark_surface_used(prog_data
, index
);
2194 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2195 inst
->src
[0].file
== UNIFORM
) {
2197 if (!get_pull_locs(inst
->src
[0], &index
, &pull_index
))
2200 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2204 inst
->remove(block
);
2206 brw_mark_surface_used(prog_data
, index
);
2209 invalidate_live_intervals();
2213 fs_visitor::opt_algebraic()
2215 bool progress
= false;
2217 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2218 switch (inst
->opcode
) {
2219 case BRW_OPCODE_MOV
:
2220 if (inst
->src
[0].file
!= IMM
)
2223 if (inst
->saturate
) {
2224 if (inst
->dst
.type
!= inst
->src
[0].type
)
2225 assert(!"unimplemented: saturate mixed types");
2227 if (brw_saturate_immediate(inst
->dst
.type
,
2228 &inst
->src
[0].as_brw_reg())) {
2229 inst
->saturate
= false;
2235 case BRW_OPCODE_MUL
:
2236 if (inst
->src
[1].file
!= IMM
)
2240 if (inst
->src
[1].is_one()) {
2241 inst
->opcode
= BRW_OPCODE_MOV
;
2242 inst
->src
[1] = reg_undef
;
2248 if (inst
->src
[1].is_negative_one()) {
2249 inst
->opcode
= BRW_OPCODE_MOV
;
2250 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2251 inst
->src
[1] = reg_undef
;
2257 if (inst
->src
[1].is_zero()) {
2258 inst
->opcode
= BRW_OPCODE_MOV
;
2259 inst
->src
[0] = inst
->src
[1];
2260 inst
->src
[1] = reg_undef
;
2265 if (inst
->src
[0].file
== IMM
) {
2266 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2267 inst
->opcode
= BRW_OPCODE_MOV
;
2268 inst
->src
[0].f
*= inst
->src
[1].f
;
2269 inst
->src
[1] = reg_undef
;
2274 case BRW_OPCODE_ADD
:
2275 if (inst
->src
[1].file
!= IMM
)
2279 if (inst
->src
[1].is_zero()) {
2280 inst
->opcode
= BRW_OPCODE_MOV
;
2281 inst
->src
[1] = reg_undef
;
2286 if (inst
->src
[0].file
== IMM
) {
2287 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2288 inst
->opcode
= BRW_OPCODE_MOV
;
2289 inst
->src
[0].f
+= inst
->src
[1].f
;
2290 inst
->src
[1] = reg_undef
;
2296 if (inst
->src
[0].equals(inst
->src
[1])) {
2297 inst
->opcode
= BRW_OPCODE_MOV
;
2298 inst
->src
[1] = reg_undef
;
2303 case BRW_OPCODE_LRP
:
2304 if (inst
->src
[1].equals(inst
->src
[2])) {
2305 inst
->opcode
= BRW_OPCODE_MOV
;
2306 inst
->src
[0] = inst
->src
[1];
2307 inst
->src
[1] = reg_undef
;
2308 inst
->src
[2] = reg_undef
;
2313 case BRW_OPCODE_CMP
:
2314 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2316 inst
->src
[0].negate
&&
2317 inst
->src
[1].is_zero()) {
2318 inst
->src
[0].abs
= false;
2319 inst
->src
[0].negate
= false;
2320 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2325 case BRW_OPCODE_SEL
:
2326 if (inst
->src
[0].equals(inst
->src
[1])) {
2327 inst
->opcode
= BRW_OPCODE_MOV
;
2328 inst
->src
[1] = reg_undef
;
2329 inst
->predicate
= BRW_PREDICATE_NONE
;
2330 inst
->predicate_inverse
= false;
2332 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2333 switch (inst
->conditional_mod
) {
2334 case BRW_CONDITIONAL_LE
:
2335 case BRW_CONDITIONAL_L
:
2336 switch (inst
->src
[1].type
) {
2337 case BRW_REGISTER_TYPE_F
:
2338 if (inst
->src
[1].f
>= 1.0f
) {
2339 inst
->opcode
= BRW_OPCODE_MOV
;
2340 inst
->src
[1] = reg_undef
;
2341 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2349 case BRW_CONDITIONAL_GE
:
2350 case BRW_CONDITIONAL_G
:
2351 switch (inst
->src
[1].type
) {
2352 case BRW_REGISTER_TYPE_F
:
2353 if (inst
->src
[1].f
<= 0.0f
) {
2354 inst
->opcode
= BRW_OPCODE_MOV
;
2355 inst
->src
[1] = reg_undef
;
2356 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2368 case BRW_OPCODE_MAD
:
2369 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2370 inst
->opcode
= BRW_OPCODE_MOV
;
2371 inst
->src
[1] = reg_undef
;
2372 inst
->src
[2] = reg_undef
;
2374 } else if (inst
->src
[0].is_zero()) {
2375 inst
->opcode
= BRW_OPCODE_MUL
;
2376 inst
->src
[0] = inst
->src
[2];
2377 inst
->src
[2] = reg_undef
;
2379 } else if (inst
->src
[1].is_one()) {
2380 inst
->opcode
= BRW_OPCODE_ADD
;
2381 inst
->src
[1] = inst
->src
[2];
2382 inst
->src
[2] = reg_undef
;
2384 } else if (inst
->src
[2].is_one()) {
2385 inst
->opcode
= BRW_OPCODE_ADD
;
2386 inst
->src
[2] = reg_undef
;
2388 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2389 inst
->opcode
= BRW_OPCODE_ADD
;
2390 inst
->src
[1].f
*= inst
->src
[2].f
;
2391 inst
->src
[2] = reg_undef
;
2395 case SHADER_OPCODE_BROADCAST
:
2396 if (is_uniform(inst
->src
[0])) {
2397 inst
->opcode
= BRW_OPCODE_MOV
;
2399 inst
->force_writemask_all
= true;
2401 } else if (inst
->src
[1].file
== IMM
) {
2402 inst
->opcode
= BRW_OPCODE_MOV
;
2403 inst
->src
[0] = component(inst
->src
[0],
2406 inst
->force_writemask_all
= true;
2415 /* Swap if src[0] is immediate. */
2416 if (progress
&& inst
->is_commutative()) {
2417 if (inst
->src
[0].file
== IMM
) {
2418 fs_reg tmp
= inst
->src
[1];
2419 inst
->src
[1] = inst
->src
[0];
2428 * Optimize sample messages that have constant zero values for the trailing
2429 * texture coordinates. We can just reduce the message length for these
2430 * instructions instead of reserving a register for it. Trailing parameters
2431 * that aren't sent default to zero anyway. This will cause the dead code
2432 * eliminator to remove the MOV instruction that would otherwise be emitted to
2433 * set up the zero value.
2436 fs_visitor::opt_zero_samples()
2438 /* Gen4 infers the texturing opcode based on the message length so we can't
2441 if (devinfo
->gen
< 5)
2444 bool progress
= false;
2446 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2447 if (!inst
->is_tex())
2450 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2452 if (load_payload
->is_head_sentinel() ||
2453 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2456 /* We don't want to remove the message header or the first parameter.
2457 * Removing the first parameter is not allowed, see the Haswell PRM
2458 * volume 7, page 149:
2460 * "Parameter 0 is required except for the sampleinfo message, which
2461 * has no parameter 0"
2463 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2464 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2465 (inst
->exec_size
/ 8) +
2466 inst
->header_size
- 1].is_zero()) {
2467 inst
->mlen
-= inst
->exec_size
/ 8;
2473 invalidate_live_intervals();
2479 * Optimize sample messages which are followed by the final RT write.
2481 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2482 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2483 * final texturing results copied to the framebuffer write payload and modify
2484 * them to write to the framebuffer directly.
2487 fs_visitor::opt_sampler_eot()
2489 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2491 if (stage
!= MESA_SHADER_FRAGMENT
)
2494 if (devinfo
->gen
!= 9 && !devinfo
->is_cherryview
)
2497 /* FINISHME: It should be possible to implement this optimization when there
2498 * are multiple drawbuffers.
2500 if (key
->nr_color_regions
!= 1)
2503 /* Requires emitting a bunch of saturating MOV instructions during logical
2504 * send lowering to clamp the color payload, which the sampler unit isn't
2505 * going to do for us.
2507 if (key
->clamp_fragment_color
)
2510 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2511 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2512 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2513 assert(fb_write
->eot
);
2514 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2516 /* There wasn't one; nothing to do. */
2517 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2520 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2522 /* 3D Sampler » Messages » Message Format
2524 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2525 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2527 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2528 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2529 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2530 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2531 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2532 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2533 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2534 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2537 /* XXX - This shouldn't be necessary. */
2538 if (tex_inst
->prev
->is_head_sentinel())
2541 /* Check that the FB write sources are fully initialized by the single
2542 * texturing instruction.
2544 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2545 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2546 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2547 fb_write
->size_read(i
) != tex_inst
->size_written
)
2549 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2550 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2555 assert(!tex_inst
->eot
); /* We can't get here twice */
2556 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2558 const fs_builder
ibld(this, block
, tex_inst
);
2560 tex_inst
->offset
|= fb_write
->target
<< 24;
2561 tex_inst
->eot
= true;
2562 tex_inst
->dst
= ibld
.null_reg_ud();
2563 tex_inst
->size_written
= 0;
2564 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2566 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2567 * flag and submit a header together with the sampler message as required
2570 invalidate_live_intervals();
2575 fs_visitor::opt_register_renaming()
2577 bool progress
= false;
2580 int remap
[alloc
.count
];
2581 memset(remap
, -1, sizeof(int) * alloc
.count
);
2583 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2584 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2586 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2587 inst
->opcode
== BRW_OPCODE_WHILE
) {
2591 /* Rewrite instruction sources. */
2592 for (int i
= 0; i
< inst
->sources
; i
++) {
2593 if (inst
->src
[i
].file
== VGRF
&&
2594 remap
[inst
->src
[i
].nr
] != -1 &&
2595 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2596 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2601 const int dst
= inst
->dst
.nr
;
2604 inst
->dst
.file
== VGRF
&&
2605 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
2606 !inst
->is_partial_write()) {
2607 if (remap
[dst
] == -1) {
2610 remap
[dst
] = alloc
.allocate(regs_written(inst
));
2611 inst
->dst
.nr
= remap
[dst
];
2614 } else if (inst
->dst
.file
== VGRF
&&
2616 remap
[dst
] != dst
) {
2617 inst
->dst
.nr
= remap
[dst
];
2623 invalidate_live_intervals();
2625 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2626 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2627 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2636 * Remove redundant or useless discard jumps.
2638 * For example, we can eliminate jumps in the following sequence:
2640 * discard-jump (redundant with the next jump)
2641 * discard-jump (useless; jumps to the next instruction)
2645 fs_visitor::opt_redundant_discard_jumps()
2647 bool progress
= false;
2649 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2651 fs_inst
*placeholder_halt
= NULL
;
2652 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2653 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2654 placeholder_halt
= inst
;
2659 if (!placeholder_halt
)
2662 /* Delete any HALTs immediately before the placeholder halt. */
2663 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2664 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2665 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2666 prev
->remove(last_bblock
);
2671 invalidate_live_intervals();
2677 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2678 * from \p r.offset which overlaps the region starting at \p s.offset and
2679 * spanning \p ds bytes.
2681 static inline unsigned
2682 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
2684 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
2685 const int shift
= rel_offset
/ REG_SIZE
;
2686 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
2687 assert(reg_space(r
) == reg_space(s
) &&
2688 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
2689 return ((1 << n
) - 1) << shift
;
2693 fs_visitor::compute_to_mrf()
2695 bool progress
= false;
2698 /* No MRFs on Gen >= 7. */
2699 if (devinfo
->gen
>= 7)
2702 calculate_live_intervals();
2704 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2708 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2709 inst
->is_partial_write() ||
2710 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2711 inst
->dst
.type
!= inst
->src
[0].type
||
2712 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2713 !inst
->src
[0].is_contiguous() ||
2714 inst
->src
[0].offset
% REG_SIZE
!= 0)
2717 /* Can't compute-to-MRF this GRF if someone else was going to
2720 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2723 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
2724 * things that computed the value of all GRFs of the source region. The
2725 * regs_left bitset keeps track of the registers we haven't yet found a
2726 * generating instruction for.
2728 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
2730 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2731 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2732 inst
->src
[0], inst
->size_read(0))) {
2733 /* Found the last thing to write our reg we want to turn
2734 * into a compute-to-MRF.
2737 /* If this one instruction didn't populate all the
2738 * channels, bail. We might be able to rewrite everything
2739 * that writes that reg, but it would require smarter
2742 if (scan_inst
->is_partial_write())
2745 /* Handling things not fully contained in the source of the copy
2746 * would need us to understand coalescing out more than one MOV at
2749 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
2750 inst
->src
[0], inst
->size_read(0)))
2753 /* SEND instructions can't have MRF as a destination. */
2754 if (scan_inst
->mlen
)
2757 if (devinfo
->gen
== 6) {
2758 /* gen6 math instructions must have the destination be
2759 * GRF, so no compute-to-MRF for them.
2761 if (scan_inst
->is_math()) {
2766 /* Clear the bits for any registers this instruction overwrites. */
2767 regs_left
&= ~mask_relative_to(
2768 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
2773 /* We don't handle control flow here. Most computation of
2774 * values that end up in MRFs are shortly before the MRF
2777 if (block
->start() == scan_inst
)
2780 /* You can't read from an MRF, so if someone else reads our
2781 * MRF's source GRF that we wanted to rewrite, that stops us.
2783 bool interfered
= false;
2784 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2785 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
2786 inst
->src
[0], inst
->size_read(0))) {
2793 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2794 inst
->dst
, inst
->size_written
)) {
2795 /* If somebody else writes our MRF here, we can't
2796 * compute-to-MRF before that.
2801 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
2802 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
2803 inst
->dst
, inst
->size_written
)) {
2804 /* Found a SEND instruction, which means that there are
2805 * live values in MRFs from base_mrf to base_mrf +
2806 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2816 /* Found all generating instructions of our MRF's source value, so it
2817 * should be safe to rewrite them to point to the MRF directly.
2819 regs_left
= (1 << regs_read(inst
, 0)) - 1;
2821 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2822 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2823 inst
->src
[0], inst
->size_read(0))) {
2824 /* Clear the bits for any registers this instruction overwrites. */
2825 regs_left
&= ~mask_relative_to(
2826 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
2828 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
2829 reg_offset(inst
->src
[0]);
2831 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2832 /* Apply the same address transformation done by the hardware
2833 * for COMPR4 MRF writes.
2835 assert(rel_offset
< 2 * REG_SIZE
);
2836 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
2838 /* Clear the COMPR4 bit if the generating instruction is not
2841 if (scan_inst
->size_written
< 2 * REG_SIZE
)
2842 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
2845 /* Calculate the MRF number the result of this instruction is
2846 * ultimately written to.
2848 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
2851 scan_inst
->dst
.file
= MRF
;
2852 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
2853 scan_inst
->saturate
|= inst
->saturate
;
2860 inst
->remove(block
);
2865 invalidate_live_intervals();
2871 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2872 * flow. We could probably do better here with some form of divergence
2876 fs_visitor::eliminate_find_live_channel()
2878 bool progress
= false;
2881 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
2882 /* The optimization below assumes that channel zero is live on thread
2883 * dispatch, which may not be the case if the fixed function dispatches
2889 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2890 switch (inst
->opcode
) {
2896 case BRW_OPCODE_ENDIF
:
2897 case BRW_OPCODE_WHILE
:
2901 case FS_OPCODE_DISCARD_JUMP
:
2902 /* This can potentially make control flow non-uniform until the end
2907 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2909 inst
->opcode
= BRW_OPCODE_MOV
;
2910 inst
->src
[0] = brw_imm_ud(0u);
2912 inst
->force_writemask_all
= true;
2926 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2927 * instructions to FS_OPCODE_REP_FB_WRITE.
2930 fs_visitor::emit_repclear_shader()
2932 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2934 int color_mrf
= base_mrf
+ 2;
2938 mov
= bld
.exec_all().group(4, 0)
2939 .MOV(brw_message_reg(color_mrf
),
2940 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2942 struct brw_reg reg
=
2943 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2944 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
2945 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2947 mov
= bld
.exec_all().group(4, 0)
2948 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
2952 if (key
->nr_color_regions
== 1) {
2953 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2954 write
->saturate
= key
->clamp_fragment_color
;
2955 write
->base_mrf
= color_mrf
;
2957 write
->header_size
= 0;
2960 assume(key
->nr_color_regions
> 0);
2961 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2962 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2963 write
->saturate
= key
->clamp_fragment_color
;
2964 write
->base_mrf
= base_mrf
;
2966 write
->header_size
= 2;
2974 assign_constant_locations();
2975 assign_curb_setup();
2977 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2979 assert(mov
->src
[0].file
== FIXED_GRF
);
2980 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2985 * Walks through basic blocks, looking for repeated MRF writes and
2986 * removing the later ones.
2989 fs_visitor::remove_duplicate_mrf_writes()
2991 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2992 bool progress
= false;
2994 /* Need to update the MRF tracking for compressed instructions. */
2995 if (dispatch_width
>= 16)
2998 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3000 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3001 if (inst
->is_control_flow()) {
3002 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3005 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3006 inst
->dst
.file
== MRF
) {
3007 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3008 if (prev_inst
&& inst
->equals(prev_inst
)) {
3009 inst
->remove(block
);
3015 /* Clear out the last-write records for MRFs that were overwritten. */
3016 if (inst
->dst
.file
== MRF
) {
3017 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3020 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3021 /* Found a SEND instruction, which will include two or fewer
3022 * implied MRF writes. We could do better here.
3024 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3025 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3029 /* Clear out any MRF move records whose sources got overwritten. */
3030 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3031 if (last_mrf_move
[i
] &&
3032 regions_overlap(inst
->dst
, inst
->size_written
,
3033 last_mrf_move
[i
]->src
[0],
3034 last_mrf_move
[i
]->size_read(0))) {
3035 last_mrf_move
[i
] = NULL
;
3039 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3040 inst
->dst
.file
== MRF
&&
3041 inst
->src
[0].file
!= ARF
&&
3042 !inst
->is_partial_write()) {
3043 last_mrf_move
[inst
->dst
.nr
] = inst
;
3048 invalidate_live_intervals();
3054 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3056 /* Clear the flag for registers that actually got read (as expected). */
3057 for (int i
= 0; i
< inst
->sources
; i
++) {
3059 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3060 grf
= inst
->src
[i
].nr
;
3065 if (grf
>= first_grf
&&
3066 grf
< first_grf
+ grf_len
) {
3067 deps
[grf
- first_grf
] = false;
3068 if (inst
->exec_size
== 16)
3069 deps
[grf
- first_grf
+ 1] = false;
3075 * Implements this workaround for the original 965:
3077 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3078 * check for post destination dependencies on this instruction, software
3079 * must ensure that there is no destination hazard for the case of ‘write
3080 * followed by a posted write’ shown in the following example.
3083 * 2. send r3.xy <rest of send instruction>
3086 * Due to no post-destination dependency check on the ‘send’, the above
3087 * code sequence could have two instructions (1 and 2) in flight at the
3088 * same time that both consider ‘r3’ as the target of their final writes.
3091 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3094 int write_len
= regs_written(inst
);
3095 int first_write_grf
= inst
->dst
.nr
;
3096 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3097 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3099 memset(needs_dep
, false, sizeof(needs_dep
));
3100 memset(needs_dep
, true, write_len
);
3102 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3104 /* Walk backwards looking for writes to registers we're writing which
3105 * aren't read since being written. If we hit the start of the program,
3106 * we assume that there are no outstanding dependencies on entry to the
3109 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3110 /* If we hit control flow, assume that there *are* outstanding
3111 * dependencies, and force their cleanup before our instruction.
3113 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3114 for (int i
= 0; i
< write_len
; i
++) {
3116 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3117 first_write_grf
+ i
);
3122 /* We insert our reads as late as possible on the assumption that any
3123 * instruction but a MOV that might have left us an outstanding
3124 * dependency has more latency than a MOV.
3126 if (scan_inst
->dst
.file
== VGRF
) {
3127 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3128 int reg
= scan_inst
->dst
.nr
+ i
;
3130 if (reg
>= first_write_grf
&&
3131 reg
< first_write_grf
+ write_len
&&
3132 needs_dep
[reg
- first_write_grf
]) {
3133 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3134 needs_dep
[reg
- first_write_grf
] = false;
3135 if (scan_inst
->exec_size
== 16)
3136 needs_dep
[reg
- first_write_grf
+ 1] = false;
3141 /* Clear the flag for registers that actually got read (as expected). */
3142 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3144 /* Continue the loop only if we haven't resolved all the dependencies */
3146 for (i
= 0; i
< write_len
; i
++) {
3156 * Implements this workaround for the original 965:
3158 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3159 * used as a destination register until after it has been sourced by an
3160 * instruction with a different destination register.
3163 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3165 int write_len
= regs_written(inst
);
3166 int first_write_grf
= inst
->dst
.nr
;
3167 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3168 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3170 memset(needs_dep
, false, sizeof(needs_dep
));
3171 memset(needs_dep
, true, write_len
);
3172 /* Walk forwards looking for writes to registers we're writing which aren't
3173 * read before being written.
3175 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3176 /* If we hit control flow, force resolve all remaining dependencies. */
3177 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3178 for (int i
= 0; i
< write_len
; i
++) {
3180 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3181 first_write_grf
+ i
);
3186 /* Clear the flag for registers that actually got read (as expected). */
3187 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3189 /* We insert our reads as late as possible since they're reading the
3190 * result of a SEND, which has massive latency.
3192 if (scan_inst
->dst
.file
== VGRF
&&
3193 scan_inst
->dst
.nr
>= first_write_grf
&&
3194 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3195 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3196 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3198 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3201 /* Continue the loop only if we haven't resolved all the dependencies */
3203 for (i
= 0; i
< write_len
; i
++) {
3213 fs_visitor::insert_gen4_send_dependency_workarounds()
3215 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3218 bool progress
= false;
3220 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3221 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3222 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3223 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3229 invalidate_live_intervals();
3233 * Turns the generic expression-style uniform pull constant load instruction
3234 * into a hardware-specific series of instructions for loading a pull
3237 * The expression style allows the CSE pass before this to optimize out
3238 * repeated loads from the same offset, and gives the pre-register-allocation
3239 * scheduling full flexibility, while the conversion to native instructions
3240 * allows the post-register-allocation scheduler the best information
3243 * Note that execution masking for setting up pull constant loads is special:
3244 * the channels that need to be written are unrelated to the current execution
3245 * mask, since a later instruction will use one of the result channels as a
3246 * source operand for all 8 or 16 of its channels.
3249 fs_visitor::lower_uniform_pull_constant_loads()
3251 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3252 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3255 if (devinfo
->gen
>= 7) {
3256 const fs_builder ubld
= fs_builder(this, block
, inst
).exec_all();
3257 const fs_reg payload
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
);
3259 ubld
.group(8, 0).MOV(payload
,
3260 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3261 ubld
.group(1, 0).MOV(component(payload
, 2),
3262 brw_imm_ud(inst
->src
[1].ud
/ 16));
3264 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3265 inst
->src
[1] = payload
;
3266 inst
->header_size
= 1;
3269 invalidate_live_intervals();
3271 /* Before register allocation, we didn't tell the scheduler about the
3272 * MRF we use. We know it's safe to use this MRF because nothing
3273 * else does except for register spill/unspill, which generates and
3274 * uses its MRF within a single IR instruction.
3276 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3283 fs_visitor::lower_load_payload()
3285 bool progress
= false;
3287 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3288 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3291 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3292 assert(inst
->saturate
== false);
3293 fs_reg dst
= inst
->dst
;
3295 /* Get rid of COMPR4. We'll add it back in if we need it */
3296 if (dst
.file
== MRF
)
3297 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3299 const fs_builder
ibld(this, block
, inst
);
3300 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3302 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3303 if (inst
->src
[i
].file
!= BAD_FILE
) {
3304 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3305 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3306 hbld
.MOV(mov_dst
, mov_src
);
3308 dst
= offset(dst
, hbld
, 1);
3311 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3312 inst
->exec_size
> 8) {
3313 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3314 * a straightforward copy. Instead, the result of the
3315 * LOAD_PAYLOAD is treated as interleaved and the first four
3316 * non-header sources are unpacked as:
3327 * This is used for gen <= 5 fb writes.
3329 assert(inst
->exec_size
== 16);
3330 assert(inst
->header_size
+ 4 <= inst
->sources
);
3331 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3332 if (inst
->src
[i
].file
!= BAD_FILE
) {
3333 if (devinfo
->has_compr4
) {
3334 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3335 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3336 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3338 /* Platform doesn't have COMPR4. We have to fake it */
3339 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3340 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3342 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3349 /* The loop above only ever incremented us through the first set
3350 * of 4 registers. However, thanks to the magic of COMPR4, we
3351 * actually wrote to the first 8 registers, so we need to take
3352 * that into account now.
3356 /* The COMPR4 code took care of the first 4 sources. We'll let
3357 * the regular path handle any remaining sources. Yes, we are
3358 * modifying the instruction but we're about to delete it so
3359 * this really doesn't hurt anything.
3361 inst
->header_size
+= 4;
3364 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3365 if (inst
->src
[i
].file
!= BAD_FILE
)
3366 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3367 dst
= offset(dst
, ibld
, 1);
3370 inst
->remove(block
);
3375 invalidate_live_intervals();
3381 fs_visitor::lower_integer_multiplication()
3383 bool progress
= false;
3385 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3386 const fs_builder
ibld(this, block
, inst
);
3388 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3389 if (inst
->dst
.is_accumulator() ||
3390 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3391 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3394 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3395 * operation directly, but CHV/BXT cannot.
3397 if (devinfo
->gen
>= 8 &&
3398 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
))
3401 if (inst
->src
[1].file
== IMM
&&
3402 inst
->src
[1].ud
< (1 << 16)) {
3403 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3404 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3407 * If multiplying by an immediate value that fits in 16-bits, do a
3408 * single MUL instruction with that value in the proper location.
3410 if (devinfo
->gen
< 7) {
3411 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3413 ibld
.MOV(imm
, inst
->src
[1]);
3414 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3416 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3417 ibld
.MUL(inst
->dst
, inst
->src
[0],
3418 ud
? brw_imm_uw(inst
->src
[1].ud
)
3419 : brw_imm_w(inst
->src
[1].d
));
3422 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3423 * do 32-bit integer multiplication in one instruction, but instead
3424 * must do a sequence (which actually calculates a 64-bit result):
3426 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3427 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3428 * mov(8) g2<1>D acc0<8,8,1>D
3430 * But on Gen > 6, the ability to use second accumulator register
3431 * (acc1) for non-float data types was removed, preventing a simple
3432 * implementation in SIMD16. A 16-channel result can be calculated by
3433 * executing the three instructions twice in SIMD8, once with quarter
3434 * control of 1Q for the first eight channels and again with 2Q for
3435 * the second eight channels.
3437 * Which accumulator register is implicitly accessed (by AccWrEnable
3438 * for instance) is determined by the quarter control. Unfortunately
3439 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3440 * implicit accumulator access by an instruction with 2Q will access
3441 * acc1 regardless of whether the data type is usable in acc1.
3443 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3444 * integer data types.
3446 * Since we only want the low 32-bits of the result, we can do two
3447 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3448 * adjust the high result and add them (like the mach is doing):
3450 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3451 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3452 * shl(8) g9<1>D g8<8,8,1>D 16D
3453 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3455 * We avoid the shl instruction by realizing that we only want to add
3456 * the low 16-bits of the "high" result to the high 16-bits of the
3457 * "low" result and using proper regioning on the add:
3459 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3460 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3461 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3463 * Since it does not use the (single) accumulator register, we can
3464 * schedule multi-component multiplications much better.
3467 fs_reg orig_dst
= inst
->dst
;
3468 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3469 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3472 fs_reg low
= inst
->dst
;
3473 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3476 if (devinfo
->gen
>= 7) {
3477 if (inst
->src
[1].file
== IMM
) {
3478 ibld
.MUL(low
, inst
->src
[0],
3479 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
3480 ibld
.MUL(high
, inst
->src
[0],
3481 brw_imm_uw(inst
->src
[1].ud
>> 16));
3483 ibld
.MUL(low
, inst
->src
[0],
3484 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
3485 ibld
.MUL(high
, inst
->src
[0],
3486 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
3489 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
3491 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
3495 ibld
.ADD(subscript(inst
->dst
, BRW_REGISTER_TYPE_UW
, 1),
3496 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3497 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
3499 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3500 set_condmod(inst
->conditional_mod
,
3501 ibld
.MOV(orig_dst
, inst
->dst
));
3505 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3506 /* Should have been lowered to 8-wide. */
3507 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
3508 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3510 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3511 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3513 if (devinfo
->gen
>= 8) {
3514 /* Until Gen8, integer multiplies read 32-bits from one source,
3515 * and 16-bits from the other, and relying on the MACH instruction
3516 * to generate the high bits of the result.
3518 * On Gen8, the multiply instruction does a full 32x32-bit
3519 * multiply, but in order to do a 64-bit multiply we can simulate
3520 * the previous behavior and then use a MACH instruction.
3522 * FINISHME: Don't use source modifiers on src1.
3524 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3525 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3526 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3527 mul
->src
[1].stride
*= 2;
3529 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3531 /* Among other things the quarter control bits influence which
3532 * accumulator register is used by the hardware for instructions
3533 * that access the accumulator implicitly (e.g. MACH). A
3534 * second-half instruction would normally map to acc1, which
3535 * doesn't exist on Gen7 and up (the hardware does emulate it for
3536 * floating-point instructions *only* by taking advantage of the
3537 * extra precision of acc0 not normally used for floating point
3540 * HSW and up are careful enough not to try to access an
3541 * accumulator register that doesn't exist, but on earlier Gen7
3542 * hardware we need to make sure that the quarter control bits are
3543 * zero to avoid non-deterministic behaviour and emit an extra MOV
3544 * to get the result masked correctly according to the current
3548 mach
->force_writemask_all
= true;
3549 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3550 ibld
.MOV(inst
->dst
, mach
->dst
);
3556 inst
->remove(block
);
3561 invalidate_live_intervals();
3567 fs_visitor::lower_minmax()
3569 assert(devinfo
->gen
< 6);
3571 bool progress
= false;
3573 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3574 const fs_builder
ibld(this, block
, inst
);
3576 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3577 inst
->predicate
== BRW_PREDICATE_NONE
) {
3578 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3579 * the original SEL.L/GE instruction
3581 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3582 inst
->conditional_mod
);
3583 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3584 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3591 invalidate_live_intervals();
3597 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3598 fs_reg
*dst
, fs_reg color
, unsigned components
)
3600 if (key
->clamp_fragment_color
) {
3601 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3602 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3604 for (unsigned i
= 0; i
< components
; i
++)
3606 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3611 for (unsigned i
= 0; i
< components
; i
++)
3612 dst
[i
] = offset(color
, bld
, i
);
3616 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3617 const struct brw_wm_prog_data
*prog_data
,
3618 const brw_wm_prog_key
*key
,
3619 const fs_visitor::thread_payload
&payload
)
3621 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3622 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3623 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3624 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3625 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3626 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3627 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3628 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3629 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3630 const unsigned components
=
3631 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3633 /* We can potentially have a message length of up to 15, so we have to set
3634 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3637 int header_size
= 2, payload_header_size
;
3638 unsigned length
= 0;
3640 /* From the Sandy Bridge PRM, volume 4, page 198:
3642 * "Dispatched Pixel Enables. One bit per pixel indicating
3643 * which pixels were originally enabled when the thread was
3644 * dispatched. This field is only required for the end-of-
3645 * thread message and on all dual-source messages."
3647 if (devinfo
->gen
>= 6 &&
3648 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3649 color1
.file
== BAD_FILE
&&
3650 key
->nr_color_regions
== 1) {
3654 if (header_size
!= 0) {
3655 assert(header_size
== 2);
3656 /* Allocate 2 registers for a header */
3660 if (payload
.aa_dest_stencil_reg
) {
3661 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3662 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3663 .MOV(sources
[length
],
3664 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3668 if (sample_mask
.file
!= BAD_FILE
) {
3669 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3670 BRW_REGISTER_TYPE_UD
);
3672 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3673 * relevant. Since it's unsigned single words one vgrf is always
3674 * 16-wide, but only the lower or higher 8 channels will be used by the
3675 * hardware when doing a SIMD8 write depending on whether we have
3676 * selected the subspans for the first or second half respectively.
3678 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3679 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3680 sample_mask
.stride
*= 2;
3682 bld
.exec_all().annotate("FB write oMask")
3683 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3689 payload_header_size
= length
;
3691 if (src0_alpha
.file
!= BAD_FILE
) {
3692 /* FIXME: This is being passed at the wrong location in the payload and
3693 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3694 * It's supposed to be immediately before oMask but there seems to be no
3695 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3696 * requires header sources to form a contiguous segment at the beginning
3697 * of the message and src0_alpha has per-channel semantics.
3699 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3701 } else if (key
->replicate_alpha
&& inst
->target
!= 0) {
3702 /* Handle the case when fragment shader doesn't write to draw buffer
3703 * zero. No need to call setup_color_payload() for src0_alpha because
3704 * alpha value will be undefined.
3709 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3712 if (color1
.file
!= BAD_FILE
) {
3713 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3717 if (src_depth
.file
!= BAD_FILE
) {
3718 sources
[length
] = src_depth
;
3722 if (dst_depth
.file
!= BAD_FILE
) {
3723 sources
[length
] = dst_depth
;
3727 if (src_stencil
.file
!= BAD_FILE
) {
3728 assert(devinfo
->gen
>= 9);
3729 assert(bld
.dispatch_width() != 16);
3731 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3732 * available on gen9+. As such it's impossible to have both enabled at the
3733 * same time and therefore length cannot overrun the array.
3735 assert(length
< 15);
3737 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3738 bld
.exec_all().annotate("FB write OS")
3739 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
3740 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
3745 if (devinfo
->gen
>= 7) {
3746 /* Send from the GRF */
3747 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3748 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3749 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
3750 load
->dst
= payload
;
3752 inst
->src
[0] = payload
;
3753 inst
->resize_sources(1);
3755 /* Send from the MRF */
3756 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3757 sources
, length
, payload_header_size
);
3759 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3760 * will do this for us if we just give it a COMPR4 destination.
3762 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3763 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3765 inst
->resize_sources(0);
3769 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3770 inst
->mlen
= regs_written(load
);
3771 inst
->header_size
= header_size
;
3775 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
3777 const fs_builder
&ubld
= bld
.exec_all();
3778 const unsigned length
= 2;
3779 const fs_reg header
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
, length
);
3782 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3784 inst
->resize_sources(1);
3785 inst
->src
[0] = header
;
3786 inst
->opcode
= FS_OPCODE_FB_READ
;
3787 inst
->mlen
= length
;
3788 inst
->header_size
= length
;
3792 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3793 const fs_reg
&coordinate
,
3794 const fs_reg
&shadow_c
,
3795 const fs_reg
&lod
, const fs_reg
&lod2
,
3796 const fs_reg
&surface
,
3797 const fs_reg
&sampler
,
3798 unsigned coord_components
,
3799 unsigned grad_components
)
3801 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3802 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3803 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3804 fs_reg msg_end
= msg_begin
;
3807 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3809 for (unsigned i
= 0; i
< coord_components
; i
++)
3810 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3811 offset(coordinate
, bld
, i
));
3813 msg_end
= offset(msg_end
, bld
, coord_components
);
3815 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3816 * require all three components to be present and zero if they are unused.
3818 if (coord_components
> 0 &&
3819 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3820 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3821 for (unsigned i
= coord_components
; i
< 3; i
++)
3822 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3824 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3827 if (op
== SHADER_OPCODE_TXD
) {
3828 /* TXD unsupported in SIMD16 mode. */
3829 assert(bld
.dispatch_width() == 8);
3831 /* the slots for u and v are always present, but r is optional */
3832 if (coord_components
< 2)
3833 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3836 * dPdx = dudx, dvdx, drdx
3837 * dPdy = dudy, dvdy, drdy
3839 * 1-arg: Does not exist.
3841 * 2-arg: dudx dvdx dudy dvdy
3842 * dPdx.x dPdx.y dPdy.x dPdy.y
3845 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3846 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3847 * m5 m6 m7 m8 m9 m10
3849 for (unsigned i
= 0; i
< grad_components
; i
++)
3850 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3852 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3854 for (unsigned i
= 0; i
< grad_components
; i
++)
3855 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3857 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3861 /* Bias/LOD with shadow comparator is unsupported in SIMD16 -- *Without*
3862 * shadow comparator (including RESINFO) it's unsupported in SIMD8 mode.
3864 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3865 bld
.dispatch_width() == 16);
3867 const brw_reg_type type
=
3868 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3869 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3870 bld
.MOV(retype(msg_end
, type
), lod
);
3871 msg_end
= offset(msg_end
, bld
, 1);
3874 if (shadow_c
.file
!= BAD_FILE
) {
3875 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3876 /* There's no plain shadow compare message, so we use shadow
3877 * compare with a bias of 0.0.
3879 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3880 msg_end
= offset(msg_end
, bld
, 1);
3883 bld
.MOV(msg_end
, shadow_c
);
3884 msg_end
= offset(msg_end
, bld
, 1);
3888 inst
->src
[0] = reg_undef
;
3889 inst
->src
[1] = surface
;
3890 inst
->src
[2] = sampler
;
3891 inst
->resize_sources(3);
3892 inst
->base_mrf
= msg_begin
.nr
;
3893 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3894 inst
->header_size
= 1;
3898 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3899 const fs_reg
&coordinate
,
3900 const fs_reg
&shadow_c
,
3901 const fs_reg
&lod
, const fs_reg
&lod2
,
3902 const fs_reg
&sample_index
,
3903 const fs_reg
&surface
,
3904 const fs_reg
&sampler
,
3905 unsigned coord_components
,
3906 unsigned grad_components
)
3908 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3909 fs_reg msg_coords
= message
;
3910 unsigned header_size
= 0;
3912 if (inst
->offset
!= 0) {
3913 /* The offsets set up by the visitor are in the m1 header, so we can't
3920 for (unsigned i
= 0; i
< coord_components
; i
++)
3921 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
3922 offset(coordinate
, bld
, i
));
3924 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3925 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3927 if (shadow_c
.file
!= BAD_FILE
) {
3928 fs_reg msg_shadow
= msg_lod
;
3929 bld
.MOV(msg_shadow
, shadow_c
);
3930 msg_lod
= offset(msg_shadow
, bld
, 1);
3935 case SHADER_OPCODE_TXL
:
3937 bld
.MOV(msg_lod
, lod
);
3938 msg_end
= offset(msg_lod
, bld
, 1);
3940 case SHADER_OPCODE_TXD
:
3943 * dPdx = dudx, dvdx, drdx
3944 * dPdy = dudy, dvdy, drdy
3946 * Load up these values:
3947 * - dudx dudy dvdx dvdy drdx drdy
3948 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3951 for (unsigned i
= 0; i
< grad_components
; i
++) {
3952 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
3953 msg_end
= offset(msg_end
, bld
, 1);
3955 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
3956 msg_end
= offset(msg_end
, bld
, 1);
3959 case SHADER_OPCODE_TXS
:
3960 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3961 bld
.MOV(msg_lod
, lod
);
3962 msg_end
= offset(msg_lod
, bld
, 1);
3964 case SHADER_OPCODE_TXF
:
3965 msg_lod
= offset(msg_coords
, bld
, 3);
3966 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3967 msg_end
= offset(msg_lod
, bld
, 1);
3969 case SHADER_OPCODE_TXF_CMS
:
3970 msg_lod
= offset(msg_coords
, bld
, 3);
3972 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
3974 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3975 msg_end
= offset(msg_lod
, bld
, 2);
3982 inst
->src
[0] = reg_undef
;
3983 inst
->src
[1] = surface
;
3984 inst
->src
[2] = sampler
;
3985 inst
->resize_sources(3);
3986 inst
->base_mrf
= message
.nr
;
3987 inst
->mlen
= msg_end
.nr
- message
.nr
;
3988 inst
->header_size
= header_size
;
3990 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3991 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3995 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
3997 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4000 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4004 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4005 const fs_reg
&coordinate
,
4006 const fs_reg
&shadow_c
,
4007 fs_reg lod
, const fs_reg
&lod2
,
4008 const fs_reg
&sample_index
,
4010 const fs_reg
&surface
,
4011 const fs_reg
&sampler
,
4012 const fs_reg
&tg4_offset
,
4013 unsigned coord_components
,
4014 unsigned grad_components
)
4016 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4017 unsigned reg_width
= bld
.dispatch_width() / 8;
4018 unsigned header_size
= 0, length
= 0;
4019 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4020 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4021 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4023 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4024 inst
->offset
!= 0 || inst
->eot
||
4025 op
== SHADER_OPCODE_SAMPLEINFO
||
4026 is_high_sampler(devinfo
, sampler
)) {
4027 /* For general texture offsets (no txf workaround), we need a header to
4028 * put them in. Note that we're only reserving space for it in the
4029 * message payload as it will be initialized implicitly by the
4032 * TG4 needs to place its channel select in the header, for interaction
4033 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4034 * larger sampler numbers we need to offset the Sampler State Pointer in
4038 sources
[0] = fs_reg();
4041 /* If we're requesting fewer than four channels worth of response,
4042 * and we have an explicit header, we need to set up the sampler
4043 * writemask. It's reversed from normal: 1 means "don't write".
4045 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4046 assert(regs_written(inst
) % reg_width
== 0);
4047 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4048 inst
->offset
|= mask
<< 12;
4052 if (shadow_c
.file
!= BAD_FILE
) {
4053 bld
.MOV(sources
[length
], shadow_c
);
4057 bool coordinate_done
= false;
4059 /* Set up the LOD info */
4062 case SHADER_OPCODE_TXL
:
4063 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4064 op
= SHADER_OPCODE_TXL_LZ
;
4067 bld
.MOV(sources
[length
], lod
);
4070 case SHADER_OPCODE_TXD
:
4071 /* TXD should have been lowered in SIMD16 mode. */
4072 assert(bld
.dispatch_width() == 8);
4074 /* Load dPdx and the coordinate together:
4075 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4077 for (unsigned i
= 0; i
< coord_components
; i
++) {
4078 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4080 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4081 * only derivatives for (u, v, r).
4083 if (i
< grad_components
) {
4084 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4085 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4089 coordinate_done
= true;
4091 case SHADER_OPCODE_TXS
:
4092 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4095 case SHADER_OPCODE_TXF
:
4096 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4097 * On Gen9 they are u, v, lod, r
4099 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4101 if (devinfo
->gen
>= 9) {
4102 if (coord_components
>= 2) {
4103 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4104 offset(coordinate
, bld
, 1));
4106 sources
[length
] = brw_imm_d(0);
4111 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4112 op
= SHADER_OPCODE_TXF_LZ
;
4114 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4118 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4119 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4120 offset(coordinate
, bld
, i
));
4122 coordinate_done
= true;
4125 case SHADER_OPCODE_TXF_CMS
:
4126 case SHADER_OPCODE_TXF_CMS_W
:
4127 case SHADER_OPCODE_TXF_UMS
:
4128 case SHADER_OPCODE_TXF_MCS
:
4129 if (op
== SHADER_OPCODE_TXF_UMS
||
4130 op
== SHADER_OPCODE_TXF_CMS
||
4131 op
== SHADER_OPCODE_TXF_CMS_W
) {
4132 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4136 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4137 /* Data from the multisample control surface. */
4138 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4141 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4144 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4145 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4148 offset(mcs
, bld
, 1));
4153 /* There is no offsetting for this message; just copy in the integer
4154 * texture coordinates.
4156 for (unsigned i
= 0; i
< coord_components
; i
++)
4157 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4158 offset(coordinate
, bld
, i
));
4160 coordinate_done
= true;
4162 case SHADER_OPCODE_TG4_OFFSET
:
4163 /* More crazy intermixing */
4164 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4165 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4167 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4168 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4169 offset(tg4_offset
, bld
, i
));
4171 if (coord_components
== 3) /* r if present */
4172 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4174 coordinate_done
= true;
4180 /* Set up the coordinate (except for cases where it was done above) */
4181 if (!coordinate_done
) {
4182 for (unsigned i
= 0; i
< coord_components
; i
++)
4183 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4188 mlen
= length
* reg_width
- header_size
;
4190 mlen
= length
* reg_width
;
4192 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4193 BRW_REGISTER_TYPE_F
);
4194 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4196 /* Generate the SEND. */
4198 inst
->src
[0] = src_payload
;
4199 inst
->src
[1] = surface
;
4200 inst
->src
[2] = sampler
;
4201 inst
->resize_sources(3);
4203 inst
->header_size
= header_size
;
4205 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4206 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4210 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4212 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4213 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4214 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4215 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4216 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4217 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4218 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4219 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4220 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4221 const fs_reg
&tg4_offset
= inst
->src
[TEX_LOGICAL_SRC_TG4_OFFSET
];
4222 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4223 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4224 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4225 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4227 if (devinfo
->gen
>= 7) {
4228 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4229 shadow_c
, lod
, lod2
, sample_index
,
4230 mcs
, surface
, sampler
, tg4_offset
,
4231 coord_components
, grad_components
);
4232 } else if (devinfo
->gen
>= 5) {
4233 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4234 shadow_c
, lod
, lod2
, sample_index
,
4236 coord_components
, grad_components
);
4238 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4239 shadow_c
, lod
, lod2
,
4241 coord_components
, grad_components
);
4246 * Initialize the header present in some typed and untyped surface
4250 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4252 fs_builder ubld
= bld
.exec_all().group(8, 0);
4253 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4254 ubld
.MOV(dst
, brw_imm_d(0));
4255 ubld
.MOV(component(dst
, 7), sample_mask
);
4260 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4261 const fs_reg
&sample_mask
)
4263 /* Get the logical send arguments. */
4264 const fs_reg
&addr
= inst
->src
[0];
4265 const fs_reg
&src
= inst
->src
[1];
4266 const fs_reg
&surface
= inst
->src
[2];
4267 const UNUSED fs_reg
&dims
= inst
->src
[3];
4268 const fs_reg
&arg
= inst
->src
[4];
4270 /* Calculate the total number of components of the payload. */
4271 const unsigned addr_sz
= inst
->components_read(0);
4272 const unsigned src_sz
= inst
->components_read(1);
4273 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4274 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4276 /* Allocate space for the payload. */
4277 fs_reg
*const components
= new fs_reg
[sz
];
4278 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4281 /* Construct the payload. */
4283 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4285 for (unsigned i
= 0; i
< addr_sz
; i
++)
4286 components
[n
++] = offset(addr
, bld
, i
);
4288 for (unsigned i
= 0; i
< src_sz
; i
++)
4289 components
[n
++] = offset(src
, bld
, i
);
4291 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4293 /* Update the original instruction. */
4295 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4296 inst
->header_size
= header_sz
;
4298 inst
->src
[0] = payload
;
4299 inst
->src
[1] = surface
;
4301 inst
->resize_sources(3);
4303 delete[] components
;
4307 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4309 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4311 if (devinfo
->gen
>= 7) {
4312 /* We are switching the instruction from an ALU-like instruction to a
4313 * send-from-grf instruction. Since sends can't handle strides or
4314 * source modifiers, we have to make a copy of the offset source.
4316 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4317 bld
.MOV(tmp
, inst
->src
[1]);
4320 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4323 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4324 BRW_REGISTER_TYPE_UD
);
4326 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4328 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4329 inst
->resize_sources(1);
4330 inst
->base_mrf
= payload
.nr
;
4331 inst
->header_size
= 1;
4332 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4337 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4339 assert(bld
.shader
->devinfo
->gen
< 6);
4342 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4344 if (inst
->sources
> 1) {
4345 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4346 * "Message Payload":
4348 * "Operand0[7]. For the INT DIV functions, this operand is the
4351 * "Operand1[7]. For the INT DIV functions, this operand is the
4354 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4355 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4356 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4358 inst
->resize_sources(1);
4359 inst
->src
[0] = src0
;
4361 assert(inst
->exec_size
== 8);
4362 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4367 fs_visitor::lower_logical_sends()
4369 bool progress
= false;
4371 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4372 const fs_builder
ibld(this, block
, inst
);
4374 switch (inst
->opcode
) {
4375 case FS_OPCODE_FB_WRITE_LOGICAL
:
4376 assert(stage
== MESA_SHADER_FRAGMENT
);
4377 lower_fb_write_logical_send(ibld
, inst
,
4378 brw_wm_prog_data(prog_data
),
4379 (const brw_wm_prog_key
*)key
,
4383 case FS_OPCODE_FB_READ_LOGICAL
:
4384 lower_fb_read_logical_send(ibld
, inst
);
4387 case SHADER_OPCODE_TEX_LOGICAL
:
4388 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4391 case SHADER_OPCODE_TXD_LOGICAL
:
4392 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4395 case SHADER_OPCODE_TXF_LOGICAL
:
4396 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4399 case SHADER_OPCODE_TXL_LOGICAL
:
4400 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4403 case SHADER_OPCODE_TXS_LOGICAL
:
4404 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4407 case FS_OPCODE_TXB_LOGICAL
:
4408 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4411 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4412 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4415 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4416 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4419 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4420 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4423 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4424 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4427 case SHADER_OPCODE_LOD_LOGICAL
:
4428 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4431 case SHADER_OPCODE_TG4_LOGICAL
:
4432 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4435 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4436 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4439 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4440 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
4443 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4444 lower_surface_logical_send(ibld
, inst
,
4445 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4449 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4450 lower_surface_logical_send(ibld
, inst
,
4451 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4452 ibld
.sample_mask_reg());
4455 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4456 lower_surface_logical_send(ibld
, inst
,
4457 SHADER_OPCODE_UNTYPED_ATOMIC
,
4458 ibld
.sample_mask_reg());
4461 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4462 lower_surface_logical_send(ibld
, inst
,
4463 SHADER_OPCODE_TYPED_SURFACE_READ
,
4467 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4468 lower_surface_logical_send(ibld
, inst
,
4469 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4470 ibld
.sample_mask_reg());
4473 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4474 lower_surface_logical_send(ibld
, inst
,
4475 SHADER_OPCODE_TYPED_ATOMIC
,
4476 ibld
.sample_mask_reg());
4479 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4480 lower_varying_pull_constant_logical_send(ibld
, inst
);
4483 case SHADER_OPCODE_RCP
:
4484 case SHADER_OPCODE_RSQ
:
4485 case SHADER_OPCODE_SQRT
:
4486 case SHADER_OPCODE_EXP2
:
4487 case SHADER_OPCODE_LOG2
:
4488 case SHADER_OPCODE_SIN
:
4489 case SHADER_OPCODE_COS
:
4490 case SHADER_OPCODE_POW
:
4491 case SHADER_OPCODE_INT_QUOTIENT
:
4492 case SHADER_OPCODE_INT_REMAINDER
:
4493 /* The math opcodes are overloaded for the send-like and
4494 * expression-like instructions which seems kind of icky. Gen6+ has
4495 * a native (but rather quirky) MATH instruction so we don't need to
4496 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
4497 * logical instructions (which we can easily recognize because they
4498 * have mlen = 0) into send-like virtual instructions.
4500 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
4501 lower_math_logical_send(ibld
, inst
);
4516 invalidate_live_intervals();
4522 * Get the closest allowed SIMD width for instruction \p inst accounting for
4523 * some common regioning and execution control restrictions that apply to FPU
4524 * instructions. These restrictions don't necessarily have any relevance to
4525 * instructions not executed by the FPU pipeline like extended math, control
4526 * flow or send message instructions.
4528 * For virtual opcodes it's really up to the instruction -- In some cases
4529 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
4530 * instructions) it may simplify virtual instruction lowering if we can
4531 * enforce FPU-like regioning restrictions already on the virtual instruction,
4532 * in other cases (e.g. virtual send-like instructions) this may be
4533 * excessively restrictive.
4536 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
4537 const fs_inst
*inst
)
4539 /* Maximum execution size representable in the instruction controls. */
4540 unsigned max_width
= MIN2(32, inst
->exec_size
);
4542 /* According to the PRMs:
4543 * "A. In Direct Addressing mode, a source cannot span more than 2
4544 * adjacent GRF registers.
4545 * B. A destination cannot span more than 2 adjacent GRF registers."
4547 * Look for the source or destination with the largest register region
4548 * which is the one that is going to limit the overall execution size of
4549 * the instruction due to this rule.
4551 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4553 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4554 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
4556 /* Calculate the maximum execution size of the instruction based on the
4557 * factor by which it goes over the hardware limit of 2 GRFs.
4560 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
4562 /* According to the IVB PRMs:
4563 * "When destination spans two registers, the source MUST span two
4564 * registers. The exception to the above rule:
4566 * - When source is scalar, the source registers are not incremented.
4567 * - When source is packed integer Word and destination is packed
4568 * integer DWord, the source register is not incremented but the
4569 * source sub register is incremented."
4571 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
4572 * restrictions. The code below intentionally doesn't check whether the
4573 * destination type is integer because empirically the hardware doesn't
4574 * seem to care what the actual type is as long as it's dword-aligned.
4576 if (devinfo
->gen
< 8) {
4577 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
4578 /* IVB implements DF scalars as <0;2,1> regions. */
4579 const bool is_scalar_exception
= is_uniform(inst
->src
[i
]) &&
4580 (devinfo
->is_haswell
|| type_sz(inst
->src
[i
].type
) != 8);
4581 const bool is_packed_word_exception
=
4582 type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
4583 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1;
4585 if (inst
->size_written
> REG_SIZE
&&
4586 inst
->size_read(i
) != 0 && inst
->size_read(i
) <= REG_SIZE
&&
4587 !is_scalar_exception
&& !is_packed_word_exception
) {
4588 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4589 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4594 /* From the IVB PRMs:
4595 * "When an instruction is SIMD32, the low 16 bits of the execution mask
4596 * are applied for both halves of the SIMD32 instruction. If different
4597 * execution mask channels are required, split the instruction into two
4598 * SIMD16 instructions."
4600 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
4601 * 32-wide control flow support in hardware and will behave similarly.
4603 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
4604 max_width
= MIN2(max_width
, 16);
4606 /* From the IVB PRMs (applies to HSW too):
4607 * "Instructions with condition modifiers must not use SIMD32."
4609 * From the BDW PRMs (applies to later hardware too):
4610 * "Ternary instruction with condition modifiers must not use SIMD32."
4612 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
4613 max_width
= MIN2(max_width
, 16);
4615 /* From the IVB PRMs (applies to other devices that don't have the
4616 * gen_device_info::supports_simd16_3src flag set):
4617 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
4618 * SIMD8 is not allowed for DF operations."
4620 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
4621 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4623 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
4624 * the 8-bit quarter of the execution mask signals specified in the
4625 * instruction control fields) for the second compressed half of any
4626 * single-precision instruction (for double-precision instructions
4627 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
4628 * the EU will apply the wrong execution controls for the second
4629 * sequential GRF write if the number of channels per GRF is not exactly
4630 * eight in single-precision mode (or four in double-float mode).
4632 * In this situation we calculate the maximum size of the split
4633 * instructions so they only ever write to a single register.
4635 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
4636 !inst
->force_writemask_all
) {
4637 const unsigned channels_per_grf
= inst
->exec_size
/
4638 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4639 const unsigned exec_type_size
= get_exec_type_size(inst
);
4640 assert(exec_type_size
);
4642 /* The hardware shifts exactly 8 channels per compressed half of the
4643 * instruction in single-precision mode and exactly 4 in double-precision.
4645 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
4646 max_width
= MIN2(max_width
, channels_per_grf
);
4648 /* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
4649 * because HW applies the same channel enable signals to both halves of
4650 * the compressed instruction which will be just wrong under
4651 * non-uniform control flow.
4653 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4654 (exec_type_size
== 8 || type_sz(inst
->dst
.type
) == 8))
4655 max_width
= MIN2(max_width
, 4);
4658 /* Only power-of-two execution sizes are representable in the instruction
4661 return 1 << _mesa_logbase2(max_width
);
4665 * Get the maximum allowed SIMD width for instruction \p inst accounting for
4666 * various payload size restrictions that apply to sampler message
4669 * This is only intended to provide a maximum theoretical bound for the
4670 * execution size of the message based on the number of argument components
4671 * alone, which in most cases will determine whether the SIMD8 or SIMD16
4672 * variant of the message can be used, though some messages may have
4673 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
4674 * the message length to determine the exact SIMD width and argument count,
4675 * which makes a number of sampler message combinations impossible to
4679 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
4680 const fs_inst
*inst
)
4682 /* Calculate the number of coordinate components that have to be present
4683 * assuming that additional arguments follow the texel coordinates in the
4684 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
4685 * need to pad to four or three components depending on the message,
4686 * pre-ILK we need to pad to at most three components.
4688 const unsigned req_coord_components
=
4689 (devinfo
->gen
>= 7 ||
4690 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
4691 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
4692 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
4695 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
4696 * variant of the TXL or TXF message.
4698 const bool implicit_lod
= devinfo
->gen
>= 9 &&
4699 (inst
->opcode
== SHADER_OPCODE_TXL
||
4700 inst
->opcode
== SHADER_OPCODE_TXF
) &&
4701 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
4703 /* Calculate the total number of argument components that need to be passed
4704 * to the sampler unit.
4706 const unsigned num_payload_components
=
4707 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
4708 req_coord_components
) +
4709 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
4710 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
4711 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
4712 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
4713 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
4714 inst
->components_read(TEX_LOGICAL_SRC_TG4_OFFSET
) : 0) +
4715 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
4717 /* SIMD16 messages with more than five arguments exceed the maximum message
4718 * size supported by the sampler, regardless of whether a header is
4721 return MIN2(inst
->exec_size
,
4722 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
4726 * Get the closest native SIMD width supported by the hardware for instruction
4727 * \p inst. The instruction will be left untouched by
4728 * fs_visitor::lower_simd_width() if the returned value is equal to the
4729 * original execution size.
4732 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
4733 const fs_inst
*inst
)
4735 switch (inst
->opcode
) {
4736 case BRW_OPCODE_MOV
:
4737 case BRW_OPCODE_SEL
:
4738 case BRW_OPCODE_NOT
:
4739 case BRW_OPCODE_AND
:
4741 case BRW_OPCODE_XOR
:
4742 case BRW_OPCODE_SHR
:
4743 case BRW_OPCODE_SHL
:
4744 case BRW_OPCODE_ASR
:
4745 case BRW_OPCODE_CMPN
:
4746 case BRW_OPCODE_CSEL
:
4747 case BRW_OPCODE_F32TO16
:
4748 case BRW_OPCODE_F16TO32
:
4749 case BRW_OPCODE_BFREV
:
4750 case BRW_OPCODE_BFE
:
4751 case BRW_OPCODE_ADD
:
4752 case BRW_OPCODE_MUL
:
4753 case BRW_OPCODE_AVG
:
4754 case BRW_OPCODE_FRC
:
4755 case BRW_OPCODE_RNDU
:
4756 case BRW_OPCODE_RNDD
:
4757 case BRW_OPCODE_RNDE
:
4758 case BRW_OPCODE_RNDZ
:
4759 case BRW_OPCODE_LZD
:
4760 case BRW_OPCODE_FBH
:
4761 case BRW_OPCODE_FBL
:
4762 case BRW_OPCODE_CBIT
:
4763 case BRW_OPCODE_SAD2
:
4764 case BRW_OPCODE_MAD
:
4765 case BRW_OPCODE_LRP
:
4766 case FS_OPCODE_PACK
:
4767 return get_fpu_lowered_simd_width(devinfo
, inst
);
4769 case BRW_OPCODE_CMP
: {
4770 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
4771 * when the destination is a GRF the dependency-clear bit on the flag
4772 * register is cleared early.
4774 * Suggested workarounds are to disable coissuing CMP instructions
4775 * or to split CMP(16) instructions into two CMP(8) instructions.
4777 * We choose to split into CMP(8) instructions since disabling
4778 * coissuing would affect CMP instructions not otherwise affected by
4781 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4782 !inst
->dst
.is_null() ? 8 : ~0);
4783 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
4785 case BRW_OPCODE_BFI1
:
4786 case BRW_OPCODE_BFI2
:
4787 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
4789 * "Force BFI instructions to be executed always in SIMD8."
4791 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
4792 get_fpu_lowered_simd_width(devinfo
, inst
));
4795 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
4796 return inst
->exec_size
;
4798 case SHADER_OPCODE_RCP
:
4799 case SHADER_OPCODE_RSQ
:
4800 case SHADER_OPCODE_SQRT
:
4801 case SHADER_OPCODE_EXP2
:
4802 case SHADER_OPCODE_LOG2
:
4803 case SHADER_OPCODE_SIN
:
4804 case SHADER_OPCODE_COS
:
4805 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
4808 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4809 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
4810 MIN2(8, inst
->exec_size
));
4812 case SHADER_OPCODE_POW
:
4813 /* SIMD16 is only allowed on Gen7+. */
4814 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4815 MIN2(8, inst
->exec_size
));
4817 case SHADER_OPCODE_INT_QUOTIENT
:
4818 case SHADER_OPCODE_INT_REMAINDER
:
4819 /* Integer division is limited to SIMD8 on all generations. */
4820 return MIN2(8, inst
->exec_size
);
4822 case FS_OPCODE_LINTERP
:
4823 case FS_OPCODE_GET_BUFFER_SIZE
:
4824 case FS_OPCODE_DDX_COARSE
:
4825 case FS_OPCODE_DDX_FINE
:
4826 case FS_OPCODE_DDY_COARSE
:
4827 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
4828 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
4829 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
4830 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
4831 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
4832 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
4833 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
4834 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
4835 return MIN2(16, inst
->exec_size
);
4837 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4838 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
4839 * message used to implement varying pull constant loads, so expand it
4840 * to SIMD16. An alternative with longer message payload length but
4841 * shorter return payload would be to use the SIMD8 sampler message that
4842 * takes (header, u, v, r) as parameters instead of (header, u).
4844 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
4846 case FS_OPCODE_DDY_FINE
:
4847 /* The implementation of this virtual opcode may require emitting
4848 * compressed Align16 instructions, which are severely limited on some
4851 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
4852 * Region Restrictions):
4854 * "In Align16 access mode, SIMD16 is not allowed for DW operations
4855 * and SIMD8 is not allowed for DF operations."
4857 * In this context, "DW operations" means "operations acting on 32-bit
4858 * values", so it includes operations on floats.
4860 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
4861 * (Instruction Compression -> Rules and Restrictions):
4863 * "A compressed instruction must be in Align1 access mode. Align16
4864 * mode instructions cannot be compressed."
4866 * Similar text exists in the g45 PRM.
4868 * Empirically, compressed align16 instructions using odd register
4869 * numbers don't appear to work on Sandybridge either.
4871 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
4872 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
4873 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
4875 case SHADER_OPCODE_MULH
:
4876 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4877 * is 8-wide on Gen7+.
4879 return (devinfo
->gen
>= 7 ? 8 :
4880 get_fpu_lowered_simd_width(devinfo
, inst
));
4882 case FS_OPCODE_FB_WRITE_LOGICAL
:
4883 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4886 assert(devinfo
->gen
!= 6 ||
4887 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4888 inst
->exec_size
== 8);
4889 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4890 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4891 8 : MIN2(16, inst
->exec_size
));
4893 case FS_OPCODE_FB_READ_LOGICAL
:
4894 return MIN2(16, inst
->exec_size
);
4896 case SHADER_OPCODE_TEX_LOGICAL
:
4897 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4898 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4899 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4900 case SHADER_OPCODE_LOD_LOGICAL
:
4901 case SHADER_OPCODE_TG4_LOGICAL
:
4902 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4903 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4904 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4905 return get_sampler_lowered_simd_width(devinfo
, inst
);
4907 case SHADER_OPCODE_TXD_LOGICAL
:
4908 /* TXD is unsupported in SIMD16 mode. */
4911 case SHADER_OPCODE_TXL_LOGICAL
:
4912 case FS_OPCODE_TXB_LOGICAL
:
4913 /* Only one execution size is representable pre-ILK depending on whether
4914 * the shadow reference argument is present.
4916 if (devinfo
->gen
== 4)
4917 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
4919 return get_sampler_lowered_simd_width(devinfo
, inst
);
4921 case SHADER_OPCODE_TXF_LOGICAL
:
4922 case SHADER_OPCODE_TXS_LOGICAL
:
4923 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4924 * messages. Use SIMD16 instead.
4926 if (devinfo
->gen
== 4)
4929 return get_sampler_lowered_simd_width(devinfo
, inst
);
4931 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4932 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4933 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4936 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4937 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4938 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4939 return MIN2(16, inst
->exec_size
);
4941 case SHADER_OPCODE_URB_READ_SIMD8
:
4942 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
4943 case SHADER_OPCODE_URB_WRITE_SIMD8
:
4944 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
4945 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
4946 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
4947 return MIN2(8, inst
->exec_size
);
4949 case SHADER_OPCODE_MOV_INDIRECT
: {
4950 /* From IVB and HSW PRMs:
4952 * "2.When the destination requires two registers and the sources are
4953 * indirect, the sources must use 1x1 regioning mode.
4955 * In case of DF instructions in HSW/IVB, the exec_size is limited by
4956 * the EU decompression logic not handling VxH indirect addressing
4959 const unsigned max_size
= (devinfo
->gen
>= 8 ? 2 : 1) * REG_SIZE
;
4960 /* Prior to Broadwell, we only have 8 address subregisters. */
4961 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
4962 max_size
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
4966 case SHADER_OPCODE_LOAD_PAYLOAD
: {
4967 const unsigned reg_count
=
4968 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
4970 if (reg_count
> 2) {
4971 /* Only LOAD_PAYLOAD instructions with per-channel destination region
4972 * can be easily lowered (which excludes headers and heterogeneous
4975 assert(!inst
->header_size
);
4976 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4977 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
4978 inst
->src
[i
].file
== BAD_FILE
);
4980 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4982 return inst
->exec_size
;
4986 return inst
->exec_size
;
4991 * Return true if splitting out the group of channels of instruction \p inst
4992 * given by lbld.group() requires allocating a temporary for the i-th source
4993 * of the lowered instruction.
4996 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
4998 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
4999 (inst
->components_read(i
) == 1 &&
5000 lbld
.dispatch_width() <= inst
->exec_size
));
5004 * Extract the data that would be consumed by the channel group given by
5005 * lbld.group() from the i-th source region of instruction \p inst and return
5006 * it as result in packed form. If any copy instructions are required they
5007 * will be emitted before the given \p inst in \p block.
5010 emit_unzip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
,
5013 /* Specified channel group from the source region. */
5014 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group());
5016 if (needs_src_copy(lbld
, inst
, i
)) {
5017 /* Builder of the right width to perform the copy avoiding uninitialized
5018 * data if the lowered execution size is greater than the original
5019 * execution size of the instruction.
5021 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5022 inst
->exec_size
), 0);
5023 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
5025 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
5026 cbld
.at(block
, inst
)
5027 .MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
5031 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
5032 /* The source is invariant for all dispatch_width-wide groups of the
5035 return inst
->src
[i
];
5038 /* We can just point the lowered instruction at the right channel group
5039 * from the original region.
5046 * Return true if splitting out the group of channels of instruction \p inst
5047 * given by lbld.group() requires allocating a temporary for the destination
5048 * of the lowered instruction and copying the data back to the original
5049 * destination region.
5052 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
5054 /* If the instruction writes more than one component we'll have to shuffle
5055 * the results of multiple lowered instructions in order to make sure that
5056 * they end up arranged correctly in the original destination region.
5058 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
5061 /* If the lowered execution size is larger than the original the result of
5062 * the instruction won't fit in the original destination, so we'll have to
5063 * allocate a temporary in any case.
5065 if (lbld
.dispatch_width() > inst
->exec_size
)
5068 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5069 /* If we already made a copy of the source for other reasons there won't
5070 * be any overlap with the destination.
5072 if (needs_src_copy(lbld
, inst
, i
))
5075 /* In order to keep the logic simple we emit a copy whenever the
5076 * destination region doesn't exactly match an overlapping source, which
5077 * may point at the source and destination not being aligned group by
5078 * group which could cause one of the lowered instructions to overwrite
5079 * the data read from the same source by other lowered instructions.
5081 if (regions_overlap(inst
->dst
, inst
->size_written
,
5082 inst
->src
[i
], inst
->size_read(i
)) &&
5083 !inst
->dst
.equals(inst
->src
[i
]))
5091 * Insert data from a packed temporary into the channel group given by
5092 * lbld.group() of the destination region of instruction \p inst and return
5093 * the temporary as result. If any copy instructions are required they will
5094 * be emitted around the given \p inst in \p block.
5097 emit_zip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
)
5099 /* Builder of the right width to perform the copy avoiding uninitialized
5100 * data if the lowered execution size is greater than the original
5101 * execution size of the instruction.
5103 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5104 inst
->exec_size
), 0);
5106 /* Specified channel group from the destination region. */
5107 const fs_reg dst
= horiz_offset(inst
->dst
, lbld
.group());
5108 const unsigned dst_size
= inst
->size_written
/
5109 inst
->dst
.component_size(inst
->exec_size
);
5111 if (needs_dst_copy(lbld
, inst
)) {
5112 const fs_reg tmp
= lbld
.vgrf(inst
->dst
.type
, dst_size
);
5114 if (inst
->predicate
) {
5115 /* Handle predication by copying the original contents of
5116 * the destination into the temporary before emitting the
5117 * lowered instruction.
5119 for (unsigned k
= 0; k
< dst_size
; ++k
)
5120 cbld
.at(block
, inst
)
5121 .MOV(offset(tmp
, lbld
, k
), offset(dst
, inst
->exec_size
, k
));
5124 for (unsigned k
= 0; k
< dst_size
; ++k
)
5125 cbld
.at(block
, inst
->next
)
5126 .MOV(offset(dst
, inst
->exec_size
, k
), offset(tmp
, lbld
, k
));
5131 /* No need to allocate a temporary for the lowered instruction, just
5132 * take the right group of channels from the original region.
5139 fs_visitor::lower_simd_width()
5141 bool progress
= false;
5143 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5144 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5146 if (lower_width
!= inst
->exec_size
) {
5147 /* Builder matching the original instruction. We may also need to
5148 * emit an instruction of width larger than the original, set the
5149 * execution size of the builder to the highest of both for now so
5150 * we're sure that both cases can be handled.
5152 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5153 const fs_builder ibld
= bld
.at(block
, inst
)
5154 .exec_all(inst
->force_writemask_all
)
5155 .group(max_width
, inst
->group
/ max_width
);
5157 /* Split the copies in chunks of the execution width of either the
5158 * original or the lowered instruction, whichever is lower.
5160 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5161 const unsigned dst_size
= inst
->size_written
/
5162 inst
->dst
.component_size(inst
->exec_size
);
5164 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5166 for (unsigned i
= 0; i
< n
; i
++) {
5167 /* Emit a copy of the original instruction with the lowered width.
5168 * If the EOT flag was set throw it away except for the last
5169 * instruction to avoid killing the thread prematurely.
5171 fs_inst split_inst
= *inst
;
5172 split_inst
.exec_size
= lower_width
;
5173 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
5175 /* Select the correct channel enables for the i-th group, then
5176 * transform the sources and destination and emit the lowered
5179 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5181 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5182 split_inst
.src
[j
] = emit_unzip(lbld
, block
, inst
, j
);
5184 split_inst
.dst
= emit_zip(lbld
, block
, inst
);
5185 split_inst
.size_written
=
5186 split_inst
.dst
.component_size(lower_width
) * dst_size
;
5188 lbld
.emit(split_inst
);
5191 inst
->remove(block
);
5197 invalidate_live_intervals();
5203 fs_visitor::dump_instructions()
5205 dump_instructions(NULL
);
5209 fs_visitor::dump_instructions(const char *name
)
5211 FILE *file
= stderr
;
5212 if (name
&& geteuid() != 0) {
5213 file
= fopen(name
, "w");
5219 calculate_register_pressure();
5220 int ip
= 0, max_pressure
= 0;
5221 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5222 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5223 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5224 dump_instruction(inst
, file
);
5227 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5230 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5231 fprintf(file
, "%4d: ", ip
++);
5232 dump_instruction(inst
, file
);
5236 if (file
!= stderr
) {
5242 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5244 dump_instruction(be_inst
, stderr
);
5248 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5250 fs_inst
*inst
= (fs_inst
*)be_inst
;
5252 if (inst
->predicate
) {
5253 fprintf(file
, "(%cf0.%d) ",
5254 inst
->predicate_inverse
? '-' : '+',
5258 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5260 fprintf(file
, ".sat");
5261 if (inst
->conditional_mod
) {
5262 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5263 if (!inst
->predicate
&&
5264 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5265 inst
->opcode
!= BRW_OPCODE_IF
&&
5266 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5267 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
5270 fprintf(file
, "(%d) ", inst
->exec_size
);
5273 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5277 fprintf(file
, "(EOT) ");
5280 switch (inst
->dst
.file
) {
5282 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
5285 fprintf(file
, "g%d", inst
->dst
.nr
);
5288 fprintf(file
, "m%d", inst
->dst
.nr
);
5291 fprintf(file
, "(null)");
5294 fprintf(file
, "***u%d***", inst
->dst
.nr
);
5297 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
5300 switch (inst
->dst
.nr
) {
5302 fprintf(file
, "null");
5304 case BRW_ARF_ADDRESS
:
5305 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
5307 case BRW_ARF_ACCUMULATOR
:
5308 fprintf(file
, "acc%d", inst
->dst
.subnr
);
5311 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5314 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5319 unreachable("not reached");
5322 if (inst
->dst
.offset
||
5323 (inst
->dst
.file
== VGRF
&&
5324 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
5325 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
5326 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
5327 inst
->dst
.offset
% reg_size
);
5330 if (inst
->dst
.stride
!= 1)
5331 fprintf(file
, "<%u>", inst
->dst
.stride
);
5332 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
5334 for (int i
= 0; i
< inst
->sources
; i
++) {
5335 if (inst
->src
[i
].negate
)
5337 if (inst
->src
[i
].abs
)
5339 switch (inst
->src
[i
].file
) {
5341 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
5344 fprintf(file
, "g%d", inst
->src
[i
].nr
);
5347 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
5350 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
5353 fprintf(file
, "u%d", inst
->src
[i
].nr
);
5356 fprintf(file
, "(null)");
5359 switch (inst
->src
[i
].type
) {
5360 case BRW_REGISTER_TYPE_F
:
5361 fprintf(file
, "%-gf", inst
->src
[i
].f
);
5363 case BRW_REGISTER_TYPE_DF
:
5364 fprintf(file
, "%fdf", inst
->src
[i
].df
);
5366 case BRW_REGISTER_TYPE_W
:
5367 case BRW_REGISTER_TYPE_D
:
5368 fprintf(file
, "%dd", inst
->src
[i
].d
);
5370 case BRW_REGISTER_TYPE_UW
:
5371 case BRW_REGISTER_TYPE_UD
:
5372 fprintf(file
, "%uu", inst
->src
[i
].ud
);
5374 case BRW_REGISTER_TYPE_VF
:
5375 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
5376 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
5377 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
5378 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
5379 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5382 fprintf(file
, "???");
5387 switch (inst
->src
[i
].nr
) {
5389 fprintf(file
, "null");
5391 case BRW_ARF_ADDRESS
:
5392 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5394 case BRW_ARF_ACCUMULATOR
:
5395 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5398 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5401 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5407 if (inst
->src
[i
].offset
||
5408 (inst
->src
[i
].file
== VGRF
&&
5409 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
5410 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
5411 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
5412 inst
->src
[i
].offset
% reg_size
);
5415 if (inst
->src
[i
].abs
)
5418 if (inst
->src
[i
].file
!= IMM
) {
5420 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5421 unsigned hstride
= inst
->src
[i
].hstride
;
5422 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5424 stride
= inst
->src
[i
].stride
;
5427 fprintf(file
, "<%u>", stride
);
5429 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
5432 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5433 fprintf(file
, ", ");
5438 if (inst
->force_writemask_all
)
5439 fprintf(file
, "NoMask ");
5441 if (inst
->exec_size
!= dispatch_width
)
5442 fprintf(file
, "group%d ", inst
->group
);
5444 fprintf(file
, "\n");
5448 * Possibly returns an instruction that set up @param reg.
5450 * Sometimes we want to take the result of some expression/variable
5451 * dereference tree and rewrite the instruction generating the result
5452 * of the tree. When processing the tree, we know that the
5453 * instructions generated are all writing temporaries that are dead
5454 * outside of this tree. So, if we have some instructions that write
5455 * a temporary, we're free to point that temp write somewhere else.
5457 * Note that this doesn't guarantee that the instruction generated
5458 * only reg -- it might be the size=4 destination of a texture instruction.
5461 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5466 end
->is_partial_write() ||
5467 !reg
.equals(end
->dst
)) {
5475 fs_visitor::setup_fs_payload_gen6()
5477 assert(stage
== MESA_SHADER_FRAGMENT
);
5478 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
5480 assert(devinfo
->gen
>= 6);
5482 /* R0-1: masks, pixel X/Y coordinates. */
5483 payload
.num_regs
= 2;
5484 /* R2: only for 32-pixel dispatch.*/
5486 /* R3-26: barycentric interpolation coordinates. These appear in the
5487 * same order that they appear in the brw_barycentric_mode
5488 * enum. Each set of coordinates occupies 2 registers if dispatch width
5489 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5490 * appear if they were enabled using the "Barycentric Interpolation
5491 * Mode" bits in WM_STATE.
5493 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
5494 if (prog_data
->barycentric_interp_modes
& (1 << i
)) {
5495 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5496 payload
.num_regs
+= 2;
5497 if (dispatch_width
== 16) {
5498 payload
.num_regs
+= 2;
5503 /* R27: interpolated depth if uses source depth */
5504 prog_data
->uses_src_depth
=
5505 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5506 if (prog_data
->uses_src_depth
) {
5507 payload
.source_depth_reg
= payload
.num_regs
;
5509 if (dispatch_width
== 16) {
5510 /* R28: interpolated depth if not SIMD8. */
5515 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5516 prog_data
->uses_src_w
=
5517 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5518 if (prog_data
->uses_src_w
) {
5519 payload
.source_w_reg
= payload
.num_regs
;
5521 if (dispatch_width
== 16) {
5522 /* R30: interpolated W if not SIMD8. */
5527 /* R31: MSAA position offsets. */
5528 if (prog_data
->persample_dispatch
&&
5529 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
)) {
5530 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
5532 * "MSDISPMODE_PERSAMPLE is required in order to select
5535 * So we can only really get sample positions if we are doing real
5536 * per-sample dispatch. If we need gl_SamplePosition and we don't have
5537 * persample dispatch, we hard-code it to 0.5.
5539 prog_data
->uses_pos_offset
= true;
5540 payload
.sample_pos_reg
= payload
.num_regs
;
5544 /* R32: MSAA input coverage mask */
5545 prog_data
->uses_sample_mask
=
5546 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5547 if (prog_data
->uses_sample_mask
) {
5548 assert(devinfo
->gen
>= 7);
5549 payload
.sample_mask_in_reg
= payload
.num_regs
;
5551 if (dispatch_width
== 16) {
5552 /* R33: input coverage mask if not SIMD8. */
5557 /* R34-: bary for 32-pixel. */
5558 /* R58-59: interp W for 32-pixel. */
5560 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5561 source_depth_to_render_target
= true;
5566 fs_visitor::setup_vs_payload()
5568 /* R0: thread header, R1: urb handles */
5569 payload
.num_regs
= 2;
5573 fs_visitor::setup_gs_payload()
5575 assert(stage
== MESA_SHADER_GEOMETRY
);
5577 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
5578 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
5580 /* R0: thread header, R1: output URB handles */
5581 payload
.num_regs
= 2;
5583 if (gs_prog_data
->include_primitive_id
) {
5584 /* R2: Primitive ID 0..7 */
5588 /* Use a maximum of 24 registers for push-model inputs. */
5589 const unsigned max_push_components
= 24;
5591 /* If pushing our inputs would take too many registers, reduce the URB read
5592 * length (which is in HWords, or 8 registers), and resort to pulling.
5594 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5595 * have to multiply by VerticesIn to obtain the total storage requirement.
5597 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5598 max_push_components
|| gs_prog_data
->invocations
> 1) {
5599 gs_prog_data
->base
.include_vue_handles
= true;
5601 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5602 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5604 vue_prog_data
->urb_read_length
=
5605 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5610 fs_visitor::setup_cs_payload()
5612 assert(devinfo
->gen
>= 7);
5613 payload
.num_regs
= 1;
5617 fs_visitor::calculate_register_pressure()
5619 invalidate_live_intervals();
5620 calculate_live_intervals();
5622 unsigned num_instructions
= 0;
5623 foreach_block(block
, cfg
)
5624 num_instructions
+= block
->instructions
.length();
5626 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5628 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5629 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5630 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5635 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
5637 * The needs_unlit_centroid_workaround ends up producing one of these per
5638 * channel of centroid input, so it's good to clean them up.
5640 * An assumption here is that nothing ever modifies the dispatched pixels
5641 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
5642 * dictates that anyway.
5645 fs_visitor::opt_drop_redundant_mov_to_flags()
5647 bool flag_mov_found
[2] = {false};
5648 bool progress
= false;
5650 /* Instructions removed by this pass can only be added if this were true */
5651 if (!devinfo
->needs_unlit_centroid_workaround
)
5654 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5655 if (inst
->is_control_flow()) {
5656 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
5657 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
5658 if (!flag_mov_found
[inst
->flag_subreg
]) {
5659 flag_mov_found
[inst
->flag_subreg
] = true;
5661 inst
->remove(block
);
5664 } else if (inst
->flags_written()) {
5665 flag_mov_found
[inst
->flag_subreg
] = false;
5673 fs_visitor::optimize()
5675 /* Start by validating the shader we currently have. */
5678 /* bld is the common builder object pointing at the end of the program we
5679 * used to translate it into i965 IR. For the optimization and lowering
5680 * passes coming next, any code added after the end of the program without
5681 * having explicitly called fs_builder::at() clearly points at a mistake.
5682 * Ideally optimization passes wouldn't be part of the visitor so they
5683 * wouldn't have access to bld at all, but they do, so just in case some
5684 * pass forgets to ask for a location explicitly set it to NULL here to
5685 * make it trip. The dispatch width is initialized to a bogus value to
5686 * make sure that optimizations set the execution controls explicitly to
5687 * match the code they are manipulating instead of relying on the defaults.
5689 bld
= fs_builder(this, 64);
5691 assign_constant_locations();
5692 lower_constant_loads();
5696 split_virtual_grfs();
5699 #define OPT(pass, args...) ({ \
5701 bool this_progress = pass(args); \
5703 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5704 char filename[64]; \
5705 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5706 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5708 backend_shader::dump_instructions(filename); \
5713 progress = progress || this_progress; \
5717 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5719 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5720 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5722 backend_shader::dump_instructions(filename
);
5725 bool progress
= false;
5729 OPT(opt_drop_redundant_mov_to_flags
);
5736 OPT(remove_duplicate_mrf_writes
);
5740 OPT(opt_copy_propagation
);
5741 OPT(opt_predicated_break
, this);
5742 OPT(opt_cmod_propagation
);
5743 OPT(dead_code_eliminate
);
5744 OPT(opt_peephole_sel
);
5745 OPT(dead_control_flow_eliminate
, this);
5746 OPT(opt_register_renaming
);
5747 OPT(opt_saturate_propagation
);
5748 OPT(register_coalesce
);
5749 OPT(compute_to_mrf
);
5750 OPT(eliminate_find_live_channel
);
5752 OPT(compact_virtual_grfs
);
5758 if (OPT(lower_pack
)) {
5759 OPT(register_coalesce
);
5760 OPT(dead_code_eliminate
);
5763 OPT(lower_simd_width
);
5765 /* After SIMD lowering just in case we had to unroll the EOT send. */
5766 OPT(opt_sampler_eot
);
5768 OPT(lower_logical_sends
);
5771 OPT(opt_copy_propagation
);
5772 /* Only run after logical send lowering because it's easier to implement
5773 * in terms of physical sends.
5775 if (OPT(opt_zero_samples
))
5776 OPT(opt_copy_propagation
);
5777 /* Run after logical send lowering to give it a chance to CSE the
5778 * LOAD_PAYLOAD instructions created to construct the payloads of
5779 * e.g. texturing messages in cases where it wasn't possible to CSE the
5780 * whole logical instruction.
5783 OPT(register_coalesce
);
5784 OPT(compute_to_mrf
);
5785 OPT(dead_code_eliminate
);
5786 OPT(remove_duplicate_mrf_writes
);
5787 OPT(opt_peephole_sel
);
5790 OPT(opt_redundant_discard_jumps
);
5792 if (OPT(lower_load_payload
)) {
5793 split_virtual_grfs();
5794 OPT(register_coalesce
);
5795 OPT(compute_to_mrf
);
5796 OPT(dead_code_eliminate
);
5799 OPT(opt_combine_constants
);
5800 OPT(lower_integer_multiplication
);
5802 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5803 OPT(opt_cmod_propagation
);
5805 OPT(opt_copy_propagation
);
5806 OPT(dead_code_eliminate
);
5809 if (OPT(lower_conversions
)) {
5810 OPT(opt_copy_propagation
);
5811 OPT(dead_code_eliminate
);
5812 OPT(lower_simd_width
);
5815 lower_uniform_pull_constant_loads();
5821 * Three source instruction must have a GRF/MRF destination register.
5822 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5825 fs_visitor::fixup_3src_null_dest()
5827 bool progress
= false;
5829 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5830 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
5831 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5838 invalidate_live_intervals();
5842 fs_visitor::allocate_registers(bool allow_spilling
)
5844 bool allocated_without_spills
;
5846 static const enum instruction_scheduler_mode pre_modes
[] = {
5848 SCHEDULE_PRE_NON_LIFO
,
5852 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
5854 /* Try each scheduling heuristic to see if it can successfully register
5855 * allocate without spilling. They should be ordered by decreasing
5856 * performance but increasing likelihood of allocating.
5858 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5859 schedule_instructions(pre_modes
[i
]);
5862 assign_regs_trivial();
5863 allocated_without_spills
= true;
5865 allocated_without_spills
= assign_regs(false, spill_all
);
5867 if (allocated_without_spills
)
5871 if (!allocated_without_spills
) {
5872 if (!allow_spilling
)
5873 fail("Failure to register allocate and spilling is not allowed.");
5875 /* We assume that any spilling is worse than just dropping back to
5876 * SIMD8. There's probably actually some intermediate point where
5877 * SIMD16 with a couple of spills is still better.
5879 if (dispatch_width
> min_dispatch_width
) {
5880 fail("Failure to register allocate. Reduce number of "
5881 "live scalar values to avoid this.");
5883 compiler
->shader_perf_log(log_data
,
5884 "%s shader triggered register spilling. "
5885 "Try reducing the number of live scalar "
5886 "values to improve performance.\n",
5890 /* Since we're out of heuristics, just go spill registers until we
5891 * get an allocation.
5893 while (!assign_regs(true, spill_all
)) {
5899 /* This must come after all optimization and register allocation, since
5900 * it inserts dead code that happens to have side effects, and it does
5901 * so based on the actual physical registers in use.
5903 insert_gen4_send_dependency_workarounds();
5908 schedule_instructions(SCHEDULE_POST
);
5910 if (last_scratch
> 0) {
5911 MAYBE_UNUSED
unsigned max_scratch_size
= 2 * 1024 * 1024;
5913 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5915 if (stage
== MESA_SHADER_COMPUTE
) {
5916 if (devinfo
->is_haswell
) {
5917 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5918 * field documentation, Haswell supports a minimum of 2kB of
5919 * scratch space for compute shaders, unlike every other stage
5922 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
5923 } else if (devinfo
->gen
<= 7) {
5924 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5925 * field documentation, platforms prior to Haswell measure scratch
5926 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
5928 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
5929 max_scratch_size
= 12 * 1024;
5933 /* We currently only support up to 2MB of scratch space. If we
5934 * need to support more eventually, the documentation suggests
5935 * that we could allocate a larger buffer, and partition it out
5936 * ourselves. We'd just have to undo the hardware's address
5937 * calculation by subtracting (FFTID * Per Thread Scratch Space)
5938 * and then add FFTID * (Larger Per Thread Scratch Space).
5940 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
5941 * Thread Group Tracking > Local Memory/Scratch Space.
5943 assert(prog_data
->total_scratch
< max_scratch_size
);
5948 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5950 assert(stage
== MESA_SHADER_VERTEX
);
5954 if (shader_time_index
>= 0)
5955 emit_shader_time_begin();
5962 compute_clip_distance(clip_planes
);
5966 if (shader_time_index
>= 0)
5967 emit_shader_time_end();
5973 assign_curb_setup();
5974 assign_vs_urb_setup();
5976 fixup_3src_null_dest();
5977 allocate_registers(true);
5983 fs_visitor::run_tcs_single_patch()
5985 assert(stage
== MESA_SHADER_TESS_CTRL
);
5987 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
5989 /* r1-r4 contain the ICP handles. */
5990 payload
.num_regs
= 5;
5992 if (shader_time_index
>= 0)
5993 emit_shader_time_begin();
5995 /* Initialize gl_InvocationID */
5996 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
5997 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5998 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
5999 bld
.MOV(channels_ud
, channels_uw
);
6001 if (tcs_prog_data
->instances
== 1) {
6002 invocation_id
= channels_ud
;
6004 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6006 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
6007 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6008 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6009 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
6010 brw_imm_ud(INTEL_MASK(23, 17)));
6011 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
6013 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
6016 /* Fix the disptach mask */
6017 if (nir
->info
.tess
.tcs_vertices_out
% 8) {
6018 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
6019 brw_imm_ud(nir
->info
.tess
.tcs_vertices_out
), BRW_CONDITIONAL_L
);
6020 bld
.IF(BRW_PREDICATE_NORMAL
);
6025 if (nir
->info
.tess
.tcs_vertices_out
% 8) {
6026 bld
.emit(BRW_OPCODE_ENDIF
);
6029 /* Emit EOT write; set TR DS Cache bit */
6031 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
6032 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
6033 fs_reg(brw_imm_ud(0)),
6035 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
6036 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
6038 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
6039 bld
.null_reg_ud(), payload
);
6043 if (shader_time_index
>= 0)
6044 emit_shader_time_end();
6053 assign_curb_setup();
6054 assign_tcs_single_patch_urb_setup();
6056 fixup_3src_null_dest();
6057 allocate_registers(true);
6063 fs_visitor::run_tes()
6065 assert(stage
== MESA_SHADER_TESS_EVAL
);
6067 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6068 payload
.num_regs
= 5;
6070 if (shader_time_index
>= 0)
6071 emit_shader_time_begin();
6080 if (shader_time_index
>= 0)
6081 emit_shader_time_end();
6087 assign_curb_setup();
6088 assign_tes_urb_setup();
6090 fixup_3src_null_dest();
6091 allocate_registers(true);
6097 fs_visitor::run_gs()
6099 assert(stage
== MESA_SHADER_GEOMETRY
);
6103 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6105 if (gs_compile
->control_data_header_size_bits
> 0) {
6106 /* Create a VGRF to store accumulated control data bits. */
6107 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6109 /* If we're outputting more than 32 control data bits, then EmitVertex()
6110 * will set control_data_bits to 0 after emitting the first vertex.
6111 * Otherwise, we need to initialize it to 0 here.
6113 if (gs_compile
->control_data_header_size_bits
<= 32) {
6114 const fs_builder abld
= bld
.annotate("initialize control data bits");
6115 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6119 if (shader_time_index
>= 0)
6120 emit_shader_time_begin();
6124 emit_gs_thread_end();
6126 if (shader_time_index
>= 0)
6127 emit_shader_time_end();
6136 assign_curb_setup();
6137 assign_gs_urb_setup();
6139 fixup_3src_null_dest();
6140 allocate_registers(true);
6146 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6148 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
6149 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6151 assert(stage
== MESA_SHADER_FRAGMENT
);
6153 if (devinfo
->gen
>= 6)
6154 setup_fs_payload_gen6();
6156 setup_fs_payload_gen4();
6160 } else if (do_rep_send
) {
6161 assert(dispatch_width
== 16);
6162 emit_repclear_shader();
6164 if (shader_time_index
>= 0)
6165 emit_shader_time_begin();
6167 calculate_urb_setup();
6168 if (nir
->info
.inputs_read
> 0 ||
6169 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
6170 if (devinfo
->gen
< 6)
6171 emit_interpolation_setup_gen4();
6173 emit_interpolation_setup_gen6();
6176 /* We handle discards by keeping track of the still-live pixels in f0.1.
6177 * Initialize it with the dispatched pixels.
6179 if (wm_prog_data
->uses_kill
) {
6180 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
6181 discard_init
->flag_subreg
= 1;
6184 /* Generate FS IR for main(). (the visitor only descends into
6185 * functions called "main").
6192 if (wm_prog_data
->uses_kill
)
6193 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6195 if (wm_key
->alpha_test_func
)
6200 if (shader_time_index
>= 0)
6201 emit_shader_time_end();
6207 assign_curb_setup();
6210 fixup_3src_null_dest();
6211 allocate_registers(allow_spilling
);
6221 fs_visitor::run_cs()
6223 assert(stage
== MESA_SHADER_COMPUTE
);
6227 if (shader_time_index
>= 0)
6228 emit_shader_time_begin();
6230 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6231 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6232 const fs_builder abld
= bld
.exec_all().group(1, 0);
6233 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
6234 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6242 emit_cs_terminate();
6244 if (shader_time_index
>= 0)
6245 emit_shader_time_end();
6251 assign_curb_setup();
6253 fixup_3src_null_dest();
6254 allocate_registers(true);
6263 * Return a bitfield where bit n is set if barycentric interpolation mode n
6264 * (see enum brw_barycentric_mode) is needed by the fragment shader.
6266 * We examine the load_barycentric intrinsics rather than looking at input
6267 * variables so that we catch interpolateAtCentroid() messages too, which
6268 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
6271 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
6272 const nir_shader
*shader
)
6274 unsigned barycentric_interp_modes
= 0;
6276 nir_foreach_function(f
, shader
) {
6280 nir_foreach_block(block
, f
->impl
) {
6281 nir_foreach_instr(instr
, block
) {
6282 if (instr
->type
!= nir_instr_type_intrinsic
)
6285 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6286 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6289 /* Ignore WPOS; it doesn't require interpolation. */
6290 if (nir_intrinsic_base(intrin
) == VARYING_SLOT_POS
)
6293 intrin
= nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6294 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
6295 nir_intrinsic_interp_mode(intrin
);
6296 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
6297 enum brw_barycentric_mode bary
=
6298 brw_barycentric_mode(interp
, bary_op
);
6300 barycentric_interp_modes
|= 1 << bary
;
6302 if (devinfo
->needs_unlit_centroid_workaround
&&
6303 bary_op
== nir_intrinsic_load_barycentric_centroid
)
6304 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
6309 return barycentric_interp_modes
;
6313 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
6314 const nir_shader
*shader
)
6316 prog_data
->flat_inputs
= 0;
6318 nir_foreach_variable(var
, &shader
->inputs
) {
6319 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
6321 if (input_index
< 0)
6325 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6326 prog_data
->flat_inputs
|= (1 << input_index
);
6331 computed_depth_mode(const nir_shader
*shader
)
6333 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6334 switch (shader
->info
.fs
.depth_layout
) {
6335 case FRAG_DEPTH_LAYOUT_NONE
:
6336 case FRAG_DEPTH_LAYOUT_ANY
:
6337 return BRW_PSCDEPTH_ON
;
6338 case FRAG_DEPTH_LAYOUT_GREATER
:
6339 return BRW_PSCDEPTH_ON_GE
;
6340 case FRAG_DEPTH_LAYOUT_LESS
:
6341 return BRW_PSCDEPTH_ON_LE
;
6342 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
6343 return BRW_PSCDEPTH_OFF
;
6346 return BRW_PSCDEPTH_OFF
;
6350 * Move load_interpolated_input with simple (payload-based) barycentric modes
6351 * to the top of the program so we don't emit multiple PLNs for the same input.
6353 * This works around CSE not being able to handle non-dominating cases
6359 * interpolate the same exact input
6362 * This should be replaced by global value numbering someday.
6365 move_interpolation_to_top(nir_shader
*nir
)
6367 bool progress
= false;
6369 nir_foreach_function(f
, nir
) {
6373 nir_block
*top
= nir_start_block(f
->impl
);
6374 exec_node
*cursor_node
= NULL
;
6376 nir_foreach_block(block
, f
->impl
) {
6380 nir_foreach_instr_safe(instr
, block
) {
6381 if (instr
->type
!= nir_instr_type_intrinsic
)
6384 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6385 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6387 nir_intrinsic_instr
*bary_intrinsic
=
6388 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6389 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
6391 /* Leave interpolateAtSample/Offset() where they are. */
6392 if (op
== nir_intrinsic_load_barycentric_at_sample
||
6393 op
== nir_intrinsic_load_barycentric_at_offset
)
6396 nir_instr
*move
[3] = {
6397 &bary_intrinsic
->instr
,
6398 intrin
->src
[1].ssa
->parent_instr
,
6402 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
6403 if (move
[i
]->block
!= top
) {
6404 move
[i
]->block
= top
;
6405 exec_node_remove(&move
[i
]->node
);
6407 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
6409 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
6411 cursor_node
= &move
[i
]->node
;
6417 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6418 ((unsigned) nir_metadata_block_index
|
6419 (unsigned) nir_metadata_dominance
));
6426 * Demote per-sample barycentric intrinsics to centroid.
6428 * Useful when rendering to a non-multisampled buffer.
6431 demote_sample_qualifiers(nir_shader
*nir
)
6433 bool progress
= true;
6435 nir_foreach_function(f
, nir
) {
6440 nir_builder_init(&b
, f
->impl
);
6442 nir_foreach_block(block
, f
->impl
) {
6443 nir_foreach_instr_safe(instr
, block
) {
6444 if (instr
->type
!= nir_instr_type_intrinsic
)
6447 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6448 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
6449 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
6452 b
.cursor
= nir_before_instr(instr
);
6453 nir_ssa_def
*centroid
=
6454 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
6455 nir_intrinsic_interp_mode(intrin
));
6456 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
6457 nir_src_for_ssa(centroid
));
6458 nir_instr_remove(instr
);
6463 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6464 ((unsigned) nir_metadata_block_index
|
6465 (unsigned) nir_metadata_dominance
));
6472 * Pre-gen6, the register file of the EUs was shared between threads,
6473 * and each thread used some subset allocated on a 16-register block
6474 * granularity. The unit states wanted these block counts.
6477 brw_register_blocks(int reg_count
)
6479 return ALIGN(reg_count
, 16) / 16 - 1;
6483 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
6485 const struct brw_wm_prog_key
*key
,
6486 struct brw_wm_prog_data
*prog_data
,
6487 const nir_shader
*src_shader
,
6488 struct gl_program
*prog
,
6489 int shader_time_index8
, int shader_time_index16
,
6490 bool allow_spilling
,
6491 bool use_rep_send
, struct brw_vue_map
*vue_map
,
6492 unsigned *final_assembly_size
,
6495 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
6497 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6498 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, true);
6499 brw_nir_lower_fs_inputs(shader
, devinfo
, key
);
6500 brw_nir_lower_fs_outputs(shader
);
6502 if (devinfo
->gen
< 6) {
6503 brw_setup_vue_interpolation(vue_map
, shader
, prog_data
, devinfo
);
6506 if (!key
->multisample_fbo
)
6507 NIR_PASS_V(shader
, demote_sample_qualifiers
);
6508 NIR_PASS_V(shader
, move_interpolation_to_top
);
6509 shader
= brw_postprocess_nir(shader
, compiler
, true);
6511 /* key->alpha_test_func means simulating alpha testing via discards,
6512 * so the shader definitely kills pixels.
6514 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
||
6515 key
->alpha_test_func
;
6516 prog_data
->uses_omask
= key
->multisample_fbo
&&
6517 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
6518 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
6519 prog_data
->computed_stencil
=
6520 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
6522 prog_data
->persample_dispatch
=
6523 key
->multisample_fbo
&&
6524 (key
->persample_interp
||
6525 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
6526 SYSTEM_BIT_SAMPLE_POS
)) ||
6527 shader
->info
.fs
.uses_sample_qualifier
||
6528 shader
->info
.outputs_read
);
6530 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
6531 prog_data
->post_depth_coverage
= shader
->info
.fs
.post_depth_coverage
;
6532 prog_data
->inner_coverage
= shader
->info
.fs
.inner_coverage
;
6534 prog_data
->barycentric_interp_modes
=
6535 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
6537 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
;
6538 uint8_t simd8_grf_start
= 0, simd16_grf_start
= 0;
6539 unsigned simd8_grf_used
= 0, simd16_grf_used
= 0;
6541 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
6542 &prog_data
->base
, prog
, shader
, 8,
6543 shader_time_index8
);
6544 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
6546 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
6549 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
6551 simd8_grf_start
= v8
.payload
.num_regs
;
6552 simd8_grf_used
= v8
.grf_used
;
6555 if (v8
.max_dispatch_width
>= 16 &&
6556 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
6557 /* Try a SIMD16 compile */
6558 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
6559 &prog_data
->base
, prog
, shader
, 16,
6560 shader_time_index16
);
6561 v16
.import_uniforms(&v8
);
6562 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
6563 compiler
->shader_perf_log(log_data
,
6564 "SIMD16 shader failed to compile: %s",
6567 simd16_cfg
= v16
.cfg
;
6568 simd16_grf_start
= v16
.payload
.num_regs
;
6569 simd16_grf_used
= v16
.grf_used
;
6573 /* When the caller requests a repclear shader, they want SIMD16-only */
6577 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
6578 * at the top to select the shader. We've never implemented that.
6579 * Instead, we just give them exactly one shader and we pick the widest one
6582 if (compiler
->devinfo
->gen
< 5 && simd16_cfg
)
6585 if (prog_data
->persample_dispatch
) {
6586 /* Starting with SandyBridge (where we first get MSAA), the different
6587 * pixel dispatch combinations are grouped into classifications A
6588 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
6589 * generations, the only configurations supporting persample dispatch
6590 * are are this in which only one dispatch width is enabled.
6592 * If computed depth is enabled, SNB only allows SIMD8 while IVB+
6593 * allow SIMD8 or SIMD16 so we choose SIMD16 if available.
6595 if (compiler
->devinfo
->gen
== 6 &&
6596 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
) {
6598 } else if (simd16_cfg
) {
6603 /* We have to compute the flat inputs after the visitor is finished running
6604 * because it relies on prog_data->urb_setup which is computed in
6605 * fs_visitor::calculate_urb_setup().
6607 brw_compute_flat_inputs(prog_data
, shader
);
6609 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
6610 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6611 MESA_SHADER_FRAGMENT
);
6613 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
6614 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
6615 shader
->info
.label
?
6616 shader
->info
.label
: "unnamed",
6617 shader
->info
.name
));
6621 prog_data
->dispatch_8
= true;
6622 g
.generate_code(simd8_cfg
, 8);
6623 prog_data
->base
.dispatch_grf_start_reg
= simd8_grf_start
;
6624 prog_data
->reg_blocks_0
= brw_register_blocks(simd8_grf_used
);
6627 prog_data
->dispatch_16
= true;
6628 prog_data
->prog_offset_2
= g
.generate_code(simd16_cfg
, 16);
6629 prog_data
->dispatch_grf_start_reg_2
= simd16_grf_start
;
6630 prog_data
->reg_blocks_2
= brw_register_blocks(simd16_grf_used
);
6632 } else if (simd16_cfg
) {
6633 prog_data
->dispatch_16
= true;
6634 g
.generate_code(simd16_cfg
, 16);
6635 prog_data
->base
.dispatch_grf_start_reg
= simd16_grf_start
;
6636 prog_data
->reg_blocks_0
= brw_register_blocks(simd16_grf_used
);
6639 return g
.get_assembly(final_assembly_size
);
6643 fs_visitor::emit_cs_work_group_id_setup()
6645 assert(stage
== MESA_SHADER_COMPUTE
);
6647 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6649 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
6650 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
6651 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
6653 bld
.MOV(*reg
, r0_1
);
6654 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
6655 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
6661 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
6663 block
->dwords
= dwords
;
6664 block
->regs
= DIV_ROUND_UP(dwords
, 8);
6665 block
->size
= block
->regs
* 32;
6669 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
6670 struct brw_cs_prog_data
*cs_prog_data
)
6672 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
6673 bool fill_thread_id
=
6674 cs_prog_data
->thread_local_id_index
>= 0 &&
6675 cs_prog_data
->thread_local_id_index
< (int)prog_data
->nr_params
;
6676 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
6678 /* The thread ID should be stored in the last param dword */
6679 assert(prog_data
->nr_params
> 0 || !fill_thread_id
);
6680 assert(!fill_thread_id
||
6681 cs_prog_data
->thread_local_id_index
==
6682 (int)prog_data
->nr_params
- 1);
6684 unsigned cross_thread_dwords
, per_thread_dwords
;
6685 if (!cross_thread_supported
) {
6686 cross_thread_dwords
= 0u;
6687 per_thread_dwords
= prog_data
->nr_params
;
6688 } else if (fill_thread_id
) {
6689 /* Fill all but the last register with cross-thread payload */
6690 cross_thread_dwords
= 8 * (cs_prog_data
->thread_local_id_index
/ 8);
6691 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
6692 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
6694 /* Fill all data using cross-thread payload */
6695 cross_thread_dwords
= prog_data
->nr_params
;
6696 per_thread_dwords
= 0u;
6699 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
6700 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
6702 unsigned total_dwords
=
6703 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
6704 cs_prog_data
->push
.cross_thread
.size
) / 4;
6705 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
6707 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
6708 cs_prog_data
->push
.per_thread
.size
== 0);
6709 assert(cs_prog_data
->push
.cross_thread
.dwords
+
6710 cs_prog_data
->push
.per_thread
.dwords
==
6711 prog_data
->nr_params
);
6715 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
6717 cs_prog_data
->simd_size
= size
;
6718 unsigned group_size
= cs_prog_data
->local_size
[0] *
6719 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
6720 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
6724 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
6726 const struct brw_cs_prog_key
*key
,
6727 struct brw_cs_prog_data
*prog_data
,
6728 const nir_shader
*src_shader
,
6729 int shader_time_index
,
6730 unsigned *final_assembly_size
,
6733 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6734 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, true);
6735 brw_nir_lower_cs_shared(shader
);
6736 prog_data
->base
.total_shared
+= shader
->num_shared
;
6738 /* Now that we cloned the nir_shader, we can update num_uniforms based on
6739 * the thread_local_id_index.
6741 assert(prog_data
->thread_local_id_index
>= 0);
6742 shader
->num_uniforms
=
6743 MAX2(shader
->num_uniforms
,
6744 (unsigned)4 * (prog_data
->thread_local_id_index
+ 1));
6746 brw_nir_lower_intrinsics(shader
, &prog_data
->base
);
6747 shader
= brw_postprocess_nir(shader
, compiler
, true);
6749 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
6750 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
6751 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
6752 unsigned local_workgroup_size
=
6753 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
6754 shader
->info
.cs
.local_size
[2];
6756 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
6757 unsigned simd_required
= DIV_ROUND_UP(local_workgroup_size
, max_cs_threads
);
6760 const char *fail_msg
= NULL
;
6762 /* Now the main event: Visit the shader IR and generate our CS IR for it.
6764 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6765 NULL
, /* Never used in core profile */
6766 shader
, 8, shader_time_index
);
6767 if (simd_required
<= 8) {
6769 fail_msg
= v8
.fail_msg
;
6772 cs_set_simd_size(prog_data
, 8);
6773 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6774 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
6778 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6779 NULL
, /* Never used in core profile */
6780 shader
, 16, shader_time_index
);
6781 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
6782 !fail_msg
&& v8
.max_dispatch_width
>= 16 &&
6783 simd_required
<= 16) {
6784 /* Try a SIMD16 compile */
6785 if (simd_required
<= 8)
6786 v16
.import_uniforms(&v8
);
6787 if (!v16
.run_cs()) {
6788 compiler
->shader_perf_log(log_data
,
6789 "SIMD16 shader failed to compile: %s",
6793 "Couldn't generate SIMD16 program and not "
6794 "enough threads for SIMD8";
6798 cs_set_simd_size(prog_data
, 16);
6799 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6800 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
6804 fs_visitor
v32(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6805 NULL
, /* Never used in core profile */
6806 shader
, 32, shader_time_index
);
6807 if (!fail_msg
&& v8
.max_dispatch_width
>= 32 &&
6808 (simd_required
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
6809 /* Try a SIMD32 compile */
6810 if (simd_required
<= 8)
6811 v32
.import_uniforms(&v8
);
6812 else if (simd_required
<= 16)
6813 v32
.import_uniforms(&v16
);
6815 if (!v32
.run_cs()) {
6816 compiler
->shader_perf_log(log_data
,
6817 "SIMD32 shader failed to compile: %s",
6821 "Couldn't generate SIMD32 program and not "
6822 "enough threads for SIMD16";
6826 cs_set_simd_size(prog_data
, 32);
6827 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6831 if (unlikely(cfg
== NULL
)) {
6834 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
6839 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
6840 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6841 MESA_SHADER_COMPUTE
);
6842 if (INTEL_DEBUG
& DEBUG_CS
) {
6843 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
6844 shader
->info
.label
? shader
->info
.label
:
6847 g
.enable_debug(name
);
6850 g
.generate_code(cfg
, prog_data
->simd_size
);
6852 return g
.get_assembly(final_assembly_size
);
6856 * Test the dispatch mask packing assumptions of
6857 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
6858 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
6859 * executed with an unexpected dispatch mask.
6862 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
6864 const gl_shader_stage stage
= bld
.shader
->stage
;
6866 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
6867 bld
.shader
->stage_prog_data
)) {
6868 const fs_builder ubld
= bld
.exec_all().group(1, 0);
6869 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
6870 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
6873 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
6874 ubld
.AND(tmp
, mask
, tmp
);
6876 /* This will loop forever if the dispatch mask doesn't have the expected
6877 * form '2^n-1', in which case tmp will be non-zero.
6879 bld
.emit(BRW_OPCODE_DO
);
6880 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
6881 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));