2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
35 #include "brw_vec4_gs_visitor.h"
37 #include "brw_dead_control_flow.h"
38 #include "common/gen_debug.h"
39 #include "compiler/glsl_types.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "program/prog_parameter.h"
45 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
49 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
50 const fs_reg
*src
, unsigned sources
)
52 memset(this, 0, sizeof(*this));
54 this->src
= new fs_reg
[MAX2(sources
, 3)];
55 for (unsigned i
= 0; i
< sources
; i
++)
56 this->src
[i
] = src
[i
];
58 this->opcode
= opcode
;
60 this->sources
= sources
;
61 this->exec_size
= exec_size
;
64 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
66 assert(this->exec_size
!= 0);
68 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
70 /* This will be the case for almost all instructions. */
77 this->size_written
= dst
.component_size(exec_size
);
80 this->size_written
= 0;
84 unreachable("Invalid destination register file");
87 this->writes_accumulator
= false;
92 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
95 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
97 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
100 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
102 init(opcode
, exec_size
, dst
, NULL
, 0);
105 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
108 const fs_reg src
[1] = { src0
};
109 init(opcode
, exec_size
, dst
, src
, 1);
112 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
113 const fs_reg
&src0
, const fs_reg
&src1
)
115 const fs_reg src
[2] = { src0
, src1
};
116 init(opcode
, exec_size
, dst
, src
, 2);
119 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
120 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
122 const fs_reg src
[3] = { src0
, src1
, src2
};
123 init(opcode
, exec_size
, dst
, src
, 3);
126 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
127 const fs_reg src
[], unsigned sources
)
129 init(opcode
, exec_width
, dst
, src
, sources
);
132 fs_inst::fs_inst(const fs_inst
&that
)
134 memcpy(this, &that
, sizeof(that
));
136 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
138 for (unsigned i
= 0; i
< that
.sources
; i
++)
139 this->src
[i
] = that
.src
[i
];
148 fs_inst::resize_sources(uint8_t num_sources
)
150 if (this->sources
!= num_sources
) {
151 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
153 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
154 src
[i
] = this->src
[i
];
158 this->sources
= num_sources
;
163 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
165 const fs_reg
&surf_index
,
166 const fs_reg
&varying_offset
,
167 uint32_t const_offset
)
169 /* We have our constant surface use a pitch of 4 bytes, so our index can
170 * be any component of a vector, and then we load 4 contiguous
171 * components starting from that.
173 * We break down the const_offset to a portion added to the variable offset
174 * and a portion done using fs_reg::offset, which means that if you have
175 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
176 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
177 * later notice that those loads are all the same and eliminate the
180 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
181 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
183 /* The pull load message will load a vec4 (16 bytes). If we are loading
184 * a double this means we are only loading 2 elements worth of data.
185 * We also want to use a 32-bit data type for the dst of the load operation
186 * so other parts of the driver don't get confused about the size of the
189 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
190 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
191 vec4_result
, surf_index
, vec4_offset
);
192 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
194 if (type_sz(dst
.type
) == 8) {
195 shuffle_32bit_load_result_to_64bit_data(
196 bld
, retype(vec4_result
, dst
.type
), vec4_result
, 2);
199 vec4_result
.type
= dst
.type
;
200 bld
.MOV(dst
, offset(vec4_result
, bld
,
201 (const_offset
& 0xf) / type_sz(vec4_result
.type
)));
205 * A helper for MOV generation for fixing up broken hardware SEND dependency
209 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
211 /* The caller always wants uncompressed to emit the minimal extra
212 * dependencies, and to avoid having to deal with aligning its regs to 2.
214 const fs_builder ubld
= bld
.annotate("send dependency resolve")
217 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
221 fs_inst::equals(fs_inst
*inst
) const
223 return (opcode
== inst
->opcode
&&
224 dst
.equals(inst
->dst
) &&
225 src
[0].equals(inst
->src
[0]) &&
226 src
[1].equals(inst
->src
[1]) &&
227 src
[2].equals(inst
->src
[2]) &&
228 saturate
== inst
->saturate
&&
229 predicate
== inst
->predicate
&&
230 conditional_mod
== inst
->conditional_mod
&&
231 mlen
== inst
->mlen
&&
232 base_mrf
== inst
->base_mrf
&&
233 target
== inst
->target
&&
235 header_size
== inst
->header_size
&&
236 shadow_compare
== inst
->shadow_compare
&&
237 exec_size
== inst
->exec_size
&&
238 offset
== inst
->offset
);
242 fs_inst::is_send_from_grf() const
245 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
246 case SHADER_OPCODE_SHADER_TIME_ADD
:
247 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
248 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
249 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
250 case SHADER_OPCODE_UNTYPED_ATOMIC
:
251 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
252 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
253 case SHADER_OPCODE_TYPED_ATOMIC
:
254 case SHADER_OPCODE_TYPED_SURFACE_READ
:
255 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
256 case SHADER_OPCODE_URB_WRITE_SIMD8
:
257 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
258 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
259 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
260 case SHADER_OPCODE_URB_READ_SIMD8
:
261 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
263 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
264 return src
[1].file
== VGRF
;
265 case FS_OPCODE_FB_WRITE
:
266 case FS_OPCODE_FB_READ
:
267 return src
[0].file
== VGRF
;
270 return src
[0].file
== VGRF
;
277 * Returns true if this instruction's sources and destinations cannot
278 * safely be the same register.
280 * In most cases, a register can be written over safely by the same
281 * instruction that is its last use. For a single instruction, the
282 * sources are dereferenced before writing of the destination starts
285 * However, there are a few cases where this can be problematic:
287 * - Virtual opcodes that translate to multiple instructions in the
288 * code generator: if src == dst and one instruction writes the
289 * destination before a later instruction reads the source, then
290 * src will have been clobbered.
292 * - SIMD16 compressed instructions with certain regioning (see below).
294 * The register allocator uses this information to set up conflicts between
295 * GRF sources and the destination.
298 fs_inst::has_source_and_destination_hazard() const
301 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
302 /* Multiple partial writes to the destination */
305 /* The SIMD16 compressed instruction
307 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
309 * is actually decoded in hardware as:
311 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
312 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
314 * Which is safe. However, if we have uniform accesses
315 * happening, we get into trouble:
317 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
318 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
320 * Now our destination for the first instruction overwrote the
321 * second instruction's src0, and we get garbage for those 8
322 * pixels. There's a similar issue for the pre-gen6
323 * pixel_x/pixel_y, which are registers of 16-bit values and thus
324 * would get stomped by the first decode as well.
326 if (exec_size
== 16) {
327 for (int i
= 0; i
< sources
; i
++) {
328 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
329 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
330 src
[i
].type
== BRW_REGISTER_TYPE_W
||
331 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
332 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
342 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
344 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
347 fs_reg reg
= this->src
[0];
348 if (reg
.file
!= VGRF
|| reg
.offset
!= 0 || reg
.stride
!= 1)
351 if (grf_alloc
.sizes
[reg
.nr
] * REG_SIZE
!= this->size_written
)
354 for (int i
= 0; i
< this->sources
; i
++) {
355 reg
.type
= this->src
[i
].type
;
356 if (!this->src
[i
].equals(reg
))
359 if (i
< this->header_size
) {
360 reg
.offset
+= REG_SIZE
;
362 reg
= horiz_offset(reg
, this->exec_size
);
370 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
)
372 if (devinfo
->gen
== 6 && is_math())
375 if (is_send_from_grf())
378 if (!backend_instruction::can_do_source_mods())
385 fs_inst::can_change_types() const
387 return dst
.type
== src
[0].type
&&
388 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
389 (opcode
== BRW_OPCODE_MOV
||
390 (opcode
== BRW_OPCODE_SEL
&&
391 dst
.type
== src
[1].type
&&
392 predicate
!= BRW_PREDICATE_NONE
&&
393 !src
[1].abs
&& !src
[1].negate
));
399 memset(this, 0, sizeof(*this));
400 type
= BRW_REGISTER_TYPE_UD
;
404 /** Generic unset register constructor. */
408 this->file
= BAD_FILE
;
411 fs_reg::fs_reg(struct ::brw_reg reg
) :
416 if (this->file
== IMM
&&
417 (this->type
!= BRW_REGISTER_TYPE_V
&&
418 this->type
!= BRW_REGISTER_TYPE_UV
&&
419 this->type
!= BRW_REGISTER_TYPE_VF
)) {
425 fs_reg::equals(const fs_reg
&r
) const
427 return (this->backend_reg::equals(r
) &&
432 fs_reg::is_contiguous() const
438 fs_reg::component_size(unsigned width
) const
440 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
443 return MAX2(width
* stride
, 1) * type_sz(type
);
447 type_size_scalar(const struct glsl_type
*type
)
449 unsigned int size
, i
;
451 switch (type
->base_type
) {
454 case GLSL_TYPE_FLOAT
:
456 return type
->components();
457 case GLSL_TYPE_DOUBLE
:
458 case GLSL_TYPE_UINT64
:
459 case GLSL_TYPE_INT64
:
460 return type
->components() * 2;
461 case GLSL_TYPE_ARRAY
:
462 return type_size_scalar(type
->fields
.array
) * type
->length
;
463 case GLSL_TYPE_STRUCT
:
465 for (i
= 0; i
< type
->length
; i
++) {
466 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
469 case GLSL_TYPE_SAMPLER
:
470 /* Samplers take up no register space, since they're baked in at
474 case GLSL_TYPE_ATOMIC_UINT
:
476 case GLSL_TYPE_SUBROUTINE
:
478 case GLSL_TYPE_IMAGE
:
479 return BRW_IMAGE_PARAM_SIZE
;
481 case GLSL_TYPE_ERROR
:
482 case GLSL_TYPE_INTERFACE
:
483 case GLSL_TYPE_FUNCTION
:
484 unreachable("not reached");
491 * Create a MOV to read the timestamp register.
493 * The caller is responsible for emitting the MOV. The return value is
494 * the destination of the MOV, with extra parameters set.
497 fs_visitor::get_timestamp(const fs_builder
&bld
)
499 assert(devinfo
->gen
>= 7);
501 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
504 BRW_REGISTER_TYPE_UD
));
506 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
508 /* We want to read the 3 fields we care about even if it's not enabled in
511 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
517 fs_visitor::emit_shader_time_begin()
519 /* We want only the low 32 bits of the timestamp. Since it's running
520 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
521 * which is plenty of time for our purposes. It is identical across the
522 * EUs, but since it's tracking GPU core speed it will increment at a
523 * varying rate as render P-states change.
525 shader_start_time
= component(
526 get_timestamp(bld
.annotate("shader time start")), 0);
530 fs_visitor::emit_shader_time_end()
532 /* Insert our code just before the final SEND with EOT. */
533 exec_node
*end
= this->instructions
.get_tail();
534 assert(end
&& ((fs_inst
*) end
)->eot
);
535 const fs_builder ibld
= bld
.annotate("shader time end")
536 .exec_all().at(NULL
, end
);
537 const fs_reg timestamp
= get_timestamp(ibld
);
539 /* We only use the low 32 bits of the timestamp - see
540 * emit_shader_time_begin()).
542 * We could also check if render P-states have changed (or anything
543 * else that might disrupt timing) by setting smear to 2 and checking if
544 * that field is != 0.
546 const fs_reg shader_end_time
= component(timestamp
, 0);
548 /* Check that there weren't any timestamp reset events (assuming these
549 * were the only two timestamp reads that happened).
551 const fs_reg reset
= component(timestamp
, 2);
552 set_condmod(BRW_CONDITIONAL_Z
,
553 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
554 ibld
.IF(BRW_PREDICATE_NORMAL
);
556 fs_reg start
= shader_start_time
;
558 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
559 BRW_REGISTER_TYPE_UD
),
561 const fs_builder cbld
= ibld
.group(1, 0);
562 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
564 /* If there were no instructions between the two timestamp gets, the diff
565 * is 2 cycles. Remove that overhead, so I can forget about that when
566 * trying to determine the time taken for single instructions.
568 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
569 SHADER_TIME_ADD(cbld
, 0, diff
);
570 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
571 ibld
.emit(BRW_OPCODE_ELSE
);
572 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
573 ibld
.emit(BRW_OPCODE_ENDIF
);
577 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
578 int shader_time_subindex
,
581 int index
= shader_time_index
* 3 + shader_time_subindex
;
582 struct brw_reg offset
= brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
);
585 if (dispatch_width
== 8)
586 payload
= vgrf(glsl_type::uvec2_type
);
588 payload
= vgrf(glsl_type::uint_type
);
590 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
594 fs_visitor::vfail(const char *format
, va_list va
)
603 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
604 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
606 this->fail_msg
= msg
;
609 fprintf(stderr
, "%s", msg
);
614 fs_visitor::fail(const char *format
, ...)
618 va_start(va
, format
);
624 * Mark this program as impossible to compile with dispatch width greater
627 * During the SIMD8 compile (which happens first), we can detect and flag
628 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
629 * SIMD16+ compile altogether.
631 * During a compile of dispatch width greater than n (if one happens anyway),
632 * this just calls fail().
635 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
637 if (dispatch_width
> n
) {
640 max_dispatch_width
= n
;
641 compiler
->shader_perf_log(log_data
,
642 "Shader dispatch width limited to SIMD%d: %s",
648 * Returns true if the instruction has a flag that means it won't
649 * update an entire destination register.
651 * For example, dead code elimination and live variable analysis want to know
652 * when a write to a variable screens off any preceding values that were in
656 fs_inst::is_partial_write() const
658 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
659 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
660 !this->dst
.is_contiguous() ||
661 this->dst
.offset
% REG_SIZE
!= 0);
665 fs_inst::components_read(unsigned i
) const
667 /* Return zero if the source is not present. */
668 if (src
[i
].file
== BAD_FILE
)
672 case FS_OPCODE_LINTERP
:
678 case FS_OPCODE_PIXEL_X
:
679 case FS_OPCODE_PIXEL_Y
:
683 case FS_OPCODE_FB_WRITE_LOGICAL
:
684 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
685 /* First/second FB write color. */
687 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
691 case SHADER_OPCODE_TEX_LOGICAL
:
692 case SHADER_OPCODE_TXD_LOGICAL
:
693 case SHADER_OPCODE_TXF_LOGICAL
:
694 case SHADER_OPCODE_TXL_LOGICAL
:
695 case SHADER_OPCODE_TXS_LOGICAL
:
696 case FS_OPCODE_TXB_LOGICAL
:
697 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
698 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
699 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
700 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
701 case SHADER_OPCODE_LOD_LOGICAL
:
702 case SHADER_OPCODE_TG4_LOGICAL
:
703 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
704 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
705 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
706 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
707 /* Texture coordinates. */
708 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
709 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
710 /* Texture derivatives. */
711 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
712 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
713 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
714 /* Texture offset. */
715 else if (i
== TEX_LOGICAL_SRC_TG4_OFFSET
)
718 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
723 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
724 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
725 assert(src
[3].file
== IMM
);
726 /* Surface coordinates. */
729 /* Surface operation source (ignored for reads). */
735 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
736 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
737 assert(src
[3].file
== IMM
&&
739 /* Surface coordinates. */
742 /* Surface operation source. */
748 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
749 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
750 assert(src
[3].file
== IMM
&&
752 const unsigned op
= src
[4].ud
;
753 /* Surface coordinates. */
756 /* Surface operation source. */
757 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
759 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
760 op
== BRW_AOP_PREDEC
))
772 fs_inst::size_read(int arg
) const
775 case FS_OPCODE_FB_WRITE
:
776 case FS_OPCODE_FB_READ
:
777 case SHADER_OPCODE_URB_WRITE_SIMD8
:
778 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
779 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
780 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
781 case SHADER_OPCODE_URB_READ_SIMD8
:
782 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
783 case SHADER_OPCODE_UNTYPED_ATOMIC
:
784 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
785 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
786 case SHADER_OPCODE_TYPED_ATOMIC
:
787 case SHADER_OPCODE_TYPED_SURFACE_READ
:
788 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
789 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
791 return mlen
* REG_SIZE
;
794 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
795 /* The payload is actually stored in src1 */
797 return mlen
* REG_SIZE
;
800 case FS_OPCODE_LINTERP
:
805 case SHADER_OPCODE_LOAD_PAYLOAD
:
806 if (arg
< this->header_size
)
810 case CS_OPCODE_CS_TERMINATE
:
811 case SHADER_OPCODE_BARRIER
:
814 case SHADER_OPCODE_MOV_INDIRECT
:
816 assert(src
[2].file
== IMM
);
822 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
823 return mlen
* REG_SIZE
;
827 switch (src
[arg
].file
) {
830 return components_read(arg
) * type_sz(src
[arg
].type
);
836 return components_read(arg
) * src
[arg
].component_size(exec_size
);
838 unreachable("MRF registers are not allowed as sources");
844 /* Return the subset of flag registers that an instruction could
845 * potentially read or write based on the execution controls and flag
846 * subregister number of the instruction.
849 flag_mask(const fs_inst
*inst
)
851 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
852 const unsigned end
= start
+ inst
->exec_size
;
853 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
859 return (n
>= CHAR_BIT
* sizeof(bit_mask(n
)) ? ~0u : (1u << n
) - 1);
863 flag_mask(const fs_reg
&r
, unsigned sz
)
866 const unsigned start
= (r
.nr
- BRW_ARF_FLAG
) * 4 + r
.subnr
;
867 const unsigned end
= start
+ sz
;
868 return bit_mask(end
) & ~bit_mask(start
);
876 fs_inst::flags_read(const gen_device_info
*devinfo
) const
878 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
879 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
880 /* The vertical predication modes combine corresponding bits from
881 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
883 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
884 return flag_mask(this) << shift
| flag_mask(this);
885 } else if (predicate
) {
886 return flag_mask(this);
889 for (int i
= 0; i
< sources
; i
++) {
890 mask
|= flag_mask(src
[i
], size_read(i
));
897 fs_inst::flags_written() const
899 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
900 opcode
!= BRW_OPCODE_IF
&&
901 opcode
!= BRW_OPCODE_WHILE
)) ||
902 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
903 return flag_mask(this);
905 return flag_mask(dst
, size_written
);
910 * Returns how many MRFs an FS opcode will write over.
912 * Note that this is not the 0 or 1 implied writes in an actual gen
913 * instruction -- the FS opcodes often generate MOVs in addition.
916 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
921 if (inst
->base_mrf
== -1)
924 switch (inst
->opcode
) {
925 case SHADER_OPCODE_RCP
:
926 case SHADER_OPCODE_RSQ
:
927 case SHADER_OPCODE_SQRT
:
928 case SHADER_OPCODE_EXP2
:
929 case SHADER_OPCODE_LOG2
:
930 case SHADER_OPCODE_SIN
:
931 case SHADER_OPCODE_COS
:
932 return 1 * dispatch_width
/ 8;
933 case SHADER_OPCODE_POW
:
934 case SHADER_OPCODE_INT_QUOTIENT
:
935 case SHADER_OPCODE_INT_REMAINDER
:
936 return 2 * dispatch_width
/ 8;
937 case SHADER_OPCODE_TEX
:
939 case SHADER_OPCODE_TXD
:
940 case SHADER_OPCODE_TXF
:
941 case SHADER_OPCODE_TXF_CMS
:
942 case SHADER_OPCODE_TXF_MCS
:
943 case SHADER_OPCODE_TG4
:
944 case SHADER_OPCODE_TG4_OFFSET
:
945 case SHADER_OPCODE_TXL
:
946 case SHADER_OPCODE_TXS
:
947 case SHADER_OPCODE_LOD
:
948 case SHADER_OPCODE_SAMPLEINFO
:
950 case FS_OPCODE_FB_WRITE
:
952 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
953 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
955 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
957 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
960 unreachable("not reached");
965 fs_visitor::vgrf(const glsl_type
*const type
)
967 int reg_width
= dispatch_width
/ 8;
968 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
969 brw_type_for_base_type(type
));
972 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
977 this->type
= BRW_REGISTER_TYPE_F
;
978 this->stride
= (file
== UNIFORM
? 0 : 1);
981 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
987 this->stride
= (file
== UNIFORM
? 0 : 1);
990 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
991 * This brings in those uniform definitions
994 fs_visitor::import_uniforms(fs_visitor
*v
)
996 this->push_constant_loc
= v
->push_constant_loc
;
997 this->pull_constant_loc
= v
->pull_constant_loc
;
998 this->uniforms
= v
->uniforms
;
1002 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1004 assert(stage
== MESA_SHADER_FRAGMENT
);
1006 /* gl_FragCoord.x */
1007 bld
.MOV(wpos
, this->pixel_x
);
1008 wpos
= offset(wpos
, bld
, 1);
1010 /* gl_FragCoord.y */
1011 bld
.MOV(wpos
, this->pixel_y
);
1012 wpos
= offset(wpos
, bld
, 1);
1014 /* gl_FragCoord.z */
1015 if (devinfo
->gen
>= 6) {
1016 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1018 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1019 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1020 interp_reg(VARYING_SLOT_POS
, 2));
1022 wpos
= offset(wpos
, bld
, 1);
1024 /* gl_FragCoord.w: Already set up in emit_interpolation */
1025 bld
.MOV(wpos
, this->wpos_w
);
1028 enum brw_barycentric_mode
1029 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1031 /* Barycentric modes don't make sense for flat inputs. */
1032 assert(mode
!= INTERP_MODE_FLAT
);
1036 case nir_intrinsic_load_barycentric_pixel
:
1037 case nir_intrinsic_load_barycentric_at_offset
:
1038 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1040 case nir_intrinsic_load_barycentric_centroid
:
1041 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1043 case nir_intrinsic_load_barycentric_sample
:
1044 case nir_intrinsic_load_barycentric_at_sample
:
1045 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1048 unreachable("invalid intrinsic");
1051 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1054 return (enum brw_barycentric_mode
) bary
;
1058 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1060 static enum brw_barycentric_mode
1061 centroid_to_pixel(enum brw_barycentric_mode bary
)
1063 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1064 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1065 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1069 fs_visitor::emit_frontfacing_interpolation()
1071 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1073 if (devinfo
->gen
>= 6) {
1074 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1075 * a boolean result from this (~0/true or 0/false).
1077 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1078 * this task in only one instruction:
1079 * - a negation source modifier will flip the bit; and
1080 * - a W -> D type conversion will sign extend the bit into the high
1081 * word of the destination.
1083 * An ASR 15 fills the low word of the destination.
1085 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1088 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1090 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1091 * a boolean result from this (1/true or 0/false).
1093 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1094 * the negation source modifier to flip it. Unfortunately the SHR
1095 * instruction only operates on UD (or D with an abs source modifier)
1096 * sources without negation.
1098 * Instead, use ASR (which will give ~0/true or 0/false).
1100 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1103 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1110 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1112 assert(stage
== MESA_SHADER_FRAGMENT
);
1113 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1114 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1116 if (wm_prog_data
->persample_dispatch
) {
1117 /* Convert int_sample_pos to floating point */
1118 bld
.MOV(dst
, int_sample_pos
);
1119 /* Scale to the range [0, 1] */
1120 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1123 /* From ARB_sample_shading specification:
1124 * "When rendering to a non-multisample buffer, or if multisample
1125 * rasterization is disabled, gl_SamplePosition will always be
1128 bld
.MOV(dst
, brw_imm_f(0.5f
));
1133 fs_visitor::emit_samplepos_setup()
1135 assert(devinfo
->gen
>= 6);
1137 const fs_builder abld
= bld
.annotate("compute sample position");
1138 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1140 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1141 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1143 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1144 * mode will be enabled.
1146 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1147 * R31.1:0 Position Offset X/Y for Slot[3:0]
1148 * R31.3:2 Position Offset X/Y for Slot[7:4]
1151 * The X, Y sample positions come in as bytes in thread payload. So, read
1152 * the positions using vstride=16, width=8, hstride=2.
1154 struct brw_reg sample_pos_reg
=
1155 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1156 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1158 if (dispatch_width
== 8) {
1159 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1161 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1162 abld
.half(1).MOV(half(int_sample_x
, 1),
1163 fs_reg(suboffset(sample_pos_reg
, 16)));
1165 /* Compute gl_SamplePosition.x */
1166 compute_sample_position(pos
, int_sample_x
);
1167 pos
= offset(pos
, abld
, 1);
1168 if (dispatch_width
== 8) {
1169 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1171 abld
.half(0).MOV(half(int_sample_y
, 0),
1172 fs_reg(suboffset(sample_pos_reg
, 1)));
1173 abld
.half(1).MOV(half(int_sample_y
, 1),
1174 fs_reg(suboffset(sample_pos_reg
, 17)));
1176 /* Compute gl_SamplePosition.y */
1177 compute_sample_position(pos
, int_sample_y
);
1182 fs_visitor::emit_sampleid_setup()
1184 assert(stage
== MESA_SHADER_FRAGMENT
);
1185 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1186 assert(devinfo
->gen
>= 6);
1188 const fs_builder abld
= bld
.annotate("compute sample id");
1189 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1191 if (!key
->multisample_fbo
) {
1192 /* As per GL_ARB_sample_shading specification:
1193 * "When rendering to a non-multisample buffer, or if multisample
1194 * rasterization is disabled, gl_SampleID will always be zero."
1196 abld
.MOV(*reg
, brw_imm_d(0));
1197 } else if (devinfo
->gen
>= 8) {
1198 /* Sample ID comes in as 4-bit numbers in g1.0:
1200 * 15:12 Slot 3 SampleID (only used in SIMD16)
1201 * 11:8 Slot 2 SampleID (only used in SIMD16)
1202 * 7:4 Slot 1 SampleID
1203 * 3:0 Slot 0 SampleID
1205 * Each slot corresponds to four channels, so we want to replicate each
1206 * half-byte value to 4 channels in a row:
1208 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1209 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1211 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1212 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1214 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1215 * channels to read the first byte (7:0), and the second group of 8
1216 * channels to read the second byte (15:8). Then, we shift right by
1217 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1218 * values into place. Finally, we AND with 0xf to keep the low nibble.
1220 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1221 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1223 * TODO: These payload bits exist on Gen7 too, but they appear to always
1224 * be zero, so this code fails to work. We should find out why.
1226 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1228 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1229 BRW_REGISTER_TYPE_B
), 1, 8, 0)),
1230 brw_imm_v(0x44440000));
1231 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1233 const fs_reg t1
= component(fs_reg(VGRF
, alloc
.allocate(1),
1234 BRW_REGISTER_TYPE_D
), 0);
1235 const fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1237 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1238 * 8x multisampling, subspan 0 will represent sample N (where N
1239 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1240 * 7. We can find the value of N by looking at R0.0 bits 7:6
1241 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1242 * (since samples are always delivered in pairs). That is, we
1243 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1244 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1245 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1246 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1247 * populating a temporary variable with the sequence (0, 1, 2, 3),
1248 * and then reading from it using vstride=1, width=4, hstride=0.
1249 * These computations hold good for 4x multisampling as well.
1251 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1252 * the first four slots are sample 0 of subspan 0; the next four
1253 * are sample 1 of subspan 0; the third group is sample 0 of
1254 * subspan 1, and finally sample 1 of subspan 1.
1257 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1258 * accomodate 16x MSAA.
1260 abld
.exec_all().group(1, 0)
1261 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1263 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1265 /* This works for both SIMD8 and SIMD16 */
1266 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1268 /* This special instruction takes care of setting vstride=1,
1269 * width=4, hstride=0 of t2 during an ADD instruction.
1271 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1278 fs_visitor::emit_samplemaskin_setup()
1280 assert(stage
== MESA_SHADER_FRAGMENT
);
1281 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1282 assert(devinfo
->gen
>= 6);
1284 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1286 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1287 BRW_REGISTER_TYPE_D
));
1289 if (wm_prog_data
->persample_dispatch
) {
1290 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1291 * and a mask representing which sample is being processed by the
1292 * current shader invocation.
1294 * From the OES_sample_variables specification:
1295 * "When per-sample shading is active due to the use of a fragment input
1296 * qualified by "sample" or due to the use of the gl_SampleID or
1297 * gl_SamplePosition variables, only the bit for the current sample is
1298 * set in gl_SampleMaskIn."
1300 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1302 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1303 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1305 fs_reg one
= vgrf(glsl_type::int_type
);
1306 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1307 abld
.MOV(one
, brw_imm_d(1));
1308 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1309 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1311 /* In per-pixel mode, the coverage mask is sufficient. */
1312 *reg
= coverage_mask
;
1318 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1320 if (!src
.abs
&& !src
.negate
)
1323 fs_reg temp
= bld
.vgrf(src
.type
);
1330 fs_visitor::emit_discard_jump()
1332 assert(brw_wm_prog_data(this->prog_data
)->uses_kill
);
1334 /* For performance, after a discard, jump to the end of the
1335 * shader if all relevant channels have been discarded.
1337 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1338 discard_jump
->flag_subreg
= 1;
1340 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1341 discard_jump
->predicate_inverse
= true;
1345 fs_visitor::emit_gs_thread_end()
1347 assert(stage
== MESA_SHADER_GEOMETRY
);
1349 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1351 if (gs_compile
->control_data_header_size_bits
> 0) {
1352 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1355 const fs_builder abld
= bld
.annotate("thread end");
1358 if (gs_prog_data
->static_vertex_count
!= -1) {
1359 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1360 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1361 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1362 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1363 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1366 /* Delete now dead instructions. */
1367 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1373 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1377 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1378 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1379 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1382 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1383 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1384 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1385 sources
[1] = this->final_gs_vertex_count
;
1386 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1387 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1395 fs_visitor::assign_curb_setup()
1397 unsigned uniform_push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
1399 unsigned ubo_push_length
= 0;
1400 unsigned ubo_push_start
[4];
1401 for (int i
= 0; i
< 4; i
++) {
1402 ubo_push_start
[i
] = 8 * (ubo_push_length
+ uniform_push_length
);
1403 ubo_push_length
+= stage_prog_data
->ubo_ranges
[i
].length
;
1406 prog_data
->curb_read_length
= uniform_push_length
+ ubo_push_length
;
1408 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1409 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1410 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1411 if (inst
->src
[i
].file
== UNIFORM
) {
1412 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1414 if (inst
->src
[i
].nr
>= UBO_START
) {
1415 /* constant_nr is in 32-bit units, the rest are in bytes */
1416 constant_nr
= ubo_push_start
[inst
->src
[i
].nr
- UBO_START
] +
1417 inst
->src
[i
].offset
/ 4;
1418 } else if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1419 constant_nr
= push_constant_loc
[uniform_nr
];
1421 /* Section 5.11 of the OpenGL 4.1 spec says:
1422 * "Out-of-bounds reads return undefined values, which include
1423 * values from other variables of the active program or zero."
1424 * Just return the first push constant.
1429 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1432 brw_reg
.abs
= inst
->src
[i
].abs
;
1433 brw_reg
.negate
= inst
->src
[i
].negate
;
1435 assert(inst
->src
[i
].stride
== 0);
1436 inst
->src
[i
] = byte_offset(
1437 retype(brw_reg
, inst
->src
[i
].type
),
1438 inst
->src
[i
].offset
% 4);
1443 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1444 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1448 fs_visitor::calculate_urb_setup()
1450 assert(stage
== MESA_SHADER_FRAGMENT
);
1451 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1452 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1454 memset(prog_data
->urb_setup
, -1,
1455 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1458 /* Figure out where each of the incoming setup attributes lands. */
1459 if (devinfo
->gen
>= 6) {
1460 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1461 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1462 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1463 * first 16 varying inputs, so we can put them wherever we want.
1464 * Just put them in order.
1466 * This is useful because it means that (a) inputs not used by the
1467 * fragment shader won't take up valuable register space, and (b) we
1468 * won't have to recompile the fragment shader if it gets paired with
1469 * a different vertex (or geometry) shader.
1471 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1472 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1473 BITFIELD64_BIT(i
)) {
1474 prog_data
->urb_setup
[i
] = urb_next
++;
1478 /* We have enough input varyings that the SF/SBE pipeline stage can't
1479 * arbitrarily rearrange them to suit our whim; we have to put them
1480 * in an order that matches the output of the previous pipeline stage
1481 * (geometry or vertex shader).
1483 struct brw_vue_map prev_stage_vue_map
;
1484 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1485 key
->input_slots_valid
,
1486 nir
->info
.separate_shader
);
1489 brw_compute_first_urb_slot_required(nir
->info
.inputs_read
,
1490 &prev_stage_vue_map
);
1492 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1493 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1495 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1496 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1497 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1498 BITFIELD64_BIT(varying
))) {
1499 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1502 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1505 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1506 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1507 /* Point size is packed into the header, not as a general attribute */
1508 if (i
== VARYING_SLOT_PSIZ
)
1511 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1512 /* The back color slot is skipped when the front color is
1513 * also written to. In addition, some slots can be
1514 * written in the vertex shader and not read in the
1515 * fragment shader. So the register number must always be
1516 * incremented, mapped or not.
1518 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1519 prog_data
->urb_setup
[i
] = urb_next
;
1525 * It's a FS only attribute, and we did interpolation for this attribute
1526 * in SF thread. So, count it here, too.
1528 * See compile_sf_prog() for more info.
1530 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1531 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1534 prog_data
->num_varying_inputs
= urb_next
;
1538 fs_visitor::assign_urb_setup()
1540 assert(stage
== MESA_SHADER_FRAGMENT
);
1541 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1543 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1545 /* Offset all the urb_setup[] index by the actual position of the
1546 * setup regs, now that the location of the constants has been chosen.
1548 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1549 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1550 assert(inst
->src
[1].file
== FIXED_GRF
);
1551 inst
->src
[1].nr
+= urb_start
;
1554 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1555 assert(inst
->src
[0].file
== FIXED_GRF
);
1556 inst
->src
[0].nr
+= urb_start
;
1560 /* Each attribute is 4 setup channels, each of which is half a reg. */
1561 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1565 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1567 for (int i
= 0; i
< inst
->sources
; i
++) {
1568 if (inst
->src
[i
].file
== ATTR
) {
1569 int grf
= payload
.num_regs
+
1570 prog_data
->curb_read_length
+
1572 inst
->src
[i
].offset
/ REG_SIZE
;
1574 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1576 * VertStride must be used to cross GRF register boundaries. This
1577 * rule implies that elements within a 'Width' cannot cross GRF
1580 * So, for registers that are large enough, we have to split the exec
1581 * size in two and trust the compression state to sort it out.
1583 unsigned total_size
= inst
->exec_size
*
1584 inst
->src
[i
].stride
*
1585 type_sz(inst
->src
[i
].type
);
1587 assert(total_size
<= 2 * REG_SIZE
);
1588 const unsigned exec_size
=
1589 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1591 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1592 struct brw_reg reg
=
1593 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1594 inst
->src
[i
].offset
% REG_SIZE
),
1595 exec_size
* inst
->src
[i
].stride
,
1596 width
, inst
->src
[i
].stride
);
1597 reg
.abs
= inst
->src
[i
].abs
;
1598 reg
.negate
= inst
->src
[i
].negate
;
1606 fs_visitor::assign_vs_urb_setup()
1608 struct brw_vs_prog_data
*vs_prog_data
= brw_vs_prog_data(prog_data
);
1610 assert(stage
== MESA_SHADER_VERTEX
);
1612 /* Each attribute is 4 regs. */
1613 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1615 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1617 /* Rewrite all ATTR file references to the hw grf that they land in. */
1618 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1619 convert_attr_sources_to_hw_regs(inst
);
1624 fs_visitor::assign_tcs_single_patch_urb_setup()
1626 assert(stage
== MESA_SHADER_TESS_CTRL
);
1628 /* Rewrite all ATTR file references to HW_REGs. */
1629 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1630 convert_attr_sources_to_hw_regs(inst
);
1635 fs_visitor::assign_tes_urb_setup()
1637 assert(stage
== MESA_SHADER_TESS_EVAL
);
1639 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1641 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1643 /* Rewrite all ATTR file references to HW_REGs. */
1644 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1645 convert_attr_sources_to_hw_regs(inst
);
1650 fs_visitor::assign_gs_urb_setup()
1652 assert(stage
== MESA_SHADER_GEOMETRY
);
1654 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1656 first_non_payload_grf
+=
1657 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1659 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1660 /* Rewrite all ATTR file references to GRFs. */
1661 convert_attr_sources_to_hw_regs(inst
);
1667 * Split large virtual GRFs into separate components if we can.
1669 * This is mostly duplicated with what brw_fs_vector_splitting does,
1670 * but that's really conservative because it's afraid of doing
1671 * splitting that doesn't result in real progress after the rest of
1672 * the optimization phases, which would cause infinite looping in
1673 * optimization. We can do it once here, safely. This also has the
1674 * opportunity to split interpolated values, or maybe even uniforms,
1675 * which we don't have at the IR level.
1677 * We want to split, because virtual GRFs are what we register
1678 * allocate and spill (due to contiguousness requirements for some
1679 * instructions), and they're what we naturally generate in the
1680 * codegen process, but most virtual GRFs don't actually need to be
1681 * contiguous sets of GRFs. If we split, we'll end up with reduced
1682 * live intervals and better dead code elimination and coalescing.
1685 fs_visitor::split_virtual_grfs()
1687 /* Compact the register file so we eliminate dead vgrfs. This
1688 * only defines split points for live registers, so if we have
1689 * too large dead registers they will hit assertions later.
1691 compact_virtual_grfs();
1693 int num_vars
= this->alloc
.count
;
1695 /* Count the total number of registers */
1697 int vgrf_to_reg
[num_vars
];
1698 for (int i
= 0; i
< num_vars
; i
++) {
1699 vgrf_to_reg
[i
] = reg_count
;
1700 reg_count
+= alloc
.sizes
[i
];
1703 /* An array of "split points". For each register slot, this indicates
1704 * if this slot can be separated from the previous slot. Every time an
1705 * instruction uses multiple elements of a register (as a source or
1706 * destination), we mark the used slots as inseparable. Then we go
1707 * through and split the registers into the smallest pieces we can.
1709 bool split_points
[reg_count
];
1710 memset(split_points
, 0, sizeof(split_points
));
1712 /* Mark all used registers as fully splittable */
1713 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1714 if (inst
->dst
.file
== VGRF
) {
1715 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1716 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1717 split_points
[reg
+ j
] = true;
1720 for (int i
= 0; i
< inst
->sources
; i
++) {
1721 if (inst
->src
[i
].file
== VGRF
) {
1722 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1723 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1724 split_points
[reg
+ j
] = true;
1729 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1730 if (inst
->dst
.file
== VGRF
) {
1731 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1732 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1733 split_points
[reg
+ j
] = false;
1735 for (int i
= 0; i
< inst
->sources
; i
++) {
1736 if (inst
->src
[i
].file
== VGRF
) {
1737 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1738 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1739 split_points
[reg
+ j
] = false;
1744 int new_virtual_grf
[reg_count
];
1745 int new_reg_offset
[reg_count
];
1748 for (int i
= 0; i
< num_vars
; i
++) {
1749 /* The first one should always be 0 as a quick sanity check. */
1750 assert(split_points
[reg
] == false);
1753 new_reg_offset
[reg
] = 0;
1758 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1759 /* If this is a split point, reset the offset to 0 and allocate a
1760 * new virtual GRF for the previous offset many registers
1762 if (split_points
[reg
]) {
1763 assert(offset
<= MAX_VGRF_SIZE
);
1764 int grf
= alloc
.allocate(offset
);
1765 for (int k
= reg
- offset
; k
< reg
; k
++)
1766 new_virtual_grf
[k
] = grf
;
1769 new_reg_offset
[reg
] = offset
;
1774 /* The last one gets the original register number */
1775 assert(offset
<= MAX_VGRF_SIZE
);
1776 alloc
.sizes
[i
] = offset
;
1777 for (int k
= reg
- offset
; k
< reg
; k
++)
1778 new_virtual_grf
[k
] = i
;
1780 assert(reg
== reg_count
);
1782 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1783 if (inst
->dst
.file
== VGRF
) {
1784 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1785 inst
->dst
.nr
= new_virtual_grf
[reg
];
1786 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
1787 inst
->dst
.offset
% REG_SIZE
;
1788 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1790 for (int i
= 0; i
< inst
->sources
; i
++) {
1791 if (inst
->src
[i
].file
== VGRF
) {
1792 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1793 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1794 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
1795 inst
->src
[i
].offset
% REG_SIZE
;
1796 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1800 invalidate_live_intervals();
1804 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1806 * During code generation, we create tons of temporary variables, many of
1807 * which get immediately killed and are never used again. Yet, in later
1808 * optimization and analysis passes, such as compute_live_intervals, we need
1809 * to loop over all the virtual GRFs. Compacting them can save a lot of
1813 fs_visitor::compact_virtual_grfs()
1815 bool progress
= false;
1816 int remap_table
[this->alloc
.count
];
1817 memset(remap_table
, -1, sizeof(remap_table
));
1819 /* Mark which virtual GRFs are used. */
1820 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1821 if (inst
->dst
.file
== VGRF
)
1822 remap_table
[inst
->dst
.nr
] = 0;
1824 for (int i
= 0; i
< inst
->sources
; i
++) {
1825 if (inst
->src
[i
].file
== VGRF
)
1826 remap_table
[inst
->src
[i
].nr
] = 0;
1830 /* Compact the GRF arrays. */
1832 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1833 if (remap_table
[i
] == -1) {
1834 /* We just found an unused register. This means that we are
1835 * actually going to compact something.
1839 remap_table
[i
] = new_index
;
1840 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1841 invalidate_live_intervals();
1846 this->alloc
.count
= new_index
;
1848 /* Patch all the instructions to use the newly renumbered registers */
1849 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1850 if (inst
->dst
.file
== VGRF
)
1851 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1853 for (int i
= 0; i
< inst
->sources
; i
++) {
1854 if (inst
->src
[i
].file
== VGRF
)
1855 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1859 /* Patch all the references to delta_xy, since they're used in register
1860 * allocation. If they're unused, switch them to BAD_FILE so we don't
1861 * think some random VGRF is delta_xy.
1863 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1864 if (delta_xy
[i
].file
== VGRF
) {
1865 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1866 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1868 delta_xy
[i
].file
= BAD_FILE
;
1877 set_push_pull_constant_loc(unsigned uniform
, int *chunk_start
,
1878 unsigned *max_chunk_bitsize
,
1879 bool contiguous
, unsigned bitsize
,
1880 const unsigned target_bitsize
,
1881 int *push_constant_loc
, int *pull_constant_loc
,
1882 unsigned *num_push_constants
,
1883 unsigned *num_pull_constants
,
1884 const unsigned max_push_components
,
1885 const unsigned max_chunk_size
,
1886 bool allow_pull_constants
,
1887 struct brw_stage_prog_data
*stage_prog_data
)
1889 /* This is the first live uniform in the chunk */
1890 if (*chunk_start
< 0)
1891 *chunk_start
= uniform
;
1893 /* Keep track of the maximum bit size access in contiguous uniforms */
1894 *max_chunk_bitsize
= MAX2(*max_chunk_bitsize
, bitsize
);
1896 /* If this element does not need to be contiguous with the next, we
1897 * split at this point and everything between chunk_start and u forms a
1901 /* If bitsize doesn't match the target one, skip it */
1902 if (*max_chunk_bitsize
!= target_bitsize
) {
1903 /* FIXME: right now we only support 32 and 64-bit accesses */
1904 assert(*max_chunk_bitsize
== 4 || *max_chunk_bitsize
== 8);
1905 *max_chunk_bitsize
= 0;
1910 unsigned chunk_size
= uniform
- *chunk_start
+ 1;
1912 /* Decide whether we should push or pull this parameter. In the
1913 * Vulkan driver, push constants are explicitly exposed via the API
1914 * so we push everything. In GL, we only push small arrays.
1916 if (!allow_pull_constants
||
1917 (*num_push_constants
+ chunk_size
<= max_push_components
&&
1918 chunk_size
<= max_chunk_size
)) {
1919 assert(*num_push_constants
+ chunk_size
<= max_push_components
);
1920 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1921 push_constant_loc
[j
] = (*num_push_constants
)++;
1923 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1924 pull_constant_loc
[j
] = (*num_pull_constants
)++;
1927 *max_chunk_bitsize
= 0;
1933 get_thread_local_id_param_index(const brw_stage_prog_data
*prog_data
)
1935 if (prog_data
->nr_params
== 0)
1938 /* The local thread id is always the last parameter in the list */
1939 uint32_t last_param
= prog_data
->param
[prog_data
->nr_params
- 1];
1940 if (last_param
== BRW_PARAM_BUILTIN_THREAD_LOCAL_ID
)
1941 return prog_data
->nr_params
- 1;
1947 * Assign UNIFORM file registers to either push constants or pull constants.
1949 * We allow a fragment shader to have more than the specified minimum
1950 * maximum number of fragment shader uniform components (64). If
1951 * there are too many of these, they'd fill up all of register space.
1952 * So, this will push some of them out to the pull constant buffer and
1953 * update the program to load them.
1956 fs_visitor::assign_constant_locations()
1958 /* Only the first compile gets to decide on locations. */
1959 if (push_constant_loc
) {
1960 assert(pull_constant_loc
);
1964 bool is_live
[uniforms
];
1965 memset(is_live
, 0, sizeof(is_live
));
1966 unsigned bitsize_access
[uniforms
];
1967 memset(bitsize_access
, 0, sizeof(bitsize_access
));
1969 /* For each uniform slot, a value of true indicates that the given slot and
1970 * the next slot must remain contiguous. This is used to keep us from
1971 * splitting arrays apart.
1973 bool contiguous
[uniforms
];
1974 memset(contiguous
, 0, sizeof(contiguous
));
1976 /* First, we walk through the instructions and do two things:
1978 * 1) Figure out which uniforms are live.
1980 * 2) Mark any indirectly used ranges of registers as contiguous.
1982 * Note that we don't move constant-indexed accesses to arrays. No
1983 * testing has been done of the performance impact of this choice.
1985 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1986 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1987 if (inst
->src
[i
].file
!= UNIFORM
)
1990 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1992 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
1993 assert(inst
->src
[2].ud
% 4 == 0);
1994 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
1995 assert(last
< uniforms
);
1997 for (unsigned j
= constant_nr
; j
< last
; j
++) {
1999 contiguous
[j
] = true;
2000 bitsize_access
[j
] = MAX2(bitsize_access
[j
], type_sz(inst
->src
[i
].type
));
2002 is_live
[last
] = true;
2003 bitsize_access
[last
] = MAX2(bitsize_access
[last
], type_sz(inst
->src
[i
].type
));
2005 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
) {
2006 int regs_read
= inst
->components_read(i
) *
2007 type_sz(inst
->src
[i
].type
) / 4;
2008 for (int j
= 0; j
< regs_read
; j
++) {
2009 is_live
[constant_nr
+ j
] = true;
2010 bitsize_access
[constant_nr
+ j
] =
2011 MAX2(bitsize_access
[constant_nr
+ j
], type_sz(inst
->src
[i
].type
));
2018 int thread_local_id_index
= get_thread_local_id_param_index(stage_prog_data
);
2020 /* Only allow 16 registers (128 uniform components) as push constants.
2022 * Just demote the end of the list. We could probably do better
2023 * here, demoting things that are rarely used in the program first.
2025 * If changing this value, note the limitation about total_regs in
2028 unsigned int max_push_components
= 16 * 8;
2029 if (thread_local_id_index
>= 0)
2030 max_push_components
--; /* Save a slot for the thread ID */
2032 /* We push small arrays, but no bigger than 16 floats. This is big enough
2033 * for a vec4 but hopefully not large enough to push out other stuff. We
2034 * should probably use a better heuristic at some point.
2036 const unsigned int max_chunk_size
= 16;
2038 unsigned int num_push_constants
= 0;
2039 unsigned int num_pull_constants
= 0;
2041 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2042 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2044 /* Default to -1 meaning no location */
2045 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2046 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2048 int chunk_start
= -1;
2049 unsigned max_chunk_bitsize
= 0;
2051 /* First push 64-bit uniforms to ensure they are properly aligned */
2052 const unsigned uniform_64_bit_size
= type_sz(BRW_REGISTER_TYPE_DF
);
2053 for (unsigned u
= 0; u
< uniforms
; u
++) {
2057 set_push_pull_constant_loc(u
, &chunk_start
, &max_chunk_bitsize
,
2058 contiguous
[u
], bitsize_access
[u
],
2059 uniform_64_bit_size
,
2060 push_constant_loc
, pull_constant_loc
,
2061 &num_push_constants
, &num_pull_constants
,
2062 max_push_components
, max_chunk_size
,
2063 compiler
->supports_pull_constants
,
2068 /* Then push the rest of uniforms */
2069 const unsigned uniform_32_bit_size
= type_sz(BRW_REGISTER_TYPE_F
);
2070 for (unsigned u
= 0; u
< uniforms
; u
++) {
2074 /* Skip thread_local_id_index to put it in the last push register. */
2075 if (thread_local_id_index
== (int)u
)
2078 set_push_pull_constant_loc(u
, &chunk_start
, &max_chunk_bitsize
,
2079 contiguous
[u
], bitsize_access
[u
],
2080 uniform_32_bit_size
,
2081 push_constant_loc
, pull_constant_loc
,
2082 &num_push_constants
, &num_pull_constants
,
2083 max_push_components
, max_chunk_size
,
2084 compiler
->supports_pull_constants
,
2088 /* Add the CS local thread ID uniform at the end of the push constants */
2089 if (thread_local_id_index
>= 0)
2090 push_constant_loc
[thread_local_id_index
] = num_push_constants
++;
2092 /* As the uniforms are going to be reordered, stash the old array and
2093 * create two new arrays for push/pull params.
2095 uint32_t *param
= stage_prog_data
->param
;
2096 stage_prog_data
->nr_params
= num_push_constants
;
2097 if (num_push_constants
) {
2098 stage_prog_data
->param
= ralloc_array(mem_ctx
, uint32_t,
2099 num_push_constants
);
2101 stage_prog_data
->param
= NULL
;
2103 assert(stage_prog_data
->nr_pull_params
== 0);
2104 assert(stage_prog_data
->pull_param
== NULL
);
2105 if (num_pull_constants
> 0) {
2106 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2107 stage_prog_data
->pull_param
= ralloc_array(mem_ctx
, uint32_t,
2108 num_pull_constants
);
2111 /* Now that we know how many regular uniforms we'll push, reduce the
2112 * UBO push ranges so we don't exceed the 3DSTATE_CONSTANT limits.
2114 unsigned push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
2115 for (int i
= 0; i
< 4; i
++) {
2116 struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2118 if (push_length
+ range
->length
> 64)
2119 range
->length
= 64 - push_length
;
2121 push_length
+= range
->length
;
2123 assert(push_length
<= 64);
2125 /* Up until now, the param[] array has been indexed by reg + offset
2126 * of UNIFORM registers. Move pull constants into pull_param[] and
2127 * condense param[] to only contain the uniforms we chose to push.
2129 * NOTE: Because we are condensing the params[] array, we know that
2130 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2131 * having to make a copy.
2133 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2134 uint32_t value
= param
[i
];
2135 if (pull_constant_loc
[i
] != -1) {
2136 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2137 } else if (push_constant_loc
[i
] != -1) {
2138 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2145 fs_visitor::get_pull_locs(const fs_reg
&src
,
2146 unsigned *out_surf_index
,
2147 unsigned *out_pull_index
)
2149 assert(src
.file
== UNIFORM
);
2151 if (src
.nr
>= UBO_START
) {
2152 const struct brw_ubo_range
*range
=
2153 &prog_data
->ubo_ranges
[src
.nr
- UBO_START
];
2155 /* If this access is in our (reduced) range, use the push data. */
2156 if (src
.offset
/ 32 < range
->length
)
2159 *out_surf_index
= prog_data
->binding_table
.ubo_start
+ range
->block
;
2160 *out_pull_index
= (32 * range
->start
+ src
.offset
) / 4;
2164 const unsigned location
= src
.nr
+ src
.offset
/ 4;
2166 if (location
< uniforms
&& pull_constant_loc
[location
] != -1) {
2167 /* A regular uniform push constant */
2168 *out_surf_index
= stage_prog_data
->binding_table
.pull_constants_start
;
2169 *out_pull_index
= pull_constant_loc
[location
];
2177 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2178 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2181 fs_visitor::lower_constant_loads()
2183 unsigned index
, pull_index
;
2185 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2186 /* Set up the annotation tracking for new generated instructions. */
2187 const fs_builder
ibld(this, block
, inst
);
2189 for (int i
= 0; i
< inst
->sources
; i
++) {
2190 if (inst
->src
[i
].file
!= UNIFORM
)
2193 /* We'll handle this case later */
2194 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2197 if (!get_pull_locs(inst
->src
[i
], &index
, &pull_index
))
2200 assert(inst
->src
[i
].stride
== 0);
2202 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
2203 const fs_builder ubld
= ibld
.exec_all().group(block_sz
/ 4, 0);
2204 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
2205 const unsigned base
= pull_index
* 4;
2207 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2208 dst
, brw_imm_ud(index
), brw_imm_ud(base
& ~(block_sz
- 1)));
2210 /* Rewrite the instruction to use the temporary VGRF. */
2211 inst
->src
[i
].file
= VGRF
;
2212 inst
->src
[i
].nr
= dst
.nr
;
2213 inst
->src
[i
].offset
= (base
& (block_sz
- 1)) +
2214 inst
->src
[i
].offset
% 4;
2216 brw_mark_surface_used(prog_data
, index
);
2219 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2220 inst
->src
[0].file
== UNIFORM
) {
2222 if (!get_pull_locs(inst
->src
[0], &index
, &pull_index
))
2225 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2229 inst
->remove(block
);
2231 brw_mark_surface_used(prog_data
, index
);
2234 invalidate_live_intervals();
2238 fs_visitor::opt_algebraic()
2240 bool progress
= false;
2242 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2243 switch (inst
->opcode
) {
2244 case BRW_OPCODE_MOV
:
2245 if (inst
->src
[0].file
!= IMM
)
2248 if (inst
->saturate
) {
2249 if (inst
->dst
.type
!= inst
->src
[0].type
)
2250 assert(!"unimplemented: saturate mixed types");
2252 if (brw_saturate_immediate(inst
->dst
.type
,
2253 &inst
->src
[0].as_brw_reg())) {
2254 inst
->saturate
= false;
2260 case BRW_OPCODE_MUL
:
2261 if (inst
->src
[1].file
!= IMM
)
2265 if (inst
->src
[1].is_one()) {
2266 inst
->opcode
= BRW_OPCODE_MOV
;
2267 inst
->src
[1] = reg_undef
;
2273 if (inst
->src
[1].is_negative_one()) {
2274 inst
->opcode
= BRW_OPCODE_MOV
;
2275 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2276 inst
->src
[1] = reg_undef
;
2282 if (inst
->src
[1].is_zero()) {
2283 inst
->opcode
= BRW_OPCODE_MOV
;
2284 inst
->src
[0] = inst
->src
[1];
2285 inst
->src
[1] = reg_undef
;
2290 if (inst
->src
[0].file
== IMM
) {
2291 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2292 inst
->opcode
= BRW_OPCODE_MOV
;
2293 inst
->src
[0].f
*= inst
->src
[1].f
;
2294 inst
->src
[1] = reg_undef
;
2299 case BRW_OPCODE_ADD
:
2300 if (inst
->src
[1].file
!= IMM
)
2304 if (inst
->src
[1].is_zero()) {
2305 inst
->opcode
= BRW_OPCODE_MOV
;
2306 inst
->src
[1] = reg_undef
;
2311 if (inst
->src
[0].file
== IMM
) {
2312 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2313 inst
->opcode
= BRW_OPCODE_MOV
;
2314 inst
->src
[0].f
+= inst
->src
[1].f
;
2315 inst
->src
[1] = reg_undef
;
2321 if (inst
->src
[0].equals(inst
->src
[1])) {
2322 inst
->opcode
= BRW_OPCODE_MOV
;
2323 inst
->src
[1] = reg_undef
;
2328 case BRW_OPCODE_LRP
:
2329 if (inst
->src
[1].equals(inst
->src
[2])) {
2330 inst
->opcode
= BRW_OPCODE_MOV
;
2331 inst
->src
[0] = inst
->src
[1];
2332 inst
->src
[1] = reg_undef
;
2333 inst
->src
[2] = reg_undef
;
2338 case BRW_OPCODE_CMP
:
2339 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2341 inst
->src
[0].negate
&&
2342 inst
->src
[1].is_zero()) {
2343 inst
->src
[0].abs
= false;
2344 inst
->src
[0].negate
= false;
2345 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2350 case BRW_OPCODE_SEL
:
2351 if (inst
->src
[0].equals(inst
->src
[1])) {
2352 inst
->opcode
= BRW_OPCODE_MOV
;
2353 inst
->src
[1] = reg_undef
;
2354 inst
->predicate
= BRW_PREDICATE_NONE
;
2355 inst
->predicate_inverse
= false;
2357 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2358 switch (inst
->conditional_mod
) {
2359 case BRW_CONDITIONAL_LE
:
2360 case BRW_CONDITIONAL_L
:
2361 switch (inst
->src
[1].type
) {
2362 case BRW_REGISTER_TYPE_F
:
2363 if (inst
->src
[1].f
>= 1.0f
) {
2364 inst
->opcode
= BRW_OPCODE_MOV
;
2365 inst
->src
[1] = reg_undef
;
2366 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2374 case BRW_CONDITIONAL_GE
:
2375 case BRW_CONDITIONAL_G
:
2376 switch (inst
->src
[1].type
) {
2377 case BRW_REGISTER_TYPE_F
:
2378 if (inst
->src
[1].f
<= 0.0f
) {
2379 inst
->opcode
= BRW_OPCODE_MOV
;
2380 inst
->src
[1] = reg_undef
;
2381 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2393 case BRW_OPCODE_MAD
:
2394 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2395 inst
->opcode
= BRW_OPCODE_MOV
;
2396 inst
->src
[1] = reg_undef
;
2397 inst
->src
[2] = reg_undef
;
2399 } else if (inst
->src
[0].is_zero()) {
2400 inst
->opcode
= BRW_OPCODE_MUL
;
2401 inst
->src
[0] = inst
->src
[2];
2402 inst
->src
[2] = reg_undef
;
2404 } else if (inst
->src
[1].is_one()) {
2405 inst
->opcode
= BRW_OPCODE_ADD
;
2406 inst
->src
[1] = inst
->src
[2];
2407 inst
->src
[2] = reg_undef
;
2409 } else if (inst
->src
[2].is_one()) {
2410 inst
->opcode
= BRW_OPCODE_ADD
;
2411 inst
->src
[2] = reg_undef
;
2413 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2414 inst
->opcode
= BRW_OPCODE_ADD
;
2415 inst
->src
[1].f
*= inst
->src
[2].f
;
2416 inst
->src
[2] = reg_undef
;
2420 case SHADER_OPCODE_BROADCAST
:
2421 if (is_uniform(inst
->src
[0])) {
2422 inst
->opcode
= BRW_OPCODE_MOV
;
2424 inst
->force_writemask_all
= true;
2426 } else if (inst
->src
[1].file
== IMM
) {
2427 inst
->opcode
= BRW_OPCODE_MOV
;
2428 /* It's possible that the selected component will be too large and
2429 * overflow the register. This can happen if someone does a
2430 * readInvocation() from GLSL or SPIR-V and provides an OOB
2431 * invocationIndex. If this happens and we some how manage
2432 * to constant fold it in and get here, then component() may cause
2433 * us to start reading outside of the VGRF which will lead to an
2434 * assert later. Instead, just let it wrap around if it goes over
2437 const unsigned comp
= inst
->src
[1].ud
& (inst
->exec_size
- 1);
2438 inst
->src
[0] = component(inst
->src
[0], comp
);
2440 inst
->force_writemask_all
= true;
2449 /* Swap if src[0] is immediate. */
2450 if (progress
&& inst
->is_commutative()) {
2451 if (inst
->src
[0].file
== IMM
) {
2452 fs_reg tmp
= inst
->src
[1];
2453 inst
->src
[1] = inst
->src
[0];
2462 * Optimize sample messages that have constant zero values for the trailing
2463 * texture coordinates. We can just reduce the message length for these
2464 * instructions instead of reserving a register for it. Trailing parameters
2465 * that aren't sent default to zero anyway. This will cause the dead code
2466 * eliminator to remove the MOV instruction that would otherwise be emitted to
2467 * set up the zero value.
2470 fs_visitor::opt_zero_samples()
2472 /* Gen4 infers the texturing opcode based on the message length so we can't
2475 if (devinfo
->gen
< 5)
2478 bool progress
= false;
2480 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2481 if (!inst
->is_tex())
2484 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2486 if (load_payload
->is_head_sentinel() ||
2487 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2490 /* We don't want to remove the message header or the first parameter.
2491 * Removing the first parameter is not allowed, see the Haswell PRM
2492 * volume 7, page 149:
2494 * "Parameter 0 is required except for the sampleinfo message, which
2495 * has no parameter 0"
2497 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2498 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2499 (inst
->exec_size
/ 8) +
2500 inst
->header_size
- 1].is_zero()) {
2501 inst
->mlen
-= inst
->exec_size
/ 8;
2507 invalidate_live_intervals();
2513 * Optimize sample messages which are followed by the final RT write.
2515 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2516 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2517 * final texturing results copied to the framebuffer write payload and modify
2518 * them to write to the framebuffer directly.
2521 fs_visitor::opt_sampler_eot()
2523 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2525 if (stage
!= MESA_SHADER_FRAGMENT
)
2528 if (devinfo
->gen
!= 9 && !devinfo
->is_cherryview
)
2531 /* FINISHME: It should be possible to implement this optimization when there
2532 * are multiple drawbuffers.
2534 if (key
->nr_color_regions
!= 1)
2537 /* Requires emitting a bunch of saturating MOV instructions during logical
2538 * send lowering to clamp the color payload, which the sampler unit isn't
2539 * going to do for us.
2541 if (key
->clamp_fragment_color
)
2544 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2545 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2546 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2547 assert(fb_write
->eot
);
2548 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2550 /* There wasn't one; nothing to do. */
2551 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2554 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2556 /* 3D Sampler » Messages » Message Format
2558 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2559 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2561 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2562 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2563 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2564 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2565 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2566 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2567 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2568 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2571 /* XXX - This shouldn't be necessary. */
2572 if (tex_inst
->prev
->is_head_sentinel())
2575 /* Check that the FB write sources are fully initialized by the single
2576 * texturing instruction.
2578 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2579 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2580 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2581 fb_write
->size_read(i
) != tex_inst
->size_written
)
2583 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2584 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2589 assert(!tex_inst
->eot
); /* We can't get here twice */
2590 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2592 const fs_builder
ibld(this, block
, tex_inst
);
2594 tex_inst
->offset
|= fb_write
->target
<< 24;
2595 tex_inst
->eot
= true;
2596 tex_inst
->dst
= ibld
.null_reg_ud();
2597 tex_inst
->size_written
= 0;
2598 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2600 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2601 * flag and submit a header together with the sampler message as required
2604 invalidate_live_intervals();
2609 fs_visitor::opt_register_renaming()
2611 bool progress
= false;
2614 int remap
[alloc
.count
];
2615 memset(remap
, -1, sizeof(int) * alloc
.count
);
2617 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2618 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2620 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2621 inst
->opcode
== BRW_OPCODE_WHILE
) {
2625 /* Rewrite instruction sources. */
2626 for (int i
= 0; i
< inst
->sources
; i
++) {
2627 if (inst
->src
[i
].file
== VGRF
&&
2628 remap
[inst
->src
[i
].nr
] != -1 &&
2629 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2630 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2635 const int dst
= inst
->dst
.nr
;
2638 inst
->dst
.file
== VGRF
&&
2639 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
2640 !inst
->is_partial_write()) {
2641 if (remap
[dst
] == -1) {
2644 remap
[dst
] = alloc
.allocate(regs_written(inst
));
2645 inst
->dst
.nr
= remap
[dst
];
2648 } else if (inst
->dst
.file
== VGRF
&&
2650 remap
[dst
] != dst
) {
2651 inst
->dst
.nr
= remap
[dst
];
2657 invalidate_live_intervals();
2659 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2660 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2661 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2670 * Remove redundant or useless discard jumps.
2672 * For example, we can eliminate jumps in the following sequence:
2674 * discard-jump (redundant with the next jump)
2675 * discard-jump (useless; jumps to the next instruction)
2679 fs_visitor::opt_redundant_discard_jumps()
2681 bool progress
= false;
2683 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2685 fs_inst
*placeholder_halt
= NULL
;
2686 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2687 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2688 placeholder_halt
= inst
;
2693 if (!placeholder_halt
)
2696 /* Delete any HALTs immediately before the placeholder halt. */
2697 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2698 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2699 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2700 prev
->remove(last_bblock
);
2705 invalidate_live_intervals();
2711 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2712 * from \p r.offset which overlaps the region starting at \p s.offset and
2713 * spanning \p ds bytes.
2715 static inline unsigned
2716 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
2718 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
2719 const int shift
= rel_offset
/ REG_SIZE
;
2720 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
2721 assert(reg_space(r
) == reg_space(s
) &&
2722 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
2723 return ((1 << n
) - 1) << shift
;
2727 fs_visitor::compute_to_mrf()
2729 bool progress
= false;
2732 /* No MRFs on Gen >= 7. */
2733 if (devinfo
->gen
>= 7)
2736 calculate_live_intervals();
2738 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2742 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2743 inst
->is_partial_write() ||
2744 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2745 inst
->dst
.type
!= inst
->src
[0].type
||
2746 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2747 !inst
->src
[0].is_contiguous() ||
2748 inst
->src
[0].offset
% REG_SIZE
!= 0)
2751 /* Can't compute-to-MRF this GRF if someone else was going to
2754 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2757 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
2758 * things that computed the value of all GRFs of the source region. The
2759 * regs_left bitset keeps track of the registers we haven't yet found a
2760 * generating instruction for.
2762 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
2764 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2765 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2766 inst
->src
[0], inst
->size_read(0))) {
2767 /* Found the last thing to write our reg we want to turn
2768 * into a compute-to-MRF.
2771 /* If this one instruction didn't populate all the
2772 * channels, bail. We might be able to rewrite everything
2773 * that writes that reg, but it would require smarter
2776 if (scan_inst
->is_partial_write())
2779 /* Handling things not fully contained in the source of the copy
2780 * would need us to understand coalescing out more than one MOV at
2783 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
2784 inst
->src
[0], inst
->size_read(0)))
2787 /* SEND instructions can't have MRF as a destination. */
2788 if (scan_inst
->mlen
)
2791 if (devinfo
->gen
== 6) {
2792 /* gen6 math instructions must have the destination be
2793 * GRF, so no compute-to-MRF for them.
2795 if (scan_inst
->is_math()) {
2800 /* Clear the bits for any registers this instruction overwrites. */
2801 regs_left
&= ~mask_relative_to(
2802 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
2807 /* We don't handle control flow here. Most computation of
2808 * values that end up in MRFs are shortly before the MRF
2811 if (block
->start() == scan_inst
)
2814 /* You can't read from an MRF, so if someone else reads our
2815 * MRF's source GRF that we wanted to rewrite, that stops us.
2817 bool interfered
= false;
2818 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2819 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
2820 inst
->src
[0], inst
->size_read(0))) {
2827 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2828 inst
->dst
, inst
->size_written
)) {
2829 /* If somebody else writes our MRF here, we can't
2830 * compute-to-MRF before that.
2835 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
2836 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
2837 inst
->dst
, inst
->size_written
)) {
2838 /* Found a SEND instruction, which means that there are
2839 * live values in MRFs from base_mrf to base_mrf +
2840 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2850 /* Found all generating instructions of our MRF's source value, so it
2851 * should be safe to rewrite them to point to the MRF directly.
2853 regs_left
= (1 << regs_read(inst
, 0)) - 1;
2855 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2856 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2857 inst
->src
[0], inst
->size_read(0))) {
2858 /* Clear the bits for any registers this instruction overwrites. */
2859 regs_left
&= ~mask_relative_to(
2860 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
2862 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
2863 reg_offset(inst
->src
[0]);
2865 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2866 /* Apply the same address transformation done by the hardware
2867 * for COMPR4 MRF writes.
2869 assert(rel_offset
< 2 * REG_SIZE
);
2870 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
2872 /* Clear the COMPR4 bit if the generating instruction is not
2875 if (scan_inst
->size_written
< 2 * REG_SIZE
)
2876 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
2879 /* Calculate the MRF number the result of this instruction is
2880 * ultimately written to.
2882 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
2885 scan_inst
->dst
.file
= MRF
;
2886 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
2887 scan_inst
->saturate
|= inst
->saturate
;
2894 inst
->remove(block
);
2899 invalidate_live_intervals();
2905 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2906 * flow. We could probably do better here with some form of divergence
2910 fs_visitor::eliminate_find_live_channel()
2912 bool progress
= false;
2915 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
2916 /* The optimization below assumes that channel zero is live on thread
2917 * dispatch, which may not be the case if the fixed function dispatches
2923 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2924 switch (inst
->opcode
) {
2930 case BRW_OPCODE_ENDIF
:
2931 case BRW_OPCODE_WHILE
:
2935 case FS_OPCODE_DISCARD_JUMP
:
2936 /* This can potentially make control flow non-uniform until the end
2941 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2943 inst
->opcode
= BRW_OPCODE_MOV
;
2944 inst
->src
[0] = brw_imm_ud(0u);
2946 inst
->force_writemask_all
= true;
2960 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2961 * instructions to FS_OPCODE_REP_FB_WRITE.
2964 fs_visitor::emit_repclear_shader()
2966 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2968 int color_mrf
= base_mrf
+ 2;
2972 mov
= bld
.exec_all().group(4, 0)
2973 .MOV(brw_message_reg(color_mrf
),
2974 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2976 struct brw_reg reg
=
2977 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2978 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
2979 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2981 mov
= bld
.exec_all().group(4, 0)
2982 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
2986 if (key
->nr_color_regions
== 1) {
2987 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2988 write
->saturate
= key
->clamp_fragment_color
;
2989 write
->base_mrf
= color_mrf
;
2991 write
->header_size
= 0;
2994 assume(key
->nr_color_regions
> 0);
2995 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2996 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2997 write
->saturate
= key
->clamp_fragment_color
;
2998 write
->base_mrf
= base_mrf
;
3000 write
->header_size
= 2;
3008 assign_constant_locations();
3009 assign_curb_setup();
3011 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3013 assert(mov
->src
[0].file
== FIXED_GRF
);
3014 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3019 * Walks through basic blocks, looking for repeated MRF writes and
3020 * removing the later ones.
3023 fs_visitor::remove_duplicate_mrf_writes()
3025 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3026 bool progress
= false;
3028 /* Need to update the MRF tracking for compressed instructions. */
3029 if (dispatch_width
>= 16)
3032 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3034 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3035 if (inst
->is_control_flow()) {
3036 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3039 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3040 inst
->dst
.file
== MRF
) {
3041 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3042 if (prev_inst
&& inst
->equals(prev_inst
)) {
3043 inst
->remove(block
);
3049 /* Clear out the last-write records for MRFs that were overwritten. */
3050 if (inst
->dst
.file
== MRF
) {
3051 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3054 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3055 /* Found a SEND instruction, which will include two or fewer
3056 * implied MRF writes. We could do better here.
3058 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3059 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3063 /* Clear out any MRF move records whose sources got overwritten. */
3064 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3065 if (last_mrf_move
[i
] &&
3066 regions_overlap(inst
->dst
, inst
->size_written
,
3067 last_mrf_move
[i
]->src
[0],
3068 last_mrf_move
[i
]->size_read(0))) {
3069 last_mrf_move
[i
] = NULL
;
3073 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3074 inst
->dst
.file
== MRF
&&
3075 inst
->src
[0].file
!= ARF
&&
3076 !inst
->is_partial_write()) {
3077 last_mrf_move
[inst
->dst
.nr
] = inst
;
3082 invalidate_live_intervals();
3088 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3090 /* Clear the flag for registers that actually got read (as expected). */
3091 for (int i
= 0; i
< inst
->sources
; i
++) {
3093 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3094 grf
= inst
->src
[i
].nr
;
3099 if (grf
>= first_grf
&&
3100 grf
< first_grf
+ grf_len
) {
3101 deps
[grf
- first_grf
] = false;
3102 if (inst
->exec_size
== 16)
3103 deps
[grf
- first_grf
+ 1] = false;
3109 * Implements this workaround for the original 965:
3111 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3112 * check for post destination dependencies on this instruction, software
3113 * must ensure that there is no destination hazard for the case of ‘write
3114 * followed by a posted write’ shown in the following example.
3117 * 2. send r3.xy <rest of send instruction>
3120 * Due to no post-destination dependency check on the ‘send’, the above
3121 * code sequence could have two instructions (1 and 2) in flight at the
3122 * same time that both consider ‘r3’ as the target of their final writes.
3125 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3128 int write_len
= regs_written(inst
);
3129 int first_write_grf
= inst
->dst
.nr
;
3130 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3131 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3133 memset(needs_dep
, false, sizeof(needs_dep
));
3134 memset(needs_dep
, true, write_len
);
3136 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3138 /* Walk backwards looking for writes to registers we're writing which
3139 * aren't read since being written. If we hit the start of the program,
3140 * we assume that there are no outstanding dependencies on entry to the
3143 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3144 /* If we hit control flow, assume that there *are* outstanding
3145 * dependencies, and force their cleanup before our instruction.
3147 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3148 for (int i
= 0; i
< write_len
; i
++) {
3150 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3151 first_write_grf
+ i
);
3156 /* We insert our reads as late as possible on the assumption that any
3157 * instruction but a MOV that might have left us an outstanding
3158 * dependency has more latency than a MOV.
3160 if (scan_inst
->dst
.file
== VGRF
) {
3161 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3162 int reg
= scan_inst
->dst
.nr
+ i
;
3164 if (reg
>= first_write_grf
&&
3165 reg
< first_write_grf
+ write_len
&&
3166 needs_dep
[reg
- first_write_grf
]) {
3167 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3168 needs_dep
[reg
- first_write_grf
] = false;
3169 if (scan_inst
->exec_size
== 16)
3170 needs_dep
[reg
- first_write_grf
+ 1] = false;
3175 /* Clear the flag for registers that actually got read (as expected). */
3176 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3178 /* Continue the loop only if we haven't resolved all the dependencies */
3180 for (i
= 0; i
< write_len
; i
++) {
3190 * Implements this workaround for the original 965:
3192 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3193 * used as a destination register until after it has been sourced by an
3194 * instruction with a different destination register.
3197 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3199 int write_len
= regs_written(inst
);
3200 int first_write_grf
= inst
->dst
.nr
;
3201 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3202 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3204 memset(needs_dep
, false, sizeof(needs_dep
));
3205 memset(needs_dep
, true, write_len
);
3206 /* Walk forwards looking for writes to registers we're writing which aren't
3207 * read before being written.
3209 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3210 /* If we hit control flow, force resolve all remaining dependencies. */
3211 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3212 for (int i
= 0; i
< write_len
; i
++) {
3214 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3215 first_write_grf
+ i
);
3220 /* Clear the flag for registers that actually got read (as expected). */
3221 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3223 /* We insert our reads as late as possible since they're reading the
3224 * result of a SEND, which has massive latency.
3226 if (scan_inst
->dst
.file
== VGRF
&&
3227 scan_inst
->dst
.nr
>= first_write_grf
&&
3228 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3229 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3230 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3232 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3235 /* Continue the loop only if we haven't resolved all the dependencies */
3237 for (i
= 0; i
< write_len
; i
++) {
3247 fs_visitor::insert_gen4_send_dependency_workarounds()
3249 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3252 bool progress
= false;
3254 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3255 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3256 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3257 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3263 invalidate_live_intervals();
3267 * Turns the generic expression-style uniform pull constant load instruction
3268 * into a hardware-specific series of instructions for loading a pull
3271 * The expression style allows the CSE pass before this to optimize out
3272 * repeated loads from the same offset, and gives the pre-register-allocation
3273 * scheduling full flexibility, while the conversion to native instructions
3274 * allows the post-register-allocation scheduler the best information
3277 * Note that execution masking for setting up pull constant loads is special:
3278 * the channels that need to be written are unrelated to the current execution
3279 * mask, since a later instruction will use one of the result channels as a
3280 * source operand for all 8 or 16 of its channels.
3283 fs_visitor::lower_uniform_pull_constant_loads()
3285 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3286 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3289 if (devinfo
->gen
>= 7) {
3290 const fs_builder ubld
= fs_builder(this, block
, inst
).exec_all();
3291 const fs_reg payload
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
);
3293 ubld
.group(8, 0).MOV(payload
,
3294 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3295 ubld
.group(1, 0).MOV(component(payload
, 2),
3296 brw_imm_ud(inst
->src
[1].ud
/ 16));
3298 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3299 inst
->src
[1] = payload
;
3300 inst
->header_size
= 1;
3303 invalidate_live_intervals();
3305 /* Before register allocation, we didn't tell the scheduler about the
3306 * MRF we use. We know it's safe to use this MRF because nothing
3307 * else does except for register spill/unspill, which generates and
3308 * uses its MRF within a single IR instruction.
3310 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3317 fs_visitor::lower_load_payload()
3319 bool progress
= false;
3321 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3322 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3325 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3326 assert(inst
->saturate
== false);
3327 fs_reg dst
= inst
->dst
;
3329 /* Get rid of COMPR4. We'll add it back in if we need it */
3330 if (dst
.file
== MRF
)
3331 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3333 const fs_builder
ibld(this, block
, inst
);
3334 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3336 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3337 if (inst
->src
[i
].file
!= BAD_FILE
) {
3338 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3339 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3340 hbld
.MOV(mov_dst
, mov_src
);
3342 dst
= offset(dst
, hbld
, 1);
3345 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3346 inst
->exec_size
> 8) {
3347 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3348 * a straightforward copy. Instead, the result of the
3349 * LOAD_PAYLOAD is treated as interleaved and the first four
3350 * non-header sources are unpacked as:
3361 * This is used for gen <= 5 fb writes.
3363 assert(inst
->exec_size
== 16);
3364 assert(inst
->header_size
+ 4 <= inst
->sources
);
3365 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3366 if (inst
->src
[i
].file
!= BAD_FILE
) {
3367 if (devinfo
->has_compr4
) {
3368 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3369 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3370 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3372 /* Platform doesn't have COMPR4. We have to fake it */
3373 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3374 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3376 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3383 /* The loop above only ever incremented us through the first set
3384 * of 4 registers. However, thanks to the magic of COMPR4, we
3385 * actually wrote to the first 8 registers, so we need to take
3386 * that into account now.
3390 /* The COMPR4 code took care of the first 4 sources. We'll let
3391 * the regular path handle any remaining sources. Yes, we are
3392 * modifying the instruction but we're about to delete it so
3393 * this really doesn't hurt anything.
3395 inst
->header_size
+= 4;
3398 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3399 if (inst
->src
[i
].file
!= BAD_FILE
)
3400 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3401 dst
= offset(dst
, ibld
, 1);
3404 inst
->remove(block
);
3409 invalidate_live_intervals();
3415 fs_visitor::lower_integer_multiplication()
3417 bool progress
= false;
3419 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3420 const fs_builder
ibld(this, block
, inst
);
3422 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3423 if (inst
->dst
.is_accumulator() ||
3424 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3425 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3428 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3429 * operation directly, but CHV/BXT cannot.
3431 if (devinfo
->gen
>= 8 &&
3432 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
))
3435 if (inst
->src
[1].file
== IMM
&&
3436 inst
->src
[1].ud
< (1 << 16)) {
3437 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3438 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3441 * If multiplying by an immediate value that fits in 16-bits, do a
3442 * single MUL instruction with that value in the proper location.
3444 if (devinfo
->gen
< 7) {
3445 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3447 ibld
.MOV(imm
, inst
->src
[1]);
3448 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3450 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3451 ibld
.MUL(inst
->dst
, inst
->src
[0],
3452 ud
? brw_imm_uw(inst
->src
[1].ud
)
3453 : brw_imm_w(inst
->src
[1].d
));
3456 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3457 * do 32-bit integer multiplication in one instruction, but instead
3458 * must do a sequence (which actually calculates a 64-bit result):
3460 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3461 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3462 * mov(8) g2<1>D acc0<8,8,1>D
3464 * But on Gen > 6, the ability to use second accumulator register
3465 * (acc1) for non-float data types was removed, preventing a simple
3466 * implementation in SIMD16. A 16-channel result can be calculated by
3467 * executing the three instructions twice in SIMD8, once with quarter
3468 * control of 1Q for the first eight channels and again with 2Q for
3469 * the second eight channels.
3471 * Which accumulator register is implicitly accessed (by AccWrEnable
3472 * for instance) is determined by the quarter control. Unfortunately
3473 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3474 * implicit accumulator access by an instruction with 2Q will access
3475 * acc1 regardless of whether the data type is usable in acc1.
3477 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3478 * integer data types.
3480 * Since we only want the low 32-bits of the result, we can do two
3481 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3482 * adjust the high result and add them (like the mach is doing):
3484 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3485 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3486 * shl(8) g9<1>D g8<8,8,1>D 16D
3487 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3489 * We avoid the shl instruction by realizing that we only want to add
3490 * the low 16-bits of the "high" result to the high 16-bits of the
3491 * "low" result and using proper regioning on the add:
3493 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3494 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3495 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3497 * Since it does not use the (single) accumulator register, we can
3498 * schedule multi-component multiplications much better.
3501 bool needs_mov
= false;
3502 fs_reg orig_dst
= inst
->dst
;
3503 fs_reg low
= inst
->dst
;
3504 if (orig_dst
.is_null() || orig_dst
.file
== MRF
||
3505 regions_overlap(inst
->dst
, inst
->size_written
,
3506 inst
->src
[0], inst
->size_read(0)) ||
3507 regions_overlap(inst
->dst
, inst
->size_written
,
3508 inst
->src
[1], inst
->size_read(1))) {
3510 low
.nr
= alloc
.allocate(regs_written(inst
));
3511 low
.offset
= low
.offset
% REG_SIZE
;
3514 fs_reg high
= inst
->dst
;
3515 high
.nr
= alloc
.allocate(regs_written(inst
));
3516 high
.offset
= high
.offset
% REG_SIZE
;
3518 if (devinfo
->gen
>= 7) {
3519 if (inst
->src
[1].file
== IMM
) {
3520 ibld
.MUL(low
, inst
->src
[0],
3521 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
3522 ibld
.MUL(high
, inst
->src
[0],
3523 brw_imm_uw(inst
->src
[1].ud
>> 16));
3525 ibld
.MUL(low
, inst
->src
[0],
3526 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
3527 ibld
.MUL(high
, inst
->src
[0],
3528 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
3531 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
3533 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
3537 ibld
.ADD(subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3538 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3539 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
3541 if (needs_mov
|| inst
->conditional_mod
) {
3542 set_condmod(inst
->conditional_mod
,
3543 ibld
.MOV(orig_dst
, low
));
3547 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3548 /* Should have been lowered to 8-wide. */
3549 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
3550 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3552 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3553 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3555 if (devinfo
->gen
>= 8) {
3556 /* Until Gen8, integer multiplies read 32-bits from one source,
3557 * and 16-bits from the other, and relying on the MACH instruction
3558 * to generate the high bits of the result.
3560 * On Gen8, the multiply instruction does a full 32x32-bit
3561 * multiply, but in order to do a 64-bit multiply we can simulate
3562 * the previous behavior and then use a MACH instruction.
3564 * FINISHME: Don't use source modifiers on src1.
3566 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3567 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3568 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3569 mul
->src
[1].stride
*= 2;
3571 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3573 /* Among other things the quarter control bits influence which
3574 * accumulator register is used by the hardware for instructions
3575 * that access the accumulator implicitly (e.g. MACH). A
3576 * second-half instruction would normally map to acc1, which
3577 * doesn't exist on Gen7 and up (the hardware does emulate it for
3578 * floating-point instructions *only* by taking advantage of the
3579 * extra precision of acc0 not normally used for floating point
3582 * HSW and up are careful enough not to try to access an
3583 * accumulator register that doesn't exist, but on earlier Gen7
3584 * hardware we need to make sure that the quarter control bits are
3585 * zero to avoid non-deterministic behaviour and emit an extra MOV
3586 * to get the result masked correctly according to the current
3590 mach
->force_writemask_all
= true;
3591 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3592 ibld
.MOV(inst
->dst
, mach
->dst
);
3598 inst
->remove(block
);
3603 invalidate_live_intervals();
3609 fs_visitor::lower_minmax()
3611 assert(devinfo
->gen
< 6);
3613 bool progress
= false;
3615 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3616 const fs_builder
ibld(this, block
, inst
);
3618 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3619 inst
->predicate
== BRW_PREDICATE_NONE
) {
3620 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3621 * the original SEL.L/GE instruction
3623 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3624 inst
->conditional_mod
);
3625 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3626 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3633 invalidate_live_intervals();
3639 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3640 fs_reg
*dst
, fs_reg color
, unsigned components
)
3642 if (key
->clamp_fragment_color
) {
3643 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3644 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3646 for (unsigned i
= 0; i
< components
; i
++)
3648 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3653 for (unsigned i
= 0; i
< components
; i
++)
3654 dst
[i
] = offset(color
, bld
, i
);
3658 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3659 const struct brw_wm_prog_data
*prog_data
,
3660 const brw_wm_prog_key
*key
,
3661 const fs_visitor::thread_payload
&payload
)
3663 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3664 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3665 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3666 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3667 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3668 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3669 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3670 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3671 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3672 const unsigned components
=
3673 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3675 /* We can potentially have a message length of up to 15, so we have to set
3676 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3679 int header_size
= 2, payload_header_size
;
3680 unsigned length
= 0;
3682 /* From the Sandy Bridge PRM, volume 4, page 198:
3684 * "Dispatched Pixel Enables. One bit per pixel indicating
3685 * which pixels were originally enabled when the thread was
3686 * dispatched. This field is only required for the end-of-
3687 * thread message and on all dual-source messages."
3689 if (devinfo
->gen
>= 6 &&
3690 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3691 color1
.file
== BAD_FILE
&&
3692 key
->nr_color_regions
== 1) {
3696 if (header_size
!= 0) {
3697 assert(header_size
== 2);
3698 /* Allocate 2 registers for a header */
3702 if (payload
.aa_dest_stencil_reg
) {
3703 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3704 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3705 .MOV(sources
[length
],
3706 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3710 if (sample_mask
.file
!= BAD_FILE
) {
3711 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3712 BRW_REGISTER_TYPE_UD
);
3714 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3715 * relevant. Since it's unsigned single words one vgrf is always
3716 * 16-wide, but only the lower or higher 8 channels will be used by the
3717 * hardware when doing a SIMD8 write depending on whether we have
3718 * selected the subspans for the first or second half respectively.
3720 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3721 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3722 sample_mask
.stride
*= 2;
3724 bld
.exec_all().annotate("FB write oMask")
3725 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3731 payload_header_size
= length
;
3733 if (src0_alpha
.file
!= BAD_FILE
) {
3734 /* FIXME: This is being passed at the wrong location in the payload and
3735 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3736 * It's supposed to be immediately before oMask but there seems to be no
3737 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3738 * requires header sources to form a contiguous segment at the beginning
3739 * of the message and src0_alpha has per-channel semantics.
3741 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3743 } else if (key
->replicate_alpha
&& inst
->target
!= 0) {
3744 /* Handle the case when fragment shader doesn't write to draw buffer
3745 * zero. No need to call setup_color_payload() for src0_alpha because
3746 * alpha value will be undefined.
3751 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3754 if (color1
.file
!= BAD_FILE
) {
3755 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3759 if (src_depth
.file
!= BAD_FILE
) {
3760 sources
[length
] = src_depth
;
3764 if (dst_depth
.file
!= BAD_FILE
) {
3765 sources
[length
] = dst_depth
;
3769 if (src_stencil
.file
!= BAD_FILE
) {
3770 assert(devinfo
->gen
>= 9);
3771 assert(bld
.dispatch_width() != 16);
3773 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3774 * available on gen9+. As such it's impossible to have both enabled at the
3775 * same time and therefore length cannot overrun the array.
3777 assert(length
< 15);
3779 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3780 bld
.exec_all().annotate("FB write OS")
3781 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
3782 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
3787 if (devinfo
->gen
>= 7) {
3788 /* Send from the GRF */
3789 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3790 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3791 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
3792 load
->dst
= payload
;
3794 inst
->src
[0] = payload
;
3795 inst
->resize_sources(1);
3797 /* Send from the MRF */
3798 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3799 sources
, length
, payload_header_size
);
3801 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3802 * will do this for us if we just give it a COMPR4 destination.
3804 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3805 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3807 inst
->resize_sources(0);
3811 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3812 inst
->mlen
= regs_written(load
);
3813 inst
->header_size
= header_size
;
3817 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
3819 const fs_builder
&ubld
= bld
.exec_all();
3820 const unsigned length
= 2;
3821 const fs_reg header
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
, length
);
3824 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3826 inst
->resize_sources(1);
3827 inst
->src
[0] = header
;
3828 inst
->opcode
= FS_OPCODE_FB_READ
;
3829 inst
->mlen
= length
;
3830 inst
->header_size
= length
;
3834 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3835 const fs_reg
&coordinate
,
3836 const fs_reg
&shadow_c
,
3837 const fs_reg
&lod
, const fs_reg
&lod2
,
3838 const fs_reg
&surface
,
3839 const fs_reg
&sampler
,
3840 unsigned coord_components
,
3841 unsigned grad_components
)
3843 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3844 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3845 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3846 fs_reg msg_end
= msg_begin
;
3849 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3851 for (unsigned i
= 0; i
< coord_components
; i
++)
3852 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3853 offset(coordinate
, bld
, i
));
3855 msg_end
= offset(msg_end
, bld
, coord_components
);
3857 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3858 * require all three components to be present and zero if they are unused.
3860 if (coord_components
> 0 &&
3861 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3862 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3863 for (unsigned i
= coord_components
; i
< 3; i
++)
3864 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3866 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3869 if (op
== SHADER_OPCODE_TXD
) {
3870 /* TXD unsupported in SIMD16 mode. */
3871 assert(bld
.dispatch_width() == 8);
3873 /* the slots for u and v are always present, but r is optional */
3874 if (coord_components
< 2)
3875 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3878 * dPdx = dudx, dvdx, drdx
3879 * dPdy = dudy, dvdy, drdy
3881 * 1-arg: Does not exist.
3883 * 2-arg: dudx dvdx dudy dvdy
3884 * dPdx.x dPdx.y dPdy.x dPdy.y
3887 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3888 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3889 * m5 m6 m7 m8 m9 m10
3891 for (unsigned i
= 0; i
< grad_components
; i
++)
3892 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3894 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3896 for (unsigned i
= 0; i
< grad_components
; i
++)
3897 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3899 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3903 /* Bias/LOD with shadow comparator is unsupported in SIMD16 -- *Without*
3904 * shadow comparator (including RESINFO) it's unsupported in SIMD8 mode.
3906 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3907 bld
.dispatch_width() == 16);
3909 const brw_reg_type type
=
3910 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3911 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3912 bld
.MOV(retype(msg_end
, type
), lod
);
3913 msg_end
= offset(msg_end
, bld
, 1);
3916 if (shadow_c
.file
!= BAD_FILE
) {
3917 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3918 /* There's no plain shadow compare message, so we use shadow
3919 * compare with a bias of 0.0.
3921 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3922 msg_end
= offset(msg_end
, bld
, 1);
3925 bld
.MOV(msg_end
, shadow_c
);
3926 msg_end
= offset(msg_end
, bld
, 1);
3930 inst
->src
[0] = reg_undef
;
3931 inst
->src
[1] = surface
;
3932 inst
->src
[2] = sampler
;
3933 inst
->resize_sources(3);
3934 inst
->base_mrf
= msg_begin
.nr
;
3935 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3936 inst
->header_size
= 1;
3940 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3941 const fs_reg
&coordinate
,
3942 const fs_reg
&shadow_c
,
3943 const fs_reg
&lod
, const fs_reg
&lod2
,
3944 const fs_reg
&sample_index
,
3945 const fs_reg
&surface
,
3946 const fs_reg
&sampler
,
3947 unsigned coord_components
,
3948 unsigned grad_components
)
3950 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3951 fs_reg msg_coords
= message
;
3952 unsigned header_size
= 0;
3954 if (inst
->offset
!= 0) {
3955 /* The offsets set up by the visitor are in the m1 header, so we can't
3962 for (unsigned i
= 0; i
< coord_components
; i
++)
3963 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
3964 offset(coordinate
, bld
, i
));
3966 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3967 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3969 if (shadow_c
.file
!= BAD_FILE
) {
3970 fs_reg msg_shadow
= msg_lod
;
3971 bld
.MOV(msg_shadow
, shadow_c
);
3972 msg_lod
= offset(msg_shadow
, bld
, 1);
3977 case SHADER_OPCODE_TXL
:
3979 bld
.MOV(msg_lod
, lod
);
3980 msg_end
= offset(msg_lod
, bld
, 1);
3982 case SHADER_OPCODE_TXD
:
3985 * dPdx = dudx, dvdx, drdx
3986 * dPdy = dudy, dvdy, drdy
3988 * Load up these values:
3989 * - dudx dudy dvdx dvdy drdx drdy
3990 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3993 for (unsigned i
= 0; i
< grad_components
; i
++) {
3994 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
3995 msg_end
= offset(msg_end
, bld
, 1);
3997 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
3998 msg_end
= offset(msg_end
, bld
, 1);
4001 case SHADER_OPCODE_TXS
:
4002 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4003 bld
.MOV(msg_lod
, lod
);
4004 msg_end
= offset(msg_lod
, bld
, 1);
4006 case SHADER_OPCODE_TXF
:
4007 msg_lod
= offset(msg_coords
, bld
, 3);
4008 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4009 msg_end
= offset(msg_lod
, bld
, 1);
4011 case SHADER_OPCODE_TXF_CMS
:
4012 msg_lod
= offset(msg_coords
, bld
, 3);
4014 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4016 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4017 msg_end
= offset(msg_lod
, bld
, 2);
4024 inst
->src
[0] = reg_undef
;
4025 inst
->src
[1] = surface
;
4026 inst
->src
[2] = sampler
;
4027 inst
->resize_sources(3);
4028 inst
->base_mrf
= message
.nr
;
4029 inst
->mlen
= msg_end
.nr
- message
.nr
;
4030 inst
->header_size
= header_size
;
4032 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4033 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4037 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
4039 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4042 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4046 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4047 const fs_reg
&coordinate
,
4048 const fs_reg
&shadow_c
,
4049 fs_reg lod
, const fs_reg
&lod2
,
4050 const fs_reg
&sample_index
,
4052 const fs_reg
&surface
,
4053 const fs_reg
&sampler
,
4054 const fs_reg
&tg4_offset
,
4055 unsigned coord_components
,
4056 unsigned grad_components
)
4058 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4059 unsigned reg_width
= bld
.dispatch_width() / 8;
4060 unsigned header_size
= 0, length
= 0;
4061 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4062 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4063 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4065 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4066 inst
->offset
!= 0 || inst
->eot
||
4067 op
== SHADER_OPCODE_SAMPLEINFO
||
4068 is_high_sampler(devinfo
, sampler
)) {
4069 /* For general texture offsets (no txf workaround), we need a header to
4070 * put them in. Note that we're only reserving space for it in the
4071 * message payload as it will be initialized implicitly by the
4074 * TG4 needs to place its channel select in the header, for interaction
4075 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4076 * larger sampler numbers we need to offset the Sampler State Pointer in
4080 sources
[0] = fs_reg();
4083 /* If we're requesting fewer than four channels worth of response,
4084 * and we have an explicit header, we need to set up the sampler
4085 * writemask. It's reversed from normal: 1 means "don't write".
4087 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4088 assert(regs_written(inst
) % reg_width
== 0);
4089 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4090 inst
->offset
|= mask
<< 12;
4094 if (shadow_c
.file
!= BAD_FILE
) {
4095 bld
.MOV(sources
[length
], shadow_c
);
4099 bool coordinate_done
= false;
4101 /* Set up the LOD info */
4104 case SHADER_OPCODE_TXL
:
4105 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4106 op
= SHADER_OPCODE_TXL_LZ
;
4109 bld
.MOV(sources
[length
], lod
);
4112 case SHADER_OPCODE_TXD
:
4113 /* TXD should have been lowered in SIMD16 mode. */
4114 assert(bld
.dispatch_width() == 8);
4116 /* Load dPdx and the coordinate together:
4117 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4119 for (unsigned i
= 0; i
< coord_components
; i
++) {
4120 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4122 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4123 * only derivatives for (u, v, r).
4125 if (i
< grad_components
) {
4126 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4127 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4131 coordinate_done
= true;
4133 case SHADER_OPCODE_TXS
:
4134 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4137 case SHADER_OPCODE_TXF
:
4138 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4139 * On Gen9 they are u, v, lod, r
4141 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4143 if (devinfo
->gen
>= 9) {
4144 if (coord_components
>= 2) {
4145 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4146 offset(coordinate
, bld
, 1));
4148 sources
[length
] = brw_imm_d(0);
4153 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4154 op
= SHADER_OPCODE_TXF_LZ
;
4156 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4160 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4161 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4162 offset(coordinate
, bld
, i
));
4164 coordinate_done
= true;
4167 case SHADER_OPCODE_TXF_CMS
:
4168 case SHADER_OPCODE_TXF_CMS_W
:
4169 case SHADER_OPCODE_TXF_UMS
:
4170 case SHADER_OPCODE_TXF_MCS
:
4171 if (op
== SHADER_OPCODE_TXF_UMS
||
4172 op
== SHADER_OPCODE_TXF_CMS
||
4173 op
== SHADER_OPCODE_TXF_CMS_W
) {
4174 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4178 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4179 /* Data from the multisample control surface. */
4180 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4183 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4186 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4187 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4190 offset(mcs
, bld
, 1));
4195 /* There is no offsetting for this message; just copy in the integer
4196 * texture coordinates.
4198 for (unsigned i
= 0; i
< coord_components
; i
++)
4199 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4200 offset(coordinate
, bld
, i
));
4202 coordinate_done
= true;
4204 case SHADER_OPCODE_TG4_OFFSET
:
4205 /* More crazy intermixing */
4206 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4207 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4209 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4210 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4211 offset(tg4_offset
, bld
, i
));
4213 if (coord_components
== 3) /* r if present */
4214 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4216 coordinate_done
= true;
4222 /* Set up the coordinate (except for cases where it was done above) */
4223 if (!coordinate_done
) {
4224 for (unsigned i
= 0; i
< coord_components
; i
++)
4225 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4230 mlen
= length
* reg_width
- header_size
;
4232 mlen
= length
* reg_width
;
4234 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4235 BRW_REGISTER_TYPE_F
);
4236 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4238 /* Generate the SEND. */
4240 inst
->src
[0] = src_payload
;
4241 inst
->src
[1] = surface
;
4242 inst
->src
[2] = sampler
;
4243 inst
->resize_sources(3);
4245 inst
->header_size
= header_size
;
4247 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4248 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4252 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4254 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4255 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4256 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4257 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4258 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4259 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4260 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4261 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4262 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4263 const fs_reg
&tg4_offset
= inst
->src
[TEX_LOGICAL_SRC_TG4_OFFSET
];
4264 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4265 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4266 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4267 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4269 if (devinfo
->gen
>= 7) {
4270 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4271 shadow_c
, lod
, lod2
, sample_index
,
4272 mcs
, surface
, sampler
, tg4_offset
,
4273 coord_components
, grad_components
);
4274 } else if (devinfo
->gen
>= 5) {
4275 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4276 shadow_c
, lod
, lod2
, sample_index
,
4278 coord_components
, grad_components
);
4280 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4281 shadow_c
, lod
, lod2
,
4283 coord_components
, grad_components
);
4288 * Initialize the header present in some typed and untyped surface
4292 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4294 fs_builder ubld
= bld
.exec_all().group(8, 0);
4295 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4296 ubld
.MOV(dst
, brw_imm_d(0));
4297 ubld
.MOV(component(dst
, 7), sample_mask
);
4302 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4303 const fs_reg
&sample_mask
)
4305 /* Get the logical send arguments. */
4306 const fs_reg
&addr
= inst
->src
[0];
4307 const fs_reg
&src
= inst
->src
[1];
4308 const fs_reg
&surface
= inst
->src
[2];
4309 const UNUSED fs_reg
&dims
= inst
->src
[3];
4310 const fs_reg
&arg
= inst
->src
[4];
4312 /* Calculate the total number of components of the payload. */
4313 const unsigned addr_sz
= inst
->components_read(0);
4314 const unsigned src_sz
= inst
->components_read(1);
4315 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4316 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4318 /* Allocate space for the payload. */
4319 fs_reg
*const components
= new fs_reg
[sz
];
4320 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4323 /* Construct the payload. */
4325 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4327 for (unsigned i
= 0; i
< addr_sz
; i
++)
4328 components
[n
++] = offset(addr
, bld
, i
);
4330 for (unsigned i
= 0; i
< src_sz
; i
++)
4331 components
[n
++] = offset(src
, bld
, i
);
4333 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4335 /* Update the original instruction. */
4337 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4338 inst
->header_size
= header_sz
;
4340 inst
->src
[0] = payload
;
4341 inst
->src
[1] = surface
;
4343 inst
->resize_sources(3);
4345 delete[] components
;
4349 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4351 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4353 if (devinfo
->gen
>= 7) {
4354 /* We are switching the instruction from an ALU-like instruction to a
4355 * send-from-grf instruction. Since sends can't handle strides or
4356 * source modifiers, we have to make a copy of the offset source.
4358 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4359 bld
.MOV(tmp
, inst
->src
[1]);
4362 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4365 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4366 BRW_REGISTER_TYPE_UD
);
4368 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4370 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4371 inst
->resize_sources(1);
4372 inst
->base_mrf
= payload
.nr
;
4373 inst
->header_size
= 1;
4374 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4379 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4381 assert(bld
.shader
->devinfo
->gen
< 6);
4384 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4386 if (inst
->sources
> 1) {
4387 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4388 * "Message Payload":
4390 * "Operand0[7]. For the INT DIV functions, this operand is the
4393 * "Operand1[7]. For the INT DIV functions, this operand is the
4396 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4397 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4398 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4400 inst
->resize_sources(1);
4401 inst
->src
[0] = src0
;
4403 assert(inst
->exec_size
== 8);
4404 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4409 fs_visitor::lower_logical_sends()
4411 bool progress
= false;
4413 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4414 const fs_builder
ibld(this, block
, inst
);
4416 switch (inst
->opcode
) {
4417 case FS_OPCODE_FB_WRITE_LOGICAL
:
4418 assert(stage
== MESA_SHADER_FRAGMENT
);
4419 lower_fb_write_logical_send(ibld
, inst
,
4420 brw_wm_prog_data(prog_data
),
4421 (const brw_wm_prog_key
*)key
,
4425 case FS_OPCODE_FB_READ_LOGICAL
:
4426 lower_fb_read_logical_send(ibld
, inst
);
4429 case SHADER_OPCODE_TEX_LOGICAL
:
4430 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4433 case SHADER_OPCODE_TXD_LOGICAL
:
4434 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4437 case SHADER_OPCODE_TXF_LOGICAL
:
4438 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4441 case SHADER_OPCODE_TXL_LOGICAL
:
4442 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4445 case SHADER_OPCODE_TXS_LOGICAL
:
4446 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4449 case FS_OPCODE_TXB_LOGICAL
:
4450 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4453 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4454 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4457 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4458 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4461 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4462 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4465 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4466 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4469 case SHADER_OPCODE_LOD_LOGICAL
:
4470 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4473 case SHADER_OPCODE_TG4_LOGICAL
:
4474 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4477 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4478 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4481 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4482 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
4485 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4486 lower_surface_logical_send(ibld
, inst
,
4487 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4491 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4492 lower_surface_logical_send(ibld
, inst
,
4493 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4494 ibld
.sample_mask_reg());
4497 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4498 lower_surface_logical_send(ibld
, inst
,
4499 SHADER_OPCODE_UNTYPED_ATOMIC
,
4500 ibld
.sample_mask_reg());
4503 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4504 lower_surface_logical_send(ibld
, inst
,
4505 SHADER_OPCODE_TYPED_SURFACE_READ
,
4509 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4510 lower_surface_logical_send(ibld
, inst
,
4511 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4512 ibld
.sample_mask_reg());
4515 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4516 lower_surface_logical_send(ibld
, inst
,
4517 SHADER_OPCODE_TYPED_ATOMIC
,
4518 ibld
.sample_mask_reg());
4521 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4522 lower_varying_pull_constant_logical_send(ibld
, inst
);
4525 case SHADER_OPCODE_RCP
:
4526 case SHADER_OPCODE_RSQ
:
4527 case SHADER_OPCODE_SQRT
:
4528 case SHADER_OPCODE_EXP2
:
4529 case SHADER_OPCODE_LOG2
:
4530 case SHADER_OPCODE_SIN
:
4531 case SHADER_OPCODE_COS
:
4532 case SHADER_OPCODE_POW
:
4533 case SHADER_OPCODE_INT_QUOTIENT
:
4534 case SHADER_OPCODE_INT_REMAINDER
:
4535 /* The math opcodes are overloaded for the send-like and
4536 * expression-like instructions which seems kind of icky. Gen6+ has
4537 * a native (but rather quirky) MATH instruction so we don't need to
4538 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
4539 * logical instructions (which we can easily recognize because they
4540 * have mlen = 0) into send-like virtual instructions.
4542 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
4543 lower_math_logical_send(ibld
, inst
);
4558 invalidate_live_intervals();
4564 * Get the closest allowed SIMD width for instruction \p inst accounting for
4565 * some common regioning and execution control restrictions that apply to FPU
4566 * instructions. These restrictions don't necessarily have any relevance to
4567 * instructions not executed by the FPU pipeline like extended math, control
4568 * flow or send message instructions.
4570 * For virtual opcodes it's really up to the instruction -- In some cases
4571 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
4572 * instructions) it may simplify virtual instruction lowering if we can
4573 * enforce FPU-like regioning restrictions already on the virtual instruction,
4574 * in other cases (e.g. virtual send-like instructions) this may be
4575 * excessively restrictive.
4578 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
4579 const fs_inst
*inst
)
4581 /* Maximum execution size representable in the instruction controls. */
4582 unsigned max_width
= MIN2(32, inst
->exec_size
);
4584 /* According to the PRMs:
4585 * "A. In Direct Addressing mode, a source cannot span more than 2
4586 * adjacent GRF registers.
4587 * B. A destination cannot span more than 2 adjacent GRF registers."
4589 * Look for the source or destination with the largest register region
4590 * which is the one that is going to limit the overall execution size of
4591 * the instruction due to this rule.
4593 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4595 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4596 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
4598 /* Calculate the maximum execution size of the instruction based on the
4599 * factor by which it goes over the hardware limit of 2 GRFs.
4602 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
4604 /* According to the IVB PRMs:
4605 * "When destination spans two registers, the source MUST span two
4606 * registers. The exception to the above rule:
4608 * - When source is scalar, the source registers are not incremented.
4609 * - When source is packed integer Word and destination is packed
4610 * integer DWord, the source register is not incremented but the
4611 * source sub register is incremented."
4613 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
4614 * restrictions. The code below intentionally doesn't check whether the
4615 * destination type is integer because empirically the hardware doesn't
4616 * seem to care what the actual type is as long as it's dword-aligned.
4618 if (devinfo
->gen
< 8) {
4619 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
4620 /* IVB implements DF scalars as <0;2,1> regions. */
4621 const bool is_scalar_exception
= is_uniform(inst
->src
[i
]) &&
4622 (devinfo
->is_haswell
|| type_sz(inst
->src
[i
].type
) != 8);
4623 const bool is_packed_word_exception
=
4624 type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
4625 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1;
4627 if (inst
->size_written
> REG_SIZE
&&
4628 inst
->size_read(i
) != 0 && inst
->size_read(i
) <= REG_SIZE
&&
4629 !is_scalar_exception
&& !is_packed_word_exception
) {
4630 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4631 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4636 /* From the IVB PRMs:
4637 * "When an instruction is SIMD32, the low 16 bits of the execution mask
4638 * are applied for both halves of the SIMD32 instruction. If different
4639 * execution mask channels are required, split the instruction into two
4640 * SIMD16 instructions."
4642 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
4643 * 32-wide control flow support in hardware and will behave similarly.
4645 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
4646 max_width
= MIN2(max_width
, 16);
4648 /* From the IVB PRMs (applies to HSW too):
4649 * "Instructions with condition modifiers must not use SIMD32."
4651 * From the BDW PRMs (applies to later hardware too):
4652 * "Ternary instruction with condition modifiers must not use SIMD32."
4654 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
4655 max_width
= MIN2(max_width
, 16);
4657 /* From the IVB PRMs (applies to other devices that don't have the
4658 * gen_device_info::supports_simd16_3src flag set):
4659 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
4660 * SIMD8 is not allowed for DF operations."
4662 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
4663 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4665 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
4666 * the 8-bit quarter of the execution mask signals specified in the
4667 * instruction control fields) for the second compressed half of any
4668 * single-precision instruction (for double-precision instructions
4669 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
4670 * the EU will apply the wrong execution controls for the second
4671 * sequential GRF write if the number of channels per GRF is not exactly
4672 * eight in single-precision mode (or four in double-float mode).
4674 * In this situation we calculate the maximum size of the split
4675 * instructions so they only ever write to a single register.
4677 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
4678 !inst
->force_writemask_all
) {
4679 const unsigned channels_per_grf
= inst
->exec_size
/
4680 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4681 const unsigned exec_type_size
= get_exec_type_size(inst
);
4682 assert(exec_type_size
);
4684 /* The hardware shifts exactly 8 channels per compressed half of the
4685 * instruction in single-precision mode and exactly 4 in double-precision.
4687 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
4688 max_width
= MIN2(max_width
, channels_per_grf
);
4690 /* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
4691 * because HW applies the same channel enable signals to both halves of
4692 * the compressed instruction which will be just wrong under
4693 * non-uniform control flow.
4695 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4696 (exec_type_size
== 8 || type_sz(inst
->dst
.type
) == 8))
4697 max_width
= MIN2(max_width
, 4);
4700 /* Only power-of-two execution sizes are representable in the instruction
4703 return 1 << _mesa_logbase2(max_width
);
4707 * Get the maximum allowed SIMD width for instruction \p inst accounting for
4708 * various payload size restrictions that apply to sampler message
4711 * This is only intended to provide a maximum theoretical bound for the
4712 * execution size of the message based on the number of argument components
4713 * alone, which in most cases will determine whether the SIMD8 or SIMD16
4714 * variant of the message can be used, though some messages may have
4715 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
4716 * the message length to determine the exact SIMD width and argument count,
4717 * which makes a number of sampler message combinations impossible to
4721 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
4722 const fs_inst
*inst
)
4724 /* Calculate the number of coordinate components that have to be present
4725 * assuming that additional arguments follow the texel coordinates in the
4726 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
4727 * need to pad to four or three components depending on the message,
4728 * pre-ILK we need to pad to at most three components.
4730 const unsigned req_coord_components
=
4731 (devinfo
->gen
>= 7 ||
4732 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
4733 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
4734 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
4737 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
4738 * variant of the TXL or TXF message.
4740 const bool implicit_lod
= devinfo
->gen
>= 9 &&
4741 (inst
->opcode
== SHADER_OPCODE_TXL
||
4742 inst
->opcode
== SHADER_OPCODE_TXF
) &&
4743 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
4745 /* Calculate the total number of argument components that need to be passed
4746 * to the sampler unit.
4748 const unsigned num_payload_components
=
4749 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
4750 req_coord_components
) +
4751 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
4752 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
4753 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
4754 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
4755 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
4756 inst
->components_read(TEX_LOGICAL_SRC_TG4_OFFSET
) : 0) +
4757 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
4759 /* SIMD16 messages with more than five arguments exceed the maximum message
4760 * size supported by the sampler, regardless of whether a header is
4763 return MIN2(inst
->exec_size
,
4764 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
4768 * Get the closest native SIMD width supported by the hardware for instruction
4769 * \p inst. The instruction will be left untouched by
4770 * fs_visitor::lower_simd_width() if the returned value is equal to the
4771 * original execution size.
4774 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
4775 const fs_inst
*inst
)
4777 switch (inst
->opcode
) {
4778 case BRW_OPCODE_MOV
:
4779 case BRW_OPCODE_SEL
:
4780 case BRW_OPCODE_NOT
:
4781 case BRW_OPCODE_AND
:
4783 case BRW_OPCODE_XOR
:
4784 case BRW_OPCODE_SHR
:
4785 case BRW_OPCODE_SHL
:
4786 case BRW_OPCODE_ASR
:
4787 case BRW_OPCODE_CMPN
:
4788 case BRW_OPCODE_CSEL
:
4789 case BRW_OPCODE_F32TO16
:
4790 case BRW_OPCODE_F16TO32
:
4791 case BRW_OPCODE_BFREV
:
4792 case BRW_OPCODE_BFE
:
4793 case BRW_OPCODE_ADD
:
4794 case BRW_OPCODE_MUL
:
4795 case BRW_OPCODE_AVG
:
4796 case BRW_OPCODE_FRC
:
4797 case BRW_OPCODE_RNDU
:
4798 case BRW_OPCODE_RNDD
:
4799 case BRW_OPCODE_RNDE
:
4800 case BRW_OPCODE_RNDZ
:
4801 case BRW_OPCODE_LZD
:
4802 case BRW_OPCODE_FBH
:
4803 case BRW_OPCODE_FBL
:
4804 case BRW_OPCODE_CBIT
:
4805 case BRW_OPCODE_SAD2
:
4806 case BRW_OPCODE_MAD
:
4807 case BRW_OPCODE_LRP
:
4808 case FS_OPCODE_PACK
:
4809 return get_fpu_lowered_simd_width(devinfo
, inst
);
4811 case BRW_OPCODE_CMP
: {
4812 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
4813 * when the destination is a GRF the dependency-clear bit on the flag
4814 * register is cleared early.
4816 * Suggested workarounds are to disable coissuing CMP instructions
4817 * or to split CMP(16) instructions into two CMP(8) instructions.
4819 * We choose to split into CMP(8) instructions since disabling
4820 * coissuing would affect CMP instructions not otherwise affected by
4823 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4824 !inst
->dst
.is_null() ? 8 : ~0);
4825 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
4827 case BRW_OPCODE_BFI1
:
4828 case BRW_OPCODE_BFI2
:
4829 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
4831 * "Force BFI instructions to be executed always in SIMD8."
4833 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
4834 get_fpu_lowered_simd_width(devinfo
, inst
));
4837 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
4838 return inst
->exec_size
;
4840 case SHADER_OPCODE_RCP
:
4841 case SHADER_OPCODE_RSQ
:
4842 case SHADER_OPCODE_SQRT
:
4843 case SHADER_OPCODE_EXP2
:
4844 case SHADER_OPCODE_LOG2
:
4845 case SHADER_OPCODE_SIN
:
4846 case SHADER_OPCODE_COS
:
4847 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
4850 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4851 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
4852 MIN2(8, inst
->exec_size
));
4854 case SHADER_OPCODE_POW
:
4855 /* SIMD16 is only allowed on Gen7+. */
4856 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4857 MIN2(8, inst
->exec_size
));
4859 case SHADER_OPCODE_INT_QUOTIENT
:
4860 case SHADER_OPCODE_INT_REMAINDER
:
4861 /* Integer division is limited to SIMD8 on all generations. */
4862 return MIN2(8, inst
->exec_size
);
4864 case FS_OPCODE_LINTERP
:
4865 case FS_OPCODE_GET_BUFFER_SIZE
:
4866 case FS_OPCODE_DDX_COARSE
:
4867 case FS_OPCODE_DDX_FINE
:
4868 case FS_OPCODE_DDY_COARSE
:
4869 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
4870 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
4871 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
4872 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
4873 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
4874 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
4875 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
4876 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
4877 return MIN2(16, inst
->exec_size
);
4879 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4880 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
4881 * message used to implement varying pull constant loads, so expand it
4882 * to SIMD16. An alternative with longer message payload length but
4883 * shorter return payload would be to use the SIMD8 sampler message that
4884 * takes (header, u, v, r) as parameters instead of (header, u).
4886 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
4888 case FS_OPCODE_DDY_FINE
:
4889 /* The implementation of this virtual opcode may require emitting
4890 * compressed Align16 instructions, which are severely limited on some
4893 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
4894 * Region Restrictions):
4896 * "In Align16 access mode, SIMD16 is not allowed for DW operations
4897 * and SIMD8 is not allowed for DF operations."
4899 * In this context, "DW operations" means "operations acting on 32-bit
4900 * values", so it includes operations on floats.
4902 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
4903 * (Instruction Compression -> Rules and Restrictions):
4905 * "A compressed instruction must be in Align1 access mode. Align16
4906 * mode instructions cannot be compressed."
4908 * Similar text exists in the g45 PRM.
4910 * Empirically, compressed align16 instructions using odd register
4911 * numbers don't appear to work on Sandybridge either.
4913 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
4914 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
4915 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
4917 case SHADER_OPCODE_MULH
:
4918 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4919 * is 8-wide on Gen7+.
4921 return (devinfo
->gen
>= 7 ? 8 :
4922 get_fpu_lowered_simd_width(devinfo
, inst
));
4924 case FS_OPCODE_FB_WRITE_LOGICAL
:
4925 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4928 assert(devinfo
->gen
!= 6 ||
4929 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4930 inst
->exec_size
== 8);
4931 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4932 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4933 8 : MIN2(16, inst
->exec_size
));
4935 case FS_OPCODE_FB_READ_LOGICAL
:
4936 return MIN2(16, inst
->exec_size
);
4938 case SHADER_OPCODE_TEX_LOGICAL
:
4939 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4940 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4941 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4942 case SHADER_OPCODE_LOD_LOGICAL
:
4943 case SHADER_OPCODE_TG4_LOGICAL
:
4944 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4945 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4946 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4947 return get_sampler_lowered_simd_width(devinfo
, inst
);
4949 case SHADER_OPCODE_TXD_LOGICAL
:
4950 /* TXD is unsupported in SIMD16 mode. */
4953 case SHADER_OPCODE_TXL_LOGICAL
:
4954 case FS_OPCODE_TXB_LOGICAL
:
4955 /* Only one execution size is representable pre-ILK depending on whether
4956 * the shadow reference argument is present.
4958 if (devinfo
->gen
== 4)
4959 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
4961 return get_sampler_lowered_simd_width(devinfo
, inst
);
4963 case SHADER_OPCODE_TXF_LOGICAL
:
4964 case SHADER_OPCODE_TXS_LOGICAL
:
4965 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4966 * messages. Use SIMD16 instead.
4968 if (devinfo
->gen
== 4)
4971 return get_sampler_lowered_simd_width(devinfo
, inst
);
4973 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4974 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4975 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4978 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4979 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4980 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4981 return MIN2(16, inst
->exec_size
);
4983 case SHADER_OPCODE_URB_READ_SIMD8
:
4984 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
4985 case SHADER_OPCODE_URB_WRITE_SIMD8
:
4986 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
4987 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
4988 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
4989 return MIN2(8, inst
->exec_size
);
4991 case SHADER_OPCODE_MOV_INDIRECT
: {
4992 /* From IVB and HSW PRMs:
4994 * "2.When the destination requires two registers and the sources are
4995 * indirect, the sources must use 1x1 regioning mode.
4997 * In case of DF instructions in HSW/IVB, the exec_size is limited by
4998 * the EU decompression logic not handling VxH indirect addressing
5001 const unsigned max_size
= (devinfo
->gen
>= 8 ? 2 : 1) * REG_SIZE
;
5002 /* Prior to Broadwell, we only have 8 address subregisters. */
5003 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
5004 max_size
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
5008 case SHADER_OPCODE_LOAD_PAYLOAD
: {
5009 const unsigned reg_count
=
5010 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
5012 if (reg_count
> 2) {
5013 /* Only LOAD_PAYLOAD instructions with per-channel destination region
5014 * can be easily lowered (which excludes headers and heterogeneous
5017 assert(!inst
->header_size
);
5018 for (unsigned i
= 0; i
< inst
->sources
; i
++)
5019 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
5020 inst
->src
[i
].file
== BAD_FILE
);
5022 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
5024 return inst
->exec_size
;
5028 return inst
->exec_size
;
5033 * Return true if splitting out the group of channels of instruction \p inst
5034 * given by lbld.group() requires allocating a temporary for the i-th source
5035 * of the lowered instruction.
5038 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
5040 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
5041 (inst
->components_read(i
) == 1 &&
5042 lbld
.dispatch_width() <= inst
->exec_size
)) ||
5043 (inst
->flags_written() &
5044 flag_mask(inst
->src
[i
], type_sz(inst
->src
[i
].type
)));
5048 * Extract the data that would be consumed by the channel group given by
5049 * lbld.group() from the i-th source region of instruction \p inst and return
5050 * it as result in packed form.
5053 emit_unzip(const fs_builder
&lbld
, fs_inst
*inst
, unsigned i
)
5055 /* Specified channel group from the source region. */
5056 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group());
5058 if (needs_src_copy(lbld
, inst
, i
)) {
5059 /* Builder of the right width to perform the copy avoiding uninitialized
5060 * data if the lowered execution size is greater than the original
5061 * execution size of the instruction.
5063 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5064 inst
->exec_size
), 0);
5065 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
5067 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
5068 cbld
.MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
5072 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
5073 /* The source is invariant for all dispatch_width-wide groups of the
5076 return inst
->src
[i
];
5079 /* We can just point the lowered instruction at the right channel group
5080 * from the original region.
5087 * Return true if splitting out the group of channels of instruction \p inst
5088 * given by lbld.group() requires allocating a temporary for the destination
5089 * of the lowered instruction and copying the data back to the original
5090 * destination region.
5093 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
5095 /* If the instruction writes more than one component we'll have to shuffle
5096 * the results of multiple lowered instructions in order to make sure that
5097 * they end up arranged correctly in the original destination region.
5099 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
5102 /* If the lowered execution size is larger than the original the result of
5103 * the instruction won't fit in the original destination, so we'll have to
5104 * allocate a temporary in any case.
5106 if (lbld
.dispatch_width() > inst
->exec_size
)
5109 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5110 /* If we already made a copy of the source for other reasons there won't
5111 * be any overlap with the destination.
5113 if (needs_src_copy(lbld
, inst
, i
))
5116 /* In order to keep the logic simple we emit a copy whenever the
5117 * destination region doesn't exactly match an overlapping source, which
5118 * may point at the source and destination not being aligned group by
5119 * group which could cause one of the lowered instructions to overwrite
5120 * the data read from the same source by other lowered instructions.
5122 if (regions_overlap(inst
->dst
, inst
->size_written
,
5123 inst
->src
[i
], inst
->size_read(i
)) &&
5124 !inst
->dst
.equals(inst
->src
[i
]))
5132 * Insert data from a packed temporary into the channel group given by
5133 * lbld.group() of the destination region of instruction \p inst and return
5134 * the temporary as result. Any copy instructions that are required for
5135 * unzipping the previous value (in the case of partial writes) will be
5136 * inserted using \p lbld_before and any copy instructions required for
5137 * zipping up the destination of \p inst will be inserted using \p lbld_after.
5140 emit_zip(const fs_builder
&lbld_before
, const fs_builder
&lbld_after
,
5143 assert(lbld_before
.dispatch_width() == lbld_after
.dispatch_width());
5144 assert(lbld_before
.group() == lbld_after
.group());
5146 /* Specified channel group from the destination region. */
5147 const fs_reg dst
= horiz_offset(inst
->dst
, lbld_after
.group());
5148 const unsigned dst_size
= inst
->size_written
/
5149 inst
->dst
.component_size(inst
->exec_size
);
5151 if (needs_dst_copy(lbld_after
, inst
)) {
5152 const fs_reg tmp
= lbld_after
.vgrf(inst
->dst
.type
, dst_size
);
5154 if (inst
->predicate
) {
5155 /* Handle predication by copying the original contents of
5156 * the destination into the temporary before emitting the
5157 * lowered instruction.
5159 const fs_builder gbld_before
=
5160 lbld_before
.group(MIN2(lbld_before
.dispatch_width(),
5161 inst
->exec_size
), 0);
5162 for (unsigned k
= 0; k
< dst_size
; ++k
) {
5163 gbld_before
.MOV(offset(tmp
, lbld_before
, k
),
5164 offset(dst
, inst
->exec_size
, k
));
5168 const fs_builder gbld_after
=
5169 lbld_after
.group(MIN2(lbld_after
.dispatch_width(),
5170 inst
->exec_size
), 0);
5171 for (unsigned k
= 0; k
< dst_size
; ++k
) {
5172 /* Use a builder of the right width to perform the copy avoiding
5173 * uninitialized data if the lowered execution size is greater than
5174 * the original execution size of the instruction.
5176 gbld_after
.MOV(offset(dst
, inst
->exec_size
, k
),
5177 offset(tmp
, lbld_after
, k
));
5183 /* No need to allocate a temporary for the lowered instruction, just
5184 * take the right group of channels from the original region.
5191 fs_visitor::lower_simd_width()
5193 bool progress
= false;
5195 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5196 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5198 if (lower_width
!= inst
->exec_size
) {
5199 /* Builder matching the original instruction. We may also need to
5200 * emit an instruction of width larger than the original, set the
5201 * execution size of the builder to the highest of both for now so
5202 * we're sure that both cases can be handled.
5204 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5205 const fs_builder ibld
= bld
.at(block
, inst
)
5206 .exec_all(inst
->force_writemask_all
)
5207 .group(max_width
, inst
->group
/ max_width
);
5209 /* Split the copies in chunks of the execution width of either the
5210 * original or the lowered instruction, whichever is lower.
5212 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5213 const unsigned dst_size
= inst
->size_written
/
5214 inst
->dst
.component_size(inst
->exec_size
);
5216 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5218 /* Inserting the zip, unzip, and duplicated instructions in all of
5219 * the right spots is somewhat tricky. All of the unzip and any
5220 * instructions from the zip which unzip the destination prior to
5221 * writing need to happen before all of the per-group instructions
5222 * and the zip instructions need to happen after. In order to sort
5223 * this all out, we insert the unzip instructions before \p inst,
5224 * insert the per-group instructions after \p inst (i.e. before
5225 * inst->next), and insert the zip instructions before the
5226 * instruction after \p inst. Since we are inserting instructions
5227 * after \p inst, inst->next is a moving target and we need to save
5228 * it off here so that we insert the zip instructions in the right
5231 exec_node
*const after_inst
= inst
->next
;
5232 for (unsigned i
= 0; i
< n
; i
++) {
5233 /* Emit a copy of the original instruction with the lowered width.
5234 * If the EOT flag was set throw it away except for the last
5235 * instruction to avoid killing the thread prematurely.
5237 fs_inst split_inst
= *inst
;
5238 split_inst
.exec_size
= lower_width
;
5239 split_inst
.eot
= inst
->eot
&& i
== 0;
5241 /* Select the correct channel enables for the i-th group, then
5242 * transform the sources and destination and emit the lowered
5245 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5247 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5248 split_inst
.src
[j
] = emit_unzip(lbld
.at(block
, inst
), inst
, j
);
5250 split_inst
.dst
= emit_zip(lbld
.at(block
, inst
),
5251 lbld
.at(block
, after_inst
), inst
);
5252 split_inst
.size_written
=
5253 split_inst
.dst
.component_size(lower_width
) * dst_size
;
5255 lbld
.at(block
, inst
->next
).emit(split_inst
);
5258 inst
->remove(block
);
5264 invalidate_live_intervals();
5270 fs_visitor::dump_instructions()
5272 dump_instructions(NULL
);
5276 fs_visitor::dump_instructions(const char *name
)
5278 FILE *file
= stderr
;
5279 if (name
&& geteuid() != 0) {
5280 file
= fopen(name
, "w");
5286 calculate_register_pressure();
5287 int ip
= 0, max_pressure
= 0;
5288 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5289 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5290 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5291 dump_instruction(inst
, file
);
5294 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5297 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5298 fprintf(file
, "%4d: ", ip
++);
5299 dump_instruction(inst
, file
);
5303 if (file
!= stderr
) {
5309 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5311 dump_instruction(be_inst
, stderr
);
5315 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5317 fs_inst
*inst
= (fs_inst
*)be_inst
;
5319 if (inst
->predicate
) {
5320 fprintf(file
, "(%cf0.%d) ",
5321 inst
->predicate_inverse
? '-' : '+',
5325 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5327 fprintf(file
, ".sat");
5328 if (inst
->conditional_mod
) {
5329 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5330 if (!inst
->predicate
&&
5331 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5332 inst
->opcode
!= BRW_OPCODE_IF
&&
5333 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5334 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
5337 fprintf(file
, "(%d) ", inst
->exec_size
);
5340 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5344 fprintf(file
, "(EOT) ");
5347 switch (inst
->dst
.file
) {
5349 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
5352 fprintf(file
, "g%d", inst
->dst
.nr
);
5355 fprintf(file
, "m%d", inst
->dst
.nr
);
5358 fprintf(file
, "(null)");
5361 fprintf(file
, "***u%d***", inst
->dst
.nr
);
5364 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
5367 switch (inst
->dst
.nr
) {
5369 fprintf(file
, "null");
5371 case BRW_ARF_ADDRESS
:
5372 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
5374 case BRW_ARF_ACCUMULATOR
:
5375 fprintf(file
, "acc%d", inst
->dst
.subnr
);
5378 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5381 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5386 unreachable("not reached");
5389 if (inst
->dst
.offset
||
5390 (inst
->dst
.file
== VGRF
&&
5391 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
5392 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
5393 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
5394 inst
->dst
.offset
% reg_size
);
5397 if (inst
->dst
.stride
!= 1)
5398 fprintf(file
, "<%u>", inst
->dst
.stride
);
5399 fprintf(file
, ":%s, ", brw_reg_type_to_letters(inst
->dst
.type
));
5401 for (int i
= 0; i
< inst
->sources
; i
++) {
5402 if (inst
->src
[i
].negate
)
5404 if (inst
->src
[i
].abs
)
5406 switch (inst
->src
[i
].file
) {
5408 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
5411 fprintf(file
, "g%d", inst
->src
[i
].nr
);
5414 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
5417 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
5420 fprintf(file
, "u%d", inst
->src
[i
].nr
);
5423 fprintf(file
, "(null)");
5426 switch (inst
->src
[i
].type
) {
5427 case BRW_REGISTER_TYPE_F
:
5428 fprintf(file
, "%-gf", inst
->src
[i
].f
);
5430 case BRW_REGISTER_TYPE_DF
:
5431 fprintf(file
, "%fdf", inst
->src
[i
].df
);
5433 case BRW_REGISTER_TYPE_W
:
5434 case BRW_REGISTER_TYPE_D
:
5435 fprintf(file
, "%dd", inst
->src
[i
].d
);
5437 case BRW_REGISTER_TYPE_UW
:
5438 case BRW_REGISTER_TYPE_UD
:
5439 fprintf(file
, "%uu", inst
->src
[i
].ud
);
5441 case BRW_REGISTER_TYPE_VF
:
5442 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
5443 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
5444 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
5445 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
5446 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5449 fprintf(file
, "???");
5454 switch (inst
->src
[i
].nr
) {
5456 fprintf(file
, "null");
5458 case BRW_ARF_ADDRESS
:
5459 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5461 case BRW_ARF_ACCUMULATOR
:
5462 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5465 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5468 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5474 if (inst
->src
[i
].offset
||
5475 (inst
->src
[i
].file
== VGRF
&&
5476 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
5477 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
5478 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
5479 inst
->src
[i
].offset
% reg_size
);
5482 if (inst
->src
[i
].abs
)
5485 if (inst
->src
[i
].file
!= IMM
) {
5487 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5488 unsigned hstride
= inst
->src
[i
].hstride
;
5489 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5491 stride
= inst
->src
[i
].stride
;
5494 fprintf(file
, "<%u>", stride
);
5496 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
5499 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5500 fprintf(file
, ", ");
5505 if (inst
->force_writemask_all
)
5506 fprintf(file
, "NoMask ");
5508 if (inst
->exec_size
!= dispatch_width
)
5509 fprintf(file
, "group%d ", inst
->group
);
5511 fprintf(file
, "\n");
5515 * Possibly returns an instruction that set up @param reg.
5517 * Sometimes we want to take the result of some expression/variable
5518 * dereference tree and rewrite the instruction generating the result
5519 * of the tree. When processing the tree, we know that the
5520 * instructions generated are all writing temporaries that are dead
5521 * outside of this tree. So, if we have some instructions that write
5522 * a temporary, we're free to point that temp write somewhere else.
5524 * Note that this doesn't guarantee that the instruction generated
5525 * only reg -- it might be the size=4 destination of a texture instruction.
5528 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5533 end
->is_partial_write() ||
5534 !reg
.equals(end
->dst
)) {
5542 fs_visitor::setup_fs_payload_gen6()
5544 assert(stage
== MESA_SHADER_FRAGMENT
);
5545 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
5547 assert(devinfo
->gen
>= 6);
5549 /* R0-1: masks, pixel X/Y coordinates. */
5550 payload
.num_regs
= 2;
5551 /* R2: only for 32-pixel dispatch.*/
5553 /* R3-26: barycentric interpolation coordinates. These appear in the
5554 * same order that they appear in the brw_barycentric_mode
5555 * enum. Each set of coordinates occupies 2 registers if dispatch width
5556 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5557 * appear if they were enabled using the "Barycentric Interpolation
5558 * Mode" bits in WM_STATE.
5560 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
5561 if (prog_data
->barycentric_interp_modes
& (1 << i
)) {
5562 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5563 payload
.num_regs
+= 2;
5564 if (dispatch_width
== 16) {
5565 payload
.num_regs
+= 2;
5570 /* R27: interpolated depth if uses source depth */
5571 prog_data
->uses_src_depth
=
5572 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5573 if (prog_data
->uses_src_depth
) {
5574 payload
.source_depth_reg
= payload
.num_regs
;
5576 if (dispatch_width
== 16) {
5577 /* R28: interpolated depth if not SIMD8. */
5582 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5583 prog_data
->uses_src_w
=
5584 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5585 if (prog_data
->uses_src_w
) {
5586 payload
.source_w_reg
= payload
.num_regs
;
5588 if (dispatch_width
== 16) {
5589 /* R30: interpolated W if not SIMD8. */
5594 /* R31: MSAA position offsets. */
5595 if (prog_data
->persample_dispatch
&&
5596 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
)) {
5597 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
5599 * "MSDISPMODE_PERSAMPLE is required in order to select
5602 * So we can only really get sample positions if we are doing real
5603 * per-sample dispatch. If we need gl_SamplePosition and we don't have
5604 * persample dispatch, we hard-code it to 0.5.
5606 prog_data
->uses_pos_offset
= true;
5607 payload
.sample_pos_reg
= payload
.num_regs
;
5611 /* R32: MSAA input coverage mask */
5612 prog_data
->uses_sample_mask
=
5613 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5614 if (prog_data
->uses_sample_mask
) {
5615 assert(devinfo
->gen
>= 7);
5616 payload
.sample_mask_in_reg
= payload
.num_regs
;
5618 if (dispatch_width
== 16) {
5619 /* R33: input coverage mask if not SIMD8. */
5624 /* R34-: bary for 32-pixel. */
5625 /* R58-59: interp W for 32-pixel. */
5627 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5628 source_depth_to_render_target
= true;
5633 fs_visitor::setup_vs_payload()
5635 /* R0: thread header, R1: urb handles */
5636 payload
.num_regs
= 2;
5640 fs_visitor::setup_gs_payload()
5642 assert(stage
== MESA_SHADER_GEOMETRY
);
5644 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
5645 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
5647 /* R0: thread header, R1: output URB handles */
5648 payload
.num_regs
= 2;
5650 if (gs_prog_data
->include_primitive_id
) {
5651 /* R2: Primitive ID 0..7 */
5655 /* Always enable VUE handles so we can safely use pull model if needed.
5657 * The push model for a GS uses a ton of register space even for trivial
5658 * scenarios with just a few inputs, so just make things easier and a bit
5659 * safer by always having pull model available.
5661 gs_prog_data
->base
.include_vue_handles
= true;
5663 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5664 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5666 /* Use a maximum of 24 registers for push-model inputs. */
5667 const unsigned max_push_components
= 24;
5669 /* If pushing our inputs would take too many registers, reduce the URB read
5670 * length (which is in HWords, or 8 registers), and resort to pulling.
5672 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5673 * have to multiply by VerticesIn to obtain the total storage requirement.
5675 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5676 max_push_components
) {
5677 vue_prog_data
->urb_read_length
=
5678 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5683 fs_visitor::setup_cs_payload()
5685 assert(devinfo
->gen
>= 7);
5686 payload
.num_regs
= 1;
5690 fs_visitor::calculate_register_pressure()
5692 invalidate_live_intervals();
5693 calculate_live_intervals();
5695 unsigned num_instructions
= 0;
5696 foreach_block(block
, cfg
)
5697 num_instructions
+= block
->instructions
.length();
5699 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5701 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5702 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5703 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5708 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
5710 * The needs_unlit_centroid_workaround ends up producing one of these per
5711 * channel of centroid input, so it's good to clean them up.
5713 * An assumption here is that nothing ever modifies the dispatched pixels
5714 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
5715 * dictates that anyway.
5718 fs_visitor::opt_drop_redundant_mov_to_flags()
5720 bool flag_mov_found
[2] = {false};
5721 bool progress
= false;
5723 /* Instructions removed by this pass can only be added if this were true */
5724 if (!devinfo
->needs_unlit_centroid_workaround
)
5727 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5728 if (inst
->is_control_flow()) {
5729 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
5730 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
5731 if (!flag_mov_found
[inst
->flag_subreg
]) {
5732 flag_mov_found
[inst
->flag_subreg
] = true;
5734 inst
->remove(block
);
5737 } else if (inst
->flags_written()) {
5738 flag_mov_found
[inst
->flag_subreg
] = false;
5746 fs_visitor::optimize()
5748 /* Start by validating the shader we currently have. */
5751 /* bld is the common builder object pointing at the end of the program we
5752 * used to translate it into i965 IR. For the optimization and lowering
5753 * passes coming next, any code added after the end of the program without
5754 * having explicitly called fs_builder::at() clearly points at a mistake.
5755 * Ideally optimization passes wouldn't be part of the visitor so they
5756 * wouldn't have access to bld at all, but they do, so just in case some
5757 * pass forgets to ask for a location explicitly set it to NULL here to
5758 * make it trip. The dispatch width is initialized to a bogus value to
5759 * make sure that optimizations set the execution controls explicitly to
5760 * match the code they are manipulating instead of relying on the defaults.
5762 bld
= fs_builder(this, 64);
5764 assign_constant_locations();
5765 lower_constant_loads();
5769 split_virtual_grfs();
5772 #define OPT(pass, args...) ({ \
5774 bool this_progress = pass(args); \
5776 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5777 char filename[64]; \
5778 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5779 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5781 backend_shader::dump_instructions(filename); \
5786 progress = progress || this_progress; \
5790 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5792 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5793 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5795 backend_shader::dump_instructions(filename
);
5798 bool progress
= false;
5802 OPT(opt_drop_redundant_mov_to_flags
);
5809 OPT(remove_duplicate_mrf_writes
);
5813 OPT(opt_copy_propagation
);
5814 OPT(opt_predicated_break
, this);
5815 OPT(opt_cmod_propagation
);
5816 OPT(dead_code_eliminate
);
5817 OPT(opt_peephole_sel
);
5818 OPT(dead_control_flow_eliminate
, this);
5819 OPT(opt_register_renaming
);
5820 OPT(opt_saturate_propagation
);
5821 OPT(register_coalesce
);
5822 OPT(compute_to_mrf
);
5823 OPT(eliminate_find_live_channel
);
5825 OPT(compact_virtual_grfs
);
5831 if (OPT(lower_pack
)) {
5832 OPT(register_coalesce
);
5833 OPT(dead_code_eliminate
);
5836 OPT(lower_simd_width
);
5838 /* After SIMD lowering just in case we had to unroll the EOT send. */
5839 OPT(opt_sampler_eot
);
5841 OPT(lower_logical_sends
);
5844 OPT(opt_copy_propagation
);
5845 /* Only run after logical send lowering because it's easier to implement
5846 * in terms of physical sends.
5848 if (OPT(opt_zero_samples
))
5849 OPT(opt_copy_propagation
);
5850 /* Run after logical send lowering to give it a chance to CSE the
5851 * LOAD_PAYLOAD instructions created to construct the payloads of
5852 * e.g. texturing messages in cases where it wasn't possible to CSE the
5853 * whole logical instruction.
5856 OPT(register_coalesce
);
5857 OPT(compute_to_mrf
);
5858 OPT(dead_code_eliminate
);
5859 OPT(remove_duplicate_mrf_writes
);
5860 OPT(opt_peephole_sel
);
5863 OPT(opt_redundant_discard_jumps
);
5865 if (OPT(lower_load_payload
)) {
5866 split_virtual_grfs();
5867 OPT(register_coalesce
);
5868 OPT(compute_to_mrf
);
5869 OPT(dead_code_eliminate
);
5872 OPT(opt_combine_constants
);
5873 OPT(lower_integer_multiplication
);
5875 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5876 OPT(opt_cmod_propagation
);
5878 OPT(opt_copy_propagation
);
5879 OPT(dead_code_eliminate
);
5882 if (OPT(lower_conversions
)) {
5883 OPT(opt_copy_propagation
);
5884 OPT(dead_code_eliminate
);
5885 OPT(lower_simd_width
);
5888 lower_uniform_pull_constant_loads();
5894 * Three source instruction must have a GRF/MRF destination register.
5895 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5898 fs_visitor::fixup_3src_null_dest()
5900 bool progress
= false;
5902 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5903 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
5904 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5911 invalidate_live_intervals();
5915 fs_visitor::allocate_registers(unsigned min_dispatch_width
, bool allow_spilling
)
5917 bool allocated_without_spills
;
5919 static const enum instruction_scheduler_mode pre_modes
[] = {
5921 SCHEDULE_PRE_NON_LIFO
,
5925 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
5927 /* Try each scheduling heuristic to see if it can successfully register
5928 * allocate without spilling. They should be ordered by decreasing
5929 * performance but increasing likelihood of allocating.
5931 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5932 schedule_instructions(pre_modes
[i
]);
5935 assign_regs_trivial();
5936 allocated_without_spills
= true;
5938 allocated_without_spills
= assign_regs(false, spill_all
);
5940 if (allocated_without_spills
)
5944 if (!allocated_without_spills
) {
5945 if (!allow_spilling
)
5946 fail("Failure to register allocate and spilling is not allowed.");
5948 /* We assume that any spilling is worse than just dropping back to
5949 * SIMD8. There's probably actually some intermediate point where
5950 * SIMD16 with a couple of spills is still better.
5952 if (dispatch_width
> min_dispatch_width
) {
5953 fail("Failure to register allocate. Reduce number of "
5954 "live scalar values to avoid this.");
5956 compiler
->shader_perf_log(log_data
,
5957 "%s shader triggered register spilling. "
5958 "Try reducing the number of live scalar "
5959 "values to improve performance.\n",
5963 /* Since we're out of heuristics, just go spill registers until we
5964 * get an allocation.
5966 while (!assign_regs(true, spill_all
)) {
5972 /* This must come after all optimization and register allocation, since
5973 * it inserts dead code that happens to have side effects, and it does
5974 * so based on the actual physical registers in use.
5976 insert_gen4_send_dependency_workarounds();
5981 schedule_instructions(SCHEDULE_POST
);
5983 if (last_scratch
> 0) {
5984 MAYBE_UNUSED
unsigned max_scratch_size
= 2 * 1024 * 1024;
5986 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5988 if (stage
== MESA_SHADER_COMPUTE
) {
5989 if (devinfo
->is_haswell
) {
5990 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5991 * field documentation, Haswell supports a minimum of 2kB of
5992 * scratch space for compute shaders, unlike every other stage
5995 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
5996 } else if (devinfo
->gen
<= 7) {
5997 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5998 * field documentation, platforms prior to Haswell measure scratch
5999 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
6001 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
6002 max_scratch_size
= 12 * 1024;
6006 /* We currently only support up to 2MB of scratch space. If we
6007 * need to support more eventually, the documentation suggests
6008 * that we could allocate a larger buffer, and partition it out
6009 * ourselves. We'd just have to undo the hardware's address
6010 * calculation by subtracting (FFTID * Per Thread Scratch Space)
6011 * and then add FFTID * (Larger Per Thread Scratch Space).
6013 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
6014 * Thread Group Tracking > Local Memory/Scratch Space.
6016 assert(prog_data
->total_scratch
< max_scratch_size
);
6021 fs_visitor::run_vs()
6023 assert(stage
== MESA_SHADER_VERTEX
);
6027 if (shader_time_index
>= 0)
6028 emit_shader_time_begin();
6035 compute_clip_distance();
6039 if (shader_time_index
>= 0)
6040 emit_shader_time_end();
6046 assign_curb_setup();
6047 assign_vs_urb_setup();
6049 fixup_3src_null_dest();
6050 allocate_registers(8, true);
6056 fs_visitor::run_tcs_single_patch()
6058 assert(stage
== MESA_SHADER_TESS_CTRL
);
6060 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
6062 /* r1-r4 contain the ICP handles. */
6063 payload
.num_regs
= 5;
6065 if (shader_time_index
>= 0)
6066 emit_shader_time_begin();
6068 /* Initialize gl_InvocationID */
6069 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
6070 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6071 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
6072 bld
.MOV(channels_ud
, channels_uw
);
6074 if (tcs_prog_data
->instances
== 1) {
6075 invocation_id
= channels_ud
;
6077 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6079 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
6080 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6081 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6082 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
6083 brw_imm_ud(INTEL_MASK(23, 17)));
6084 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
6086 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
6089 /* Fix the disptach mask */
6090 if (nir
->info
.tess
.tcs_vertices_out
% 8) {
6091 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
6092 brw_imm_ud(nir
->info
.tess
.tcs_vertices_out
), BRW_CONDITIONAL_L
);
6093 bld
.IF(BRW_PREDICATE_NORMAL
);
6098 if (nir
->info
.tess
.tcs_vertices_out
% 8) {
6099 bld
.emit(BRW_OPCODE_ENDIF
);
6102 /* Emit EOT write; set TR DS Cache bit */
6104 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
6105 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
6106 fs_reg(brw_imm_ud(0)),
6108 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
6109 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
6111 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
6112 bld
.null_reg_ud(), payload
);
6116 if (shader_time_index
>= 0)
6117 emit_shader_time_end();
6126 assign_curb_setup();
6127 assign_tcs_single_patch_urb_setup();
6129 fixup_3src_null_dest();
6130 allocate_registers(8, true);
6136 fs_visitor::run_tes()
6138 assert(stage
== MESA_SHADER_TESS_EVAL
);
6140 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6141 payload
.num_regs
= 5;
6143 if (shader_time_index
>= 0)
6144 emit_shader_time_begin();
6153 if (shader_time_index
>= 0)
6154 emit_shader_time_end();
6160 assign_curb_setup();
6161 assign_tes_urb_setup();
6163 fixup_3src_null_dest();
6164 allocate_registers(8, true);
6170 fs_visitor::run_gs()
6172 assert(stage
== MESA_SHADER_GEOMETRY
);
6176 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6178 if (gs_compile
->control_data_header_size_bits
> 0) {
6179 /* Create a VGRF to store accumulated control data bits. */
6180 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6182 /* If we're outputting more than 32 control data bits, then EmitVertex()
6183 * will set control_data_bits to 0 after emitting the first vertex.
6184 * Otherwise, we need to initialize it to 0 here.
6186 if (gs_compile
->control_data_header_size_bits
<= 32) {
6187 const fs_builder abld
= bld
.annotate("initialize control data bits");
6188 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6192 if (shader_time_index
>= 0)
6193 emit_shader_time_begin();
6197 emit_gs_thread_end();
6199 if (shader_time_index
>= 0)
6200 emit_shader_time_end();
6209 assign_curb_setup();
6210 assign_gs_urb_setup();
6212 fixup_3src_null_dest();
6213 allocate_registers(8, true);
6218 /* From the SKL PRM, Volume 16, Workarounds:
6220 * 0877 3D Pixel Shader Hang possible when pixel shader dispatched with
6221 * only header phases (R0-R2)
6223 * WA: Enable a non-header phase (e.g. push constant) when dispatch would
6224 * have been header only.
6226 * Instead of enabling push constants one can alternatively enable one of the
6227 * inputs. Here one simply chooses "layer" which shouldn't impose much
6231 gen9_ps_header_only_workaround(struct brw_wm_prog_data
*wm_prog_data
)
6233 if (wm_prog_data
->num_varying_inputs
)
6236 if (wm_prog_data
->base
.curb_read_length
)
6239 wm_prog_data
->urb_setup
[VARYING_SLOT_LAYER
] = 0;
6240 wm_prog_data
->num_varying_inputs
= 1;
6244 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6246 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
6247 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6249 assert(stage
== MESA_SHADER_FRAGMENT
);
6251 if (devinfo
->gen
>= 6)
6252 setup_fs_payload_gen6();
6254 setup_fs_payload_gen4();
6258 } else if (do_rep_send
) {
6259 assert(dispatch_width
== 16);
6260 emit_repclear_shader();
6262 if (shader_time_index
>= 0)
6263 emit_shader_time_begin();
6265 calculate_urb_setup();
6266 if (nir
->info
.inputs_read
> 0 ||
6267 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
6268 if (devinfo
->gen
< 6)
6269 emit_interpolation_setup_gen4();
6271 emit_interpolation_setup_gen6();
6274 /* We handle discards by keeping track of the still-live pixels in f0.1.
6275 * Initialize it with the dispatched pixels.
6277 if (wm_prog_data
->uses_kill
) {
6278 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
6279 discard_init
->flag_subreg
= 1;
6282 /* Generate FS IR for main(). (the visitor only descends into
6283 * functions called "main").
6290 if (wm_prog_data
->uses_kill
)
6291 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6293 if (wm_key
->alpha_test_func
)
6298 if (shader_time_index
>= 0)
6299 emit_shader_time_end();
6305 assign_curb_setup();
6307 if (devinfo
->gen
>= 9)
6308 gen9_ps_header_only_workaround(wm_prog_data
);
6312 fixup_3src_null_dest();
6313 allocate_registers(8, allow_spilling
);
6323 fs_visitor::run_cs(unsigned min_dispatch_width
)
6325 assert(stage
== MESA_SHADER_COMPUTE
);
6326 assert(dispatch_width
>= min_dispatch_width
);
6330 if (shader_time_index
>= 0)
6331 emit_shader_time_begin();
6333 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6334 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6335 const fs_builder abld
= bld
.exec_all().group(1, 0);
6336 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
6337 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6345 emit_cs_terminate();
6347 if (shader_time_index
>= 0)
6348 emit_shader_time_end();
6354 assign_curb_setup();
6356 fixup_3src_null_dest();
6357 allocate_registers(min_dispatch_width
, true);
6366 * Return a bitfield where bit n is set if barycentric interpolation mode n
6367 * (see enum brw_barycentric_mode) is needed by the fragment shader.
6369 * We examine the load_barycentric intrinsics rather than looking at input
6370 * variables so that we catch interpolateAtCentroid() messages too, which
6371 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
6374 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
6375 const nir_shader
*shader
)
6377 unsigned barycentric_interp_modes
= 0;
6379 nir_foreach_function(f
, shader
) {
6383 nir_foreach_block(block
, f
->impl
) {
6384 nir_foreach_instr(instr
, block
) {
6385 if (instr
->type
!= nir_instr_type_intrinsic
)
6388 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6389 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6392 /* Ignore WPOS; it doesn't require interpolation. */
6393 if (nir_intrinsic_base(intrin
) == VARYING_SLOT_POS
)
6396 intrin
= nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6397 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
6398 nir_intrinsic_interp_mode(intrin
);
6399 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
6400 enum brw_barycentric_mode bary
=
6401 brw_barycentric_mode(interp
, bary_op
);
6403 barycentric_interp_modes
|= 1 << bary
;
6405 if (devinfo
->needs_unlit_centroid_workaround
&&
6406 bary_op
== nir_intrinsic_load_barycentric_centroid
)
6407 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
6412 return barycentric_interp_modes
;
6416 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
6417 const nir_shader
*shader
)
6419 prog_data
->flat_inputs
= 0;
6421 nir_foreach_variable(var
, &shader
->inputs
) {
6422 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
6424 if (input_index
< 0)
6428 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6429 prog_data
->flat_inputs
|= (1 << input_index
);
6434 computed_depth_mode(const nir_shader
*shader
)
6436 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6437 switch (shader
->info
.fs
.depth_layout
) {
6438 case FRAG_DEPTH_LAYOUT_NONE
:
6439 case FRAG_DEPTH_LAYOUT_ANY
:
6440 return BRW_PSCDEPTH_ON
;
6441 case FRAG_DEPTH_LAYOUT_GREATER
:
6442 return BRW_PSCDEPTH_ON_GE
;
6443 case FRAG_DEPTH_LAYOUT_LESS
:
6444 return BRW_PSCDEPTH_ON_LE
;
6445 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
6446 return BRW_PSCDEPTH_OFF
;
6449 return BRW_PSCDEPTH_OFF
;
6453 * Move load_interpolated_input with simple (payload-based) barycentric modes
6454 * to the top of the program so we don't emit multiple PLNs for the same input.
6456 * This works around CSE not being able to handle non-dominating cases
6462 * interpolate the same exact input
6465 * This should be replaced by global value numbering someday.
6468 move_interpolation_to_top(nir_shader
*nir
)
6470 bool progress
= false;
6472 nir_foreach_function(f
, nir
) {
6476 nir_block
*top
= nir_start_block(f
->impl
);
6477 exec_node
*cursor_node
= NULL
;
6479 nir_foreach_block(block
, f
->impl
) {
6483 nir_foreach_instr_safe(instr
, block
) {
6484 if (instr
->type
!= nir_instr_type_intrinsic
)
6487 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6488 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6490 nir_intrinsic_instr
*bary_intrinsic
=
6491 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6492 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
6494 /* Leave interpolateAtSample/Offset() where they are. */
6495 if (op
== nir_intrinsic_load_barycentric_at_sample
||
6496 op
== nir_intrinsic_load_barycentric_at_offset
)
6499 nir_instr
*move
[3] = {
6500 &bary_intrinsic
->instr
,
6501 intrin
->src
[1].ssa
->parent_instr
,
6505 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
6506 if (move
[i
]->block
!= top
) {
6507 move
[i
]->block
= top
;
6508 exec_node_remove(&move
[i
]->node
);
6510 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
6512 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
6514 cursor_node
= &move
[i
]->node
;
6520 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6521 ((unsigned) nir_metadata_block_index
|
6522 (unsigned) nir_metadata_dominance
));
6529 * Demote per-sample barycentric intrinsics to centroid.
6531 * Useful when rendering to a non-multisampled buffer.
6534 demote_sample_qualifiers(nir_shader
*nir
)
6536 bool progress
= true;
6538 nir_foreach_function(f
, nir
) {
6543 nir_builder_init(&b
, f
->impl
);
6545 nir_foreach_block(block
, f
->impl
) {
6546 nir_foreach_instr_safe(instr
, block
) {
6547 if (instr
->type
!= nir_instr_type_intrinsic
)
6550 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6551 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
6552 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
6555 b
.cursor
= nir_before_instr(instr
);
6556 nir_ssa_def
*centroid
=
6557 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
6558 nir_intrinsic_interp_mode(intrin
));
6559 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
6560 nir_src_for_ssa(centroid
));
6561 nir_instr_remove(instr
);
6566 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6567 ((unsigned) nir_metadata_block_index
|
6568 (unsigned) nir_metadata_dominance
));
6575 * Pre-gen6, the register file of the EUs was shared between threads,
6576 * and each thread used some subset allocated on a 16-register block
6577 * granularity. The unit states wanted these block counts.
6580 brw_register_blocks(int reg_count
)
6582 return ALIGN(reg_count
, 16) / 16 - 1;
6586 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
6588 const struct brw_wm_prog_key
*key
,
6589 struct brw_wm_prog_data
*prog_data
,
6590 const nir_shader
*src_shader
,
6591 struct gl_program
*prog
,
6592 int shader_time_index8
, int shader_time_index16
,
6593 bool allow_spilling
,
6594 bool use_rep_send
, struct brw_vue_map
*vue_map
,
6597 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
6599 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6600 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, true);
6601 brw_nir_lower_fs_inputs(shader
, devinfo
, key
);
6602 brw_nir_lower_fs_outputs(shader
);
6604 if (devinfo
->gen
< 6) {
6605 brw_setup_vue_interpolation(vue_map
, shader
, prog_data
, devinfo
);
6608 if (!key
->multisample_fbo
)
6609 NIR_PASS_V(shader
, demote_sample_qualifiers
);
6610 NIR_PASS_V(shader
, move_interpolation_to_top
);
6611 shader
= brw_postprocess_nir(shader
, compiler
, true);
6613 /* key->alpha_test_func means simulating alpha testing via discards,
6614 * so the shader definitely kills pixels.
6616 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
||
6617 key
->alpha_test_func
;
6618 prog_data
->uses_omask
= key
->multisample_fbo
&&
6619 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
6620 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
6621 prog_data
->computed_stencil
=
6622 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
6624 prog_data
->persample_dispatch
=
6625 key
->multisample_fbo
&&
6626 (key
->persample_interp
||
6627 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
6628 SYSTEM_BIT_SAMPLE_POS
)) ||
6629 shader
->info
.fs
.uses_sample_qualifier
||
6630 shader
->info
.outputs_read
);
6632 prog_data
->has_render_target_reads
= shader
->info
.outputs_read
!= 0ull;
6634 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
6635 prog_data
->post_depth_coverage
= shader
->info
.fs
.post_depth_coverage
;
6636 prog_data
->inner_coverage
= shader
->info
.fs
.inner_coverage
;
6638 prog_data
->barycentric_interp_modes
=
6639 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
6641 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
;
6642 uint8_t simd8_grf_start
= 0, simd16_grf_start
= 0;
6643 unsigned simd8_grf_used
= 0, simd16_grf_used
= 0;
6645 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
6646 &prog_data
->base
, prog
, shader
, 8,
6647 shader_time_index8
);
6648 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
6650 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
6653 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
6655 simd8_grf_start
= v8
.payload
.num_regs
;
6656 simd8_grf_used
= v8
.grf_used
;
6659 if (v8
.max_dispatch_width
>= 16 &&
6660 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
6661 /* Try a SIMD16 compile */
6662 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
6663 &prog_data
->base
, prog
, shader
, 16,
6664 shader_time_index16
);
6665 v16
.import_uniforms(&v8
);
6666 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
6667 compiler
->shader_perf_log(log_data
,
6668 "SIMD16 shader failed to compile: %s",
6671 simd16_cfg
= v16
.cfg
;
6672 simd16_grf_start
= v16
.payload
.num_regs
;
6673 simd16_grf_used
= v16
.grf_used
;
6677 /* When the caller requests a repclear shader, they want SIMD16-only */
6681 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
6682 * at the top to select the shader. We've never implemented that.
6683 * Instead, we just give them exactly one shader and we pick the widest one
6686 if (compiler
->devinfo
->gen
< 5 && simd16_cfg
)
6689 if (prog_data
->persample_dispatch
) {
6690 /* Starting with SandyBridge (where we first get MSAA), the different
6691 * pixel dispatch combinations are grouped into classifications A
6692 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
6693 * generations, the only configurations supporting persample dispatch
6694 * are are this in which only one dispatch width is enabled.
6696 * If computed depth is enabled, SNB only allows SIMD8 while IVB+
6697 * allow SIMD8 or SIMD16 so we choose SIMD16 if available.
6699 if (compiler
->devinfo
->gen
== 6 &&
6700 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
) {
6702 } else if (simd16_cfg
) {
6707 /* We have to compute the flat inputs after the visitor is finished running
6708 * because it relies on prog_data->urb_setup which is computed in
6709 * fs_visitor::calculate_urb_setup().
6711 brw_compute_flat_inputs(prog_data
, shader
);
6713 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
6714 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6715 MESA_SHADER_FRAGMENT
);
6717 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
6718 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
6719 shader
->info
.label
?
6720 shader
->info
.label
: "unnamed",
6721 shader
->info
.name
));
6725 prog_data
->dispatch_8
= true;
6726 g
.generate_code(simd8_cfg
, 8);
6727 prog_data
->base
.dispatch_grf_start_reg
= simd8_grf_start
;
6728 prog_data
->reg_blocks_0
= brw_register_blocks(simd8_grf_used
);
6731 prog_data
->dispatch_16
= true;
6732 prog_data
->prog_offset_2
= g
.generate_code(simd16_cfg
, 16);
6733 prog_data
->dispatch_grf_start_reg_2
= simd16_grf_start
;
6734 prog_data
->reg_blocks_2
= brw_register_blocks(simd16_grf_used
);
6736 } else if (simd16_cfg
) {
6737 prog_data
->dispatch_16
= true;
6738 g
.generate_code(simd16_cfg
, 16);
6739 prog_data
->base
.dispatch_grf_start_reg
= simd16_grf_start
;
6740 prog_data
->reg_blocks_0
= brw_register_blocks(simd16_grf_used
);
6743 return g
.get_assembly(&prog_data
->base
.program_size
);
6747 fs_visitor::emit_cs_work_group_id_setup()
6749 assert(stage
== MESA_SHADER_COMPUTE
);
6751 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6753 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
6754 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
6755 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
6757 bld
.MOV(*reg
, r0_1
);
6758 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
6759 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
6765 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
6767 block
->dwords
= dwords
;
6768 block
->regs
= DIV_ROUND_UP(dwords
, 8);
6769 block
->size
= block
->regs
* 32;
6773 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
6774 struct brw_cs_prog_data
*cs_prog_data
)
6776 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
6777 int thread_local_id_index
= get_thread_local_id_param_index(prog_data
);
6778 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
6780 /* The thread ID should be stored in the last param dword */
6781 assert(thread_local_id_index
== -1 ||
6782 thread_local_id_index
== (int)prog_data
->nr_params
- 1);
6784 unsigned cross_thread_dwords
, per_thread_dwords
;
6785 if (!cross_thread_supported
) {
6786 cross_thread_dwords
= 0u;
6787 per_thread_dwords
= prog_data
->nr_params
;
6788 } else if (thread_local_id_index
>= 0) {
6789 /* Fill all but the last register with cross-thread payload */
6790 cross_thread_dwords
= 8 * (thread_local_id_index
/ 8);
6791 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
6792 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
6794 /* Fill all data using cross-thread payload */
6795 cross_thread_dwords
= prog_data
->nr_params
;
6796 per_thread_dwords
= 0u;
6799 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
6800 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
6802 unsigned total_dwords
=
6803 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
6804 cs_prog_data
->push
.cross_thread
.size
) / 4;
6805 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
6807 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
6808 cs_prog_data
->push
.per_thread
.size
== 0);
6809 assert(cs_prog_data
->push
.cross_thread
.dwords
+
6810 cs_prog_data
->push
.per_thread
.dwords
==
6811 prog_data
->nr_params
);
6815 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
6817 cs_prog_data
->simd_size
= size
;
6818 unsigned group_size
= cs_prog_data
->local_size
[0] *
6819 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
6820 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
6824 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
6826 const struct brw_cs_prog_key
*key
,
6827 struct brw_cs_prog_data
*prog_data
,
6828 const nir_shader
*src_shader
,
6829 int shader_time_index
,
6832 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6833 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, true);
6835 brw_nir_lower_cs_intrinsics(shader
, prog_data
);
6836 shader
= brw_postprocess_nir(shader
, compiler
, true);
6838 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
6839 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
6840 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
6841 unsigned local_workgroup_size
=
6842 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
6843 shader
->info
.cs
.local_size
[2];
6845 unsigned min_dispatch_width
=
6846 DIV_ROUND_UP(local_workgroup_size
, compiler
->devinfo
->max_cs_threads
);
6847 min_dispatch_width
= MAX2(8, min_dispatch_width
);
6848 min_dispatch_width
= util_next_power_of_two(min_dispatch_width
);
6849 assert(min_dispatch_width
<= 32);
6852 const char *fail_msg
= NULL
;
6854 /* Now the main event: Visit the shader IR and generate our CS IR for it.
6856 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6857 NULL
, /* Never used in core profile */
6858 shader
, 8, shader_time_index
);
6859 if (min_dispatch_width
<= 8) {
6860 if (!v8
.run_cs(min_dispatch_width
)) {
6861 fail_msg
= v8
.fail_msg
;
6863 /* We should always be able to do SIMD32 for compute shaders */
6864 assert(v8
.max_dispatch_width
>= 32);
6867 cs_set_simd_size(prog_data
, 8);
6868 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6869 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
6873 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6874 NULL
, /* Never used in core profile */
6875 shader
, 16, shader_time_index
);
6876 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
6877 !fail_msg
&& min_dispatch_width
<= 16) {
6878 /* Try a SIMD16 compile */
6879 if (min_dispatch_width
<= 8)
6880 v16
.import_uniforms(&v8
);
6881 if (!v16
.run_cs(min_dispatch_width
)) {
6882 compiler
->shader_perf_log(log_data
,
6883 "SIMD16 shader failed to compile: %s",
6887 "Couldn't generate SIMD16 program and not "
6888 "enough threads for SIMD8";
6891 /* We should always be able to do SIMD32 for compute shaders */
6892 assert(v16
.max_dispatch_width
>= 32);
6895 cs_set_simd_size(prog_data
, 16);
6896 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6897 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
6901 fs_visitor
v32(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6902 NULL
, /* Never used in core profile */
6903 shader
, 32, shader_time_index
);
6904 if (!fail_msg
&& (min_dispatch_width
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
6905 /* Try a SIMD32 compile */
6906 if (min_dispatch_width
<= 8)
6907 v32
.import_uniforms(&v8
);
6908 else if (min_dispatch_width
<= 16)
6909 v32
.import_uniforms(&v16
);
6911 if (!v32
.run_cs(min_dispatch_width
)) {
6912 compiler
->shader_perf_log(log_data
,
6913 "SIMD32 shader failed to compile: %s",
6917 "Couldn't generate SIMD32 program and not "
6918 "enough threads for SIMD16";
6922 cs_set_simd_size(prog_data
, 32);
6923 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6927 if (unlikely(cfg
== NULL
)) {
6930 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
6935 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
6936 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6937 MESA_SHADER_COMPUTE
);
6938 if (INTEL_DEBUG
& DEBUG_CS
) {
6939 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
6940 shader
->info
.label
? shader
->info
.label
:
6943 g
.enable_debug(name
);
6946 g
.generate_code(cfg
, prog_data
->simd_size
);
6948 return g
.get_assembly(&prog_data
->base
.program_size
);
6952 * Test the dispatch mask packing assumptions of
6953 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
6954 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
6955 * executed with an unexpected dispatch mask.
6958 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
6960 const gl_shader_stage stage
= bld
.shader
->stage
;
6962 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
6963 bld
.shader
->stage_prog_data
)) {
6964 const fs_builder ubld
= bld
.exec_all().group(1, 0);
6965 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
6966 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
6969 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
6970 ubld
.AND(tmp
, mask
, tmp
);
6972 /* This will loop forever if the dispatch mask doesn't have the expected
6973 * form '2^n-1', in which case tmp will be non-zero.
6975 bld
.emit(BRW_OPCODE_DO
);
6976 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
6977 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));