2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
35 #include "brw_vec4_gs_visitor.h"
37 #include "brw_dead_control_flow.h"
38 #include "common/gen_debug.h"
39 #include "compiler/glsl_types.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "program/prog_parameter.h"
42 #include "util/u_math.h"
46 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
50 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
51 const fs_reg
*src
, unsigned sources
)
53 memset((void*)this, 0, sizeof(*this));
55 this->src
= new fs_reg
[MAX2(sources
, 3)];
56 for (unsigned i
= 0; i
< sources
; i
++)
57 this->src
[i
] = src
[i
];
59 this->opcode
= opcode
;
61 this->sources
= sources
;
62 this->exec_size
= exec_size
;
65 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
67 assert(this->exec_size
!= 0);
69 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
71 /* This will be the case for almost all instructions. */
78 this->size_written
= dst
.component_size(exec_size
);
81 this->size_written
= 0;
85 unreachable("Invalid destination register file");
88 this->writes_accumulator
= false;
93 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
96 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
98 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
101 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
103 init(opcode
, exec_size
, dst
, NULL
, 0);
106 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
109 const fs_reg src
[1] = { src0
};
110 init(opcode
, exec_size
, dst
, src
, 1);
113 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
114 const fs_reg
&src0
, const fs_reg
&src1
)
116 const fs_reg src
[2] = { src0
, src1
};
117 init(opcode
, exec_size
, dst
, src
, 2);
120 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
121 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
123 const fs_reg src
[3] = { src0
, src1
, src2
};
124 init(opcode
, exec_size
, dst
, src
, 3);
127 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
128 const fs_reg src
[], unsigned sources
)
130 init(opcode
, exec_width
, dst
, src
, sources
);
133 fs_inst::fs_inst(const fs_inst
&that
)
135 memcpy((void*)this, &that
, sizeof(that
));
137 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
139 for (unsigned i
= 0; i
< that
.sources
; i
++)
140 this->src
[i
] = that
.src
[i
];
149 fs_inst::resize_sources(uint8_t num_sources
)
151 if (this->sources
!= num_sources
) {
152 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
154 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
155 src
[i
] = this->src
[i
];
159 this->sources
= num_sources
;
164 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
166 const fs_reg
&surf_index
,
167 const fs_reg
&varying_offset
,
168 uint32_t const_offset
)
170 /* We have our constant surface use a pitch of 4 bytes, so our index can
171 * be any component of a vector, and then we load 4 contiguous
172 * components starting from that.
174 * We break down the const_offset to a portion added to the variable offset
175 * and a portion done using fs_reg::offset, which means that if you have
176 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
177 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
178 * later notice that those loads are all the same and eliminate the
181 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
182 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
184 /* The pull load message will load a vec4 (16 bytes). If we are loading
185 * a double this means we are only loading 2 elements worth of data.
186 * We also want to use a 32-bit data type for the dst of the load operation
187 * so other parts of the driver don't get confused about the size of the
190 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
191 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
192 vec4_result
, surf_index
, vec4_offset
);
193 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
195 shuffle_from_32bit_read(bld
, dst
, vec4_result
,
196 (const_offset
& 0xf) / type_sz(dst
.type
), 1);
200 * A helper for MOV generation for fixing up broken hardware SEND dependency
204 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
206 /* The caller always wants uncompressed to emit the minimal extra
207 * dependencies, and to avoid having to deal with aligning its regs to 2.
209 const fs_builder ubld
= bld
.annotate("send dependency resolve")
212 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
216 fs_inst::equals(fs_inst
*inst
) const
218 return (opcode
== inst
->opcode
&&
219 dst
.equals(inst
->dst
) &&
220 src
[0].equals(inst
->src
[0]) &&
221 src
[1].equals(inst
->src
[1]) &&
222 src
[2].equals(inst
->src
[2]) &&
223 saturate
== inst
->saturate
&&
224 predicate
== inst
->predicate
&&
225 conditional_mod
== inst
->conditional_mod
&&
226 mlen
== inst
->mlen
&&
227 base_mrf
== inst
->base_mrf
&&
228 target
== inst
->target
&&
230 header_size
== inst
->header_size
&&
231 shadow_compare
== inst
->shadow_compare
&&
232 exec_size
== inst
->exec_size
&&
233 offset
== inst
->offset
);
237 fs_inst::is_send_from_grf() const
240 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
241 case SHADER_OPCODE_SHADER_TIME_ADD
:
242 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
243 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
244 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
245 case SHADER_OPCODE_UNTYPED_ATOMIC
:
246 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT
:
247 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
248 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
249 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
250 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
251 case SHADER_OPCODE_TYPED_ATOMIC
:
252 case SHADER_OPCODE_TYPED_SURFACE_READ
:
253 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
254 case SHADER_OPCODE_URB_WRITE_SIMD8
:
255 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
256 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
257 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
258 case SHADER_OPCODE_URB_READ_SIMD8
:
259 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
261 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
262 return src
[1].file
== VGRF
;
263 case FS_OPCODE_FB_WRITE
:
264 case FS_OPCODE_FB_READ
:
265 return src
[0].file
== VGRF
;
268 return src
[0].file
== VGRF
;
275 * Returns true if this instruction's sources and destinations cannot
276 * safely be the same register.
278 * In most cases, a register can be written over safely by the same
279 * instruction that is its last use. For a single instruction, the
280 * sources are dereferenced before writing of the destination starts
283 * However, there are a few cases where this can be problematic:
285 * - Virtual opcodes that translate to multiple instructions in the
286 * code generator: if src == dst and one instruction writes the
287 * destination before a later instruction reads the source, then
288 * src will have been clobbered.
290 * - SIMD16 compressed instructions with certain regioning (see below).
292 * The register allocator uses this information to set up conflicts between
293 * GRF sources and the destination.
296 fs_inst::has_source_and_destination_hazard() const
299 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
300 /* Multiple partial writes to the destination */
302 case SHADER_OPCODE_SHUFFLE
:
303 /* This instruction returns an arbitrary channel from the source and
304 * gets split into smaller instructions in the generator. It's possible
305 * that one of the instructions will read from a channel corresponding
306 * to an earlier instruction.
308 case SHADER_OPCODE_SEL_EXEC
:
309 /* This is implemented as
311 * mov(16) g4<1>D 0D { align1 WE_all 1H };
312 * mov(16) g4<1>D g5<8,8,1>D { align1 1H }
314 * Because the source is only read in the second instruction, the first
315 * may stomp all over it.
318 case SHADER_OPCODE_QUAD_SWIZZLE
:
320 case BRW_SWIZZLE_XXXX
:
321 case BRW_SWIZZLE_YYYY
:
322 case BRW_SWIZZLE_ZZZZ
:
323 case BRW_SWIZZLE_WWWW
:
324 case BRW_SWIZZLE_XXZZ
:
325 case BRW_SWIZZLE_YYWW
:
326 case BRW_SWIZZLE_XYXY
:
327 case BRW_SWIZZLE_ZWZW
:
328 /* These can be implemented as a single Align1 region on all
329 * platforms, so there's never a hazard between source and
330 * destination. C.f. fs_generator::generate_quad_swizzle().
334 return !is_uniform(src
[0]);
337 /* The SIMD16 compressed instruction
339 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
341 * is actually decoded in hardware as:
343 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
344 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
346 * Which is safe. However, if we have uniform accesses
347 * happening, we get into trouble:
349 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
350 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
352 * Now our destination for the first instruction overwrote the
353 * second instruction's src0, and we get garbage for those 8
354 * pixels. There's a similar issue for the pre-gen6
355 * pixel_x/pixel_y, which are registers of 16-bit values and thus
356 * would get stomped by the first decode as well.
358 if (exec_size
== 16) {
359 for (int i
= 0; i
< sources
; i
++) {
360 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
361 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
362 src
[i
].type
== BRW_REGISTER_TYPE_W
||
363 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
364 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
374 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
376 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
379 fs_reg reg
= this->src
[0];
380 if (reg
.file
!= VGRF
|| reg
.offset
!= 0 || reg
.stride
!= 1)
383 if (grf_alloc
.sizes
[reg
.nr
] * REG_SIZE
!= this->size_written
)
386 for (int i
= 0; i
< this->sources
; i
++) {
387 reg
.type
= this->src
[i
].type
;
388 if (!this->src
[i
].equals(reg
))
391 if (i
< this->header_size
) {
392 reg
.offset
+= REG_SIZE
;
394 reg
= horiz_offset(reg
, this->exec_size
);
402 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
) const
404 if (devinfo
->gen
== 6 && is_math())
407 if (is_send_from_grf())
410 if (!backend_instruction::can_do_source_mods())
417 fs_inst::can_do_cmod()
419 if (!backend_instruction::can_do_cmod())
422 /* The accumulator result appears to get used for the conditional modifier
423 * generation. When negating a UD value, there is a 33rd bit generated for
424 * the sign in the accumulator value, so now you can't check, for example,
425 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
427 for (unsigned i
= 0; i
< sources
; i
++) {
428 if (type_is_unsigned_int(src
[i
].type
) && src
[i
].negate
)
436 fs_inst::can_change_types() const
438 return dst
.type
== src
[0].type
&&
439 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
440 (opcode
== BRW_OPCODE_MOV
||
441 (opcode
== BRW_OPCODE_SEL
&&
442 dst
.type
== src
[1].type
&&
443 predicate
!= BRW_PREDICATE_NONE
&&
444 !src
[1].abs
&& !src
[1].negate
));
450 memset((void*)this, 0, sizeof(*this));
451 type
= BRW_REGISTER_TYPE_UD
;
455 /** Generic unset register constructor. */
459 this->file
= BAD_FILE
;
462 fs_reg::fs_reg(struct ::brw_reg reg
) :
467 if (this->file
== IMM
&&
468 (this->type
!= BRW_REGISTER_TYPE_V
&&
469 this->type
!= BRW_REGISTER_TYPE_UV
&&
470 this->type
!= BRW_REGISTER_TYPE_VF
)) {
476 fs_reg::equals(const fs_reg
&r
) const
478 return (this->backend_reg::equals(r
) &&
483 fs_reg::negative_equals(const fs_reg
&r
) const
485 return (this->backend_reg::negative_equals(r
) &&
490 fs_reg::is_contiguous() const
496 fs_reg::component_size(unsigned width
) const
498 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
501 return MAX2(width
* stride
, 1) * type_sz(type
);
505 type_size_scalar(const struct glsl_type
*type
)
507 unsigned int size
, i
;
509 switch (type
->base_type
) {
512 case GLSL_TYPE_FLOAT
:
514 return type
->components();
515 case GLSL_TYPE_UINT16
:
516 case GLSL_TYPE_INT16
:
517 case GLSL_TYPE_FLOAT16
:
518 return DIV_ROUND_UP(type
->components(), 2);
519 case GLSL_TYPE_UINT8
:
521 return DIV_ROUND_UP(type
->components(), 4);
522 case GLSL_TYPE_DOUBLE
:
523 case GLSL_TYPE_UINT64
:
524 case GLSL_TYPE_INT64
:
525 return type
->components() * 2;
526 case GLSL_TYPE_ARRAY
:
527 return type_size_scalar(type
->fields
.array
) * type
->length
;
528 case GLSL_TYPE_STRUCT
:
530 for (i
= 0; i
< type
->length
; i
++) {
531 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
534 case GLSL_TYPE_SAMPLER
:
535 case GLSL_TYPE_ATOMIC_UINT
:
536 case GLSL_TYPE_IMAGE
:
537 /* Samplers, atomics, and images take up no register space, since
538 * they're baked in at link time.
541 case GLSL_TYPE_SUBROUTINE
:
544 case GLSL_TYPE_ERROR
:
545 case GLSL_TYPE_INTERFACE
:
546 case GLSL_TYPE_FUNCTION
:
547 unreachable("not reached");
554 * Create a MOV to read the timestamp register.
556 * The caller is responsible for emitting the MOV. The return value is
557 * the destination of the MOV, with extra parameters set.
560 fs_visitor::get_timestamp(const fs_builder
&bld
)
562 assert(devinfo
->gen
>= 7);
564 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
567 BRW_REGISTER_TYPE_UD
));
569 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
571 /* We want to read the 3 fields we care about even if it's not enabled in
574 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
580 fs_visitor::emit_shader_time_begin()
582 /* We want only the low 32 bits of the timestamp. Since it's running
583 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
584 * which is plenty of time for our purposes. It is identical across the
585 * EUs, but since it's tracking GPU core speed it will increment at a
586 * varying rate as render P-states change.
588 shader_start_time
= component(
589 get_timestamp(bld
.annotate("shader time start")), 0);
593 fs_visitor::emit_shader_time_end()
595 /* Insert our code just before the final SEND with EOT. */
596 exec_node
*end
= this->instructions
.get_tail();
597 assert(end
&& ((fs_inst
*) end
)->eot
);
598 const fs_builder ibld
= bld
.annotate("shader time end")
599 .exec_all().at(NULL
, end
);
600 const fs_reg timestamp
= get_timestamp(ibld
);
602 /* We only use the low 32 bits of the timestamp - see
603 * emit_shader_time_begin()).
605 * We could also check if render P-states have changed (or anything
606 * else that might disrupt timing) by setting smear to 2 and checking if
607 * that field is != 0.
609 const fs_reg shader_end_time
= component(timestamp
, 0);
611 /* Check that there weren't any timestamp reset events (assuming these
612 * were the only two timestamp reads that happened).
614 const fs_reg reset
= component(timestamp
, 2);
615 set_condmod(BRW_CONDITIONAL_Z
,
616 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
617 ibld
.IF(BRW_PREDICATE_NORMAL
);
619 fs_reg start
= shader_start_time
;
621 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
622 BRW_REGISTER_TYPE_UD
),
624 const fs_builder cbld
= ibld
.group(1, 0);
625 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
627 /* If there were no instructions between the two timestamp gets, the diff
628 * is 2 cycles. Remove that overhead, so I can forget about that when
629 * trying to determine the time taken for single instructions.
631 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
632 SHADER_TIME_ADD(cbld
, 0, diff
);
633 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
634 ibld
.emit(BRW_OPCODE_ELSE
);
635 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
636 ibld
.emit(BRW_OPCODE_ENDIF
);
640 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
641 int shader_time_subindex
,
644 int index
= shader_time_index
* 3 + shader_time_subindex
;
645 struct brw_reg offset
= brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
);
648 if (dispatch_width
== 8)
649 payload
= vgrf(glsl_type::uvec2_type
);
651 payload
= vgrf(glsl_type::uint_type
);
653 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
657 fs_visitor::vfail(const char *format
, va_list va
)
666 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
667 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
669 this->fail_msg
= msg
;
672 fprintf(stderr
, "%s", msg
);
677 fs_visitor::fail(const char *format
, ...)
681 va_start(va
, format
);
687 * Mark this program as impossible to compile with dispatch width greater
690 * During the SIMD8 compile (which happens first), we can detect and flag
691 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
692 * SIMD16+ compile altogether.
694 * During a compile of dispatch width greater than n (if one happens anyway),
695 * this just calls fail().
698 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
700 if (dispatch_width
> n
) {
703 max_dispatch_width
= n
;
704 compiler
->shader_perf_log(log_data
,
705 "Shader dispatch width limited to SIMD%d: %s",
711 * Returns true if the instruction has a flag that means it won't
712 * update an entire destination register.
714 * For example, dead code elimination and live variable analysis want to know
715 * when a write to a variable screens off any preceding values that were in
719 fs_inst::is_partial_write() const
721 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
722 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
723 !this->dst
.is_contiguous() ||
724 this->dst
.offset
% REG_SIZE
!= 0);
728 fs_inst::components_read(unsigned i
) const
730 /* Return zero if the source is not present. */
731 if (src
[i
].file
== BAD_FILE
)
735 case FS_OPCODE_LINTERP
:
741 case FS_OPCODE_PIXEL_X
:
742 case FS_OPCODE_PIXEL_Y
:
746 case FS_OPCODE_FB_WRITE_LOGICAL
:
747 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
748 /* First/second FB write color. */
750 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
754 case SHADER_OPCODE_TEX_LOGICAL
:
755 case SHADER_OPCODE_TXD_LOGICAL
:
756 case SHADER_OPCODE_TXF_LOGICAL
:
757 case SHADER_OPCODE_TXL_LOGICAL
:
758 case SHADER_OPCODE_TXS_LOGICAL
:
759 case FS_OPCODE_TXB_LOGICAL
:
760 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
761 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
762 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
763 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
764 case SHADER_OPCODE_LOD_LOGICAL
:
765 case SHADER_OPCODE_TG4_LOGICAL
:
766 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
767 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
768 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
769 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
770 /* Texture coordinates. */
771 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
772 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
773 /* Texture derivatives. */
774 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
775 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
776 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
777 /* Texture offset. */
778 else if (i
== TEX_LOGICAL_SRC_TG4_OFFSET
)
781 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
786 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
787 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
788 assert(src
[3].file
== IMM
);
789 /* Surface coordinates. */
792 /* Surface operation source (ignored for reads). */
798 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
799 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
800 assert(src
[3].file
== IMM
&&
802 /* Surface coordinates. */
805 /* Surface operation source. */
811 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
812 /* Scattered logical opcodes use the following params:
813 * src[0] Surface coordinates
814 * src[1] Surface operation source (ignored for reads)
816 * src[3] IMM with always 1 dimension.
817 * src[4] IMM with arg bitsize for scattered read/write 8, 16, 32
819 assert(src
[3].file
== IMM
&&
821 return i
== 1 ? 0 : 1;
823 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
824 assert(src
[3].file
== IMM
&&
828 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
829 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
830 assert(src
[3].file
== IMM
&&
832 const unsigned op
= src
[4].ud
;
833 /* Surface coordinates. */
836 /* Surface operation source. */
837 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
839 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
840 op
== BRW_AOP_PREDEC
))
845 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
846 return (i
== 0 ? 2 : 1);
848 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
: {
849 assert(src
[3].file
== IMM
&&
851 const unsigned op
= src
[4].ud
;
852 /* Surface coordinates. */
855 /* Surface operation source. */
856 else if (i
== 1 && op
== BRW_AOP_FCMPWR
)
868 fs_inst::size_read(int arg
) const
871 case FS_OPCODE_FB_WRITE
:
872 case FS_OPCODE_REP_FB_WRITE
:
875 return src
[0].file
== BAD_FILE
? 0 : 2 * REG_SIZE
;
877 return mlen
* REG_SIZE
;
881 case FS_OPCODE_FB_READ
:
882 case SHADER_OPCODE_URB_WRITE_SIMD8
:
883 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
884 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
885 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
886 case SHADER_OPCODE_URB_READ_SIMD8
:
887 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
888 case SHADER_OPCODE_UNTYPED_ATOMIC
:
889 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT
:
890 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
891 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
892 case SHADER_OPCODE_TYPED_ATOMIC
:
893 case SHADER_OPCODE_TYPED_SURFACE_READ
:
894 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
895 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
896 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
897 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
898 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
900 return mlen
* REG_SIZE
;
903 case FS_OPCODE_SET_SAMPLE_ID
:
908 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
909 /* The payload is actually stored in src1 */
911 return mlen
* REG_SIZE
;
914 case FS_OPCODE_LINTERP
:
919 case SHADER_OPCODE_LOAD_PAYLOAD
:
920 if (arg
< this->header_size
)
924 case CS_OPCODE_CS_TERMINATE
:
925 case SHADER_OPCODE_BARRIER
:
928 case SHADER_OPCODE_MOV_INDIRECT
:
930 assert(src
[2].file
== IMM
);
936 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
937 return mlen
* REG_SIZE
;
941 switch (src
[arg
].file
) {
944 return components_read(arg
) * type_sz(src
[arg
].type
);
950 return components_read(arg
) * src
[arg
].component_size(exec_size
);
952 unreachable("MRF registers are not allowed as sources");
958 /* Return the subset of flag registers that an instruction could
959 * potentially read or write based on the execution controls and flag
960 * subregister number of the instruction.
963 flag_mask(const fs_inst
*inst
)
965 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
966 const unsigned end
= start
+ inst
->exec_size
;
967 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
973 return (n
>= CHAR_BIT
* sizeof(bit_mask(n
)) ? ~0u : (1u << n
) - 1);
977 flag_mask(const fs_reg
&r
, unsigned sz
)
980 const unsigned start
= (r
.nr
- BRW_ARF_FLAG
) * 4 + r
.subnr
;
981 const unsigned end
= start
+ sz
;
982 return bit_mask(end
) & ~bit_mask(start
);
990 fs_inst::flags_read(const gen_device_info
*devinfo
) const
992 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
993 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
994 /* The vertical predication modes combine corresponding bits from
995 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
997 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
998 return flag_mask(this) << shift
| flag_mask(this);
999 } else if (predicate
) {
1000 return flag_mask(this);
1003 for (int i
= 0; i
< sources
; i
++) {
1004 mask
|= flag_mask(src
[i
], size_read(i
));
1011 fs_inst::flags_written() const
1013 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
1014 opcode
!= BRW_OPCODE_CSEL
&&
1015 opcode
!= BRW_OPCODE_IF
&&
1016 opcode
!= BRW_OPCODE_WHILE
)) ||
1017 opcode
== SHADER_OPCODE_FIND_LIVE_CHANNEL
||
1018 opcode
== FS_OPCODE_FB_WRITE
) {
1019 return flag_mask(this);
1021 return flag_mask(dst
, size_written
);
1026 * Returns how many MRFs an FS opcode will write over.
1028 * Note that this is not the 0 or 1 implied writes in an actual gen
1029 * instruction -- the FS opcodes often generate MOVs in addition.
1032 fs_visitor::implied_mrf_writes(fs_inst
*inst
) const
1034 if (inst
->mlen
== 0)
1037 if (inst
->base_mrf
== -1)
1040 switch (inst
->opcode
) {
1041 case SHADER_OPCODE_RCP
:
1042 case SHADER_OPCODE_RSQ
:
1043 case SHADER_OPCODE_SQRT
:
1044 case SHADER_OPCODE_EXP2
:
1045 case SHADER_OPCODE_LOG2
:
1046 case SHADER_OPCODE_SIN
:
1047 case SHADER_OPCODE_COS
:
1048 return 1 * dispatch_width
/ 8;
1049 case SHADER_OPCODE_POW
:
1050 case SHADER_OPCODE_INT_QUOTIENT
:
1051 case SHADER_OPCODE_INT_REMAINDER
:
1052 return 2 * dispatch_width
/ 8;
1053 case SHADER_OPCODE_TEX
:
1055 case SHADER_OPCODE_TXD
:
1056 case SHADER_OPCODE_TXF
:
1057 case SHADER_OPCODE_TXF_CMS
:
1058 case SHADER_OPCODE_TXF_MCS
:
1059 case SHADER_OPCODE_TG4
:
1060 case SHADER_OPCODE_TG4_OFFSET
:
1061 case SHADER_OPCODE_TXL
:
1062 case SHADER_OPCODE_TXS
:
1063 case SHADER_OPCODE_LOD
:
1064 case SHADER_OPCODE_SAMPLEINFO
:
1066 case FS_OPCODE_FB_WRITE
:
1067 case FS_OPCODE_REP_FB_WRITE
:
1068 return inst
->src
[0].file
== BAD_FILE
? 0 : 2;
1069 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1070 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1072 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
1074 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1077 unreachable("not reached");
1082 fs_visitor::vgrf(const glsl_type
*const type
)
1084 int reg_width
= dispatch_width
/ 8;
1085 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
1086 brw_type_for_base_type(type
));
1089 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1094 this->type
= BRW_REGISTER_TYPE_F
;
1095 this->stride
= (file
== UNIFORM
? 0 : 1);
1098 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1104 this->stride
= (file
== UNIFORM
? 0 : 1);
1107 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1108 * This brings in those uniform definitions
1111 fs_visitor::import_uniforms(fs_visitor
*v
)
1113 this->push_constant_loc
= v
->push_constant_loc
;
1114 this->pull_constant_loc
= v
->pull_constant_loc
;
1115 this->uniforms
= v
->uniforms
;
1116 this->subgroup_id
= v
->subgroup_id
;
1120 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1122 assert(stage
== MESA_SHADER_FRAGMENT
);
1124 /* gl_FragCoord.x */
1125 bld
.MOV(wpos
, this->pixel_x
);
1126 wpos
= offset(wpos
, bld
, 1);
1128 /* gl_FragCoord.y */
1129 bld
.MOV(wpos
, this->pixel_y
);
1130 wpos
= offset(wpos
, bld
, 1);
1132 /* gl_FragCoord.z */
1133 if (devinfo
->gen
>= 6) {
1134 bld
.MOV(wpos
, fetch_payload_reg(bld
, payload
.source_depth_reg
));
1136 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1137 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1138 component(interp_reg(VARYING_SLOT_POS
, 2), 0));
1140 wpos
= offset(wpos
, bld
, 1);
1142 /* gl_FragCoord.w: Already set up in emit_interpolation */
1143 bld
.MOV(wpos
, this->wpos_w
);
1146 enum brw_barycentric_mode
1147 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1149 /* Barycentric modes don't make sense for flat inputs. */
1150 assert(mode
!= INTERP_MODE_FLAT
);
1154 case nir_intrinsic_load_barycentric_pixel
:
1155 case nir_intrinsic_load_barycentric_at_offset
:
1156 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1158 case nir_intrinsic_load_barycentric_centroid
:
1159 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1161 case nir_intrinsic_load_barycentric_sample
:
1162 case nir_intrinsic_load_barycentric_at_sample
:
1163 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1166 unreachable("invalid intrinsic");
1169 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1172 return (enum brw_barycentric_mode
) bary
;
1176 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1178 static enum brw_barycentric_mode
1179 centroid_to_pixel(enum brw_barycentric_mode bary
)
1181 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1182 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1183 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1187 fs_visitor::emit_frontfacing_interpolation()
1189 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1191 if (devinfo
->gen
>= 6) {
1192 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1193 * a boolean result from this (~0/true or 0/false).
1195 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1196 * this task in only one instruction:
1197 * - a negation source modifier will flip the bit; and
1198 * - a W -> D type conversion will sign extend the bit into the high
1199 * word of the destination.
1201 * An ASR 15 fills the low word of the destination.
1203 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1206 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1208 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1209 * a boolean result from this (1/true or 0/false).
1211 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1212 * the negation source modifier to flip it. Unfortunately the SHR
1213 * instruction only operates on UD (or D with an abs source modifier)
1214 * sources without negation.
1216 * Instead, use ASR (which will give ~0/true or 0/false).
1218 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1221 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1228 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1230 assert(stage
== MESA_SHADER_FRAGMENT
);
1231 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1232 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1234 if (wm_prog_data
->persample_dispatch
) {
1235 /* Convert int_sample_pos to floating point */
1236 bld
.MOV(dst
, int_sample_pos
);
1237 /* Scale to the range [0, 1] */
1238 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1241 /* From ARB_sample_shading specification:
1242 * "When rendering to a non-multisample buffer, or if multisample
1243 * rasterization is disabled, gl_SamplePosition will always be
1246 bld
.MOV(dst
, brw_imm_f(0.5f
));
1251 fs_visitor::emit_samplepos_setup()
1253 assert(devinfo
->gen
>= 6);
1255 const fs_builder abld
= bld
.annotate("compute sample position");
1256 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1258 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1259 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1261 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1262 * mode will be enabled.
1264 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1265 * R31.1:0 Position Offset X/Y for Slot[3:0]
1266 * R31.3:2 Position Offset X/Y for Slot[7:4]
1269 * The X, Y sample positions come in as bytes in thread payload. So, read
1270 * the positions using vstride=16, width=8, hstride=2.
1272 const fs_reg sample_pos_reg
=
1273 fetch_payload_reg(abld
, payload
.sample_pos_reg
, BRW_REGISTER_TYPE_W
);
1275 /* Compute gl_SamplePosition.x */
1276 abld
.MOV(int_sample_x
, subscript(sample_pos_reg
, BRW_REGISTER_TYPE_B
, 0));
1277 compute_sample_position(offset(pos
, abld
, 0), int_sample_x
);
1279 /* Compute gl_SamplePosition.y */
1280 abld
.MOV(int_sample_y
, subscript(sample_pos_reg
, BRW_REGISTER_TYPE_B
, 1));
1281 compute_sample_position(offset(pos
, abld
, 1), int_sample_y
);
1286 fs_visitor::emit_sampleid_setup()
1288 assert(stage
== MESA_SHADER_FRAGMENT
);
1289 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1290 assert(devinfo
->gen
>= 6);
1292 const fs_builder abld
= bld
.annotate("compute sample id");
1293 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uint_type
));
1295 if (!key
->multisample_fbo
) {
1296 /* As per GL_ARB_sample_shading specification:
1297 * "When rendering to a non-multisample buffer, or if multisample
1298 * rasterization is disabled, gl_SampleID will always be zero."
1300 abld
.MOV(*reg
, brw_imm_d(0));
1301 } else if (devinfo
->gen
>= 8) {
1302 /* Sample ID comes in as 4-bit numbers in g1.0:
1304 * 15:12 Slot 3 SampleID (only used in SIMD16)
1305 * 11:8 Slot 2 SampleID (only used in SIMD16)
1306 * 7:4 Slot 1 SampleID
1307 * 3:0 Slot 0 SampleID
1309 * Each slot corresponds to four channels, so we want to replicate each
1310 * half-byte value to 4 channels in a row:
1312 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1313 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1315 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1316 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1318 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1319 * channels to read the first byte (7:0), and the second group of 8
1320 * channels to read the second byte (15:8). Then, we shift right by
1321 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1322 * values into place. Finally, we AND with 0xf to keep the low nibble.
1324 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1325 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1327 * TODO: These payload bits exist on Gen7 too, but they appear to always
1328 * be zero, so this code fails to work. We should find out why.
1330 const fs_reg tmp
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
1332 for (unsigned i
= 0; i
< DIV_ROUND_UP(dispatch_width
, 16); i
++) {
1333 const fs_builder hbld
= abld
.group(MIN2(16, dispatch_width
), i
);
1334 hbld
.SHR(offset(tmp
, hbld
, i
),
1335 stride(retype(brw_vec1_grf(1 + i
, 0), BRW_REGISTER_TYPE_UB
),
1337 brw_imm_v(0x44440000));
1340 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1342 const fs_reg t1
= component(abld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
1343 const fs_reg t2
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
1345 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1346 * 8x multisampling, subspan 0 will represent sample N (where N
1347 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1348 * 7. We can find the value of N by looking at R0.0 bits 7:6
1349 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1350 * (since samples are always delivered in pairs). That is, we
1351 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1352 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1353 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1354 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1355 * populating a temporary variable with the sequence (0, 1, 2, 3),
1356 * and then reading from it using vstride=1, width=4, hstride=0.
1357 * These computations hold good for 4x multisampling as well.
1359 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1360 * the first four slots are sample 0 of subspan 0; the next four
1361 * are sample 1 of subspan 0; the third group is sample 0 of
1362 * subspan 1, and finally sample 1 of subspan 1.
1365 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1366 * accomodate 16x MSAA.
1368 abld
.exec_all().group(1, 0)
1369 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1371 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1373 /* This works for SIMD8-SIMD16. It also works for SIMD32 but only if we
1374 * can assume 4x MSAA. Disallow it on IVB+
1376 * FINISHME: One day, we could come up with a way to do this that
1377 * actually works on gen7.
1379 if (devinfo
->gen
>= 7)
1380 limit_dispatch_width(16, "gl_SampleId is unsupported in SIMD32 on gen7");
1381 abld
.exec_all().group(8, 0).MOV(t2
, brw_imm_v(0x32103210));
1383 /* This special instruction takes care of setting vstride=1,
1384 * width=4, hstride=0 of t2 during an ADD instruction.
1386 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1393 fs_visitor::emit_samplemaskin_setup()
1395 assert(stage
== MESA_SHADER_FRAGMENT
);
1396 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1397 assert(devinfo
->gen
>= 6);
1399 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1401 fs_reg coverage_mask
=
1402 fetch_payload_reg(bld
, payload
.sample_mask_in_reg
, BRW_REGISTER_TYPE_D
);
1404 if (wm_prog_data
->persample_dispatch
) {
1405 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1406 * and a mask representing which sample is being processed by the
1407 * current shader invocation.
1409 * From the OES_sample_variables specification:
1410 * "When per-sample shading is active due to the use of a fragment input
1411 * qualified by "sample" or due to the use of the gl_SampleID or
1412 * gl_SamplePosition variables, only the bit for the current sample is
1413 * set in gl_SampleMaskIn."
1415 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1417 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1418 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1420 fs_reg one
= vgrf(glsl_type::int_type
);
1421 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1422 abld
.MOV(one
, brw_imm_d(1));
1423 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1424 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1426 /* In per-pixel mode, the coverage mask is sufficient. */
1427 *reg
= coverage_mask
;
1433 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1435 if (!src
.abs
&& !src
.negate
)
1438 fs_reg temp
= bld
.vgrf(src
.type
);
1445 fs_visitor::emit_discard_jump()
1447 assert(brw_wm_prog_data(this->prog_data
)->uses_kill
);
1449 /* For performance, after a discard, jump to the end of the
1450 * shader if all relevant channels have been discarded.
1452 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1453 discard_jump
->flag_subreg
= 1;
1455 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1456 discard_jump
->predicate_inverse
= true;
1460 fs_visitor::emit_gs_thread_end()
1462 assert(stage
== MESA_SHADER_GEOMETRY
);
1464 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1466 if (gs_compile
->control_data_header_size_bits
> 0) {
1467 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1470 const fs_builder abld
= bld
.annotate("thread end");
1473 if (gs_prog_data
->static_vertex_count
!= -1) {
1474 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1475 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1476 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1477 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1478 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1481 /* Delete now dead instructions. */
1482 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1488 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1492 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1493 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1494 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1497 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1498 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1499 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1500 sources
[1] = this->final_gs_vertex_count
;
1501 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1502 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1510 fs_visitor::assign_curb_setup()
1512 unsigned uniform_push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
1514 unsigned ubo_push_length
= 0;
1515 unsigned ubo_push_start
[4];
1516 for (int i
= 0; i
< 4; i
++) {
1517 ubo_push_start
[i
] = 8 * (ubo_push_length
+ uniform_push_length
);
1518 ubo_push_length
+= stage_prog_data
->ubo_ranges
[i
].length
;
1521 prog_data
->curb_read_length
= uniform_push_length
+ ubo_push_length
;
1523 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1524 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1525 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1526 if (inst
->src
[i
].file
== UNIFORM
) {
1527 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1529 if (inst
->src
[i
].nr
>= UBO_START
) {
1530 /* constant_nr is in 32-bit units, the rest are in bytes */
1531 constant_nr
= ubo_push_start
[inst
->src
[i
].nr
- UBO_START
] +
1532 inst
->src
[i
].offset
/ 4;
1533 } else if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1534 constant_nr
= push_constant_loc
[uniform_nr
];
1536 /* Section 5.11 of the OpenGL 4.1 spec says:
1537 * "Out-of-bounds reads return undefined values, which include
1538 * values from other variables of the active program or zero."
1539 * Just return the first push constant.
1544 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1547 brw_reg
.abs
= inst
->src
[i
].abs
;
1548 brw_reg
.negate
= inst
->src
[i
].negate
;
1550 assert(inst
->src
[i
].stride
== 0);
1551 inst
->src
[i
] = byte_offset(
1552 retype(brw_reg
, inst
->src
[i
].type
),
1553 inst
->src
[i
].offset
% 4);
1558 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1559 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1563 fs_visitor::calculate_urb_setup()
1565 assert(stage
== MESA_SHADER_FRAGMENT
);
1566 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1567 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1569 memset(prog_data
->urb_setup
, -1,
1570 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1573 /* Figure out where each of the incoming setup attributes lands. */
1574 if (devinfo
->gen
>= 6) {
1575 if (util_bitcount64(nir
->info
.inputs_read
&
1576 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1577 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1578 * first 16 varying inputs, so we can put them wherever we want.
1579 * Just put them in order.
1581 * This is useful because it means that (a) inputs not used by the
1582 * fragment shader won't take up valuable register space, and (b) we
1583 * won't have to recompile the fragment shader if it gets paired with
1584 * a different vertex (or geometry) shader.
1586 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1587 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1588 BITFIELD64_BIT(i
)) {
1589 prog_data
->urb_setup
[i
] = urb_next
++;
1593 /* We have enough input varyings that the SF/SBE pipeline stage can't
1594 * arbitrarily rearrange them to suit our whim; we have to put them
1595 * in an order that matches the output of the previous pipeline stage
1596 * (geometry or vertex shader).
1598 struct brw_vue_map prev_stage_vue_map
;
1599 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1600 key
->input_slots_valid
,
1601 nir
->info
.separate_shader
);
1604 brw_compute_first_urb_slot_required(nir
->info
.inputs_read
,
1605 &prev_stage_vue_map
);
1607 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1608 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1610 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1611 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1612 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1613 BITFIELD64_BIT(varying
))) {
1614 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1617 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1620 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1621 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1622 /* Point size is packed into the header, not as a general attribute */
1623 if (i
== VARYING_SLOT_PSIZ
)
1626 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1627 /* The back color slot is skipped when the front color is
1628 * also written to. In addition, some slots can be
1629 * written in the vertex shader and not read in the
1630 * fragment shader. So the register number must always be
1631 * incremented, mapped or not.
1633 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1634 prog_data
->urb_setup
[i
] = urb_next
;
1640 * It's a FS only attribute, and we did interpolation for this attribute
1641 * in SF thread. So, count it here, too.
1643 * See compile_sf_prog() for more info.
1645 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1646 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1649 prog_data
->num_varying_inputs
= urb_next
;
1653 fs_visitor::assign_urb_setup()
1655 assert(stage
== MESA_SHADER_FRAGMENT
);
1656 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1658 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1660 /* Offset all the urb_setup[] index by the actual position of the
1661 * setup regs, now that the location of the constants has been chosen.
1663 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1664 for (int i
= 0; i
< inst
->sources
; i
++) {
1665 if (inst
->src
[i
].file
== ATTR
) {
1666 /* ATTR regs in the FS are in units of logical scalar inputs each
1667 * of which consumes half of a GRF register.
1669 assert(inst
->src
[i
].offset
< REG_SIZE
/ 2);
1670 const unsigned grf
= urb_start
+ inst
->src
[i
].nr
/ 2;
1671 const unsigned offset
= (inst
->src
[i
].nr
% 2) * (REG_SIZE
/ 2) +
1672 inst
->src
[i
].offset
;
1673 const unsigned width
= inst
->src
[i
].stride
== 0 ?
1674 1 : MIN2(inst
->exec_size
, 8);
1675 struct brw_reg reg
= stride(
1676 byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1678 width
* inst
->src
[i
].stride
,
1679 width
, inst
->src
[i
].stride
);
1680 reg
.abs
= inst
->src
[i
].abs
;
1681 reg
.negate
= inst
->src
[i
].negate
;
1687 /* Each attribute is 4 setup channels, each of which is half a reg. */
1688 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1692 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1694 for (int i
= 0; i
< inst
->sources
; i
++) {
1695 if (inst
->src
[i
].file
== ATTR
) {
1696 int grf
= payload
.num_regs
+
1697 prog_data
->curb_read_length
+
1699 inst
->src
[i
].offset
/ REG_SIZE
;
1701 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1703 * VertStride must be used to cross GRF register boundaries. This
1704 * rule implies that elements within a 'Width' cannot cross GRF
1707 * So, for registers that are large enough, we have to split the exec
1708 * size in two and trust the compression state to sort it out.
1710 unsigned total_size
= inst
->exec_size
*
1711 inst
->src
[i
].stride
*
1712 type_sz(inst
->src
[i
].type
);
1714 assert(total_size
<= 2 * REG_SIZE
);
1715 const unsigned exec_size
=
1716 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1718 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1719 struct brw_reg reg
=
1720 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1721 inst
->src
[i
].offset
% REG_SIZE
),
1722 exec_size
* inst
->src
[i
].stride
,
1723 width
, inst
->src
[i
].stride
);
1724 reg
.abs
= inst
->src
[i
].abs
;
1725 reg
.negate
= inst
->src
[i
].negate
;
1733 fs_visitor::assign_vs_urb_setup()
1735 struct brw_vs_prog_data
*vs_prog_data
= brw_vs_prog_data(prog_data
);
1737 assert(stage
== MESA_SHADER_VERTEX
);
1739 /* Each attribute is 4 regs. */
1740 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1742 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1744 /* Rewrite all ATTR file references to the hw grf that they land in. */
1745 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1746 convert_attr_sources_to_hw_regs(inst
);
1751 fs_visitor::assign_tcs_single_patch_urb_setup()
1753 assert(stage
== MESA_SHADER_TESS_CTRL
);
1755 /* Rewrite all ATTR file references to HW_REGs. */
1756 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1757 convert_attr_sources_to_hw_regs(inst
);
1762 fs_visitor::assign_tes_urb_setup()
1764 assert(stage
== MESA_SHADER_TESS_EVAL
);
1766 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1768 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1770 /* Rewrite all ATTR file references to HW_REGs. */
1771 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1772 convert_attr_sources_to_hw_regs(inst
);
1777 fs_visitor::assign_gs_urb_setup()
1779 assert(stage
== MESA_SHADER_GEOMETRY
);
1781 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1783 first_non_payload_grf
+=
1784 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1786 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1787 /* Rewrite all ATTR file references to GRFs. */
1788 convert_attr_sources_to_hw_regs(inst
);
1794 * Split large virtual GRFs into separate components if we can.
1796 * This is mostly duplicated with what brw_fs_vector_splitting does,
1797 * but that's really conservative because it's afraid of doing
1798 * splitting that doesn't result in real progress after the rest of
1799 * the optimization phases, which would cause infinite looping in
1800 * optimization. We can do it once here, safely. This also has the
1801 * opportunity to split interpolated values, or maybe even uniforms,
1802 * which we don't have at the IR level.
1804 * We want to split, because virtual GRFs are what we register
1805 * allocate and spill (due to contiguousness requirements for some
1806 * instructions), and they're what we naturally generate in the
1807 * codegen process, but most virtual GRFs don't actually need to be
1808 * contiguous sets of GRFs. If we split, we'll end up with reduced
1809 * live intervals and better dead code elimination and coalescing.
1812 fs_visitor::split_virtual_grfs()
1814 /* Compact the register file so we eliminate dead vgrfs. This
1815 * only defines split points for live registers, so if we have
1816 * too large dead registers they will hit assertions later.
1818 compact_virtual_grfs();
1820 int num_vars
= this->alloc
.count
;
1822 /* Count the total number of registers */
1824 int vgrf_to_reg
[num_vars
];
1825 for (int i
= 0; i
< num_vars
; i
++) {
1826 vgrf_to_reg
[i
] = reg_count
;
1827 reg_count
+= alloc
.sizes
[i
];
1830 /* An array of "split points". For each register slot, this indicates
1831 * if this slot can be separated from the previous slot. Every time an
1832 * instruction uses multiple elements of a register (as a source or
1833 * destination), we mark the used slots as inseparable. Then we go
1834 * through and split the registers into the smallest pieces we can.
1836 bool split_points
[reg_count
];
1837 memset(split_points
, 0, sizeof(split_points
));
1839 /* Mark all used registers as fully splittable */
1840 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1841 if (inst
->dst
.file
== VGRF
) {
1842 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1843 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1844 split_points
[reg
+ j
] = true;
1847 for (int i
= 0; i
< inst
->sources
; i
++) {
1848 if (inst
->src
[i
].file
== VGRF
) {
1849 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1850 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1851 split_points
[reg
+ j
] = true;
1856 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1857 if (inst
->dst
.file
== VGRF
) {
1858 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1859 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1860 split_points
[reg
+ j
] = false;
1862 for (int i
= 0; i
< inst
->sources
; i
++) {
1863 if (inst
->src
[i
].file
== VGRF
) {
1864 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1865 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1866 split_points
[reg
+ j
] = false;
1871 int new_virtual_grf
[reg_count
];
1872 int new_reg_offset
[reg_count
];
1875 for (int i
= 0; i
< num_vars
; i
++) {
1876 /* The first one should always be 0 as a quick sanity check. */
1877 assert(split_points
[reg
] == false);
1880 new_reg_offset
[reg
] = 0;
1885 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1886 /* If this is a split point, reset the offset to 0 and allocate a
1887 * new virtual GRF for the previous offset many registers
1889 if (split_points
[reg
]) {
1890 assert(offset
<= MAX_VGRF_SIZE
);
1891 int grf
= alloc
.allocate(offset
);
1892 for (int k
= reg
- offset
; k
< reg
; k
++)
1893 new_virtual_grf
[k
] = grf
;
1896 new_reg_offset
[reg
] = offset
;
1901 /* The last one gets the original register number */
1902 assert(offset
<= MAX_VGRF_SIZE
);
1903 alloc
.sizes
[i
] = offset
;
1904 for (int k
= reg
- offset
; k
< reg
; k
++)
1905 new_virtual_grf
[k
] = i
;
1907 assert(reg
== reg_count
);
1909 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1910 if (inst
->dst
.file
== VGRF
) {
1911 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1912 inst
->dst
.nr
= new_virtual_grf
[reg
];
1913 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
1914 inst
->dst
.offset
% REG_SIZE
;
1915 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1917 for (int i
= 0; i
< inst
->sources
; i
++) {
1918 if (inst
->src
[i
].file
== VGRF
) {
1919 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1920 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1921 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
1922 inst
->src
[i
].offset
% REG_SIZE
;
1923 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1927 invalidate_live_intervals();
1931 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1933 * During code generation, we create tons of temporary variables, many of
1934 * which get immediately killed and are never used again. Yet, in later
1935 * optimization and analysis passes, such as compute_live_intervals, we need
1936 * to loop over all the virtual GRFs. Compacting them can save a lot of
1940 fs_visitor::compact_virtual_grfs()
1942 bool progress
= false;
1943 int remap_table
[this->alloc
.count
];
1944 memset(remap_table
, -1, sizeof(remap_table
));
1946 /* Mark which virtual GRFs are used. */
1947 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1948 if (inst
->dst
.file
== VGRF
)
1949 remap_table
[inst
->dst
.nr
] = 0;
1951 for (int i
= 0; i
< inst
->sources
; i
++) {
1952 if (inst
->src
[i
].file
== VGRF
)
1953 remap_table
[inst
->src
[i
].nr
] = 0;
1957 /* Compact the GRF arrays. */
1959 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1960 if (remap_table
[i
] == -1) {
1961 /* We just found an unused register. This means that we are
1962 * actually going to compact something.
1966 remap_table
[i
] = new_index
;
1967 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1968 invalidate_live_intervals();
1973 this->alloc
.count
= new_index
;
1975 /* Patch all the instructions to use the newly renumbered registers */
1976 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1977 if (inst
->dst
.file
== VGRF
)
1978 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1980 for (int i
= 0; i
< inst
->sources
; i
++) {
1981 if (inst
->src
[i
].file
== VGRF
)
1982 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1986 /* Patch all the references to delta_xy, since they're used in register
1987 * allocation. If they're unused, switch them to BAD_FILE so we don't
1988 * think some random VGRF is delta_xy.
1990 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1991 if (delta_xy
[i
].file
== VGRF
) {
1992 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1993 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1995 delta_xy
[i
].file
= BAD_FILE
;
2004 get_subgroup_id_param_index(const brw_stage_prog_data
*prog_data
)
2006 if (prog_data
->nr_params
== 0)
2009 /* The local thread id is always the last parameter in the list */
2010 uint32_t last_param
= prog_data
->param
[prog_data
->nr_params
- 1];
2011 if (last_param
== BRW_PARAM_BUILTIN_SUBGROUP_ID
)
2012 return prog_data
->nr_params
- 1;
2018 * Struct for handling complex alignments.
2020 * A complex alignment is stored as multiplier and an offset. A value is
2021 * considered to be aligned if it is {offset} larger than a multiple of {mul}.
2022 * For instance, with an alignment of {8, 2}, cplx_align_apply would do the
2025 * N | cplx_align_apply({8, 2}, N)
2026 * ----+-----------------------------
2040 #define CPLX_ALIGN_MAX_MUL 8
2043 cplx_align_assert_sane(struct cplx_align a
)
2045 assert(a
.mul
> 0 && util_is_power_of_two_nonzero(a
.mul
));
2046 assert(a
.offset
< a
.mul
);
2050 * Combines two alignments to produce a least multiple of sorts.
2052 * The returned alignment is the smallest (in terms of multiplier) such that
2053 * anything aligned to both a and b will be aligned to the new alignment.
2054 * This function will assert-fail if a and b are not compatible, i.e. if the
2055 * offset parameters are such that no common alignment is possible.
2057 static struct cplx_align
2058 cplx_align_combine(struct cplx_align a
, struct cplx_align b
)
2060 cplx_align_assert_sane(a
);
2061 cplx_align_assert_sane(b
);
2063 /* Assert that the alignments agree. */
2064 assert((a
.offset
& (b
.mul
- 1)) == (b
.offset
& (a
.mul
- 1)));
2066 return a
.mul
> b
.mul
? a
: b
;
2070 * Apply a complex alignment
2072 * This function will return the smallest number greater than or equal to
2073 * offset that is aligned to align.
2076 cplx_align_apply(struct cplx_align align
, unsigned offset
)
2078 return ALIGN(offset
- align
.offset
, align
.mul
) + align
.offset
;
2081 #define UNIFORM_SLOT_SIZE 4
2083 struct uniform_slot_info
{
2084 /** True if the given uniform slot is live */
2087 /** True if this slot and the next slot must remain contiguous */
2088 unsigned contiguous
:1;
2090 struct cplx_align align
;
2094 mark_uniform_slots_read(struct uniform_slot_info
*slots
,
2095 unsigned num_slots
, unsigned alignment
)
2097 assert(alignment
> 0 && util_is_power_of_two_nonzero(alignment
));
2098 assert(alignment
<= CPLX_ALIGN_MAX_MUL
);
2100 /* We can't align a slot to anything less than the slot size */
2101 alignment
= MAX2(alignment
, UNIFORM_SLOT_SIZE
);
2103 struct cplx_align align
= {alignment
, 0};
2104 cplx_align_assert_sane(align
);
2106 for (unsigned i
= 0; i
< num_slots
; i
++) {
2107 slots
[i
].is_live
= true;
2108 if (i
< num_slots
- 1)
2109 slots
[i
].contiguous
= true;
2111 align
.offset
= (i
* UNIFORM_SLOT_SIZE
) & (align
.mul
- 1);
2112 if (slots
[i
].align
.mul
== 0) {
2113 slots
[i
].align
= align
;
2115 slots
[i
].align
= cplx_align_combine(slots
[i
].align
, align
);
2121 * Assign UNIFORM file registers to either push constants or pull constants.
2123 * We allow a fragment shader to have more than the specified minimum
2124 * maximum number of fragment shader uniform components (64). If
2125 * there are too many of these, they'd fill up all of register space.
2126 * So, this will push some of them out to the pull constant buffer and
2127 * update the program to load them.
2130 fs_visitor::assign_constant_locations()
2132 /* Only the first compile gets to decide on locations. */
2133 if (push_constant_loc
) {
2134 assert(pull_constant_loc
);
2138 struct uniform_slot_info slots
[uniforms
];
2139 memset(slots
, 0, sizeof(slots
));
2141 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2142 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2143 if (inst
->src
[i
].file
!= UNIFORM
)
2146 /* NIR tightly packs things so the uniform number might not be
2147 * aligned (if we have a double right after a float, for instance).
2148 * This is fine because the process of re-arranging them will ensure
2149 * that things are properly aligned. The offset into that uniform,
2150 * however, must be aligned.
2152 * In Vulkan, we have explicit offsets but everything is crammed
2153 * into a single "variable" so inst->src[i].nr will always be 0.
2154 * Everything will be properly aligned relative to that one base.
2156 assert(inst
->src
[i
].offset
% type_sz(inst
->src
[i
].type
) == 0);
2158 unsigned u
= inst
->src
[i
].nr
+
2159 inst
->src
[i
].offset
/ UNIFORM_SLOT_SIZE
;
2164 unsigned slots_read
;
2165 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2166 slots_read
= DIV_ROUND_UP(inst
->src
[2].ud
, UNIFORM_SLOT_SIZE
);
2168 unsigned bytes_read
= inst
->components_read(i
) *
2169 type_sz(inst
->src
[i
].type
);
2170 slots_read
= DIV_ROUND_UP(bytes_read
, UNIFORM_SLOT_SIZE
);
2173 assert(u
+ slots_read
<= uniforms
);
2174 mark_uniform_slots_read(&slots
[u
], slots_read
,
2175 type_sz(inst
->src
[i
].type
));
2179 int subgroup_id_index
= get_subgroup_id_param_index(stage_prog_data
);
2181 /* Only allow 16 registers (128 uniform components) as push constants.
2183 * Just demote the end of the list. We could probably do better
2184 * here, demoting things that are rarely used in the program first.
2186 * If changing this value, note the limitation about total_regs in
2189 unsigned int max_push_components
= 16 * 8;
2190 if (subgroup_id_index
>= 0)
2191 max_push_components
--; /* Save a slot for the thread ID */
2193 /* We push small arrays, but no bigger than 16 floats. This is big enough
2194 * for a vec4 but hopefully not large enough to push out other stuff. We
2195 * should probably use a better heuristic at some point.
2197 const unsigned int max_chunk_size
= 16;
2199 unsigned int num_push_constants
= 0;
2200 unsigned int num_pull_constants
= 0;
2202 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2203 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2205 /* Default to -1 meaning no location */
2206 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2207 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2209 int chunk_start
= -1;
2210 struct cplx_align align
;
2211 for (unsigned u
= 0; u
< uniforms
; u
++) {
2212 if (!slots
[u
].is_live
) {
2213 assert(chunk_start
== -1);
2217 /* Skip subgroup_id_index to put it in the last push register. */
2218 if (subgroup_id_index
== (int)u
)
2221 if (chunk_start
== -1) {
2223 align
= slots
[u
].align
;
2225 /* Offset into the chunk */
2226 unsigned chunk_offset
= (u
- chunk_start
) * UNIFORM_SLOT_SIZE
;
2228 /* Shift the slot alignment down by the chunk offset so it is
2229 * comparable with the base chunk alignment.
2231 struct cplx_align slot_align
= slots
[u
].align
;
2233 (slot_align
.offset
- chunk_offset
) & (align
.mul
- 1);
2235 align
= cplx_align_combine(align
, slot_align
);
2238 /* Sanity check the alignment */
2239 cplx_align_assert_sane(align
);
2241 if (slots
[u
].contiguous
)
2244 /* Adjust the alignment to be in terms of slots, not bytes */
2245 assert((align
.mul
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2246 assert((align
.offset
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2247 align
.mul
/= UNIFORM_SLOT_SIZE
;
2248 align
.offset
/= UNIFORM_SLOT_SIZE
;
2250 unsigned push_start_align
= cplx_align_apply(align
, num_push_constants
);
2251 unsigned chunk_size
= u
- chunk_start
+ 1;
2252 if ((!compiler
->supports_pull_constants
&& u
< UBO_START
) ||
2253 (chunk_size
< max_chunk_size
&&
2254 push_start_align
+ chunk_size
<= max_push_components
)) {
2255 /* Align up the number of push constants */
2256 num_push_constants
= push_start_align
;
2257 for (unsigned i
= 0; i
< chunk_size
; i
++)
2258 push_constant_loc
[chunk_start
+ i
] = num_push_constants
++;
2260 /* We need to pull this one */
2261 num_pull_constants
= cplx_align_apply(align
, num_pull_constants
);
2262 for (unsigned i
= 0; i
< chunk_size
; i
++)
2263 pull_constant_loc
[chunk_start
+ i
] = num_pull_constants
++;
2266 /* Reset the chunk and start again */
2270 /* Add the CS local thread ID uniform at the end of the push constants */
2271 if (subgroup_id_index
>= 0)
2272 push_constant_loc
[subgroup_id_index
] = num_push_constants
++;
2274 /* As the uniforms are going to be reordered, stash the old array and
2275 * create two new arrays for push/pull params.
2277 uint32_t *param
= stage_prog_data
->param
;
2278 stage_prog_data
->nr_params
= num_push_constants
;
2279 if (num_push_constants
) {
2280 stage_prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t,
2281 num_push_constants
);
2283 stage_prog_data
->param
= NULL
;
2285 assert(stage_prog_data
->nr_pull_params
== 0);
2286 assert(stage_prog_data
->pull_param
== NULL
);
2287 if (num_pull_constants
> 0) {
2288 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2289 stage_prog_data
->pull_param
= rzalloc_array(mem_ctx
, uint32_t,
2290 num_pull_constants
);
2293 /* Now that we know how many regular uniforms we'll push, reduce the
2294 * UBO push ranges so we don't exceed the 3DSTATE_CONSTANT limits.
2296 unsigned push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
2297 for (int i
= 0; i
< 4; i
++) {
2298 struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2300 if (push_length
+ range
->length
> 64)
2301 range
->length
= 64 - push_length
;
2303 push_length
+= range
->length
;
2305 assert(push_length
<= 64);
2307 /* Up until now, the param[] array has been indexed by reg + offset
2308 * of UNIFORM registers. Move pull constants into pull_param[] and
2309 * condense param[] to only contain the uniforms we chose to push.
2311 * NOTE: Because we are condensing the params[] array, we know that
2312 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2313 * having to make a copy.
2315 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2316 uint32_t value
= param
[i
];
2317 if (pull_constant_loc
[i
] != -1) {
2318 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2319 } else if (push_constant_loc
[i
] != -1) {
2320 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2327 fs_visitor::get_pull_locs(const fs_reg
&src
,
2328 unsigned *out_surf_index
,
2329 unsigned *out_pull_index
)
2331 assert(src
.file
== UNIFORM
);
2333 if (src
.nr
>= UBO_START
) {
2334 const struct brw_ubo_range
*range
=
2335 &prog_data
->ubo_ranges
[src
.nr
- UBO_START
];
2337 /* If this access is in our (reduced) range, use the push data. */
2338 if (src
.offset
/ 32 < range
->length
)
2341 *out_surf_index
= prog_data
->binding_table
.ubo_start
+ range
->block
;
2342 *out_pull_index
= (32 * range
->start
+ src
.offset
) / 4;
2346 const unsigned location
= src
.nr
+ src
.offset
/ 4;
2348 if (location
< uniforms
&& pull_constant_loc
[location
] != -1) {
2349 /* A regular uniform push constant */
2350 *out_surf_index
= stage_prog_data
->binding_table
.pull_constants_start
;
2351 *out_pull_index
= pull_constant_loc
[location
];
2359 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2360 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2363 fs_visitor::lower_constant_loads()
2365 unsigned index
, pull_index
;
2367 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2368 /* Set up the annotation tracking for new generated instructions. */
2369 const fs_builder
ibld(this, block
, inst
);
2371 for (int i
= 0; i
< inst
->sources
; i
++) {
2372 if (inst
->src
[i
].file
!= UNIFORM
)
2375 /* We'll handle this case later */
2376 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2379 if (!get_pull_locs(inst
->src
[i
], &index
, &pull_index
))
2382 assert(inst
->src
[i
].stride
== 0);
2384 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
2385 const fs_builder ubld
= ibld
.exec_all().group(block_sz
/ 4, 0);
2386 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
2387 const unsigned base
= pull_index
* 4;
2389 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2390 dst
, brw_imm_ud(index
), brw_imm_ud(base
& ~(block_sz
- 1)));
2392 /* Rewrite the instruction to use the temporary VGRF. */
2393 inst
->src
[i
].file
= VGRF
;
2394 inst
->src
[i
].nr
= dst
.nr
;
2395 inst
->src
[i
].offset
= (base
& (block_sz
- 1)) +
2396 inst
->src
[i
].offset
% 4;
2398 brw_mark_surface_used(prog_data
, index
);
2401 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2402 inst
->src
[0].file
== UNIFORM
) {
2404 if (!get_pull_locs(inst
->src
[0], &index
, &pull_index
))
2407 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2411 inst
->remove(block
);
2413 brw_mark_surface_used(prog_data
, index
);
2416 invalidate_live_intervals();
2420 fs_visitor::opt_algebraic()
2422 bool progress
= false;
2424 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2425 switch (inst
->opcode
) {
2426 case BRW_OPCODE_MOV
:
2427 if ((inst
->conditional_mod
== BRW_CONDITIONAL_Z
||
2428 inst
->conditional_mod
== BRW_CONDITIONAL_NZ
) &&
2429 inst
->dst
.is_null() &&
2430 (inst
->src
[0].abs
|| inst
->src
[0].negate
)) {
2431 inst
->src
[0].abs
= false;
2432 inst
->src
[0].negate
= false;
2437 if (inst
->src
[0].file
!= IMM
)
2440 if (inst
->saturate
) {
2441 /* Full mixed-type saturates don't happen. However, we can end up
2444 * mov.sat(8) g21<1>DF -1F
2446 * Other mixed-size-but-same-base-type cases may also be possible.
2448 if (inst
->dst
.type
!= inst
->src
[0].type
&&
2449 inst
->dst
.type
!= BRW_REGISTER_TYPE_DF
&&
2450 inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
)
2451 assert(!"unimplemented: saturate mixed types");
2453 if (brw_saturate_immediate(inst
->src
[0].type
,
2454 &inst
->src
[0].as_brw_reg())) {
2455 inst
->saturate
= false;
2461 case BRW_OPCODE_MUL
:
2462 if (inst
->src
[1].file
!= IMM
)
2466 if (inst
->src
[1].is_one()) {
2467 inst
->opcode
= BRW_OPCODE_MOV
;
2468 inst
->src
[1] = reg_undef
;
2474 if (inst
->src
[1].is_negative_one()) {
2475 inst
->opcode
= BRW_OPCODE_MOV
;
2476 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2477 inst
->src
[1] = reg_undef
;
2483 if (inst
->src
[1].is_zero()) {
2484 inst
->opcode
= BRW_OPCODE_MOV
;
2485 inst
->src
[0] = inst
->src
[1];
2486 inst
->src
[1] = reg_undef
;
2491 if (inst
->src
[0].file
== IMM
) {
2492 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2493 inst
->opcode
= BRW_OPCODE_MOV
;
2494 inst
->src
[0].f
*= inst
->src
[1].f
;
2495 inst
->src
[1] = reg_undef
;
2500 case BRW_OPCODE_ADD
:
2501 if (inst
->src
[1].file
!= IMM
)
2505 if (inst
->src
[1].is_zero()) {
2506 inst
->opcode
= BRW_OPCODE_MOV
;
2507 inst
->src
[1] = reg_undef
;
2512 if (inst
->src
[0].file
== IMM
) {
2513 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2514 inst
->opcode
= BRW_OPCODE_MOV
;
2515 inst
->src
[0].f
+= inst
->src
[1].f
;
2516 inst
->src
[1] = reg_undef
;
2522 if (inst
->src
[0].equals(inst
->src
[1]) ||
2523 inst
->src
[1].is_zero()) {
2524 inst
->opcode
= BRW_OPCODE_MOV
;
2525 inst
->src
[1] = reg_undef
;
2530 case BRW_OPCODE_LRP
:
2531 if (inst
->src
[1].equals(inst
->src
[2])) {
2532 inst
->opcode
= BRW_OPCODE_MOV
;
2533 inst
->src
[0] = inst
->src
[1];
2534 inst
->src
[1] = reg_undef
;
2535 inst
->src
[2] = reg_undef
;
2540 case BRW_OPCODE_CMP
:
2541 if ((inst
->conditional_mod
== BRW_CONDITIONAL_Z
||
2542 inst
->conditional_mod
== BRW_CONDITIONAL_NZ
) &&
2543 inst
->src
[1].is_zero() &&
2544 (inst
->src
[0].abs
|| inst
->src
[0].negate
)) {
2545 inst
->src
[0].abs
= false;
2546 inst
->src
[0].negate
= false;
2551 case BRW_OPCODE_SEL
:
2552 if (inst
->src
[0].equals(inst
->src
[1])) {
2553 inst
->opcode
= BRW_OPCODE_MOV
;
2554 inst
->src
[1] = reg_undef
;
2555 inst
->predicate
= BRW_PREDICATE_NONE
;
2556 inst
->predicate_inverse
= false;
2558 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2559 switch (inst
->conditional_mod
) {
2560 case BRW_CONDITIONAL_LE
:
2561 case BRW_CONDITIONAL_L
:
2562 switch (inst
->src
[1].type
) {
2563 case BRW_REGISTER_TYPE_F
:
2564 if (inst
->src
[1].f
>= 1.0f
) {
2565 inst
->opcode
= BRW_OPCODE_MOV
;
2566 inst
->src
[1] = reg_undef
;
2567 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2575 case BRW_CONDITIONAL_GE
:
2576 case BRW_CONDITIONAL_G
:
2577 switch (inst
->src
[1].type
) {
2578 case BRW_REGISTER_TYPE_F
:
2579 if (inst
->src
[1].f
<= 0.0f
) {
2580 inst
->opcode
= BRW_OPCODE_MOV
;
2581 inst
->src
[1] = reg_undef
;
2582 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2594 case BRW_OPCODE_MAD
:
2595 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2596 inst
->opcode
= BRW_OPCODE_MOV
;
2597 inst
->src
[1] = reg_undef
;
2598 inst
->src
[2] = reg_undef
;
2600 } else if (inst
->src
[0].is_zero()) {
2601 inst
->opcode
= BRW_OPCODE_MUL
;
2602 inst
->src
[0] = inst
->src
[2];
2603 inst
->src
[2] = reg_undef
;
2605 } else if (inst
->src
[1].is_one()) {
2606 inst
->opcode
= BRW_OPCODE_ADD
;
2607 inst
->src
[1] = inst
->src
[2];
2608 inst
->src
[2] = reg_undef
;
2610 } else if (inst
->src
[2].is_one()) {
2611 inst
->opcode
= BRW_OPCODE_ADD
;
2612 inst
->src
[2] = reg_undef
;
2614 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2615 inst
->opcode
= BRW_OPCODE_ADD
;
2616 inst
->src
[1].f
*= inst
->src
[2].f
;
2617 inst
->src
[2] = reg_undef
;
2621 case SHADER_OPCODE_BROADCAST
:
2622 if (is_uniform(inst
->src
[0])) {
2623 inst
->opcode
= BRW_OPCODE_MOV
;
2625 inst
->force_writemask_all
= true;
2627 } else if (inst
->src
[1].file
== IMM
) {
2628 inst
->opcode
= BRW_OPCODE_MOV
;
2629 /* It's possible that the selected component will be too large and
2630 * overflow the register. This can happen if someone does a
2631 * readInvocation() from GLSL or SPIR-V and provides an OOB
2632 * invocationIndex. If this happens and we some how manage
2633 * to constant fold it in and get here, then component() may cause
2634 * us to start reading outside of the VGRF which will lead to an
2635 * assert later. Instead, just let it wrap around if it goes over
2638 const unsigned comp
= inst
->src
[1].ud
& (inst
->exec_size
- 1);
2639 inst
->src
[0] = component(inst
->src
[0], comp
);
2641 inst
->force_writemask_all
= true;
2646 case SHADER_OPCODE_SHUFFLE
:
2647 if (is_uniform(inst
->src
[0])) {
2648 inst
->opcode
= BRW_OPCODE_MOV
;
2651 } else if (inst
->src
[1].file
== IMM
) {
2652 inst
->opcode
= BRW_OPCODE_MOV
;
2653 inst
->src
[0] = component(inst
->src
[0],
2664 /* Swap if src[0] is immediate. */
2665 if (progress
&& inst
->is_commutative()) {
2666 if (inst
->src
[0].file
== IMM
) {
2667 fs_reg tmp
= inst
->src
[1];
2668 inst
->src
[1] = inst
->src
[0];
2677 * Optimize sample messages that have constant zero values for the trailing
2678 * texture coordinates. We can just reduce the message length for these
2679 * instructions instead of reserving a register for it. Trailing parameters
2680 * that aren't sent default to zero anyway. This will cause the dead code
2681 * eliminator to remove the MOV instruction that would otherwise be emitted to
2682 * set up the zero value.
2685 fs_visitor::opt_zero_samples()
2687 /* Gen4 infers the texturing opcode based on the message length so we can't
2690 if (devinfo
->gen
< 5)
2693 bool progress
= false;
2695 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2696 if (!inst
->is_tex())
2699 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2701 if (load_payload
->is_head_sentinel() ||
2702 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2705 /* We don't want to remove the message header or the first parameter.
2706 * Removing the first parameter is not allowed, see the Haswell PRM
2707 * volume 7, page 149:
2709 * "Parameter 0 is required except for the sampleinfo message, which
2710 * has no parameter 0"
2712 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2713 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2714 (inst
->exec_size
/ 8) +
2715 inst
->header_size
- 1].is_zero()) {
2716 inst
->mlen
-= inst
->exec_size
/ 8;
2722 invalidate_live_intervals();
2728 * Optimize sample messages which are followed by the final RT write.
2730 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2731 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2732 * final texturing results copied to the framebuffer write payload and modify
2733 * them to write to the framebuffer directly.
2736 fs_visitor::opt_sampler_eot()
2738 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2740 if (stage
!= MESA_SHADER_FRAGMENT
|| dispatch_width
> 16)
2743 if (devinfo
->gen
!= 9 && !devinfo
->is_cherryview
)
2746 /* FINISHME: It should be possible to implement this optimization when there
2747 * are multiple drawbuffers.
2749 if (key
->nr_color_regions
!= 1)
2752 /* Requires emitting a bunch of saturating MOV instructions during logical
2753 * send lowering to clamp the color payload, which the sampler unit isn't
2754 * going to do for us.
2756 if (key
->clamp_fragment_color
)
2759 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2760 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2761 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2762 assert(fb_write
->eot
);
2763 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2765 /* There wasn't one; nothing to do. */
2766 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2769 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2771 /* 3D Sampler » Messages » Message Format
2773 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2774 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2776 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2777 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2778 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2779 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2780 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2781 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2782 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2783 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2786 /* XXX - This shouldn't be necessary. */
2787 if (tex_inst
->prev
->is_head_sentinel())
2790 /* Check that the FB write sources are fully initialized by the single
2791 * texturing instruction.
2793 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2794 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2795 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2796 fb_write
->size_read(i
) != tex_inst
->size_written
)
2798 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2799 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2804 assert(!tex_inst
->eot
); /* We can't get here twice */
2805 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2807 const fs_builder
ibld(this, block
, tex_inst
);
2809 tex_inst
->offset
|= fb_write
->target
<< 24;
2810 tex_inst
->eot
= true;
2811 tex_inst
->dst
= ibld
.null_reg_ud();
2812 tex_inst
->size_written
= 0;
2813 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2815 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2816 * flag and submit a header together with the sampler message as required
2819 invalidate_live_intervals();
2824 fs_visitor::opt_register_renaming()
2826 bool progress
= false;
2829 int remap
[alloc
.count
];
2830 memset(remap
, -1, sizeof(int) * alloc
.count
);
2832 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2833 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2835 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2836 inst
->opcode
== BRW_OPCODE_WHILE
) {
2840 /* Rewrite instruction sources. */
2841 for (int i
= 0; i
< inst
->sources
; i
++) {
2842 if (inst
->src
[i
].file
== VGRF
&&
2843 remap
[inst
->src
[i
].nr
] != -1 &&
2844 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2845 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2850 const int dst
= inst
->dst
.nr
;
2853 inst
->dst
.file
== VGRF
&&
2854 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
2855 !inst
->is_partial_write()) {
2856 if (remap
[dst
] == -1) {
2859 remap
[dst
] = alloc
.allocate(regs_written(inst
));
2860 inst
->dst
.nr
= remap
[dst
];
2863 } else if (inst
->dst
.file
== VGRF
&&
2865 remap
[dst
] != dst
) {
2866 inst
->dst
.nr
= remap
[dst
];
2872 invalidate_live_intervals();
2874 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2875 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2876 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2885 * Remove redundant or useless discard jumps.
2887 * For example, we can eliminate jumps in the following sequence:
2889 * discard-jump (redundant with the next jump)
2890 * discard-jump (useless; jumps to the next instruction)
2894 fs_visitor::opt_redundant_discard_jumps()
2896 bool progress
= false;
2898 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2900 fs_inst
*placeholder_halt
= NULL
;
2901 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2902 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2903 placeholder_halt
= inst
;
2908 if (!placeholder_halt
)
2911 /* Delete any HALTs immediately before the placeholder halt. */
2912 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2913 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2914 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2915 prev
->remove(last_bblock
);
2920 invalidate_live_intervals();
2926 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2927 * from \p r.offset which overlaps the region starting at \p s.offset and
2928 * spanning \p ds bytes.
2930 static inline unsigned
2931 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
2933 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
2934 const int shift
= rel_offset
/ REG_SIZE
;
2935 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
2936 assert(reg_space(r
) == reg_space(s
) &&
2937 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
2938 return ((1 << n
) - 1) << shift
;
2942 fs_visitor::opt_peephole_csel()
2944 if (devinfo
->gen
< 8)
2947 bool progress
= false;
2949 foreach_block_reverse(block
, cfg
) {
2950 int ip
= block
->end_ip
+ 1;
2952 foreach_inst_in_block_reverse_safe(fs_inst
, inst
, block
) {
2955 if (inst
->opcode
!= BRW_OPCODE_SEL
||
2956 inst
->predicate
!= BRW_PREDICATE_NORMAL
||
2957 (inst
->dst
.type
!= BRW_REGISTER_TYPE_F
&&
2958 inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
2959 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
2962 /* Because it is a 3-src instruction, CSEL cannot have an immediate
2963 * value as a source, but we can sometimes handle zero.
2965 if ((inst
->src
[0].file
!= VGRF
&& inst
->src
[0].file
!= ATTR
&&
2966 inst
->src
[0].file
!= UNIFORM
) ||
2967 (inst
->src
[1].file
!= VGRF
&& inst
->src
[1].file
!= ATTR
&&
2968 inst
->src
[1].file
!= UNIFORM
&& !inst
->src
[1].is_zero()))
2971 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2972 if (!scan_inst
->flags_written())
2975 if ((scan_inst
->opcode
!= BRW_OPCODE_CMP
&&
2976 scan_inst
->opcode
!= BRW_OPCODE_MOV
) ||
2977 scan_inst
->predicate
!= BRW_PREDICATE_NONE
||
2978 (scan_inst
->src
[0].file
!= VGRF
&&
2979 scan_inst
->src
[0].file
!= ATTR
&&
2980 scan_inst
->src
[0].file
!= UNIFORM
) ||
2981 scan_inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
)
2984 if (scan_inst
->opcode
== BRW_OPCODE_CMP
&& !scan_inst
->src
[1].is_zero())
2987 const brw::fs_builder
ibld(this, block
, inst
);
2989 const enum brw_conditional_mod cond
=
2990 inst
->predicate_inverse
2991 ? brw_negate_cmod(scan_inst
->conditional_mod
)
2992 : scan_inst
->conditional_mod
;
2994 fs_inst
*csel_inst
= NULL
;
2996 if (inst
->src
[1].file
!= IMM
) {
2997 csel_inst
= ibld
.CSEL(inst
->dst
,
3002 } else if (cond
== BRW_CONDITIONAL_NZ
) {
3003 /* Consider the sequence
3005 * cmp.nz.f0 null<1>F g3<8,8,1>F 0F
3006 * (+f0) sel g124<1>UD g2<8,8,1>UD 0x00000000UD
3008 * The sel will pick the immediate value 0 if r0 is ±0.0.
3009 * Therefore, this sequence is equivalent:
3011 * cmp.nz.f0 null<1>F g3<8,8,1>F 0F
3012 * (+f0) sel g124<1>F g2<8,8,1>F (abs)g3<8,8,1>F
3014 * The abs is ensures that the result is 0UD when g3 is -0.0F.
3015 * By normal cmp-sel merging, this is also equivalent:
3017 * csel.nz g124<1>F g2<4,4,1>F (abs)g3<4,4,1>F g3<4,4,1>F
3019 csel_inst
= ibld
.CSEL(inst
->dst
,
3025 csel_inst
->src
[1].abs
= true;
3028 if (csel_inst
!= NULL
) {
3030 inst
->remove(block
);
3042 fs_visitor::compute_to_mrf()
3044 bool progress
= false;
3047 /* No MRFs on Gen >= 7. */
3048 if (devinfo
->gen
>= 7)
3051 calculate_live_intervals();
3053 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3057 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3058 inst
->is_partial_write() ||
3059 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
3060 inst
->dst
.type
!= inst
->src
[0].type
||
3061 inst
->src
[0].abs
|| inst
->src
[0].negate
||
3062 !inst
->src
[0].is_contiguous() ||
3063 inst
->src
[0].offset
% REG_SIZE
!= 0)
3066 /* Can't compute-to-MRF this GRF if someone else was going to
3069 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
3072 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
3073 * things that computed the value of all GRFs of the source region. The
3074 * regs_left bitset keeps track of the registers we haven't yet found a
3075 * generating instruction for.
3077 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
3079 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3080 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3081 inst
->src
[0], inst
->size_read(0))) {
3082 /* Found the last thing to write our reg we want to turn
3083 * into a compute-to-MRF.
3086 /* If this one instruction didn't populate all the
3087 * channels, bail. We might be able to rewrite everything
3088 * that writes that reg, but it would require smarter
3091 if (scan_inst
->is_partial_write())
3094 /* Handling things not fully contained in the source of the copy
3095 * would need us to understand coalescing out more than one MOV at
3098 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
3099 inst
->src
[0], inst
->size_read(0)))
3102 /* SEND instructions can't have MRF as a destination. */
3103 if (scan_inst
->mlen
)
3106 if (devinfo
->gen
== 6) {
3107 /* gen6 math instructions must have the destination be
3108 * GRF, so no compute-to-MRF for them.
3110 if (scan_inst
->is_math()) {
3115 /* Clear the bits for any registers this instruction overwrites. */
3116 regs_left
&= ~mask_relative_to(
3117 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3122 /* We don't handle control flow here. Most computation of
3123 * values that end up in MRFs are shortly before the MRF
3126 if (block
->start() == scan_inst
)
3129 /* You can't read from an MRF, so if someone else reads our
3130 * MRF's source GRF that we wanted to rewrite, that stops us.
3132 bool interfered
= false;
3133 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
3134 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
3135 inst
->src
[0], inst
->size_read(0))) {
3142 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3143 inst
->dst
, inst
->size_written
)) {
3144 /* If somebody else writes our MRF here, we can't
3145 * compute-to-MRF before that.
3150 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
3151 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
3152 inst
->dst
, inst
->size_written
)) {
3153 /* Found a SEND instruction, which means that there are
3154 * live values in MRFs from base_mrf to base_mrf +
3155 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3165 /* Found all generating instructions of our MRF's source value, so it
3166 * should be safe to rewrite them to point to the MRF directly.
3168 regs_left
= (1 << regs_read(inst
, 0)) - 1;
3170 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3171 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3172 inst
->src
[0], inst
->size_read(0))) {
3173 /* Clear the bits for any registers this instruction overwrites. */
3174 regs_left
&= ~mask_relative_to(
3175 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3177 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
3178 reg_offset(inst
->src
[0]);
3180 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
3181 /* Apply the same address transformation done by the hardware
3182 * for COMPR4 MRF writes.
3184 assert(rel_offset
< 2 * REG_SIZE
);
3185 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
3187 /* Clear the COMPR4 bit if the generating instruction is not
3190 if (scan_inst
->size_written
< 2 * REG_SIZE
)
3191 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
3194 /* Calculate the MRF number the result of this instruction is
3195 * ultimately written to.
3197 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
3200 scan_inst
->dst
.file
= MRF
;
3201 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
3202 scan_inst
->saturate
|= inst
->saturate
;
3209 inst
->remove(block
);
3214 invalidate_live_intervals();
3220 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
3221 * flow. We could probably do better here with some form of divergence
3225 fs_visitor::eliminate_find_live_channel()
3227 bool progress
= false;
3230 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
3231 /* The optimization below assumes that channel zero is live on thread
3232 * dispatch, which may not be the case if the fixed function dispatches
3238 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3239 switch (inst
->opcode
) {
3245 case BRW_OPCODE_ENDIF
:
3246 case BRW_OPCODE_WHILE
:
3250 case FS_OPCODE_DISCARD_JUMP
:
3251 /* This can potentially make control flow non-uniform until the end
3256 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
3258 inst
->opcode
= BRW_OPCODE_MOV
;
3259 inst
->src
[0] = brw_imm_ud(0u);
3261 inst
->force_writemask_all
= true;
3275 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
3276 * instructions to FS_OPCODE_REP_FB_WRITE.
3279 fs_visitor::emit_repclear_shader()
3281 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3283 int color_mrf
= base_mrf
+ 2;
3287 mov
= bld
.exec_all().group(4, 0)
3288 .MOV(brw_message_reg(color_mrf
),
3289 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
3291 struct brw_reg reg
=
3292 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
3293 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
3294 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
3296 mov
= bld
.exec_all().group(4, 0)
3297 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
3300 fs_inst
*write
= NULL
;
3301 if (key
->nr_color_regions
== 1) {
3302 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3303 write
->saturate
= key
->clamp_fragment_color
;
3304 write
->base_mrf
= color_mrf
;
3306 write
->header_size
= 0;
3309 assume(key
->nr_color_regions
> 0);
3311 struct brw_reg header
=
3312 retype(brw_message_reg(base_mrf
), BRW_REGISTER_TYPE_UD
);
3313 bld
.exec_all().group(16, 0)
3314 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3316 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
3318 bld
.exec_all().group(1, 0)
3319 .MOV(component(header
, 2), brw_imm_ud(i
));
3322 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3323 write
->saturate
= key
->clamp_fragment_color
;
3324 write
->base_mrf
= base_mrf
;
3326 write
->header_size
= 2;
3331 write
->last_rt
= true;
3335 assign_constant_locations();
3336 assign_curb_setup();
3338 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3340 assert(mov
->src
[0].file
== FIXED_GRF
);
3341 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3346 * Walks through basic blocks, looking for repeated MRF writes and
3347 * removing the later ones.
3350 fs_visitor::remove_duplicate_mrf_writes()
3352 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3353 bool progress
= false;
3355 /* Need to update the MRF tracking for compressed instructions. */
3356 if (dispatch_width
>= 16)
3359 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3361 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3362 if (inst
->is_control_flow()) {
3363 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3366 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3367 inst
->dst
.file
== MRF
) {
3368 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3369 if (prev_inst
&& inst
->equals(prev_inst
)) {
3370 inst
->remove(block
);
3376 /* Clear out the last-write records for MRFs that were overwritten. */
3377 if (inst
->dst
.file
== MRF
) {
3378 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3381 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3382 /* Found a SEND instruction, which will include two or fewer
3383 * implied MRF writes. We could do better here.
3385 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3386 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3390 /* Clear out any MRF move records whose sources got overwritten. */
3391 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3392 if (last_mrf_move
[i
] &&
3393 regions_overlap(inst
->dst
, inst
->size_written
,
3394 last_mrf_move
[i
]->src
[0],
3395 last_mrf_move
[i
]->size_read(0))) {
3396 last_mrf_move
[i
] = NULL
;
3400 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3401 inst
->dst
.file
== MRF
&&
3402 inst
->src
[0].file
!= ARF
&&
3403 !inst
->is_partial_write()) {
3404 last_mrf_move
[inst
->dst
.nr
] = inst
;
3409 invalidate_live_intervals();
3415 * Rounding modes for conversion instructions are included for each
3416 * conversion, but right now it is a state. So once it is set,
3417 * we don't need to call it again for subsequent calls.
3419 * This is useful for vector/matrices conversions, as setting the
3420 * mode once is enough for the full vector/matrix
3423 fs_visitor::remove_extra_rounding_modes()
3425 bool progress
= false;
3427 foreach_block (block
, cfg
) {
3428 brw_rnd_mode prev_mode
= BRW_RND_MODE_UNSPECIFIED
;
3430 foreach_inst_in_block_safe (fs_inst
, inst
, block
) {
3431 if (inst
->opcode
== SHADER_OPCODE_RND_MODE
) {
3432 assert(inst
->src
[0].file
== BRW_IMMEDIATE_VALUE
);
3433 const brw_rnd_mode mode
= (brw_rnd_mode
) inst
->src
[0].d
;
3434 if (mode
== prev_mode
) {
3435 inst
->remove(block
);
3445 invalidate_live_intervals();
3451 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3453 /* Clear the flag for registers that actually got read (as expected). */
3454 for (int i
= 0; i
< inst
->sources
; i
++) {
3456 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3457 grf
= inst
->src
[i
].nr
;
3462 if (grf
>= first_grf
&&
3463 grf
< first_grf
+ grf_len
) {
3464 deps
[grf
- first_grf
] = false;
3465 if (inst
->exec_size
== 16)
3466 deps
[grf
- first_grf
+ 1] = false;
3472 * Implements this workaround for the original 965:
3474 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3475 * check for post destination dependencies on this instruction, software
3476 * must ensure that there is no destination hazard for the case of ‘write
3477 * followed by a posted write’ shown in the following example.
3480 * 2. send r3.xy <rest of send instruction>
3483 * Due to no post-destination dependency check on the ‘send’, the above
3484 * code sequence could have two instructions (1 and 2) in flight at the
3485 * same time that both consider ‘r3’ as the target of their final writes.
3488 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3491 int write_len
= regs_written(inst
);
3492 int first_write_grf
= inst
->dst
.nr
;
3493 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3494 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3496 memset(needs_dep
, false, sizeof(needs_dep
));
3497 memset(needs_dep
, true, write_len
);
3499 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3501 /* Walk backwards looking for writes to registers we're writing which
3502 * aren't read since being written. If we hit the start of the program,
3503 * we assume that there are no outstanding dependencies on entry to the
3506 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3507 /* If we hit control flow, assume that there *are* outstanding
3508 * dependencies, and force their cleanup before our instruction.
3510 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3511 for (int i
= 0; i
< write_len
; i
++) {
3513 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3514 first_write_grf
+ i
);
3519 /* We insert our reads as late as possible on the assumption that any
3520 * instruction but a MOV that might have left us an outstanding
3521 * dependency has more latency than a MOV.
3523 if (scan_inst
->dst
.file
== VGRF
) {
3524 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3525 int reg
= scan_inst
->dst
.nr
+ i
;
3527 if (reg
>= first_write_grf
&&
3528 reg
< first_write_grf
+ write_len
&&
3529 needs_dep
[reg
- first_write_grf
]) {
3530 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3531 needs_dep
[reg
- first_write_grf
] = false;
3532 if (scan_inst
->exec_size
== 16)
3533 needs_dep
[reg
- first_write_grf
+ 1] = false;
3538 /* Clear the flag for registers that actually got read (as expected). */
3539 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3541 /* Continue the loop only if we haven't resolved all the dependencies */
3543 for (i
= 0; i
< write_len
; i
++) {
3553 * Implements this workaround for the original 965:
3555 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3556 * used as a destination register until after it has been sourced by an
3557 * instruction with a different destination register.
3560 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3562 int write_len
= regs_written(inst
);
3563 int first_write_grf
= inst
->dst
.nr
;
3564 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3565 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3567 memset(needs_dep
, false, sizeof(needs_dep
));
3568 memset(needs_dep
, true, write_len
);
3569 /* Walk forwards looking for writes to registers we're writing which aren't
3570 * read before being written.
3572 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3573 /* If we hit control flow, force resolve all remaining dependencies. */
3574 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3575 for (int i
= 0; i
< write_len
; i
++) {
3577 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3578 first_write_grf
+ i
);
3583 /* Clear the flag for registers that actually got read (as expected). */
3584 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3586 /* We insert our reads as late as possible since they're reading the
3587 * result of a SEND, which has massive latency.
3589 if (scan_inst
->dst
.file
== VGRF
&&
3590 scan_inst
->dst
.nr
>= first_write_grf
&&
3591 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3592 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3593 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3595 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3598 /* Continue the loop only if we haven't resolved all the dependencies */
3600 for (i
= 0; i
< write_len
; i
++) {
3610 fs_visitor::insert_gen4_send_dependency_workarounds()
3612 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3615 bool progress
= false;
3617 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3618 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3619 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3620 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3626 invalidate_live_intervals();
3630 * Turns the generic expression-style uniform pull constant load instruction
3631 * into a hardware-specific series of instructions for loading a pull
3634 * The expression style allows the CSE pass before this to optimize out
3635 * repeated loads from the same offset, and gives the pre-register-allocation
3636 * scheduling full flexibility, while the conversion to native instructions
3637 * allows the post-register-allocation scheduler the best information
3640 * Note that execution masking for setting up pull constant loads is special:
3641 * the channels that need to be written are unrelated to the current execution
3642 * mask, since a later instruction will use one of the result channels as a
3643 * source operand for all 8 or 16 of its channels.
3646 fs_visitor::lower_uniform_pull_constant_loads()
3648 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3649 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3652 if (devinfo
->gen
>= 7) {
3653 const fs_builder ubld
= fs_builder(this, block
, inst
).exec_all();
3654 const fs_reg payload
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
);
3656 ubld
.group(8, 0).MOV(payload
,
3657 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3658 ubld
.group(1, 0).MOV(component(payload
, 2),
3659 brw_imm_ud(inst
->src
[1].ud
/ 16));
3661 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3662 inst
->src
[1] = payload
;
3663 inst
->header_size
= 1;
3666 invalidate_live_intervals();
3668 /* Before register allocation, we didn't tell the scheduler about the
3669 * MRF we use. We know it's safe to use this MRF because nothing
3670 * else does except for register spill/unspill, which generates and
3671 * uses its MRF within a single IR instruction.
3673 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3680 fs_visitor::lower_load_payload()
3682 bool progress
= false;
3684 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3685 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3688 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3689 assert(inst
->saturate
== false);
3690 fs_reg dst
= inst
->dst
;
3692 /* Get rid of COMPR4. We'll add it back in if we need it */
3693 if (dst
.file
== MRF
)
3694 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3696 const fs_builder
ibld(this, block
, inst
);
3697 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3699 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3700 if (inst
->src
[i
].file
!= BAD_FILE
) {
3701 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3702 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3703 hbld
.MOV(mov_dst
, mov_src
);
3705 dst
= offset(dst
, hbld
, 1);
3708 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3709 inst
->exec_size
> 8) {
3710 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3711 * a straightforward copy. Instead, the result of the
3712 * LOAD_PAYLOAD is treated as interleaved and the first four
3713 * non-header sources are unpacked as:
3724 * This is used for gen <= 5 fb writes.
3726 assert(inst
->exec_size
== 16);
3727 assert(inst
->header_size
+ 4 <= inst
->sources
);
3728 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3729 if (inst
->src
[i
].file
!= BAD_FILE
) {
3730 if (devinfo
->has_compr4
) {
3731 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3732 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3733 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3735 /* Platform doesn't have COMPR4. We have to fake it */
3736 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3737 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3739 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3746 /* The loop above only ever incremented us through the first set
3747 * of 4 registers. However, thanks to the magic of COMPR4, we
3748 * actually wrote to the first 8 registers, so we need to take
3749 * that into account now.
3753 /* The COMPR4 code took care of the first 4 sources. We'll let
3754 * the regular path handle any remaining sources. Yes, we are
3755 * modifying the instruction but we're about to delete it so
3756 * this really doesn't hurt anything.
3758 inst
->header_size
+= 4;
3761 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3762 if (inst
->src
[i
].file
!= BAD_FILE
)
3763 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3764 dst
= offset(dst
, ibld
, 1);
3767 inst
->remove(block
);
3772 invalidate_live_intervals();
3778 fs_visitor::lower_integer_multiplication()
3780 bool progress
= false;
3782 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3783 const fs_builder
ibld(this, block
, inst
);
3785 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3786 if (inst
->dst
.is_accumulator() ||
3787 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3788 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3791 if (devinfo
->has_integer_dword_mul
)
3794 if (inst
->src
[1].file
== IMM
&&
3795 inst
->src
[1].ud
< (1 << 16)) {
3796 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3797 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3800 * If multiplying by an immediate value that fits in 16-bits, do a
3801 * single MUL instruction with that value in the proper location.
3803 if (devinfo
->gen
< 7) {
3804 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3806 ibld
.MOV(imm
, inst
->src
[1]);
3807 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3809 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3810 ibld
.MUL(inst
->dst
, inst
->src
[0],
3811 ud
? brw_imm_uw(inst
->src
[1].ud
)
3812 : brw_imm_w(inst
->src
[1].d
));
3815 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3816 * do 32-bit integer multiplication in one instruction, but instead
3817 * must do a sequence (which actually calculates a 64-bit result):
3819 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3820 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3821 * mov(8) g2<1>D acc0<8,8,1>D
3823 * But on Gen > 6, the ability to use second accumulator register
3824 * (acc1) for non-float data types was removed, preventing a simple
3825 * implementation in SIMD16. A 16-channel result can be calculated by
3826 * executing the three instructions twice in SIMD8, once with quarter
3827 * control of 1Q for the first eight channels and again with 2Q for
3828 * the second eight channels.
3830 * Which accumulator register is implicitly accessed (by AccWrEnable
3831 * for instance) is determined by the quarter control. Unfortunately
3832 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3833 * implicit accumulator access by an instruction with 2Q will access
3834 * acc1 regardless of whether the data type is usable in acc1.
3836 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3837 * integer data types.
3839 * Since we only want the low 32-bits of the result, we can do two
3840 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3841 * adjust the high result and add them (like the mach is doing):
3843 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3844 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3845 * shl(8) g9<1>D g8<8,8,1>D 16D
3846 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3848 * We avoid the shl instruction by realizing that we only want to add
3849 * the low 16-bits of the "high" result to the high 16-bits of the
3850 * "low" result and using proper regioning on the add:
3852 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3853 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3854 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3856 * Since it does not use the (single) accumulator register, we can
3857 * schedule multi-component multiplications much better.
3860 bool needs_mov
= false;
3861 fs_reg orig_dst
= inst
->dst
;
3862 fs_reg low
= inst
->dst
;
3863 if (orig_dst
.is_null() || orig_dst
.file
== MRF
||
3864 regions_overlap(inst
->dst
, inst
->size_written
,
3865 inst
->src
[0], inst
->size_read(0)) ||
3866 regions_overlap(inst
->dst
, inst
->size_written
,
3867 inst
->src
[1], inst
->size_read(1))) {
3869 /* Get a new VGRF but keep the same stride as inst->dst */
3870 low
= fs_reg(VGRF
, alloc
.allocate(regs_written(inst
)),
3872 low
.stride
= inst
->dst
.stride
;
3873 low
.offset
= inst
->dst
.offset
% REG_SIZE
;
3876 /* Get a new VGRF but keep the same stride as inst->dst */
3877 fs_reg
high(VGRF
, alloc
.allocate(regs_written(inst
)),
3879 high
.stride
= inst
->dst
.stride
;
3880 high
.offset
= inst
->dst
.offset
% REG_SIZE
;
3882 if (devinfo
->gen
>= 7) {
3883 if (inst
->src
[1].abs
)
3884 lower_src_modifiers(this, block
, inst
, 1);
3886 if (inst
->src
[1].file
== IMM
) {
3887 ibld
.MUL(low
, inst
->src
[0],
3888 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
3889 ibld
.MUL(high
, inst
->src
[0],
3890 brw_imm_uw(inst
->src
[1].ud
>> 16));
3892 ibld
.MUL(low
, inst
->src
[0],
3893 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
3894 ibld
.MUL(high
, inst
->src
[0],
3895 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
3898 if (inst
->src
[0].abs
)
3899 lower_src_modifiers(this, block
, inst
, 0);
3901 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
3903 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
3907 ibld
.ADD(subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3908 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3909 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
3911 if (needs_mov
|| inst
->conditional_mod
) {
3912 set_condmod(inst
->conditional_mod
,
3913 ibld
.MOV(orig_dst
, low
));
3917 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3918 /* According to the BDW+ BSpec page for the "Multiply Accumulate
3919 * High" instruction:
3921 * "An added preliminary mov is required for source modification on
3923 * mov (8) r3.0<1>:d -r3<8;8,1>:d
3924 * mul (8) acc0:d r2.0<8;8,1>:d r3.0<16;8,2>:uw
3925 * mach (8) r5.0<1>:d r2.0<8;8,1>:d r3.0<8;8,1>:d"
3927 if (devinfo
->gen
>= 8 && (inst
->src
[1].negate
|| inst
->src
[1].abs
))
3928 lower_src_modifiers(this, block
, inst
, 1);
3930 /* Should have been lowered to 8-wide. */
3931 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
3932 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3934 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3935 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3937 if (devinfo
->gen
>= 8) {
3938 /* Until Gen8, integer multiplies read 32-bits from one source,
3939 * and 16-bits from the other, and relying on the MACH instruction
3940 * to generate the high bits of the result.
3942 * On Gen8, the multiply instruction does a full 32x32-bit
3943 * multiply, but in order to do a 64-bit multiply we can simulate
3944 * the previous behavior and then use a MACH instruction.
3946 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3947 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3948 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3949 mul
->src
[1].stride
*= 2;
3951 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3953 /* Among other things the quarter control bits influence which
3954 * accumulator register is used by the hardware for instructions
3955 * that access the accumulator implicitly (e.g. MACH). A
3956 * second-half instruction would normally map to acc1, which
3957 * doesn't exist on Gen7 and up (the hardware does emulate it for
3958 * floating-point instructions *only* by taking advantage of the
3959 * extra precision of acc0 not normally used for floating point
3962 * HSW and up are careful enough not to try to access an
3963 * accumulator register that doesn't exist, but on earlier Gen7
3964 * hardware we need to make sure that the quarter control bits are
3965 * zero to avoid non-deterministic behaviour and emit an extra MOV
3966 * to get the result masked correctly according to the current
3970 mach
->force_writemask_all
= true;
3971 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3972 ibld
.MOV(inst
->dst
, mach
->dst
);
3978 inst
->remove(block
);
3983 invalidate_live_intervals();
3989 fs_visitor::lower_minmax()
3991 assert(devinfo
->gen
< 6);
3993 bool progress
= false;
3995 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3996 const fs_builder
ibld(this, block
, inst
);
3998 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3999 inst
->predicate
== BRW_PREDICATE_NONE
) {
4000 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
4001 * the original SEL.L/GE instruction
4003 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
4004 inst
->conditional_mod
);
4005 inst
->predicate
= BRW_PREDICATE_NORMAL
;
4006 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
4013 invalidate_live_intervals();
4019 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
4020 fs_reg
*dst
, fs_reg color
, unsigned components
)
4022 if (key
->clamp_fragment_color
) {
4023 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
4024 assert(color
.type
== BRW_REGISTER_TYPE_F
);
4026 for (unsigned i
= 0; i
< components
; i
++)
4028 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
4033 for (unsigned i
= 0; i
< components
; i
++)
4034 dst
[i
] = offset(color
, bld
, i
);
4038 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
4039 const struct brw_wm_prog_data
*prog_data
,
4040 const brw_wm_prog_key
*key
,
4041 const fs_visitor::thread_payload
&payload
)
4043 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
4044 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4045 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
4046 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
4047 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
4048 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
4049 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
4050 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
4051 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
4052 const unsigned components
=
4053 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
4055 /* We can potentially have a message length of up to 15, so we have to set
4056 * base_mrf to either 0 or 1 in order to fit in m0..m15.
4059 int header_size
= 2, payload_header_size
;
4060 unsigned length
= 0;
4062 if (devinfo
->gen
< 6) {
4063 /* TODO: Support SIMD32 on gen4-5 */
4064 assert(bld
.group() < 16);
4066 /* For gen4-5, we always have a header consisting of g0 and g1. We have
4067 * an implied MOV from g0,g1 to the start of the message. The MOV from
4068 * g0 is handled by the hardware and the MOV from g1 is provided by the
4069 * generator. This is required because, on gen4-5, the generator may
4070 * generate two write messages with different message lengths in order
4071 * to handle AA data properly.
4073 * Also, since the pixel mask goes in the g0 portion of the message and
4074 * since render target writes are the last thing in the shader, we write
4075 * the pixel mask directly into g0 and it will get copied as part of the
4078 if (prog_data
->uses_kill
) {
4079 bld
.exec_all().group(1, 0)
4080 .MOV(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
),
4081 brw_flag_reg(0, 1));
4084 assert(length
== 0);
4086 } else if ((devinfo
->gen
<= 7 && !devinfo
->is_haswell
&&
4087 prog_data
->uses_kill
) ||
4088 color1
.file
!= BAD_FILE
||
4089 key
->nr_color_regions
> 1) {
4090 /* From the Sandy Bridge PRM, volume 4, page 198:
4092 * "Dispatched Pixel Enables. One bit per pixel indicating
4093 * which pixels were originally enabled when the thread was
4094 * dispatched. This field is only required for the end-of-
4095 * thread message and on all dual-source messages."
4097 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4099 fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4100 if (bld
.group() < 16) {
4101 /* The header starts off as g0 and g1 for the first half */
4102 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4103 BRW_REGISTER_TYPE_UD
));
4105 /* The header starts off as g0 and g2 for the second half */
4106 assert(bld
.group() < 32);
4107 const fs_reg header_sources
[2] = {
4108 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4109 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
),
4111 ubld
.LOAD_PAYLOAD(header
, header_sources
, 2, 0);
4114 uint32_t g00_bits
= 0;
4116 /* Set "Source0 Alpha Present to RenderTarget" bit in message
4119 if (inst
->target
> 0 && key
->replicate_alpha
)
4120 g00_bits
|= 1 << 11;
4122 /* Set computes stencil to render target */
4123 if (prog_data
->computed_stencil
)
4124 g00_bits
|= 1 << 14;
4127 /* OR extra bits into g0.0 */
4128 ubld
.group(1, 0).OR(component(header
, 0),
4129 retype(brw_vec1_grf(0, 0),
4130 BRW_REGISTER_TYPE_UD
),
4131 brw_imm_ud(g00_bits
));
4134 /* Set the render target index for choosing BLEND_STATE. */
4135 if (inst
->target
> 0) {
4136 ubld
.group(1, 0).MOV(component(header
, 2), brw_imm_ud(inst
->target
));
4139 if (prog_data
->uses_kill
) {
4140 assert(bld
.group() < 16);
4141 ubld
.group(1, 0).MOV(retype(component(header
, 15),
4142 BRW_REGISTER_TYPE_UW
),
4143 brw_flag_reg(0, 1));
4146 assert(length
== 0);
4147 sources
[0] = header
;
4148 sources
[1] = horiz_offset(header
, 8);
4151 assert(length
== 0 || length
== 2);
4152 header_size
= length
;
4154 if (payload
.aa_dest_stencil_reg
[0]) {
4155 assert(inst
->group
< 16);
4156 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
4157 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
4158 .MOV(sources
[length
],
4159 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
[0], 0)));
4163 if (sample_mask
.file
!= BAD_FILE
) {
4164 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
4165 BRW_REGISTER_TYPE_UD
);
4167 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
4168 * relevant. Since it's unsigned single words one vgrf is always
4169 * 16-wide, but only the lower or higher 8 channels will be used by the
4170 * hardware when doing a SIMD8 write depending on whether we have
4171 * selected the subspans for the first or second half respectively.
4173 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
4174 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
4175 sample_mask
.stride
*= 2;
4177 bld
.exec_all().annotate("FB write oMask")
4178 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
4184 payload_header_size
= length
;
4186 if (src0_alpha
.file
!= BAD_FILE
) {
4187 /* FIXME: This is being passed at the wrong location in the payload and
4188 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
4189 * It's supposed to be immediately before oMask but there seems to be no
4190 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
4191 * requires header sources to form a contiguous segment at the beginning
4192 * of the message and src0_alpha has per-channel semantics.
4194 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
4196 } else if (key
->replicate_alpha
&& inst
->target
!= 0) {
4197 /* Handle the case when fragment shader doesn't write to draw buffer
4198 * zero. No need to call setup_color_payload() for src0_alpha because
4199 * alpha value will be undefined.
4204 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
4207 if (color1
.file
!= BAD_FILE
) {
4208 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
4212 if (src_depth
.file
!= BAD_FILE
) {
4213 sources
[length
] = src_depth
;
4217 if (dst_depth
.file
!= BAD_FILE
) {
4218 sources
[length
] = dst_depth
;
4222 if (src_stencil
.file
!= BAD_FILE
) {
4223 assert(devinfo
->gen
>= 9);
4224 assert(bld
.dispatch_width() == 8);
4226 /* XXX: src_stencil is only available on gen9+. dst_depth is never
4227 * available on gen9+. As such it's impossible to have both enabled at the
4228 * same time and therefore length cannot overrun the array.
4230 assert(length
< 15);
4232 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4233 bld
.exec_all().annotate("FB write OS")
4234 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
4235 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
4240 if (devinfo
->gen
>= 7) {
4241 /* Send from the GRF */
4242 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
4243 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
4244 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
4245 load
->dst
= payload
;
4247 inst
->src
[0] = payload
;
4248 inst
->resize_sources(1);
4250 /* Send from the MRF */
4251 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
4252 sources
, length
, payload_header_size
);
4254 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
4255 * will do this for us if we just give it a COMPR4 destination.
4257 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
4258 load
->dst
.nr
|= BRW_MRF_COMPR4
;
4260 if (devinfo
->gen
< 6) {
4261 /* Set up src[0] for the implied MOV from grf0-1 */
4262 inst
->resize_sources(1);
4263 inst
->src
[0] = brw_vec8_grf(0, 0);
4265 inst
->resize_sources(0);
4270 inst
->opcode
= FS_OPCODE_FB_WRITE
;
4271 inst
->mlen
= regs_written(load
);
4272 inst
->header_size
= header_size
;
4276 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4278 const fs_builder
&ubld
= bld
.exec_all().group(8, 0);
4279 const unsigned length
= 2;
4280 const fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, length
);
4282 if (bld
.group() < 16) {
4283 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4284 BRW_REGISTER_TYPE_UD
));
4286 assert(bld
.group() < 32);
4287 const fs_reg header_sources
[] = {
4288 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4289 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
)
4291 ubld
.LOAD_PAYLOAD(header
, header_sources
, ARRAY_SIZE(header_sources
), 0);
4294 inst
->resize_sources(1);
4295 inst
->src
[0] = header
;
4296 inst
->opcode
= FS_OPCODE_FB_READ
;
4297 inst
->mlen
= length
;
4298 inst
->header_size
= length
;
4302 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4303 const fs_reg
&coordinate
,
4304 const fs_reg
&shadow_c
,
4305 const fs_reg
&lod
, const fs_reg
&lod2
,
4306 const fs_reg
&surface
,
4307 const fs_reg
&sampler
,
4308 unsigned coord_components
,
4309 unsigned grad_components
)
4311 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
4312 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
4313 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
4314 fs_reg msg_end
= msg_begin
;
4317 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
4319 for (unsigned i
= 0; i
< coord_components
; i
++)
4320 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
4321 offset(coordinate
, bld
, i
));
4323 msg_end
= offset(msg_end
, bld
, coord_components
);
4325 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
4326 * require all three components to be present and zero if they are unused.
4328 if (coord_components
> 0 &&
4329 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
4330 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
4331 for (unsigned i
= coord_components
; i
< 3; i
++)
4332 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
4334 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
4337 if (op
== SHADER_OPCODE_TXD
) {
4338 /* TXD unsupported in SIMD16 mode. */
4339 assert(bld
.dispatch_width() == 8);
4341 /* the slots for u and v are always present, but r is optional */
4342 if (coord_components
< 2)
4343 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
4346 * dPdx = dudx, dvdx, drdx
4347 * dPdy = dudy, dvdy, drdy
4349 * 1-arg: Does not exist.
4351 * 2-arg: dudx dvdx dudy dvdy
4352 * dPdx.x dPdx.y dPdy.x dPdy.y
4355 * 3-arg: dudx dvdx drdx dudy dvdy drdy
4356 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
4357 * m5 m6 m7 m8 m9 m10
4359 for (unsigned i
= 0; i
< grad_components
; i
++)
4360 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
4362 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4364 for (unsigned i
= 0; i
< grad_components
; i
++)
4365 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
4367 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4371 /* Bias/LOD with shadow comparator is unsupported in SIMD16 -- *Without*
4372 * shadow comparator (including RESINFO) it's unsupported in SIMD8 mode.
4374 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
4375 bld
.dispatch_width() == 16);
4377 const brw_reg_type type
=
4378 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
4379 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
4380 bld
.MOV(retype(msg_end
, type
), lod
);
4381 msg_end
= offset(msg_end
, bld
, 1);
4384 if (shadow_c
.file
!= BAD_FILE
) {
4385 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
4386 /* There's no plain shadow compare message, so we use shadow
4387 * compare with a bias of 0.0.
4389 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
4390 msg_end
= offset(msg_end
, bld
, 1);
4393 bld
.MOV(msg_end
, shadow_c
);
4394 msg_end
= offset(msg_end
, bld
, 1);
4398 inst
->src
[0] = reg_undef
;
4399 inst
->src
[1] = surface
;
4400 inst
->src
[2] = sampler
;
4401 inst
->resize_sources(3);
4402 inst
->base_mrf
= msg_begin
.nr
;
4403 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
4404 inst
->header_size
= 1;
4408 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4409 const fs_reg
&coordinate
,
4410 const fs_reg
&shadow_c
,
4411 const fs_reg
&lod
, const fs_reg
&lod2
,
4412 const fs_reg
&sample_index
,
4413 const fs_reg
&surface
,
4414 const fs_reg
&sampler
,
4415 unsigned coord_components
,
4416 unsigned grad_components
)
4418 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
4419 fs_reg msg_coords
= message
;
4420 unsigned header_size
= 0;
4422 if (inst
->offset
!= 0) {
4423 /* The offsets set up by the visitor are in the m1 header, so we can't
4430 for (unsigned i
= 0; i
< coord_components
; i
++)
4431 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
4432 offset(coordinate
, bld
, i
));
4434 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
4435 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
4437 if (shadow_c
.file
!= BAD_FILE
) {
4438 fs_reg msg_shadow
= msg_lod
;
4439 bld
.MOV(msg_shadow
, shadow_c
);
4440 msg_lod
= offset(msg_shadow
, bld
, 1);
4445 case SHADER_OPCODE_TXL
:
4447 bld
.MOV(msg_lod
, lod
);
4448 msg_end
= offset(msg_lod
, bld
, 1);
4450 case SHADER_OPCODE_TXD
:
4453 * dPdx = dudx, dvdx, drdx
4454 * dPdy = dudy, dvdy, drdy
4456 * Load up these values:
4457 * - dudx dudy dvdx dvdy drdx drdy
4458 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
4461 for (unsigned i
= 0; i
< grad_components
; i
++) {
4462 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
4463 msg_end
= offset(msg_end
, bld
, 1);
4465 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
4466 msg_end
= offset(msg_end
, bld
, 1);
4469 case SHADER_OPCODE_TXS
:
4470 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4471 bld
.MOV(msg_lod
, lod
);
4472 msg_end
= offset(msg_lod
, bld
, 1);
4474 case SHADER_OPCODE_TXF
:
4475 msg_lod
= offset(msg_coords
, bld
, 3);
4476 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4477 msg_end
= offset(msg_lod
, bld
, 1);
4479 case SHADER_OPCODE_TXF_CMS
:
4480 msg_lod
= offset(msg_coords
, bld
, 3);
4482 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4484 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4485 msg_end
= offset(msg_lod
, bld
, 2);
4492 inst
->src
[0] = reg_undef
;
4493 inst
->src
[1] = surface
;
4494 inst
->src
[2] = sampler
;
4495 inst
->resize_sources(3);
4496 inst
->base_mrf
= message
.nr
;
4497 inst
->mlen
= msg_end
.nr
- message
.nr
;
4498 inst
->header_size
= header_size
;
4500 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4501 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4505 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
4507 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4510 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4514 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4515 const fs_reg
&coordinate
,
4516 const fs_reg
&shadow_c
,
4517 fs_reg lod
, const fs_reg
&lod2
,
4518 const fs_reg
&min_lod
,
4519 const fs_reg
&sample_index
,
4521 const fs_reg
&surface
,
4522 const fs_reg
&sampler
,
4523 const fs_reg
&tg4_offset
,
4524 unsigned coord_components
,
4525 unsigned grad_components
)
4527 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4528 unsigned reg_width
= bld
.dispatch_width() / 8;
4529 unsigned header_size
= 0, length
= 0;
4530 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4531 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4532 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4534 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4535 inst
->offset
!= 0 || inst
->eot
||
4536 op
== SHADER_OPCODE_SAMPLEINFO
||
4537 is_high_sampler(devinfo
, sampler
)) {
4538 /* For general texture offsets (no txf workaround), we need a header to
4541 * TG4 needs to place its channel select in the header, for interaction
4542 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4543 * larger sampler numbers we need to offset the Sampler State Pointer in
4546 fs_reg header
= retype(sources
[0], BRW_REGISTER_TYPE_UD
);
4550 /* If we're requesting fewer than four channels worth of response,
4551 * and we have an explicit header, we need to set up the sampler
4552 * writemask. It's reversed from normal: 1 means "don't write".
4554 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4555 assert(regs_written(inst
) % reg_width
== 0);
4556 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4557 inst
->offset
|= mask
<< 12;
4560 /* Build the actual header */
4561 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4562 const fs_builder ubld1
= ubld
.group(1, 0);
4563 ubld
.MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
4565 ubld1
.MOV(component(header
, 2), brw_imm_ud(inst
->offset
));
4566 } else if (bld
.shader
->stage
!= MESA_SHADER_VERTEX
&&
4567 bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
) {
4568 /* The vertex and fragment stages have g0.2 set to 0, so
4569 * header0.2 is 0 when g0 is copied. Other stages may not, so we
4570 * must set it to 0 to avoid setting undesirable bits in the
4573 ubld1
.MOV(component(header
, 2), brw_imm_ud(0));
4576 if (is_high_sampler(devinfo
, sampler
)) {
4577 if (sampler
.file
== BRW_IMMEDIATE_VALUE
) {
4578 assert(sampler
.ud
>= 16);
4579 const int sampler_state_size
= 16; /* 16 bytes */
4581 ubld1
.ADD(component(header
, 3),
4582 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
4583 brw_imm_ud(16 * (sampler
.ud
/ 16) * sampler_state_size
));
4585 fs_reg tmp
= ubld1
.vgrf(BRW_REGISTER_TYPE_UD
);
4586 ubld1
.AND(tmp
, sampler
, brw_imm_ud(0x0f0));
4587 ubld1
.SHL(tmp
, tmp
, brw_imm_ud(4));
4588 ubld1
.ADD(component(header
, 3),
4589 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
4595 if (shadow_c
.file
!= BAD_FILE
) {
4596 bld
.MOV(sources
[length
], shadow_c
);
4600 bool coordinate_done
= false;
4602 /* Set up the LOD info */
4605 case SHADER_OPCODE_TXL
:
4606 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4607 op
= SHADER_OPCODE_TXL_LZ
;
4610 bld
.MOV(sources
[length
], lod
);
4613 case SHADER_OPCODE_TXD
:
4614 /* TXD should have been lowered in SIMD16 mode. */
4615 assert(bld
.dispatch_width() == 8);
4617 /* Load dPdx and the coordinate together:
4618 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4620 for (unsigned i
= 0; i
< coord_components
; i
++) {
4621 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4623 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4624 * only derivatives for (u, v, r).
4626 if (i
< grad_components
) {
4627 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4628 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4632 coordinate_done
= true;
4634 case SHADER_OPCODE_TXS
:
4635 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4638 case SHADER_OPCODE_TXF
:
4639 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4640 * On Gen9 they are u, v, lod, r
4642 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4644 if (devinfo
->gen
>= 9) {
4645 if (coord_components
>= 2) {
4646 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4647 offset(coordinate
, bld
, 1));
4649 sources
[length
] = brw_imm_d(0);
4654 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4655 op
= SHADER_OPCODE_TXF_LZ
;
4657 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4661 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4662 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4663 offset(coordinate
, bld
, i
));
4665 coordinate_done
= true;
4668 case SHADER_OPCODE_TXF_CMS
:
4669 case SHADER_OPCODE_TXF_CMS_W
:
4670 case SHADER_OPCODE_TXF_UMS
:
4671 case SHADER_OPCODE_TXF_MCS
:
4672 if (op
== SHADER_OPCODE_TXF_UMS
||
4673 op
== SHADER_OPCODE_TXF_CMS
||
4674 op
== SHADER_OPCODE_TXF_CMS_W
) {
4675 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4679 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4680 /* Data from the multisample control surface. */
4681 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4684 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4687 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4688 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4691 offset(mcs
, bld
, 1));
4696 /* There is no offsetting for this message; just copy in the integer
4697 * texture coordinates.
4699 for (unsigned i
= 0; i
< coord_components
; i
++)
4700 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4701 offset(coordinate
, bld
, i
));
4703 coordinate_done
= true;
4705 case SHADER_OPCODE_TG4_OFFSET
:
4706 /* More crazy intermixing */
4707 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4708 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4710 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4711 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4712 offset(tg4_offset
, bld
, i
));
4714 if (coord_components
== 3) /* r if present */
4715 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4717 coordinate_done
= true;
4723 /* Set up the coordinate (except for cases where it was done above) */
4724 if (!coordinate_done
) {
4725 for (unsigned i
= 0; i
< coord_components
; i
++)
4726 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4729 if (min_lod
.file
!= BAD_FILE
) {
4730 /* Account for all of the missing coordinate sources */
4731 length
+= 4 - coord_components
;
4732 if (op
== SHADER_OPCODE_TXD
)
4733 length
+= (3 - grad_components
) * 2;
4735 bld
.MOV(sources
[length
++], min_lod
);
4740 mlen
= length
* reg_width
- header_size
;
4742 mlen
= length
* reg_width
;
4744 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4745 BRW_REGISTER_TYPE_F
);
4746 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4748 /* Generate the SEND. */
4750 inst
->src
[0] = src_payload
;
4751 inst
->src
[1] = surface
;
4752 inst
->src
[2] = sampler
;
4753 inst
->resize_sources(3);
4755 inst
->header_size
= header_size
;
4757 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4758 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4762 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4764 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4765 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4766 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4767 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4768 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4769 const fs_reg
&min_lod
= inst
->src
[TEX_LOGICAL_SRC_MIN_LOD
];
4770 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4771 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4772 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4773 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4774 const fs_reg
&tg4_offset
= inst
->src
[TEX_LOGICAL_SRC_TG4_OFFSET
];
4775 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4776 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4777 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4778 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4780 if (devinfo
->gen
>= 7) {
4781 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4782 shadow_c
, lod
, lod2
, min_lod
,
4784 mcs
, surface
, sampler
, tg4_offset
,
4785 coord_components
, grad_components
);
4786 } else if (devinfo
->gen
>= 5) {
4787 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4788 shadow_c
, lod
, lod2
, sample_index
,
4790 coord_components
, grad_components
);
4792 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4793 shadow_c
, lod
, lod2
,
4795 coord_components
, grad_components
);
4800 * Initialize the header present in some typed and untyped surface
4804 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4806 fs_builder ubld
= bld
.exec_all().group(8, 0);
4807 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4808 ubld
.MOV(dst
, brw_imm_d(0));
4809 ubld
.group(1, 0).MOV(component(dst
, 7), sample_mask
);
4814 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4815 const fs_reg
&sample_mask
)
4817 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4819 /* Get the logical send arguments. */
4820 const fs_reg
&addr
= inst
->src
[0];
4821 const fs_reg
&src
= inst
->src
[1];
4822 const fs_reg
&surface
= inst
->src
[2];
4823 const UNUSED fs_reg
&dims
= inst
->src
[3];
4824 const fs_reg
&arg
= inst
->src
[4];
4826 /* Calculate the total number of components of the payload. */
4827 const unsigned addr_sz
= inst
->components_read(0);
4828 const unsigned src_sz
= inst
->components_read(1);
4829 /* From the BDW PRM Volume 7, page 147:
4831 * "For the Data Cache Data Port*, the header must be present for the
4832 * following message types: [...] Typed read/write/atomics"
4834 * Earlier generations have a similar wording. Because of this restriction
4835 * we don't attempt to implement sample masks via predication for such
4836 * messages prior to Gen9, since we have to provide a header anyway. On
4837 * Gen11+ the header has been removed so we can only use predication.
4839 const unsigned header_sz
= devinfo
->gen
< 9 &&
4840 (op
== SHADER_OPCODE_TYPED_SURFACE_READ
||
4841 op
== SHADER_OPCODE_TYPED_SURFACE_WRITE
||
4842 op
== SHADER_OPCODE_TYPED_ATOMIC
) ? 1 : 0;
4843 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4845 /* Allocate space for the payload. */
4846 fs_reg
*const components
= new fs_reg
[sz
];
4847 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4850 /* Construct the payload. */
4852 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4854 for (unsigned i
= 0; i
< addr_sz
; i
++)
4855 components
[n
++] = offset(addr
, bld
, i
);
4857 for (unsigned i
= 0; i
< src_sz
; i
++)
4858 components
[n
++] = offset(src
, bld
, i
);
4860 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4862 /* Predicate the instruction on the sample mask if no header is
4865 if (!header_sz
&& sample_mask
.file
!= BAD_FILE
&&
4866 sample_mask
.file
!= IMM
) {
4867 const fs_builder ubld
= bld
.group(1, 0).exec_all();
4868 if (inst
->predicate
) {
4869 assert(inst
->predicate
== BRW_PREDICATE_NORMAL
);
4870 assert(!inst
->predicate_inverse
);
4871 assert(inst
->flag_subreg
< 2);
4872 /* Combine the sample mask with the existing predicate by using a
4873 * vertical predication mode.
4875 inst
->predicate
= BRW_PREDICATE_ALIGN1_ALLV
;
4876 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
+ 2),
4880 inst
->flag_subreg
= 2;
4881 inst
->predicate
= BRW_PREDICATE_NORMAL
;
4882 inst
->predicate_inverse
= false;
4883 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
), sample_mask
.type
),
4888 /* Update the original instruction. */
4890 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4891 inst
->header_size
= header_sz
;
4893 inst
->src
[0] = payload
;
4894 inst
->src
[1] = surface
;
4896 inst
->resize_sources(3);
4898 delete[] components
;
4902 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4904 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4906 if (devinfo
->gen
>= 7) {
4907 /* We are switching the instruction from an ALU-like instruction to a
4908 * send-from-grf instruction. Since sends can't handle strides or
4909 * source modifiers, we have to make a copy of the offset source.
4911 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4912 bld
.MOV(tmp
, inst
->src
[1]);
4915 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4916 inst
->mlen
= inst
->exec_size
/ 8;
4918 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4919 BRW_REGISTER_TYPE_UD
);
4921 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4923 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4924 inst
->resize_sources(1);
4925 inst
->base_mrf
= payload
.nr
;
4926 inst
->header_size
= 1;
4927 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4932 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4934 assert(bld
.shader
->devinfo
->gen
< 6);
4937 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4939 if (inst
->sources
> 1) {
4940 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4941 * "Message Payload":
4943 * "Operand0[7]. For the INT DIV functions, this operand is the
4946 * "Operand1[7]. For the INT DIV functions, this operand is the
4949 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4950 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4951 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4953 inst
->resize_sources(1);
4954 inst
->src
[0] = src0
;
4956 assert(inst
->exec_size
== 8);
4957 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4962 fs_visitor::lower_logical_sends()
4964 bool progress
= false;
4966 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4967 const fs_builder
ibld(this, block
, inst
);
4969 switch (inst
->opcode
) {
4970 case FS_OPCODE_FB_WRITE_LOGICAL
:
4971 assert(stage
== MESA_SHADER_FRAGMENT
);
4972 lower_fb_write_logical_send(ibld
, inst
,
4973 brw_wm_prog_data(prog_data
),
4974 (const brw_wm_prog_key
*)key
,
4978 case FS_OPCODE_FB_READ_LOGICAL
:
4979 lower_fb_read_logical_send(ibld
, inst
);
4982 case SHADER_OPCODE_TEX_LOGICAL
:
4983 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4986 case SHADER_OPCODE_TXD_LOGICAL
:
4987 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4990 case SHADER_OPCODE_TXF_LOGICAL
:
4991 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4994 case SHADER_OPCODE_TXL_LOGICAL
:
4995 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4998 case SHADER_OPCODE_TXS_LOGICAL
:
4999 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
5002 case FS_OPCODE_TXB_LOGICAL
:
5003 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
5006 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
5007 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
5010 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
5011 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
5014 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
5015 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
5018 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
5019 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
5022 case SHADER_OPCODE_LOD_LOGICAL
:
5023 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
5026 case SHADER_OPCODE_TG4_LOGICAL
:
5027 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
5030 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
5031 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
5034 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
5035 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
5038 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5039 lower_surface_logical_send(ibld
, inst
,
5040 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
5044 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5045 lower_surface_logical_send(ibld
, inst
,
5046 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
5047 ibld
.sample_mask_reg());
5050 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5051 lower_surface_logical_send(ibld
, inst
,
5052 SHADER_OPCODE_BYTE_SCATTERED_READ
,
5056 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5057 lower_surface_logical_send(ibld
, inst
,
5058 SHADER_OPCODE_BYTE_SCATTERED_WRITE
,
5059 ibld
.sample_mask_reg());
5062 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5063 lower_surface_logical_send(ibld
, inst
,
5064 SHADER_OPCODE_UNTYPED_ATOMIC
,
5065 ibld
.sample_mask_reg());
5068 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5069 lower_surface_logical_send(ibld
, inst
,
5070 SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT
,
5071 ibld
.sample_mask_reg());
5074 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5075 lower_surface_logical_send(ibld
, inst
,
5076 SHADER_OPCODE_TYPED_SURFACE_READ
,
5080 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5081 lower_surface_logical_send(ibld
, inst
,
5082 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
5083 ibld
.sample_mask_reg());
5086 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5087 lower_surface_logical_send(ibld
, inst
,
5088 SHADER_OPCODE_TYPED_ATOMIC
,
5089 ibld
.sample_mask_reg());
5092 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
5093 lower_varying_pull_constant_logical_send(ibld
, inst
);
5096 case SHADER_OPCODE_RCP
:
5097 case SHADER_OPCODE_RSQ
:
5098 case SHADER_OPCODE_SQRT
:
5099 case SHADER_OPCODE_EXP2
:
5100 case SHADER_OPCODE_LOG2
:
5101 case SHADER_OPCODE_SIN
:
5102 case SHADER_OPCODE_COS
:
5103 case SHADER_OPCODE_POW
:
5104 case SHADER_OPCODE_INT_QUOTIENT
:
5105 case SHADER_OPCODE_INT_REMAINDER
:
5106 /* The math opcodes are overloaded for the send-like and
5107 * expression-like instructions which seems kind of icky. Gen6+ has
5108 * a native (but rather quirky) MATH instruction so we don't need to
5109 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
5110 * logical instructions (which we can easily recognize because they
5111 * have mlen = 0) into send-like virtual instructions.
5113 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
5114 lower_math_logical_send(ibld
, inst
);
5129 invalidate_live_intervals();
5135 * Get the closest allowed SIMD width for instruction \p inst accounting for
5136 * some common regioning and execution control restrictions that apply to FPU
5137 * instructions. These restrictions don't necessarily have any relevance to
5138 * instructions not executed by the FPU pipeline like extended math, control
5139 * flow or send message instructions.
5141 * For virtual opcodes it's really up to the instruction -- In some cases
5142 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
5143 * instructions) it may simplify virtual instruction lowering if we can
5144 * enforce FPU-like regioning restrictions already on the virtual instruction,
5145 * in other cases (e.g. virtual send-like instructions) this may be
5146 * excessively restrictive.
5149 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
5150 const fs_inst
*inst
)
5152 /* Maximum execution size representable in the instruction controls. */
5153 unsigned max_width
= MIN2(32, inst
->exec_size
);
5155 /* According to the PRMs:
5156 * "A. In Direct Addressing mode, a source cannot span more than 2
5157 * adjacent GRF registers.
5158 * B. A destination cannot span more than 2 adjacent GRF registers."
5160 * Look for the source or destination with the largest register region
5161 * which is the one that is going to limit the overall execution size of
5162 * the instruction due to this rule.
5164 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
5166 for (unsigned i
= 0; i
< inst
->sources
; i
++)
5167 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
5169 /* Calculate the maximum execution size of the instruction based on the
5170 * factor by which it goes over the hardware limit of 2 GRFs.
5173 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
5175 /* According to the IVB PRMs:
5176 * "When destination spans two registers, the source MUST span two
5177 * registers. The exception to the above rule:
5179 * - When source is scalar, the source registers are not incremented.
5180 * - When source is packed integer Word and destination is packed
5181 * integer DWord, the source register is not incremented but the
5182 * source sub register is incremented."
5184 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
5185 * restrictions. The code below intentionally doesn't check whether the
5186 * destination type is integer because empirically the hardware doesn't
5187 * seem to care what the actual type is as long as it's dword-aligned.
5189 if (devinfo
->gen
< 8) {
5190 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5191 /* IVB implements DF scalars as <0;2,1> regions. */
5192 const bool is_scalar_exception
= is_uniform(inst
->src
[i
]) &&
5193 (devinfo
->is_haswell
|| type_sz(inst
->src
[i
].type
) != 8);
5194 const bool is_packed_word_exception
=
5195 type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
5196 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1;
5198 /* We check size_read(i) against size_written instead of REG_SIZE
5199 * because we want to properly handle SIMD32. In SIMD32, you can end
5200 * up with writes to 4 registers and a source that reads 2 registers
5201 * and we may still need to lower all the way to SIMD8 in that case.
5203 if (inst
->size_written
> REG_SIZE
&&
5204 inst
->size_read(i
) != 0 &&
5205 inst
->size_read(i
) < inst
->size_written
&&
5206 !is_scalar_exception
&& !is_packed_word_exception
) {
5207 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
5208 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
5213 if (devinfo
->gen
< 6) {
5214 /* From the G45 PRM, Volume 4 Page 361:
5216 * "Operand Alignment Rule: With the exceptions listed below, a
5217 * source/destination operand in general should be aligned to even
5218 * 256-bit physical register with a region size equal to two 256-bit
5219 * physical registers."
5221 * Normally we enforce this by allocating virtual registers to the
5222 * even-aligned class. But we need to handle payload registers.
5224 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5225 if (inst
->src
[i
].file
== FIXED_GRF
&& (inst
->src
[i
].nr
& 1) &&
5226 inst
->size_read(i
) > REG_SIZE
) {
5227 max_width
= MIN2(max_width
, 8);
5232 /* From the IVB PRMs:
5233 * "When an instruction is SIMD32, the low 16 bits of the execution mask
5234 * are applied for both halves of the SIMD32 instruction. If different
5235 * execution mask channels are required, split the instruction into two
5236 * SIMD16 instructions."
5238 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
5239 * 32-wide control flow support in hardware and will behave similarly.
5241 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
5242 max_width
= MIN2(max_width
, 16);
5244 /* From the IVB PRMs (applies to HSW too):
5245 * "Instructions with condition modifiers must not use SIMD32."
5247 * From the BDW PRMs (applies to later hardware too):
5248 * "Ternary instruction with condition modifiers must not use SIMD32."
5250 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
5251 max_width
= MIN2(max_width
, 16);
5253 /* From the IVB PRMs (applies to other devices that don't have the
5254 * gen_device_info::supports_simd16_3src flag set):
5255 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
5256 * SIMD8 is not allowed for DF operations."
5258 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
5259 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
5261 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
5262 * the 8-bit quarter of the execution mask signals specified in the
5263 * instruction control fields) for the second compressed half of any
5264 * single-precision instruction (for double-precision instructions
5265 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
5266 * the EU will apply the wrong execution controls for the second
5267 * sequential GRF write if the number of channels per GRF is not exactly
5268 * eight in single-precision mode (or four in double-float mode).
5270 * In this situation we calculate the maximum size of the split
5271 * instructions so they only ever write to a single register.
5273 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
5274 !inst
->force_writemask_all
) {
5275 const unsigned channels_per_grf
= inst
->exec_size
/
5276 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
5277 const unsigned exec_type_size
= get_exec_type_size(inst
);
5278 assert(exec_type_size
);
5280 /* The hardware shifts exactly 8 channels per compressed half of the
5281 * instruction in single-precision mode and exactly 4 in double-precision.
5283 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
5284 max_width
= MIN2(max_width
, channels_per_grf
);
5286 /* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
5287 * because HW applies the same channel enable signals to both halves of
5288 * the compressed instruction which will be just wrong under
5289 * non-uniform control flow.
5291 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
5292 (exec_type_size
== 8 || type_sz(inst
->dst
.type
) == 8))
5293 max_width
= MIN2(max_width
, 4);
5296 /* Only power-of-two execution sizes are representable in the instruction
5299 return 1 << _mesa_logbase2(max_width
);
5303 * Get the maximum allowed SIMD width for instruction \p inst accounting for
5304 * various payload size restrictions that apply to sampler message
5307 * This is only intended to provide a maximum theoretical bound for the
5308 * execution size of the message based on the number of argument components
5309 * alone, which in most cases will determine whether the SIMD8 or SIMD16
5310 * variant of the message can be used, though some messages may have
5311 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
5312 * the message length to determine the exact SIMD width and argument count,
5313 * which makes a number of sampler message combinations impossible to
5317 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
5318 const fs_inst
*inst
)
5320 /* If we have a min_lod parameter on anything other than a simple sample
5321 * message, it will push it over 5 arguments and we have to fall back to
5324 if (inst
->opcode
!= SHADER_OPCODE_TEX
&&
5325 inst
->components_read(TEX_LOGICAL_SRC_MIN_LOD
))
5328 /* Calculate the number of coordinate components that have to be present
5329 * assuming that additional arguments follow the texel coordinates in the
5330 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
5331 * need to pad to four or three components depending on the message,
5332 * pre-ILK we need to pad to at most three components.
5334 const unsigned req_coord_components
=
5335 (devinfo
->gen
>= 7 ||
5336 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
5337 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
5338 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
5341 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
5342 * variant of the TXL or TXF message.
5344 const bool implicit_lod
= devinfo
->gen
>= 9 &&
5345 (inst
->opcode
== SHADER_OPCODE_TXL
||
5346 inst
->opcode
== SHADER_OPCODE_TXF
) &&
5347 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
5349 /* Calculate the total number of argument components that need to be passed
5350 * to the sampler unit.
5352 const unsigned num_payload_components
=
5353 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
5354 req_coord_components
) +
5355 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
5356 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
5357 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
5358 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
5359 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
5360 inst
->components_read(TEX_LOGICAL_SRC_TG4_OFFSET
) : 0) +
5361 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
5363 /* SIMD16 messages with more than five arguments exceed the maximum message
5364 * size supported by the sampler, regardless of whether a header is
5367 return MIN2(inst
->exec_size
,
5368 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
5372 * Get the closest native SIMD width supported by the hardware for instruction
5373 * \p inst. The instruction will be left untouched by
5374 * fs_visitor::lower_simd_width() if the returned value is equal to the
5375 * original execution size.
5378 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
5379 const fs_inst
*inst
)
5381 switch (inst
->opcode
) {
5382 case BRW_OPCODE_MOV
:
5383 case BRW_OPCODE_SEL
:
5384 case BRW_OPCODE_NOT
:
5385 case BRW_OPCODE_AND
:
5387 case BRW_OPCODE_XOR
:
5388 case BRW_OPCODE_SHR
:
5389 case BRW_OPCODE_SHL
:
5390 case BRW_OPCODE_ASR
:
5391 case BRW_OPCODE_CMPN
:
5392 case BRW_OPCODE_CSEL
:
5393 case BRW_OPCODE_F32TO16
:
5394 case BRW_OPCODE_F16TO32
:
5395 case BRW_OPCODE_BFREV
:
5396 case BRW_OPCODE_BFE
:
5397 case BRW_OPCODE_ADD
:
5398 case BRW_OPCODE_MUL
:
5399 case BRW_OPCODE_AVG
:
5400 case BRW_OPCODE_FRC
:
5401 case BRW_OPCODE_RNDU
:
5402 case BRW_OPCODE_RNDD
:
5403 case BRW_OPCODE_RNDE
:
5404 case BRW_OPCODE_RNDZ
:
5405 case BRW_OPCODE_LZD
:
5406 case BRW_OPCODE_FBH
:
5407 case BRW_OPCODE_FBL
:
5408 case BRW_OPCODE_CBIT
:
5409 case BRW_OPCODE_SAD2
:
5410 case BRW_OPCODE_MAD
:
5411 case BRW_OPCODE_LRP
:
5412 case FS_OPCODE_PACK
:
5413 case SHADER_OPCODE_SEL_EXEC
:
5414 case SHADER_OPCODE_CLUSTER_BROADCAST
:
5415 return get_fpu_lowered_simd_width(devinfo
, inst
);
5417 case BRW_OPCODE_CMP
: {
5418 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
5419 * when the destination is a GRF the dependency-clear bit on the flag
5420 * register is cleared early.
5422 * Suggested workarounds are to disable coissuing CMP instructions
5423 * or to split CMP(16) instructions into two CMP(8) instructions.
5425 * We choose to split into CMP(8) instructions since disabling
5426 * coissuing would affect CMP instructions not otherwise affected by
5429 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
5430 !inst
->dst
.is_null() ? 8 : ~0);
5431 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
5433 case BRW_OPCODE_BFI1
:
5434 case BRW_OPCODE_BFI2
:
5435 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
5437 * "Force BFI instructions to be executed always in SIMD8."
5439 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
5440 get_fpu_lowered_simd_width(devinfo
, inst
));
5443 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
5444 return inst
->exec_size
;
5446 case SHADER_OPCODE_RCP
:
5447 case SHADER_OPCODE_RSQ
:
5448 case SHADER_OPCODE_SQRT
:
5449 case SHADER_OPCODE_EXP2
:
5450 case SHADER_OPCODE_LOG2
:
5451 case SHADER_OPCODE_SIN
:
5452 case SHADER_OPCODE_COS
:
5453 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
5456 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
5457 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
5458 MIN2(8, inst
->exec_size
));
5460 case SHADER_OPCODE_POW
:
5461 /* SIMD16 is only allowed on Gen7+. */
5462 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
5463 MIN2(8, inst
->exec_size
));
5465 case SHADER_OPCODE_INT_QUOTIENT
:
5466 case SHADER_OPCODE_INT_REMAINDER
:
5467 /* Integer division is limited to SIMD8 on all generations. */
5468 return MIN2(8, inst
->exec_size
);
5470 case FS_OPCODE_LINTERP
:
5471 case SHADER_OPCODE_GET_BUFFER_SIZE
:
5472 case FS_OPCODE_DDX_COARSE
:
5473 case FS_OPCODE_DDX_FINE
:
5474 case FS_OPCODE_DDY_COARSE
:
5475 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
5476 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
5477 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
5478 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
5479 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
5480 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
5481 return MIN2(16, inst
->exec_size
);
5483 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
5484 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
5485 * message used to implement varying pull constant loads, so expand it
5486 * to SIMD16. An alternative with longer message payload length but
5487 * shorter return payload would be to use the SIMD8 sampler message that
5488 * takes (header, u, v, r) as parameters instead of (header, u).
5490 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
5492 case FS_OPCODE_DDY_FINE
:
5493 /* The implementation of this virtual opcode may require emitting
5494 * compressed Align16 instructions, which are severely limited on some
5497 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
5498 * Region Restrictions):
5500 * "In Align16 access mode, SIMD16 is not allowed for DW operations
5501 * and SIMD8 is not allowed for DF operations."
5503 * In this context, "DW operations" means "operations acting on 32-bit
5504 * values", so it includes operations on floats.
5506 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
5507 * (Instruction Compression -> Rules and Restrictions):
5509 * "A compressed instruction must be in Align1 access mode. Align16
5510 * mode instructions cannot be compressed."
5512 * Similar text exists in the g45 PRM.
5514 * Empirically, compressed align16 instructions using odd register
5515 * numbers don't appear to work on Sandybridge either.
5517 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
5518 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
5519 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
5521 case SHADER_OPCODE_MULH
:
5522 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
5523 * is 8-wide on Gen7+.
5525 return (devinfo
->gen
>= 7 ? 8 :
5526 get_fpu_lowered_simd_width(devinfo
, inst
));
5528 case FS_OPCODE_FB_WRITE_LOGICAL
:
5529 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
5532 assert(devinfo
->gen
!= 6 ||
5533 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
5534 inst
->exec_size
== 8);
5535 /* Dual-source FB writes are unsupported in SIMD16 mode. */
5536 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
5537 8 : MIN2(16, inst
->exec_size
));
5539 case FS_OPCODE_FB_READ_LOGICAL
:
5540 return MIN2(16, inst
->exec_size
);
5542 case SHADER_OPCODE_TEX_LOGICAL
:
5543 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
5544 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
5545 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
5546 case SHADER_OPCODE_LOD_LOGICAL
:
5547 case SHADER_OPCODE_TG4_LOGICAL
:
5548 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
5549 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
5550 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
5551 return get_sampler_lowered_simd_width(devinfo
, inst
);
5553 case SHADER_OPCODE_TXD_LOGICAL
:
5554 /* TXD is unsupported in SIMD16 mode. */
5557 case SHADER_OPCODE_TXL_LOGICAL
:
5558 case FS_OPCODE_TXB_LOGICAL
:
5559 /* Only one execution size is representable pre-ILK depending on whether
5560 * the shadow reference argument is present.
5562 if (devinfo
->gen
== 4)
5563 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
5565 return get_sampler_lowered_simd_width(devinfo
, inst
);
5567 case SHADER_OPCODE_TXF_LOGICAL
:
5568 case SHADER_OPCODE_TXS_LOGICAL
:
5569 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
5570 * messages. Use SIMD16 instead.
5572 if (devinfo
->gen
== 4)
5575 return get_sampler_lowered_simd_width(devinfo
, inst
);
5577 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5578 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5579 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5582 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5583 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5584 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5585 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5586 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5587 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5588 return MIN2(16, inst
->exec_size
);
5590 case SHADER_OPCODE_URB_READ_SIMD8
:
5591 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
5592 case SHADER_OPCODE_URB_WRITE_SIMD8
:
5593 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
5594 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
5595 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
5596 return MIN2(8, inst
->exec_size
);
5598 case SHADER_OPCODE_QUAD_SWIZZLE
: {
5599 const unsigned swiz
= inst
->src
[1].ud
;
5600 return (is_uniform(inst
->src
[0]) ?
5601 get_fpu_lowered_simd_width(devinfo
, inst
) :
5602 devinfo
->gen
< 11 && type_sz(inst
->src
[0].type
) == 4 ? 8 :
5603 swiz
== BRW_SWIZZLE_XYXY
|| swiz
== BRW_SWIZZLE_ZWZW
? 4 :
5604 get_fpu_lowered_simd_width(devinfo
, inst
));
5606 case SHADER_OPCODE_MOV_INDIRECT
: {
5607 /* From IVB and HSW PRMs:
5609 * "2.When the destination requires two registers and the sources are
5610 * indirect, the sources must use 1x1 regioning mode.
5612 * In case of DF instructions in HSW/IVB, the exec_size is limited by
5613 * the EU decompression logic not handling VxH indirect addressing
5616 const unsigned max_size
= (devinfo
->gen
>= 8 ? 2 : 1) * REG_SIZE
;
5617 /* Prior to Broadwell, we only have 8 address subregisters. */
5618 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
5619 max_size
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
5623 case SHADER_OPCODE_LOAD_PAYLOAD
: {
5624 const unsigned reg_count
=
5625 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
5627 if (reg_count
> 2) {
5628 /* Only LOAD_PAYLOAD instructions with per-channel destination region
5629 * can be easily lowered (which excludes headers and heterogeneous
5632 assert(!inst
->header_size
);
5633 for (unsigned i
= 0; i
< inst
->sources
; i
++)
5634 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
5635 inst
->src
[i
].file
== BAD_FILE
);
5637 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
5639 return inst
->exec_size
;
5643 return inst
->exec_size
;
5648 * Return true if splitting out the group of channels of instruction \p inst
5649 * given by lbld.group() requires allocating a temporary for the i-th source
5650 * of the lowered instruction.
5653 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
5655 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
5656 (inst
->components_read(i
) == 1 &&
5657 lbld
.dispatch_width() <= inst
->exec_size
)) ||
5658 (inst
->flags_written() &
5659 flag_mask(inst
->src
[i
], type_sz(inst
->src
[i
].type
)));
5663 * Extract the data that would be consumed by the channel group given by
5664 * lbld.group() from the i-th source region of instruction \p inst and return
5665 * it as result in packed form.
5668 emit_unzip(const fs_builder
&lbld
, fs_inst
*inst
, unsigned i
)
5670 assert(lbld
.group() >= inst
->group
);
5672 /* Specified channel group from the source region. */
5673 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group() - inst
->group
);
5675 if (needs_src_copy(lbld
, inst
, i
)) {
5676 /* Builder of the right width to perform the copy avoiding uninitialized
5677 * data if the lowered execution size is greater than the original
5678 * execution size of the instruction.
5680 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5681 inst
->exec_size
), 0);
5682 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
5684 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
5685 cbld
.MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
5689 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
5690 /* The source is invariant for all dispatch_width-wide groups of the
5693 return inst
->src
[i
];
5696 /* We can just point the lowered instruction at the right channel group
5697 * from the original region.
5704 * Return true if splitting out the group of channels of instruction \p inst
5705 * given by lbld.group() requires allocating a temporary for the destination
5706 * of the lowered instruction and copying the data back to the original
5707 * destination region.
5710 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
5712 /* If the instruction writes more than one component we'll have to shuffle
5713 * the results of multiple lowered instructions in order to make sure that
5714 * they end up arranged correctly in the original destination region.
5716 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
5719 /* If the lowered execution size is larger than the original the result of
5720 * the instruction won't fit in the original destination, so we'll have to
5721 * allocate a temporary in any case.
5723 if (lbld
.dispatch_width() > inst
->exec_size
)
5726 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5727 /* If we already made a copy of the source for other reasons there won't
5728 * be any overlap with the destination.
5730 if (needs_src_copy(lbld
, inst
, i
))
5733 /* In order to keep the logic simple we emit a copy whenever the
5734 * destination region doesn't exactly match an overlapping source, which
5735 * may point at the source and destination not being aligned group by
5736 * group which could cause one of the lowered instructions to overwrite
5737 * the data read from the same source by other lowered instructions.
5739 if (regions_overlap(inst
->dst
, inst
->size_written
,
5740 inst
->src
[i
], inst
->size_read(i
)) &&
5741 !inst
->dst
.equals(inst
->src
[i
]))
5749 * Insert data from a packed temporary into the channel group given by
5750 * lbld.group() of the destination region of instruction \p inst and return
5751 * the temporary as result. Any copy instructions that are required for
5752 * unzipping the previous value (in the case of partial writes) will be
5753 * inserted using \p lbld_before and any copy instructions required for
5754 * zipping up the destination of \p inst will be inserted using \p lbld_after.
5757 emit_zip(const fs_builder
&lbld_before
, const fs_builder
&lbld_after
,
5760 assert(lbld_before
.dispatch_width() == lbld_after
.dispatch_width());
5761 assert(lbld_before
.group() == lbld_after
.group());
5762 assert(lbld_after
.group() >= inst
->group
);
5764 /* Specified channel group from the destination region. */
5765 const fs_reg dst
= horiz_offset(inst
->dst
, lbld_after
.group() - inst
->group
);
5766 const unsigned dst_size
= inst
->size_written
/
5767 inst
->dst
.component_size(inst
->exec_size
);
5769 if (needs_dst_copy(lbld_after
, inst
)) {
5770 const fs_reg tmp
= lbld_after
.vgrf(inst
->dst
.type
, dst_size
);
5772 if (inst
->predicate
) {
5773 /* Handle predication by copying the original contents of
5774 * the destination into the temporary before emitting the
5775 * lowered instruction.
5777 const fs_builder gbld_before
=
5778 lbld_before
.group(MIN2(lbld_before
.dispatch_width(),
5779 inst
->exec_size
), 0);
5780 for (unsigned k
= 0; k
< dst_size
; ++k
) {
5781 gbld_before
.MOV(offset(tmp
, lbld_before
, k
),
5782 offset(dst
, inst
->exec_size
, k
));
5786 const fs_builder gbld_after
=
5787 lbld_after
.group(MIN2(lbld_after
.dispatch_width(),
5788 inst
->exec_size
), 0);
5789 for (unsigned k
= 0; k
< dst_size
; ++k
) {
5790 /* Use a builder of the right width to perform the copy avoiding
5791 * uninitialized data if the lowered execution size is greater than
5792 * the original execution size of the instruction.
5794 gbld_after
.MOV(offset(dst
, inst
->exec_size
, k
),
5795 offset(tmp
, lbld_after
, k
));
5801 /* No need to allocate a temporary for the lowered instruction, just
5802 * take the right group of channels from the original region.
5809 fs_visitor::lower_simd_width()
5811 bool progress
= false;
5813 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5814 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5816 if (lower_width
!= inst
->exec_size
) {
5817 /* Builder matching the original instruction. We may also need to
5818 * emit an instruction of width larger than the original, set the
5819 * execution size of the builder to the highest of both for now so
5820 * we're sure that both cases can be handled.
5822 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5823 const fs_builder ibld
= bld
.at(block
, inst
)
5824 .exec_all(inst
->force_writemask_all
)
5825 .group(max_width
, inst
->group
/ max_width
);
5827 /* Split the copies in chunks of the execution width of either the
5828 * original or the lowered instruction, whichever is lower.
5830 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5831 const unsigned dst_size
= inst
->size_written
/
5832 inst
->dst
.component_size(inst
->exec_size
);
5834 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5836 /* Inserting the zip, unzip, and duplicated instructions in all of
5837 * the right spots is somewhat tricky. All of the unzip and any
5838 * instructions from the zip which unzip the destination prior to
5839 * writing need to happen before all of the per-group instructions
5840 * and the zip instructions need to happen after. In order to sort
5841 * this all out, we insert the unzip instructions before \p inst,
5842 * insert the per-group instructions after \p inst (i.e. before
5843 * inst->next), and insert the zip instructions before the
5844 * instruction after \p inst. Since we are inserting instructions
5845 * after \p inst, inst->next is a moving target and we need to save
5846 * it off here so that we insert the zip instructions in the right
5849 * Since we're inserting split instructions after after_inst, the
5850 * instructions will end up in the reverse order that we insert them.
5851 * However, certain render target writes require that the low group
5852 * instructions come before the high group. From the Ivy Bridge PRM
5853 * Vol. 4, Pt. 1, Section 3.9.11:
5855 * "If multiple SIMD8 Dual Source messages are delivered by the
5856 * pixel shader thread, each SIMD8_DUALSRC_LO message must be
5857 * issued before the SIMD8_DUALSRC_HI message with the same Slot
5858 * Group Select setting."
5860 * And, from Section 3.9.11.1 of the same PRM:
5862 * "When SIMD32 or SIMD16 PS threads send render target writes
5863 * with multiple SIMD8 and SIMD16 messages, the following must
5866 * All the slots (as described above) must have a corresponding
5867 * render target write irrespective of the slot's validity. A slot
5868 * is considered valid when at least one sample is enabled. For
5869 * example, a SIMD16 PS thread must send two SIMD8 render target
5870 * writes to cover all the slots.
5872 * PS thread must send SIMD render target write messages with
5873 * increasing slot numbers. For example, SIMD16 thread has
5874 * Slot[15:0] and if two SIMD8 render target writes are used, the
5875 * first SIMD8 render target write must send Slot[7:0] and the
5876 * next one must send Slot[15:8]."
5878 * In order to make low group instructions come before high group
5879 * instructions (this is required for some render target writes), we
5880 * split from the highest group to lowest.
5882 exec_node
*const after_inst
= inst
->next
;
5883 for (int i
= n
- 1; i
>= 0; i
--) {
5884 /* Emit a copy of the original instruction with the lowered width.
5885 * If the EOT flag was set throw it away except for the last
5886 * instruction to avoid killing the thread prematurely.
5888 fs_inst split_inst
= *inst
;
5889 split_inst
.exec_size
= lower_width
;
5890 split_inst
.eot
= inst
->eot
&& i
== int(n
- 1);
5892 /* Select the correct channel enables for the i-th group, then
5893 * transform the sources and destination and emit the lowered
5896 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5898 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5899 split_inst
.src
[j
] = emit_unzip(lbld
.at(block
, inst
), inst
, j
);
5901 split_inst
.dst
= emit_zip(lbld
.at(block
, inst
),
5902 lbld
.at(block
, after_inst
), inst
);
5903 split_inst
.size_written
=
5904 split_inst
.dst
.component_size(lower_width
) * dst_size
;
5906 lbld
.at(block
, inst
->next
).emit(split_inst
);
5909 inst
->remove(block
);
5915 invalidate_live_intervals();
5921 fs_visitor::dump_instructions()
5923 dump_instructions(NULL
);
5927 fs_visitor::dump_instructions(const char *name
)
5929 FILE *file
= stderr
;
5930 if (name
&& geteuid() != 0) {
5931 file
= fopen(name
, "w");
5937 calculate_register_pressure();
5938 int ip
= 0, max_pressure
= 0;
5939 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5940 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5941 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5942 dump_instruction(inst
, file
);
5945 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5948 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5949 fprintf(file
, "%4d: ", ip
++);
5950 dump_instruction(inst
, file
);
5954 if (file
!= stderr
) {
5960 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5962 dump_instruction(be_inst
, stderr
);
5966 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5968 fs_inst
*inst
= (fs_inst
*)be_inst
;
5970 if (inst
->predicate
) {
5971 fprintf(file
, "(%cf%d.%d) ",
5972 inst
->predicate_inverse
? '-' : '+',
5973 inst
->flag_subreg
/ 2,
5974 inst
->flag_subreg
% 2);
5977 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5979 fprintf(file
, ".sat");
5980 if (inst
->conditional_mod
) {
5981 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5982 if (!inst
->predicate
&&
5983 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5984 inst
->opcode
!= BRW_OPCODE_CSEL
&&
5985 inst
->opcode
!= BRW_OPCODE_IF
&&
5986 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5987 fprintf(file
, ".f%d.%d", inst
->flag_subreg
/ 2,
5988 inst
->flag_subreg
% 2);
5991 fprintf(file
, "(%d) ", inst
->exec_size
);
5994 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5998 fprintf(file
, "(EOT) ");
6001 switch (inst
->dst
.file
) {
6003 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
6006 fprintf(file
, "g%d", inst
->dst
.nr
);
6009 fprintf(file
, "m%d", inst
->dst
.nr
);
6012 fprintf(file
, "(null)");
6015 fprintf(file
, "***u%d***", inst
->dst
.nr
);
6018 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
6021 switch (inst
->dst
.nr
) {
6023 fprintf(file
, "null");
6025 case BRW_ARF_ADDRESS
:
6026 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
6028 case BRW_ARF_ACCUMULATOR
:
6029 fprintf(file
, "acc%d", inst
->dst
.subnr
);
6032 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
6035 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
6040 unreachable("not reached");
6043 if (inst
->dst
.offset
||
6044 (inst
->dst
.file
== VGRF
&&
6045 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
6046 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
6047 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
6048 inst
->dst
.offset
% reg_size
);
6051 if (inst
->dst
.stride
!= 1)
6052 fprintf(file
, "<%u>", inst
->dst
.stride
);
6053 fprintf(file
, ":%s, ", brw_reg_type_to_letters(inst
->dst
.type
));
6055 for (int i
= 0; i
< inst
->sources
; i
++) {
6056 if (inst
->src
[i
].negate
)
6058 if (inst
->src
[i
].abs
)
6060 switch (inst
->src
[i
].file
) {
6062 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
6065 fprintf(file
, "g%d", inst
->src
[i
].nr
);
6068 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
6071 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
6074 fprintf(file
, "u%d", inst
->src
[i
].nr
);
6077 fprintf(file
, "(null)");
6080 switch (inst
->src
[i
].type
) {
6081 case BRW_REGISTER_TYPE_F
:
6082 fprintf(file
, "%-gf", inst
->src
[i
].f
);
6084 case BRW_REGISTER_TYPE_DF
:
6085 fprintf(file
, "%fdf", inst
->src
[i
].df
);
6087 case BRW_REGISTER_TYPE_W
:
6088 case BRW_REGISTER_TYPE_D
:
6089 fprintf(file
, "%dd", inst
->src
[i
].d
);
6091 case BRW_REGISTER_TYPE_UW
:
6092 case BRW_REGISTER_TYPE_UD
:
6093 fprintf(file
, "%uu", inst
->src
[i
].ud
);
6095 case BRW_REGISTER_TYPE_Q
:
6096 fprintf(file
, "%" PRId64
"q", inst
->src
[i
].d64
);
6098 case BRW_REGISTER_TYPE_UQ
:
6099 fprintf(file
, "%" PRIu64
"uq", inst
->src
[i
].u64
);
6101 case BRW_REGISTER_TYPE_VF
:
6102 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
6103 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
6104 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
6105 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
6106 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
6108 case BRW_REGISTER_TYPE_V
:
6109 case BRW_REGISTER_TYPE_UV
:
6110 fprintf(file
, "%08x%s", inst
->src
[i
].ud
,
6111 inst
->src
[i
].type
== BRW_REGISTER_TYPE_V
? "V" : "UV");
6114 fprintf(file
, "???");
6119 switch (inst
->src
[i
].nr
) {
6121 fprintf(file
, "null");
6123 case BRW_ARF_ADDRESS
:
6124 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
6126 case BRW_ARF_ACCUMULATOR
:
6127 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
6130 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
6133 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
6139 if (inst
->src
[i
].offset
||
6140 (inst
->src
[i
].file
== VGRF
&&
6141 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
6142 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
6143 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
6144 inst
->src
[i
].offset
% reg_size
);
6147 if (inst
->src
[i
].abs
)
6150 if (inst
->src
[i
].file
!= IMM
) {
6152 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
6153 unsigned hstride
= inst
->src
[i
].hstride
;
6154 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
6156 stride
= inst
->src
[i
].stride
;
6159 fprintf(file
, "<%u>", stride
);
6161 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
6164 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
6165 fprintf(file
, ", ");
6170 if (inst
->force_writemask_all
)
6171 fprintf(file
, "NoMask ");
6173 if (inst
->exec_size
!= dispatch_width
)
6174 fprintf(file
, "group%d ", inst
->group
);
6176 fprintf(file
, "\n");
6180 fs_visitor::setup_fs_payload_gen6()
6182 assert(stage
== MESA_SHADER_FRAGMENT
);
6183 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
6184 const unsigned payload_width
= MIN2(16, dispatch_width
);
6185 assert(dispatch_width
% payload_width
== 0);
6186 assert(devinfo
->gen
>= 6);
6188 prog_data
->uses_src_depth
= prog_data
->uses_src_w
=
6189 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
6191 prog_data
->uses_sample_mask
=
6192 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
6194 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
6196 * "MSDISPMODE_PERSAMPLE is required in order to select
6199 * So we can only really get sample positions if we are doing real
6200 * per-sample dispatch. If we need gl_SamplePosition and we don't have
6201 * persample dispatch, we hard-code it to 0.5.
6203 prog_data
->uses_pos_offset
= prog_data
->persample_dispatch
&&
6204 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
6206 /* R0: PS thread payload header. */
6209 for (unsigned j
= 0; j
< dispatch_width
/ payload_width
; j
++) {
6210 /* R1: masks, pixel X/Y coordinates. */
6211 payload
.subspan_coord_reg
[j
] = payload
.num_regs
++;
6214 for (unsigned j
= 0; j
< dispatch_width
/ payload_width
; j
++) {
6215 /* R3-26: barycentric interpolation coordinates. These appear in the
6216 * same order that they appear in the brw_barycentric_mode enum. Each
6217 * set of coordinates occupies 2 registers if dispatch width == 8 and 4
6218 * registers if dispatch width == 16. Coordinates only appear if they
6219 * were enabled using the "Barycentric Interpolation Mode" bits in
6222 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
6223 if (prog_data
->barycentric_interp_modes
& (1 << i
)) {
6224 payload
.barycentric_coord_reg
[i
][j
] = payload
.num_regs
;
6225 payload
.num_regs
+= payload_width
/ 4;
6229 /* R27-28: interpolated depth if uses source depth */
6230 if (prog_data
->uses_src_depth
) {
6231 payload
.source_depth_reg
[j
] = payload
.num_regs
;
6232 payload
.num_regs
+= payload_width
/ 8;
6235 /* R29-30: interpolated W set if GEN6_WM_USES_SOURCE_W. */
6236 if (prog_data
->uses_src_w
) {
6237 payload
.source_w_reg
[j
] = payload
.num_regs
;
6238 payload
.num_regs
+= payload_width
/ 8;
6241 /* R31: MSAA position offsets. */
6242 if (prog_data
->uses_pos_offset
) {
6243 payload
.sample_pos_reg
[j
] = payload
.num_regs
;
6247 /* R32-33: MSAA input coverage mask */
6248 if (prog_data
->uses_sample_mask
) {
6249 assert(devinfo
->gen
>= 7);
6250 payload
.sample_mask_in_reg
[j
] = payload
.num_regs
;
6251 payload
.num_regs
+= payload_width
/ 8;
6255 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6256 source_depth_to_render_target
= true;
6261 fs_visitor::setup_vs_payload()
6263 /* R0: thread header, R1: urb handles */
6264 payload
.num_regs
= 2;
6268 fs_visitor::setup_gs_payload()
6270 assert(stage
== MESA_SHADER_GEOMETRY
);
6272 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
6273 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
6275 /* R0: thread header, R1: output URB handles */
6276 payload
.num_regs
= 2;
6278 if (gs_prog_data
->include_primitive_id
) {
6279 /* R2: Primitive ID 0..7 */
6283 /* Always enable VUE handles so we can safely use pull model if needed.
6285 * The push model for a GS uses a ton of register space even for trivial
6286 * scenarios with just a few inputs, so just make things easier and a bit
6287 * safer by always having pull model available.
6289 gs_prog_data
->base
.include_vue_handles
= true;
6291 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
6292 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
6294 /* Use a maximum of 24 registers for push-model inputs. */
6295 const unsigned max_push_components
= 24;
6297 /* If pushing our inputs would take too many registers, reduce the URB read
6298 * length (which is in HWords, or 8 registers), and resort to pulling.
6300 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
6301 * have to multiply by VerticesIn to obtain the total storage requirement.
6303 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
6304 max_push_components
) {
6305 vue_prog_data
->urb_read_length
=
6306 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
6311 fs_visitor::setup_cs_payload()
6313 assert(devinfo
->gen
>= 7);
6314 payload
.num_regs
= 1;
6318 fs_visitor::calculate_register_pressure()
6320 invalidate_live_intervals();
6321 calculate_live_intervals();
6323 unsigned num_instructions
= 0;
6324 foreach_block(block
, cfg
)
6325 num_instructions
+= block
->instructions
.length();
6327 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
6329 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
6330 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
6331 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
6336 fs_visitor::optimize()
6338 /* Start by validating the shader we currently have. */
6341 /* bld is the common builder object pointing at the end of the program we
6342 * used to translate it into i965 IR. For the optimization and lowering
6343 * passes coming next, any code added after the end of the program without
6344 * having explicitly called fs_builder::at() clearly points at a mistake.
6345 * Ideally optimization passes wouldn't be part of the visitor so they
6346 * wouldn't have access to bld at all, but they do, so just in case some
6347 * pass forgets to ask for a location explicitly set it to NULL here to
6348 * make it trip. The dispatch width is initialized to a bogus value to
6349 * make sure that optimizations set the execution controls explicitly to
6350 * match the code they are manipulating instead of relying on the defaults.
6352 bld
= fs_builder(this, 64);
6354 assign_constant_locations();
6355 lower_constant_loads();
6359 split_virtual_grfs();
6362 #define OPT(pass, args...) ({ \
6364 bool this_progress = pass(args); \
6366 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
6367 char filename[64]; \
6368 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
6369 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
6371 backend_shader::dump_instructions(filename); \
6376 progress = progress || this_progress; \
6380 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
6382 snprintf(filename
, 64, "%s%d-%s-00-00-start",
6383 stage_abbrev
, dispatch_width
, nir
->info
.name
);
6385 backend_shader::dump_instructions(filename
);
6388 bool progress
= false;
6392 OPT(remove_extra_rounding_modes
);
6399 OPT(remove_duplicate_mrf_writes
);
6403 OPT(opt_copy_propagation
);
6404 OPT(opt_predicated_break
, this);
6405 OPT(opt_cmod_propagation
);
6406 OPT(dead_code_eliminate
);
6407 OPT(opt_peephole_sel
);
6408 OPT(dead_control_flow_eliminate
, this);
6409 OPT(opt_register_renaming
);
6410 OPT(opt_saturate_propagation
);
6411 OPT(register_coalesce
);
6412 OPT(compute_to_mrf
);
6413 OPT(eliminate_find_live_channel
);
6415 OPT(compact_virtual_grfs
);
6418 /* Do this after cmod propagation has had every possible opportunity to
6419 * propagate results into SEL instructions.
6421 if (OPT(opt_peephole_csel
))
6422 OPT(dead_code_eliminate
);
6427 if (OPT(lower_pack
)) {
6428 OPT(register_coalesce
);
6429 OPT(dead_code_eliminate
);
6432 OPT(lower_simd_width
);
6434 /* After SIMD lowering just in case we had to unroll the EOT send. */
6435 OPT(opt_sampler_eot
);
6437 OPT(lower_logical_sends
);
6440 OPT(opt_copy_propagation
);
6441 /* Only run after logical send lowering because it's easier to implement
6442 * in terms of physical sends.
6444 if (OPT(opt_zero_samples
))
6445 OPT(opt_copy_propagation
);
6446 /* Run after logical send lowering to give it a chance to CSE the
6447 * LOAD_PAYLOAD instructions created to construct the payloads of
6448 * e.g. texturing messages in cases where it wasn't possible to CSE the
6449 * whole logical instruction.
6452 OPT(register_coalesce
);
6453 OPT(compute_to_mrf
);
6454 OPT(dead_code_eliminate
);
6455 OPT(remove_duplicate_mrf_writes
);
6456 OPT(opt_peephole_sel
);
6459 OPT(opt_redundant_discard_jumps
);
6461 if (OPT(lower_load_payload
)) {
6462 split_virtual_grfs();
6463 OPT(register_coalesce
);
6464 OPT(lower_simd_width
);
6465 OPT(compute_to_mrf
);
6466 OPT(dead_code_eliminate
);
6469 OPT(opt_combine_constants
);
6470 OPT(lower_integer_multiplication
);
6472 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
6473 OPT(opt_cmod_propagation
);
6475 OPT(opt_copy_propagation
);
6476 OPT(dead_code_eliminate
);
6479 if (OPT(lower_regioning
)) {
6480 OPT(opt_copy_propagation
);
6481 OPT(dead_code_eliminate
);
6482 OPT(lower_simd_width
);
6485 lower_uniform_pull_constant_loads();
6491 * Three source instruction must have a GRF/MRF destination register.
6492 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
6495 fs_visitor::fixup_3src_null_dest()
6497 bool progress
= false;
6499 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
6500 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
6501 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
6508 invalidate_live_intervals();
6512 fs_visitor::allocate_registers(unsigned min_dispatch_width
, bool allow_spilling
)
6514 bool allocated_without_spills
;
6516 static const enum instruction_scheduler_mode pre_modes
[] = {
6518 SCHEDULE_PRE_NON_LIFO
,
6522 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
6524 /* Try each scheduling heuristic to see if it can successfully register
6525 * allocate without spilling. They should be ordered by decreasing
6526 * performance but increasing likelihood of allocating.
6528 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
6529 schedule_instructions(pre_modes
[i
]);
6532 assign_regs_trivial();
6533 allocated_without_spills
= true;
6535 allocated_without_spills
= assign_regs(false, spill_all
);
6537 if (allocated_without_spills
)
6541 if (!allocated_without_spills
) {
6542 if (!allow_spilling
)
6543 fail("Failure to register allocate and spilling is not allowed.");
6545 /* We assume that any spilling is worse than just dropping back to
6546 * SIMD8. There's probably actually some intermediate point where
6547 * SIMD16 with a couple of spills is still better.
6549 if (dispatch_width
> min_dispatch_width
) {
6550 fail("Failure to register allocate. Reduce number of "
6551 "live scalar values to avoid this.");
6553 compiler
->shader_perf_log(log_data
,
6554 "%s shader triggered register spilling. "
6555 "Try reducing the number of live scalar "
6556 "values to improve performance.\n",
6560 /* Since we're out of heuristics, just go spill registers until we
6561 * get an allocation.
6563 while (!assign_regs(true, spill_all
)) {
6569 /* This must come after all optimization and register allocation, since
6570 * it inserts dead code that happens to have side effects, and it does
6571 * so based on the actual physical registers in use.
6573 insert_gen4_send_dependency_workarounds();
6578 opt_bank_conflicts();
6580 schedule_instructions(SCHEDULE_POST
);
6582 if (last_scratch
> 0) {
6583 MAYBE_UNUSED
unsigned max_scratch_size
= 2 * 1024 * 1024;
6585 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
6587 if (stage
== MESA_SHADER_COMPUTE
) {
6588 if (devinfo
->is_haswell
) {
6589 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
6590 * field documentation, Haswell supports a minimum of 2kB of
6591 * scratch space for compute shaders, unlike every other stage
6594 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
6595 } else if (devinfo
->gen
<= 7) {
6596 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
6597 * field documentation, platforms prior to Haswell measure scratch
6598 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
6600 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
6601 max_scratch_size
= 12 * 1024;
6605 /* We currently only support up to 2MB of scratch space. If we
6606 * need to support more eventually, the documentation suggests
6607 * that we could allocate a larger buffer, and partition it out
6608 * ourselves. We'd just have to undo the hardware's address
6609 * calculation by subtracting (FFTID * Per Thread Scratch Space)
6610 * and then add FFTID * (Larger Per Thread Scratch Space).
6612 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
6613 * Thread Group Tracking > Local Memory/Scratch Space.
6615 assert(prog_data
->total_scratch
< max_scratch_size
);
6620 fs_visitor::run_vs()
6622 assert(stage
== MESA_SHADER_VERTEX
);
6626 if (shader_time_index
>= 0)
6627 emit_shader_time_begin();
6634 compute_clip_distance();
6638 if (shader_time_index
>= 0)
6639 emit_shader_time_end();
6645 assign_curb_setup();
6646 assign_vs_urb_setup();
6648 fixup_3src_null_dest();
6649 allocate_registers(8, true);
6655 fs_visitor::run_tcs_single_patch()
6657 assert(stage
== MESA_SHADER_TESS_CTRL
);
6659 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
6661 /* r1-r4 contain the ICP handles. */
6662 payload
.num_regs
= 5;
6664 if (shader_time_index
>= 0)
6665 emit_shader_time_begin();
6667 /* Initialize gl_InvocationID */
6668 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
6669 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6670 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
6671 bld
.MOV(channels_ud
, channels_uw
);
6673 if (tcs_prog_data
->instances
== 1) {
6674 invocation_id
= channels_ud
;
6676 const unsigned invocation_id_mask
= devinfo
->gen
>= 11 ?
6677 INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
6678 const unsigned invocation_id_shift
= devinfo
->gen
>= 11 ? 16 : 17;
6680 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6682 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
6683 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6684 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6685 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
6686 brw_imm_ud(invocation_id_mask
));
6687 bld
.SHR(instance_times_8
, t
, brw_imm_ud(invocation_id_shift
- 3));
6689 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
6692 /* Fix the disptach mask */
6693 if (nir
->info
.tess
.tcs_vertices_out
% 8) {
6694 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
6695 brw_imm_ud(nir
->info
.tess
.tcs_vertices_out
), BRW_CONDITIONAL_L
);
6696 bld
.IF(BRW_PREDICATE_NORMAL
);
6701 if (nir
->info
.tess
.tcs_vertices_out
% 8) {
6702 bld
.emit(BRW_OPCODE_ENDIF
);
6705 /* Emit EOT write; set TR DS Cache bit */
6707 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
6708 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
6709 fs_reg(brw_imm_ud(0)),
6711 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
6712 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
6714 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
6715 bld
.null_reg_ud(), payload
);
6719 if (shader_time_index
>= 0)
6720 emit_shader_time_end();
6729 assign_curb_setup();
6730 assign_tcs_single_patch_urb_setup();
6732 fixup_3src_null_dest();
6733 allocate_registers(8, true);
6739 fs_visitor::run_tes()
6741 assert(stage
== MESA_SHADER_TESS_EVAL
);
6743 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6744 payload
.num_regs
= 5;
6746 if (shader_time_index
>= 0)
6747 emit_shader_time_begin();
6756 if (shader_time_index
>= 0)
6757 emit_shader_time_end();
6763 assign_curb_setup();
6764 assign_tes_urb_setup();
6766 fixup_3src_null_dest();
6767 allocate_registers(8, true);
6773 fs_visitor::run_gs()
6775 assert(stage
== MESA_SHADER_GEOMETRY
);
6779 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6781 if (gs_compile
->control_data_header_size_bits
> 0) {
6782 /* Create a VGRF to store accumulated control data bits. */
6783 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6785 /* If we're outputting more than 32 control data bits, then EmitVertex()
6786 * will set control_data_bits to 0 after emitting the first vertex.
6787 * Otherwise, we need to initialize it to 0 here.
6789 if (gs_compile
->control_data_header_size_bits
<= 32) {
6790 const fs_builder abld
= bld
.annotate("initialize control data bits");
6791 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6795 if (shader_time_index
>= 0)
6796 emit_shader_time_begin();
6800 emit_gs_thread_end();
6802 if (shader_time_index
>= 0)
6803 emit_shader_time_end();
6812 assign_curb_setup();
6813 assign_gs_urb_setup();
6815 fixup_3src_null_dest();
6816 allocate_registers(8, true);
6821 /* From the SKL PRM, Volume 16, Workarounds:
6823 * 0877 3D Pixel Shader Hang possible when pixel shader dispatched with
6824 * only header phases (R0-R2)
6826 * WA: Enable a non-header phase (e.g. push constant) when dispatch would
6827 * have been header only.
6829 * Instead of enabling push constants one can alternatively enable one of the
6830 * inputs. Here one simply chooses "layer" which shouldn't impose much
6834 gen9_ps_header_only_workaround(struct brw_wm_prog_data
*wm_prog_data
)
6836 if (wm_prog_data
->num_varying_inputs
)
6839 if (wm_prog_data
->base
.curb_read_length
)
6842 wm_prog_data
->urb_setup
[VARYING_SLOT_LAYER
] = 0;
6843 wm_prog_data
->num_varying_inputs
= 1;
6847 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6849 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
6850 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6852 assert(stage
== MESA_SHADER_FRAGMENT
);
6854 if (devinfo
->gen
>= 6)
6855 setup_fs_payload_gen6();
6857 setup_fs_payload_gen4();
6861 } else if (do_rep_send
) {
6862 assert(dispatch_width
== 16);
6863 emit_repclear_shader();
6865 if (shader_time_index
>= 0)
6866 emit_shader_time_begin();
6868 calculate_urb_setup();
6869 if (nir
->info
.inputs_read
> 0 ||
6870 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
6871 if (devinfo
->gen
< 6)
6872 emit_interpolation_setup_gen4();
6874 emit_interpolation_setup_gen6();
6877 /* We handle discards by keeping track of the still-live pixels in f0.1.
6878 * Initialize it with the dispatched pixels.
6880 if (wm_prog_data
->uses_kill
) {
6881 const fs_reg dispatch_mask
=
6882 devinfo
->gen
>= 6 ? brw_vec1_grf(1, 7) : brw_vec1_grf(0, 0);
6883 bld
.exec_all().group(1, 0)
6884 .MOV(retype(brw_flag_reg(0, 1), BRW_REGISTER_TYPE_UW
),
6885 retype(dispatch_mask
, BRW_REGISTER_TYPE_UW
));
6893 if (wm_prog_data
->uses_kill
)
6894 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6896 if (wm_key
->alpha_test_func
)
6901 if (shader_time_index
>= 0)
6902 emit_shader_time_end();
6908 assign_curb_setup();
6910 if (devinfo
->gen
>= 9)
6911 gen9_ps_header_only_workaround(wm_prog_data
);
6915 fixup_3src_null_dest();
6916 allocate_registers(8, allow_spilling
);
6926 fs_visitor::run_cs(unsigned min_dispatch_width
)
6928 assert(stage
== MESA_SHADER_COMPUTE
);
6929 assert(dispatch_width
>= min_dispatch_width
);
6933 if (shader_time_index
>= 0)
6934 emit_shader_time_begin();
6936 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6937 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6938 const fs_builder abld
= bld
.exec_all().group(1, 0);
6939 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
6940 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6948 emit_cs_terminate();
6950 if (shader_time_index
>= 0)
6951 emit_shader_time_end();
6957 assign_curb_setup();
6959 fixup_3src_null_dest();
6960 allocate_registers(min_dispatch_width
, true);
6969 * Return a bitfield where bit n is set if barycentric interpolation mode n
6970 * (see enum brw_barycentric_mode) is needed by the fragment shader.
6972 * We examine the load_barycentric intrinsics rather than looking at input
6973 * variables so that we catch interpolateAtCentroid() messages too, which
6974 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
6977 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
6978 const nir_shader
*shader
)
6980 unsigned barycentric_interp_modes
= 0;
6982 nir_foreach_function(f
, shader
) {
6986 nir_foreach_block(block
, f
->impl
) {
6987 nir_foreach_instr(instr
, block
) {
6988 if (instr
->type
!= nir_instr_type_intrinsic
)
6991 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6992 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6995 /* Ignore WPOS; it doesn't require interpolation. */
6996 if (nir_intrinsic_base(intrin
) == VARYING_SLOT_POS
)
6999 intrin
= nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
7000 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
7001 nir_intrinsic_interp_mode(intrin
);
7002 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
7003 enum brw_barycentric_mode bary
=
7004 brw_barycentric_mode(interp
, bary_op
);
7006 barycentric_interp_modes
|= 1 << bary
;
7008 if (devinfo
->needs_unlit_centroid_workaround
&&
7009 bary_op
== nir_intrinsic_load_barycentric_centroid
)
7010 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
7015 return barycentric_interp_modes
;
7019 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
7020 const nir_shader
*shader
)
7022 prog_data
->flat_inputs
= 0;
7024 nir_foreach_variable(var
, &shader
->inputs
) {
7025 unsigned slots
= glsl_count_attribute_slots(var
->type
, false);
7026 for (unsigned s
= 0; s
< slots
; s
++) {
7027 int input_index
= prog_data
->urb_setup
[var
->data
.location
+ s
];
7029 if (input_index
< 0)
7033 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
7034 prog_data
->flat_inputs
|= 1 << input_index
;
7040 computed_depth_mode(const nir_shader
*shader
)
7042 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
7043 switch (shader
->info
.fs
.depth_layout
) {
7044 case FRAG_DEPTH_LAYOUT_NONE
:
7045 case FRAG_DEPTH_LAYOUT_ANY
:
7046 return BRW_PSCDEPTH_ON
;
7047 case FRAG_DEPTH_LAYOUT_GREATER
:
7048 return BRW_PSCDEPTH_ON_GE
;
7049 case FRAG_DEPTH_LAYOUT_LESS
:
7050 return BRW_PSCDEPTH_ON_LE
;
7051 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
7052 return BRW_PSCDEPTH_OFF
;
7055 return BRW_PSCDEPTH_OFF
;
7059 * Move load_interpolated_input with simple (payload-based) barycentric modes
7060 * to the top of the program so we don't emit multiple PLNs for the same input.
7062 * This works around CSE not being able to handle non-dominating cases
7068 * interpolate the same exact input
7071 * This should be replaced by global value numbering someday.
7074 move_interpolation_to_top(nir_shader
*nir
)
7076 bool progress
= false;
7078 nir_foreach_function(f
, nir
) {
7082 nir_block
*top
= nir_start_block(f
->impl
);
7083 exec_node
*cursor_node
= NULL
;
7085 nir_foreach_block(block
, f
->impl
) {
7089 nir_foreach_instr_safe(instr
, block
) {
7090 if (instr
->type
!= nir_instr_type_intrinsic
)
7093 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
7094 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
7096 nir_intrinsic_instr
*bary_intrinsic
=
7097 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
7098 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
7100 /* Leave interpolateAtSample/Offset() where they are. */
7101 if (op
== nir_intrinsic_load_barycentric_at_sample
||
7102 op
== nir_intrinsic_load_barycentric_at_offset
)
7105 nir_instr
*move
[3] = {
7106 &bary_intrinsic
->instr
,
7107 intrin
->src
[1].ssa
->parent_instr
,
7111 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
7112 if (move
[i
]->block
!= top
) {
7113 move
[i
]->block
= top
;
7114 exec_node_remove(&move
[i
]->node
);
7116 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
7118 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
7120 cursor_node
= &move
[i
]->node
;
7126 nir_metadata_preserve(f
->impl
, (nir_metadata
)
7127 ((unsigned) nir_metadata_block_index
|
7128 (unsigned) nir_metadata_dominance
));
7135 * Demote per-sample barycentric intrinsics to centroid.
7137 * Useful when rendering to a non-multisampled buffer.
7140 demote_sample_qualifiers(nir_shader
*nir
)
7142 bool progress
= true;
7144 nir_foreach_function(f
, nir
) {
7149 nir_builder_init(&b
, f
->impl
);
7151 nir_foreach_block(block
, f
->impl
) {
7152 nir_foreach_instr_safe(instr
, block
) {
7153 if (instr
->type
!= nir_instr_type_intrinsic
)
7156 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
7157 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
7158 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
7161 b
.cursor
= nir_before_instr(instr
);
7162 nir_ssa_def
*centroid
=
7163 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
7164 nir_intrinsic_interp_mode(intrin
));
7165 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
7166 nir_src_for_ssa(centroid
));
7167 nir_instr_remove(instr
);
7172 nir_metadata_preserve(f
->impl
, (nir_metadata
)
7173 ((unsigned) nir_metadata_block_index
|
7174 (unsigned) nir_metadata_dominance
));
7181 * Pre-gen6, the register file of the EUs was shared between threads,
7182 * and each thread used some subset allocated on a 16-register block
7183 * granularity. The unit states wanted these block counts.
7186 brw_register_blocks(int reg_count
)
7188 return ALIGN(reg_count
, 16) / 16 - 1;
7192 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
7194 const struct brw_wm_prog_key
*key
,
7195 struct brw_wm_prog_data
*prog_data
,
7197 struct gl_program
*prog
,
7198 int shader_time_index8
, int shader_time_index16
,
7199 int shader_time_index32
, bool allow_spilling
,
7200 bool use_rep_send
, struct brw_vue_map
*vue_map
,
7203 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
7205 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, true);
7206 brw_nir_lower_fs_inputs(shader
, devinfo
, key
);
7207 brw_nir_lower_fs_outputs(shader
);
7209 if (devinfo
->gen
< 6) {
7210 brw_setup_vue_interpolation(vue_map
, shader
, prog_data
, devinfo
);
7213 if (!key
->multisample_fbo
)
7214 NIR_PASS_V(shader
, demote_sample_qualifiers
);
7215 NIR_PASS_V(shader
, move_interpolation_to_top
);
7216 shader
= brw_postprocess_nir(shader
, compiler
, true);
7218 /* key->alpha_test_func means simulating alpha testing via discards,
7219 * so the shader definitely kills pixels.
7221 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
||
7222 key
->alpha_test_func
;
7223 prog_data
->uses_omask
= key
->multisample_fbo
&&
7224 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
7225 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
7226 prog_data
->computed_stencil
=
7227 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
7229 prog_data
->persample_dispatch
=
7230 key
->multisample_fbo
&&
7231 (key
->persample_interp
||
7232 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
7233 SYSTEM_BIT_SAMPLE_POS
)) ||
7234 shader
->info
.fs
.uses_sample_qualifier
||
7235 shader
->info
.outputs_read
);
7237 prog_data
->has_render_target_reads
= shader
->info
.outputs_read
!= 0ull;
7239 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
7240 prog_data
->post_depth_coverage
= shader
->info
.fs
.post_depth_coverage
;
7241 prog_data
->inner_coverage
= shader
->info
.fs
.inner_coverage
;
7243 prog_data
->barycentric_interp_modes
=
7244 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
7246 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
, *simd32_cfg
= NULL
;
7248 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
7249 &prog_data
->base
, prog
, shader
, 8,
7250 shader_time_index8
);
7251 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
7253 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
7256 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
7258 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
7259 prog_data
->reg_blocks_8
= brw_register_blocks(v8
.grf_used
);
7262 if (v8
.max_dispatch_width
>= 16 &&
7263 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
7264 /* Try a SIMD16 compile */
7265 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
7266 &prog_data
->base
, prog
, shader
, 16,
7267 shader_time_index16
);
7268 v16
.import_uniforms(&v8
);
7269 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
7270 compiler
->shader_perf_log(log_data
,
7271 "SIMD16 shader failed to compile: %s",
7274 simd16_cfg
= v16
.cfg
;
7275 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
7276 prog_data
->reg_blocks_16
= brw_register_blocks(v16
.grf_used
);
7280 /* Currently, the compiler only supports SIMD32 on SNB+ */
7281 if (v8
.max_dispatch_width
>= 32 && !use_rep_send
&&
7282 compiler
->devinfo
->gen
>= 6 &&
7283 unlikely(INTEL_DEBUG
& DEBUG_DO32
)) {
7284 /* Try a SIMD32 compile */
7285 fs_visitor
v32(compiler
, log_data
, mem_ctx
, key
,
7286 &prog_data
->base
, prog
, shader
, 32,
7287 shader_time_index32
);
7288 v32
.import_uniforms(&v8
);
7289 if (!v32
.run_fs(allow_spilling
, false)) {
7290 compiler
->shader_perf_log(log_data
,
7291 "SIMD32 shader failed to compile: %s",
7294 simd32_cfg
= v32
.cfg
;
7295 prog_data
->dispatch_grf_start_reg_32
= v32
.payload
.num_regs
;
7296 prog_data
->reg_blocks_32
= brw_register_blocks(v32
.grf_used
);
7300 /* When the caller requests a repclear shader, they want SIMD16-only */
7304 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
7305 * at the top to select the shader. We've never implemented that.
7306 * Instead, we just give them exactly one shader and we pick the widest one
7309 if (compiler
->devinfo
->gen
< 5) {
7310 if (simd32_cfg
|| simd16_cfg
)
7316 /* If computed depth is enabled SNB only allows SIMD8. */
7317 if (compiler
->devinfo
->gen
== 6 &&
7318 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
)
7319 assert(simd16_cfg
== NULL
&& simd32_cfg
== NULL
);
7321 if (compiler
->devinfo
->gen
<= 5 && !simd8_cfg
) {
7322 /* Iron lake and earlier only have one Dispatch GRF start field. Make
7323 * the data available in the base prog data struct for convenience.
7326 prog_data
->base
.dispatch_grf_start_reg
=
7327 prog_data
->dispatch_grf_start_reg_16
;
7328 } else if (simd32_cfg
) {
7329 prog_data
->base
.dispatch_grf_start_reg
=
7330 prog_data
->dispatch_grf_start_reg_32
;
7334 if (prog_data
->persample_dispatch
) {
7335 /* Starting with SandyBridge (where we first get MSAA), the different
7336 * pixel dispatch combinations are grouped into classifications A
7337 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
7338 * generations, the only configurations supporting persample dispatch
7339 * are are this in which only one dispatch width is enabled.
7341 if (simd32_cfg
|| simd16_cfg
)
7347 /* We have to compute the flat inputs after the visitor is finished running
7348 * because it relies on prog_data->urb_setup which is computed in
7349 * fs_visitor::calculate_urb_setup().
7351 brw_compute_flat_inputs(prog_data
, shader
);
7353 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
7354 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
7355 MESA_SHADER_FRAGMENT
);
7357 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
7358 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
7359 shader
->info
.label
?
7360 shader
->info
.label
: "unnamed",
7361 shader
->info
.name
));
7365 prog_data
->dispatch_8
= true;
7366 g
.generate_code(simd8_cfg
, 8);
7370 prog_data
->dispatch_16
= true;
7371 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
7375 prog_data
->dispatch_32
= true;
7376 prog_data
->prog_offset_32
= g
.generate_code(simd32_cfg
, 32);
7379 return g
.get_assembly();
7383 fs_visitor::emit_cs_work_group_id_setup()
7385 assert(stage
== MESA_SHADER_COMPUTE
);
7387 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
7389 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
7390 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
7391 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
7393 bld
.MOV(*reg
, r0_1
);
7394 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
7395 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
7401 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
7403 block
->dwords
= dwords
;
7404 block
->regs
= DIV_ROUND_UP(dwords
, 8);
7405 block
->size
= block
->regs
* 32;
7409 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
7410 struct brw_cs_prog_data
*cs_prog_data
)
7412 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
7413 int subgroup_id_index
= get_subgroup_id_param_index(prog_data
);
7414 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
7416 /* The thread ID should be stored in the last param dword */
7417 assert(subgroup_id_index
== -1 ||
7418 subgroup_id_index
== (int)prog_data
->nr_params
- 1);
7420 unsigned cross_thread_dwords
, per_thread_dwords
;
7421 if (!cross_thread_supported
) {
7422 cross_thread_dwords
= 0u;
7423 per_thread_dwords
= prog_data
->nr_params
;
7424 } else if (subgroup_id_index
>= 0) {
7425 /* Fill all but the last register with cross-thread payload */
7426 cross_thread_dwords
= 8 * (subgroup_id_index
/ 8);
7427 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
7428 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
7430 /* Fill all data using cross-thread payload */
7431 cross_thread_dwords
= prog_data
->nr_params
;
7432 per_thread_dwords
= 0u;
7435 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
7436 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
7438 unsigned total_dwords
=
7439 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
7440 cs_prog_data
->push
.cross_thread
.size
) / 4;
7441 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
7443 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
7444 cs_prog_data
->push
.per_thread
.size
== 0);
7445 assert(cs_prog_data
->push
.cross_thread
.dwords
+
7446 cs_prog_data
->push
.per_thread
.dwords
==
7447 prog_data
->nr_params
);
7451 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
7453 cs_prog_data
->simd_size
= size
;
7454 unsigned group_size
= cs_prog_data
->local_size
[0] *
7455 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
7456 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
7460 compile_cs_to_nir(const struct brw_compiler
*compiler
,
7462 const struct brw_cs_prog_key
*key
,
7463 const nir_shader
*src_shader
,
7464 unsigned dispatch_width
)
7466 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
7467 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, true);
7468 brw_nir_lower_cs_intrinsics(shader
, dispatch_width
);
7469 return brw_postprocess_nir(shader
, compiler
, true);
7473 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
7475 const struct brw_cs_prog_key
*key
,
7476 struct brw_cs_prog_data
*prog_data
,
7477 const nir_shader
*src_shader
,
7478 int shader_time_index
,
7481 prog_data
->local_size
[0] = src_shader
->info
.cs
.local_size
[0];
7482 prog_data
->local_size
[1] = src_shader
->info
.cs
.local_size
[1];
7483 prog_data
->local_size
[2] = src_shader
->info
.cs
.local_size
[2];
7484 unsigned local_workgroup_size
=
7485 src_shader
->info
.cs
.local_size
[0] * src_shader
->info
.cs
.local_size
[1] *
7486 src_shader
->info
.cs
.local_size
[2];
7488 unsigned min_dispatch_width
=
7489 DIV_ROUND_UP(local_workgroup_size
, compiler
->devinfo
->max_cs_threads
);
7490 min_dispatch_width
= MAX2(8, min_dispatch_width
);
7491 min_dispatch_width
= util_next_power_of_two(min_dispatch_width
);
7492 assert(min_dispatch_width
<= 32);
7494 fs_visitor
*v8
= NULL
, *v16
= NULL
, *v32
= NULL
;
7496 const char *fail_msg
= NULL
;
7497 unsigned promoted_constants
= 0;
7499 /* Now the main event: Visit the shader IR and generate our CS IR for it.
7501 if (min_dispatch_width
<= 8) {
7502 nir_shader
*nir8
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
7504 v8
= new fs_visitor(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
7505 NULL
, /* Never used in core profile */
7506 nir8
, 8, shader_time_index
);
7507 if (!v8
->run_cs(min_dispatch_width
)) {
7508 fail_msg
= v8
->fail_msg
;
7510 /* We should always be able to do SIMD32 for compute shaders */
7511 assert(v8
->max_dispatch_width
>= 32);
7514 cs_set_simd_size(prog_data
, 8);
7515 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
7516 promoted_constants
= v8
->promoted_constants
;
7520 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
7521 !fail_msg
&& min_dispatch_width
<= 16) {
7522 /* Try a SIMD16 compile */
7523 nir_shader
*nir16
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
7525 v16
= new fs_visitor(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
7526 NULL
, /* Never used in core profile */
7527 nir16
, 16, shader_time_index
);
7529 v16
->import_uniforms(v8
);
7531 if (!v16
->run_cs(min_dispatch_width
)) {
7532 compiler
->shader_perf_log(log_data
,
7533 "SIMD16 shader failed to compile: %s",
7537 "Couldn't generate SIMD16 program and not "
7538 "enough threads for SIMD8";
7541 /* We should always be able to do SIMD32 for compute shaders */
7542 assert(v16
->max_dispatch_width
>= 32);
7545 cs_set_simd_size(prog_data
, 16);
7546 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
7547 promoted_constants
= v16
->promoted_constants
;
7551 /* We should always be able to do SIMD32 for compute shaders */
7552 assert(!v16
|| v16
->max_dispatch_width
>= 32);
7554 if (!fail_msg
&& (min_dispatch_width
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
7555 /* Try a SIMD32 compile */
7556 nir_shader
*nir32
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
7558 v32
= new fs_visitor(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
7559 NULL
, /* Never used in core profile */
7560 nir32
, 32, shader_time_index
);
7562 v32
->import_uniforms(v8
);
7564 v32
->import_uniforms(v16
);
7566 if (!v32
->run_cs(min_dispatch_width
)) {
7567 compiler
->shader_perf_log(log_data
,
7568 "SIMD32 shader failed to compile: %s",
7572 "Couldn't generate SIMD32 program and not "
7573 "enough threads for SIMD16";
7577 cs_set_simd_size(prog_data
, 32);
7578 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
7579 promoted_constants
= v32
->promoted_constants
;
7583 const unsigned *ret
= NULL
;
7584 if (unlikely(cfg
== NULL
)) {
7587 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
7589 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
7590 promoted_constants
, false, MESA_SHADER_COMPUTE
);
7591 if (INTEL_DEBUG
& DEBUG_CS
) {
7592 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
7593 src_shader
->info
.label
?
7594 src_shader
->info
.label
: "unnamed",
7595 src_shader
->info
.name
);
7596 g
.enable_debug(name
);
7599 g
.generate_code(cfg
, prog_data
->simd_size
);
7601 ret
= g
.get_assembly();
7612 * Test the dispatch mask packing assumptions of
7613 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
7614 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
7615 * executed with an unexpected dispatch mask.
7618 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
7620 const gl_shader_stage stage
= bld
.shader
->stage
;
7622 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
7623 bld
.shader
->stage_prog_data
)) {
7624 const fs_builder ubld
= bld
.exec_all().group(1, 0);
7625 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
7626 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
7629 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
7630 ubld
.AND(tmp
, mask
, tmp
);
7632 /* This will loop forever if the dispatch mask doesn't have the expected
7633 * form '2^n-1', in which case tmp will be non-zero.
7635 bld
.emit(BRW_OPCODE_DO
);
7636 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
7637 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));